N-type high-efficiency battery and battery assembly
By adopting the structure of a front ejaculation layer and a multi-layer doped crystal silicon layer on the front of the N-type high-efficiency battery, the composite loss problem in the prior art is solved, and higher battery efficiency and comprehensive performance are achieved.
Patent Information
- Application Number
- CN202421194782.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-29
- Publication Date
- 2025-03-14
- Estimated Expiration
- 2034-05-29
AI Technical Summary
The direct contact of the front surface metal semiconductors of existing TOPCon solar cells leads to composite losses, limiting the further improvement of battery efficiency.
The front-side transverse layer is used to combine the multi-layer doped crystal silicon layer with specific concentration changes to reduce photoparametric absorption and recombination losses, and improve carrier mobility and passivation effect.
Through the structural design of the multi-layer doped crystalline silicon layer, the resistivity is reduced, the passivation effect and light absorption capacity are improved, thereby improving the overall performance of the N-type high-efficiency battery.
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Figure CN222621525U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of batteries, in particular to an N-type high-efficiency battery and a battery assembly. Background Art
[0002] TOPCon cells use ultra-thin silicon oxide and doped polysilicon to passivate the front and back surfaces of crystalline silicon and achieve selective carrier transport, which improves the efficiency of crystalline silicon solar cells. Tunneling oxide passivation contact is a passivation structure used for crystalline silicon solar cells. It consists of an ultra-thin layer of silicon oxide and a layer of heavily doped polysilicon. It is mainly used for the passivation of the back surface of the cell. It can achieve excellent surface passivation and selective collection of carriers. The conversion efficiency of crystalline silicon solar cells prepared with it has exceeded 25.7%. However, the front surface of this cell is still in direct contact with the metal semiconductor, and the recombination loss at the metal semiconductor contact limits the further improvement of the cell efficiency. Utility Model Content
[0003] The purpose of the utility model is to provide an N-type high-efficiency battery. The front side of the N-type high-efficiency battery adopts a front tunneling layer combined with a multi-layer doped crystalline silicon layer with a specific concentration change, which can reduce light parasitic absorption, reduce recombination loss, and reduce resistivity, thereby improving the comprehensive performance of the N-type high-efficiency battery.
[0004] The second object of the utility model is to provide a battery assembly, which has low resistivity and good overall performance.
[0005] To achieve this purpose, the utility model adopts the following technical solutions:
[0006] The utility model discloses an N-type high-efficiency battery, comprising an N-type silicon substrate and a front tunneling layer, a doped crystalline silicon layer and a front anti-reflection functional layer sequentially arranged on the front side of the N-type silicon substrate, wherein the doped crystalline silicon layer at least comprises a first doped crystalline silicon layer, a second doped crystalline silicon layer and a third doped crystalline silicon layer sequentially arranged in a front direction away from the N-type silicon substrate; the doping concentration of the first doped crystalline silicon layer is greater than the doping concentration of the N-type silicon substrate; wherein: the doping concentrations of the first doped crystalline silicon layer and the third doped crystalline silicon layer are both greater than the doping concentration of the second doped crystalline silicon layer; or: the doping concentrations of the first doped crystalline silicon layer and the third doped crystalline silicon layer are both less than the doping concentration of the second doped crystalline silicon layer.
[0007] In some embodiments, the doping concentrations of the first doped crystalline silicon layer and the third doped crystalline silicon layer are both greater than the doping concentration of the second doped crystalline silicon layer.
[0008] In some embodiments, the doping concentrations of the first doped crystalline silicon layer and the third doped crystalline silicon layer are both less than the doping concentration of the second doped crystalline silicon layer.
[0009] In some embodiments, the N-type high-efficiency battery further includes a boron diffusion layer, and the boron diffusion layer is disposed between the front surface of the N-type silicon substrate and the front tunneling layer.
[0010] In some embodiments, the N-type high-efficiency battery further includes at least one front polysilicon layer, and the front polysilicon layer is disposed between the front tunneling layer and the first doped crystalline silicon layer.
[0011] In some specific embodiments, the N-type high-efficiency battery further includes a silicon oxide layer, which is disposed between the front polysilicon layer and the first doped crystalline silicon layer, between two adjacent front polysilicon layers, or between two adjacent doped crystalline silicon layers.
[0012] In some embodiments, the first doped crystalline silicon layer, the second doped crystalline silicon layer and the third doped crystalline silicon layer are all microcrystalline silicon layers; or: the first doped crystalline silicon layer, the second doped crystalline silicon layer and the third doped crystalline silicon layer are all nanocrystalline silicon layers.
[0013] In some embodiments, the front anti-reflection functional layer includes a silicon nitride layer or a TCO layer; and / or: the front tunneling layer is one of silicon oxide, silicon carbide, silicon oxycarbide, silicon nitride and aluminum oxide.
[0014] In some embodiments, the thickness of the first doped crystalline silicon layer, the second doped crystalline silicon layer and the third doped crystalline silicon layer is 10 nm to 60 nm; the thickness of the front tunneling layer is 1 nm to 2 nm.
[0015] Beneficial effects of the utility model: Since the N-type high-efficiency battery of the utility model forms a doped crystalline silicon layer on the front, the doped crystalline silicon layer includes at least a first doped crystalline silicon layer, a second doped crystalline silicon layer and a third doped crystalline silicon layer, and multiple layers of doped crystalline silicon layers with different doping concentrations are used, the structural orderliness of the doped crystalline silicon layer makes the carrier mobility relatively high, and is also conducive to the collection of photogenerated electrons and hole pairs by the electrode. Since the doping concentrations of the first doped crystalline silicon layer and the third doped crystalline silicon layer are both greater than or less than the doping concentration of the second doped crystalline silicon layer. In this way, in the actual working process, the doping concentration of the first doped crystalline silicon layer will be higher than the doping concentration of the N-type silicon substrate, so that the Fermi level is closer to the conduction band, and the potential barrier can be guaranteed. The one with a higher doping concentration in the second doped crystalline silicon layer and the third doped crystalline silicon layer is conducive to reducing the resistivity and improving the passivation effect, and the one with a lower doping concentration is conducive to effectively reducing parasitic absorption and reducing recombination, thereby facilitating the N-type silicon substrate to absorb light.
[0016] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 This is a schematic diagram of the front structure of the N-type high-efficiency battery of the utility model;
[0018] Figure 2 This is a complete structural diagram of an N-type high-efficiency battery of the first structure of the utility model;
[0019] Figure 3 This is a complete structural diagram of an N-type high-efficiency battery of the second structure of the utility model;
[0020] Figure 4 This is a complete structural diagram of an N-type high-efficiency battery of the third structure of the utility model;
[0021] Figure 5 It is a complete structural schematic diagram of the fourth structure of the N-type high-efficiency battery of the utility model.
[0022] Reference numerals:
[0023] 10. N-type silicon substrate; 20. front tunneling layer; 30. first doped crystalline silicon layer; 40. second doped crystalline silicon layer; 50. third doped crystalline silicon layer; 60. boron diffusion layer; 70. front polysilicon layer; 80. front silicon oxide layer; 90. front anti-reflection functional layer; 100. back tunneling layer; 200. back polysilicon layer; 300. back anti-reflection functional layer; 400. electrode. DETAILED DESCRIPTION
[0024] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only the parts related to the present invention, rather than all structures, are shown in the accompanying drawings.
[0025] In the description of the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", and "fixed" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0026] In the present utility model, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.
[0027] In the description of this embodiment, the terms "upper", "lower", "right", etc., are based on the directions or positions shown in the drawings, and are only for the convenience of description and simplified operation, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation of the present invention. In addition, the terms "first" and "second" are only used to distinguish in the description and have no special meaning.
[0028] The utility model discloses an N-type high-efficiency battery, such as Figure 1 As shown, the N-type high-efficiency battery of the utility model includes an N-type silicon substrate 10 and a front tunneling layer 20, a doped crystalline silicon layer and a front anti-reflection functional layer 90 arranged in sequence on the front side of the N-type silicon substrate 10, and the doped crystalline silicon layer at least includes a first doped crystalline silicon layer 30, a second doped crystalline silicon layer 40 and a third doped crystalline silicon layer 50 arranged in sequence in the front direction away from the N-type silicon substrate 10; the doping concentration of the first doped crystalline silicon layer 30 is greater than the doping concentration of the N-type silicon substrate 10.
[0029] In the N-type high-efficiency battery of the present utility model, in some embodiments, the doping concentrations of the first doped crystalline silicon layer 30 and the third doped crystalline silicon layer 50 are both greater than the doping concentration of the second doped crystalline silicon layer 40. In other embodiments, the doping concentrations of the first doped crystalline silicon layer 30 and the third doped crystalline silicon layer 50 are both less than the doping concentration of the second doped crystalline silicon layer 40.
[0030] It can be understood that, since the N-type high-efficiency battery of the utility model forms a doped crystalline silicon layer on the front, the doped crystalline silicon layer includes at least a first doped crystalline silicon layer 30, a second doped crystalline silicon layer 40 and a third doped crystalline silicon layer 50, and multiple layers of doped crystalline silicon layers with different doping concentrations are used, the structural orderliness of the doped crystalline silicon layer makes the carrier mobility relatively high, and is also conducive to the collection of photogenerated electrons and hole pairs by the electrode 400. Since the doping concentrations of the first doped crystalline silicon layer 30 and the third doped crystalline silicon layer 50 are both greater than or less than the doping concentration of the second doped crystalline silicon layer 40. In this way, in the actual working process, the doping concentration of the first doped crystalline silicon layer 30 will be higher than the doping concentration of the N-type silicon substrate 10, so that the Fermi level is closer to the conduction band, and the potential barrier can be guaranteed. The one with a higher doping concentration in the second doped crystalline silicon layer 40 and the third doped crystalline silicon layer 50 is conducive to reducing the resistivity and improving the passivation effect, and the one with a lower doping concentration is conducive to effectively reducing parasitic absorption and reducing recombination, thereby facilitating the N-type silicon substrate 10 to absorb light.
[0031] It should be supplemented that, in the embodiments of the present invention, the doped crystalline silicon layer may be a single layer or multiple layers, which may be selected according to actual needs.
[0032] In some embodiments, the doping concentrations of the first doped crystalline silicon layer 30 and the third doped crystalline silicon layer 50 are both greater than the doping concentration of the second doped crystalline silicon layer 40, wherein the doping concentration of the first doped crystalline silicon layer 30 is 1×10 19 cm -3 ~3×10 19 cm -3 The doping concentration of the second doped crystalline silicon layer 40 is 5×10 18 cm -3 ~1×10 19 cm -3 The doping concentration of the third doped crystalline silicon layer 50 is 5×10 19 cm -3 ~1×10 20 cm -3 It can be understood that the doping concentration of the first doped crystalline silicon layer 30 is relatively high. The higher the doping concentration, the closer the Fermi level is to the conduction band, which can ensure the potential barrier. The doping concentration of the second doped crystalline silicon layer 40 is relatively low, which effectively reduces parasitic absorption and reduces recombination. The doping concentration of the third doped crystalline silicon layer 50 is relatively high, which is conducive to reducing resistivity. In addition, when used with the front anti-reflection functional layer 90, the high doping concentration helps to reduce the contact resistance.
[0033] Preferably, the doping concentration of the first doped crystalline silicon layer 30 is lower than the doping concentration of the third doped crystalline silicon layer 50. The advantage of such a setting is that the potential barrier is ensured while reducing the resistivity. The principle is that the doping concentration of the crystalline silicon close to the N-type silicon substrate 10 is several orders of magnitude higher than that of the N-type silicon substrate 10. The higher the doping concentration, the closer the Fermi level is to the valence band, ensuring the energy level difference. The doping concentration of the crystalline silicon far from the N-type silicon substrate 10 is high, which can improve mobility, reduce resistivity, and reduce the metal semiconductor contact resistivity.
[0034] In some embodiments, the doping concentrations of the first doped crystalline silicon layer 30 and the third doped crystalline silicon layer 50 are both less than the doping concentration of the second doped crystalline silicon layer 40: wherein the doping concentration of the first doped crystalline silicon layer 30 is 1×10 19 cm -3 ~3×10 19 cm -3 The doping concentration of the second doped crystalline silicon layer 40 is 5×10 19 cm -3 ~1×10 20 cm -3 The doping concentration of the third doped crystalline silicon layer 50 is 3×10 19 cm -3 ~5×10 19 cm -3 It can be understood that the doping concentration of the first doped crystalline silicon layer 30 is lower than that of the second doped crystalline silicon layer 40, but still higher than that of the N-type silicon substrate 10, so that the Fermi level is closer to the conduction band, the potential barrier can be guaranteed, the doping concentration of the second doped crystalline silicon layer 40 is relatively high, which can effectively reduce the resistivity, and the doping concentration of the third doped crystalline silicon layer 50 is relatively low, which effectively reduces parasitic absorption and reduces recombination.
[0035] Preferably, the doping concentration of the first doped crystalline silicon layer 30 is lower than the doping concentration of the third doped crystalline silicon layer 50. The advantage of such a setting is that the potential barrier is ensured while reducing the resistivity. The principle is that the doping concentration of the crystalline silicon close to the N-type silicon substrate 10 is several orders of magnitude higher than that of the N-type silicon substrate 10. The higher the doping concentration, the closer the Fermi level is to the conduction band, ensuring the energy level difference. The doping concentration of the crystalline silicon far from the N-type silicon substrate 10 is high, which can improve mobility, reduce resistivity, and reduce the metal semiconductor contact resistivity.
[0036] In some embodiments, the N-type high-efficiency battery further includes a boron diffusion layer 60, which is disposed between the front surface of the N-type silicon substrate 10 and the front tunneling layer 20. It is understandable that the additional boron diffusion layer 60 can enhance the passivation effect of the front surface of the N-type silicon substrate 10, thereby facilitating the improvement of the energy efficiency of the N-type high-efficiency battery.
[0037] In some embodiments, the N-type high-efficiency battery further includes at least one front polysilicon layer 70, and the front polysilicon layer 70 is disposed between the front tunneling layer 20 and the first doped crystalline silicon layer 30. It can be understood that the polysilicon structure has a higher crystallization rate and smaller parasitic absorption. Adding the front polysilicon layer 70 between the front tunneling layer 20 and the first doped crystalline silicon layer 30 can be more conducive to reducing parasitic absorption, so that the N-type silicon substrate 10 receives more light, which is conducive to improving the performance of the N-type high-efficiency battery.
[0038] Optionally, the thickness of the front polysilicon layer 70 is 20nm to 60nm, specifically 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm. Of course, in other embodiments of the utility model, the thickness of the front polysilicon layer 70 can also be selected according to actual needs.
[0039] In some specific embodiments, the N-type high-efficiency battery further includes a front silicon oxide layer 80, which is disposed between the front polysilicon layer 70 and the first doped crystalline silicon layer 30, and between two adjacent front polysilicon layers 70 or between two adjacent doped crystalline silicon layers. Adding the front silicon oxide layer 80 can suppress excessive diffusion of phosphorus during annealing, which is beneficial to improving the performance of the N-type high-efficiency battery.
[0040] It should be noted here that in the present invention, when the front polysilicon layer 70 is one layer, the front silicon oxide layer 80 is also one layer, and the front silicon oxide layer 80 is arranged between the first doped crystalline silicon layer 30 and the front polysilicon layer 70. When the front polysilicon layer 70 is two or more layers, the front silicon oxide layer 80 is also two or more layers, and the front silicon oxide layer 80 is arranged between the first doped crystalline silicon layer 30 and the front polysilicon layer 70 and between two adjacent layers of the front polysilicon layer 70. In some embodiments, the doped crystalline silicon layer can also be multiple layers, in which case the front silicon oxide layer 80 is arranged between two adjacent doped crystalline silicon layers. The number of the front silicon oxide layers 80, the number of the front polysilicon layers 70, and the number of the doped crystalline silicon layers can be selected according to the design requirements of the actual N-type high-efficiency battery.
[0041] In some embodiments, the first doped crystalline silicon layer 30, the second doped crystalline silicon layer 40 and the third doped crystalline silicon layer 50 are all microcrystalline silicon layers. It is understandable that the microcrystalline silicon layer has smaller grains, which is beneficial to improving the hydrogen passivation effect of the N-type high-efficiency battery.
[0042] In some embodiments, the first doped crystalline silicon layer 30, the second doped crystalline silicon layer 40 and the third doped crystalline silicon layer 50 are all nanocrystalline silicon layers. It is understood that compared with microcrystalline silicon layers, nanocrystalline silicon layers have smaller grains and are more conducive to improving the hydrogen passivation effect of crystalline silicon.
[0043] In some embodiments, the front anti-reflection functional layer 90 includes a silicon nitride layer.
[0044] In some embodiments, the front anti-reflection functional layer 90 includes a TCO layer. The TCO layer is used as the front anti-reflection functional layer 90. Based on the conductive properties of the TCO layer, the screen end of the printing process can use a relatively low-temperature silver paste sintering technology, thereby avoiding the contact between the gate line of the electrode 400 and the crystalline silicon, effectively reducing the contact resistance; and the relatively low-temperature sintering is conducive to inhibiting hydrogen diffusion and escape, and improving the hydrogen passivation of the crystalline silicon.
[0045] In some embodiments, front tunneling layer 20 includes silicon oxide.
[0046] In some embodiments, the front tunneling layer 20 includes at least one of silicon carbide, silicon oxycarbide, silicon nitride and aluminum oxide. It is understood that the introduction of carbon elements can make the film structure more compact and effectively inhibit film explosion; and during annealing, the introduction of carbon elements can effectively prevent excessive diffusion of phosphorus into the silicon substrate.
[0047] In some embodiments, the thickness of the first doped crystalline silicon layer 30, the second doped crystalline silicon layer 40, and the third doped crystalline silicon layer 50 are all 10 nm to 60 nm, and can be 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, or 60 nm. Of course, in other embodiments of the present invention, the thickness of the first doped crystalline silicon layer 30, the second doped crystalline silicon layer 40, and the third doped crystalline silicon layer 50 can also be selected from other thicknesses according to actual needs.
[0048] In some embodiments, the thickness of the front tunneling layer 20 is 1 nm to 2 nm. Specifically, it can be 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2.0 nm. Of course, in other embodiments of the present invention, the thickness of the front tunneling layer 20 can also be selected according to actual needs.
[0049] The specific structures of the N-type high-efficiency batteries according to the seven embodiments of the present utility model are described below.
[0050] Embodiment 1:
[0051] like Figure 2As shown, the N-type high-efficiency cell of this embodiment includes an N-type silicon substrate 10, a front tunneling layer 20, a first doped crystalline silicon layer 30, a second doped crystalline silicon layer 40, a third doped crystalline silicon layer 50 and a front anti-reflection functional layer 90 sequentially arranged on the front of the N-type silicon substrate 10, and a back tunneling layer 100, a back polycrystalline silicon layer 200 and a back anti-reflection functional layer 300 sequentially arranged on the back of the N-type silicon substrate 10. Electrodes 400 are arranged on the front and back of the N-type high-efficiency cell, and the electrode 400 located on the front is arranged through the front anti-reflection functional layer 90, and the electrode 400 located on the back is arranged through the back anti-reflection functional layer 300.
[0052] The first doped crystalline silicon layer 30, the second doped crystalline silicon layer 40, and the third doped crystalline silicon layer 50 are all microcrystalline silicon layers, and the doping concentrations of the first doped crystalline silicon layer 30 and the third doped crystalline silicon layer 50 are greater than the doping concentration of the second doped crystalline silicon layer 40. The front tunneling layer 20 and the back tunneling layer 100 are silicon oxide layers, and the front anti-reflection functional layer 90 is a silicon nitride layer.
[0053] The N-type high-efficiency battery of the first embodiment can ensure the thickness and doping concentration of doped crystalline silicon, reduce the recombination current, and ensure the potential barrier, reduce light parasitic absorption, and better balance the light absorption and passivation effects of the N-type high-efficiency battery. At the same time, the process steps of the N-type high-efficiency battery of the first embodiment are relatively few, and the process cost is lower.
[0054] It should be noted that, in the case of completely identical structures, in the N-type high-efficiency battery of the first embodiment, the doping concentrations of the first doped crystalline silicon layer 30 and the third doped crystalline silicon layer 50 may also be less than the doping concentration of the second doped crystalline silicon layer 40. The two structures of the N-type high-efficiency batteries have the same advantages.
[0055] Embodiment 2:
[0056] like Figure 3 As shown, the N-type high-efficiency cell of this embodiment includes an N-type silicon substrate 10, a boron diffusion layer 60, a front tunneling layer 20, a first doped crystalline silicon layer 30, a second doped crystalline silicon layer 40, a third doped crystalline silicon layer 50, and a front anti-reflection functional layer 90 sequentially arranged on the front side of the N-type silicon substrate 10, and a back tunneling layer 100, a back polycrystalline silicon layer 200, and a back anti-reflection functional layer 300 sequentially arranged on the back side of the N-type silicon substrate 10. Electrodes 400 are arranged on both the front and back sides of the N-type high-efficiency cell, the electrode 400 located on the front side is arranged through the front anti-reflection functional layer 90, and the electrode 400 located on the back side is arranged through the back anti-reflection functional layer 300.
[0057] The first doped crystalline silicon layer 30, the second doped crystalline silicon layer 40, and the third doped crystalline silicon layer 50 are all microcrystalline silicon layers, and the doping concentrations of the first doped crystalline silicon layer 30 and the third doped crystalline silicon layer 50 are greater than the doping concentration of the second doped crystalline silicon layer 40. The front tunneling layer 20 and the back tunneling layer 100 are silicon oxide layers, and the front anti-reflection functional layer 90 is a silicon nitride layer.
[0058] The N-type high-efficiency battery of the second embodiment is provided with a boron diffusion layer 60 on the basis of the first embodiment, which can improve the passivation effect of the front side of the N-type high-efficiency battery.
[0059] It should be noted that, in the case of completely identical structures, in the N-type high-efficiency battery of the first embodiment, the doping concentrations of the first doped crystalline silicon layer 30 and the third doped crystalline silicon layer 50 may also be less than the doping concentration of the second doped crystalline silicon layer 40. The two structures of the N-type high-efficiency batteries have the same advantages.
[0060] Embodiment three:
[0061] The structure of the N-type high-efficiency battery of this embodiment is basically similar to that of the N-type high-efficiency battery of the second embodiment, except that the first doped crystalline silicon layer 30 , the second doped crystalline silicon layer 40 and the third doped crystalline silicon layer 50 are all nanocrystalline silicon layers.
[0062] The N-type high-efficiency battery of the third embodiment uses a nanocrystalline silicon layer as the doped crystalline silicon layer on the basis of the second embodiment. The nanocrystalline silicon has smaller grains and better passivation effect.
[0063] It should be noted that, in the case of completely identical structures, in the N-type high-efficiency battery of the third embodiment, the doping concentrations of the first doped crystalline silicon layer 30 and the third doped crystalline silicon layer 50 may also be less than the doping concentration of the second doped crystalline silicon layer 40. The two structures of the N-type high-efficiency batteries have the same advantages.
[0064] Embodiment 4:
[0065] The structure of the N-type high-efficiency battery of this embodiment is basically similar to that of the N-type high-efficiency battery of the second embodiment, except that the front tunneling layer 20 includes at least one of silicon carbide, silicon oxycarbide, silicon nitride and aluminum oxide.
[0066] The N-type high-efficiency battery of Example 4 replaces the material of the front tunneling layer 20 on the basis of Example 2. The introduction of carbon elements can make the film structure denser and effectively suppress film explosion. During annealing, the introduction of carbon elements can effectively prevent excessive diffusion of phosphorus into the silicon substrate.
[0067] It should be noted that, in the case of completely identical structures, in the N-type high-efficiency battery of the third embodiment, the doping concentrations of the first doped crystalline silicon layer 30 and the third doped crystalline silicon layer 50 may also be less than the doping concentration of the second doped crystalline silicon layer 40. The two structures of the N-type high-efficiency batteries have the same advantages.
[0068] Embodiment five:
[0069] like Figure 4 As shown, the structure of the N-type high-efficiency battery in this embodiment is basically similar to that of the N-type high-efficiency battery in Embodiment 1, except that the N-type high-efficiency battery further includes a front polysilicon layer 70 disposed between the front tunneling layer 20 and the first doped crystalline silicon layer 30.
[0070] The N-type high-efficiency battery of the fourth embodiment adds a front polysilicon layer 70 on the basis of the second embodiment. The polysilicon structure has a higher crystallization rate and smaller parasitic absorption, which can make the light absorption function of the N-type high-efficiency battery better.
[0071] It should be noted that, in the case of completely identical structures, in the N-type high-efficiency battery of the fifth embodiment, the doping concentrations of the first doped crystalline silicon layer 30 and the third doped crystalline silicon layer 50 may also be less than the doping concentration of the second doped crystalline silicon layer 4032. The two structures of the N-type high-efficiency batteries have the same advantages.
[0072] Embodiment six:
[0073] like Figure 5 As shown, the structure of the N-type high-efficiency battery in this embodiment is basically similar to that of the N-type high-efficiency battery in Embodiment 5, except that the N-type high-efficiency battery further includes a front silicon oxide layer 80 disposed between the first doped crystalline silicon layer 30 and the front polysilicon layer 70 .
[0074] The N-type high-efficiency battery of the sixth embodiment adds a front silicon oxide layer 80 on the basis of the fifth embodiment. The added front silicon oxide layer 80 can suppress the excessive diffusion of phosphorus during annealing.
[0075] It should be noted that, in the case of completely identical structures, in the N-type high-efficiency battery of the fifth embodiment, the doping concentrations of the first doped crystalline silicon layer 30 and the third doped crystalline silicon layer 50 may also be less than the doping concentration of the second doped crystalline silicon layer 40. The two structures of the N-type high-efficiency batteries have the same advantages.
[0076] Embodiment seven:
[0077] The structure of the N-type high-efficiency battery of this embodiment is basically similar to that of the N-type high-efficiency battery of Example 2, except that the back anti-reflection functional layer 300 and the front anti-reflection functional layer 90 are TCO layers. Based on the conductive properties of the TCO layer, the screen end of the printing process can use a relatively low-temperature silver paste sintering technology, thereby avoiding contact between the gate line of the electrode 400 and the crystalline silicon, effectively reducing the contact resistance; and relatively low-temperature sintering is beneficial to inhibiting diffusion escape and improving the passivation of crystalline silicon.
[0078] It should be noted that, in the case of completely identical structures, in the N-type high-efficiency battery of Example 6, the doping concentrations of the first doped crystalline silicon layer 30 and the third doped crystalline silicon layer 50 may also be less than the doping concentration of the second doped crystalline silicon layer 40. The two structures of the N-type high-efficiency batteries have the same advantages.
[0079] The present utility model also discloses a battery assembly, including any one of the N-type high-efficiency batteries described above. Since the battery assembly disclosed in the present utility model is composed of the N-type high-efficiency batteries described above, the battery assembly of the present utility model has the advantages of low parasitic absorption and low resistivity, has good overall performance, is conducive to extending the service life, and enhances the market competitiveness of the product. The battery assembly disclosed in the present utility model may include only one N-type high-efficiency battery, or may include multiple N-type high-efficiency batteries. When the battery assembly disclosed in the present utility model includes multiple N-type high-efficiency batteries, the structures of the multiple N-type high-efficiency batteries may be completely the same and any one of the above-mentioned embodiments 1 to 7. The structures of the multiple N-type high-efficiency batteries may also be different. The structure of each N-type high-efficiency battery may be selected from any one of embodiments 1 to 7, as long as it can meet the actual needs.
[0080] It should be noted here that the battery assembly also includes a packaging structure for encapsulating the battery and a lead-out structure that can realize the lead-out of the N-type high-efficiency battery. The specific forms of the packaging structure and the lead-out structure can be selected according to the existing technology, and there is no need to describe the specific forms of the packaging structure and the lead-out structure here.
[0081] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.
[0082] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the implementation methods of the present invention. For those skilled in the art, various obvious changes, readjustments and substitutions can be made without departing from the scope of protection of the present invention. It is not necessary and impossible to list all implementation methods here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention shall be included in the scope of protection of the claims of the present invention.
Claims
1. An N-type high-efficiency battery, characterized in that: The invention comprises an N-type silicon substrate (10), and a front tunneling layer (20), a doped crystalline silicon layer and a front anti-reflection functional layer (90) sequentially arranged on the front side of the N-type silicon substrate (10), wherein the doped crystalline silicon layer at least comprises a first doped crystalline silicon layer (30), a second doped crystalline silicon layer (40) and a third doped crystalline silicon layer (50) sequentially arranged in a front direction away from the N-type silicon substrate (10); the doping concentration of the first doped crystalline silicon layer (30) is greater than the doping concentration of the N-type silicon substrate (10); wherein: The doping concentrations of the first doped crystalline silicon layer (30) and the third doped crystalline silicon layer (50) are both greater than the doping concentration of the second doped crystalline silicon layer (40); or: The doping concentrations of the first doped crystalline silicon layer (30) and the third doped crystalline silicon layer (50) are both lower than the doping concentration of the second doped crystalline silicon layer (40).
2. The N-type high-efficiency battery according to claim 1, characterized in that: The doping concentrations of the first doped crystalline silicon layer (30) and the third doped crystalline silicon layer (50) are both greater than the doping concentration of the second doped crystalline silicon layer (40).
3. The N-type high-efficiency battery according to claim 1, characterized in that: The doping concentrations of the first doped crystalline silicon layer (30) and the third doped crystalline silicon layer (50) are both lower than the doping concentration of the second doped crystalline silicon layer (40).
4. The N-type high-efficiency battery according to claim 1, characterized in that: The N-type high-efficiency battery further comprises a boron diffusion layer (60), wherein the boron diffusion layer (60) is arranged between the front surface of the N-type silicon substrate (10) and the front tunneling layer (20).
5. The N-type high-efficiency battery according to claim 1, characterized in that: The N-type high-efficiency battery further comprises at least one front polysilicon layer (70), wherein the front polysilicon layer (70) is arranged between the front tunneling layer (20) and the first doped crystalline silicon layer (30).
6. The N-type high-efficiency battery according to claim 5, characterized in that: The N-type high-efficiency battery further comprises a front silicon oxide layer (80), wherein the front silicon oxide layer (80) is arranged between the front polysilicon layer (70) and the first doped crystalline silicon layer (30), and between two adjacent front polysilicon layers (70) or between two adjacent doped crystalline silicon layers.
7. The N-type high-efficiency battery according to any one of claims 1 to 6, characterized in that: The first doped crystalline silicon layer (30), the second doped crystalline silicon layer (40) and the third doped crystalline silicon layer (50) are all microcrystalline silicon layers; or: The first doped crystalline silicon layer (30), the second doped crystalline silicon layer (40) and the third doped crystalline silicon layer (50) are all nanocrystalline silicon layers.
8. The N-type high-efficiency battery according to any one of claims 1 to 6, characterized in that: The front anti-reflection functional layer (90) comprises a silicon nitride layer or a TCO layer; and / or: The front tunneling layer (20) is one of silicon oxide, silicon carbide, silicon oxycarbide, silicon nitride and aluminum oxide.
9. The N-type high-efficiency battery according to any one of claims 1 to 6, characterized in that: The thickness of the first doped crystalline silicon layer (30), the second doped crystalline silicon layer (40) and the third doped crystalline silicon layer (50) is 10 nm. ～ 60nm; The thickness of the front tunneling layer (20) is 1 nm. ～ 2nm.
10. A battery assembly, characterized in that: It comprises an N-type high-efficiency battery as described in any one of claims 1 to 9.