Verilog code generation method for Ethernet cyclic redundancy check (CRC) 32 calculation and related equipment

Abstract

The invention discloses a method for generating a verilog code calculated by an Ethernet cyclic redundancy check (CRC) 32 and related equipment, and the method for generating the verilog code calculated by the Ethernet CRC 32 comprises the following steps: obtaining a target data bit width calculated by the Ethernet CRC 32; according to the target data bit width, a data bit width variable in a preset shell script is changed to obtain a target shell script, and the preset shell script comprises an execution code used for generating the verilog code; and executing the target shell script so as to generate a verilog code calculated by the Ethernet CRC32 corresponding to the target data bit width through the execution code. Through the method, the technical scheme of the invention can automatically generate the verilog code calculated by the Ethernet CRC32 through the shell script, so that the generation efficiency and convenience of the verilog code are improved.

Description

Technical Field

[0001] The present application relates to the technical field of Ethernet data processing, and in particular to a Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation and related equipment. Background Art

[0002] Cyclic redundancy check (CRC) is a hash function that generates a short fixed-bit check code based on data such as online data packets or computer files. It is mainly used to detect or verify errors that may occur after data transmission or storage. The generated number is calculated and appended to the data before transmission or storage, and then the receiver checks to determine whether the data has changed.

[0003] Generally speaking, the value of the cyclic redundancy check is a 32-bit integer. This function is widely used because it is easy to use with binary computer hardware, easy to perform mathematical analysis, and particularly good at detecting errors caused by transmission channel interference. For serial execution languages ​​such as C, CRC32 calculation is relatively simple, but for parallel execution languages ​​such as Verilog, CRC calculation will greatly increase the workload of writing Verilog code as the data bit width increases.

[0004] Therefore, for small bit width data, the Verilog code can be written by manually calculating CRC, but when the data bit width is relatively large, such as 128-bit data, the workload of manually calculating CRC32 and writing Verilog code will be difficult to complete. Summary of the invention

[0005] To solve the above technical problems, the embodiments of the present application provide a Verilog code generation method and related equipment for Ethernet cyclic redundancy check CRC32 calculation.

[0006] According to one aspect of an embodiment of the present application, a Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation is provided, comprising: obtaining a target data bit width for Ethernet CRC32 calculation; changing a data bit width variable in a preset shell script according to the target data bit width to obtain a target shell script, wherein the preset shell script includes an execution code for generating the Verilog code; executing the target shell script to generate a Verilog code for Ethernet CRC32 corresponding to the target data bit width through the execution code.

[0007] In some embodiments of the present application, based on the above technical solution, before changing the data width variable in the preset shell script according to the target data width to obtain the target shell script, the method also includes: writing the module definition in the execution code into the initial shell script, the module definition is used to define multiple associated parameters of the Ethernet CRC32 calculation, and the associated parameters include the data width variable; according to the multiple associated parameters and the calculation rules corresponding to the Ethernet CRC32 calculation, obtaining the verification expression of the Ethernet CRC32 calculation, and writing the verification expression into a preset first loop statement, and writing the first loop statement into the initial shell script; writing the module end statement in the execution code into the initial shell script to obtain the preset shell script, and the module end statement is used to end the generation of the Verilog code.

[0008] In some embodiments of the present application, based on the above technical solution, before writing the module definition in the execution code into the initial shell script, it also includes: writing the module definition information required to generate the Verilog code into a preset Verilog file through a preset command for information input in the initial shell script, and obtaining the module definition in the execution code, so that the associated parameters are defined according to the module definition information in the module definition.

[0009] In some embodiments of the present application, based on the above technical solution, the verification expression of the Ethernet CRC32 calculation is obtained according to the multiple associated parameters and the calculation rules corresponding to the Ethernet CRC32 calculation, including: obtaining the assignment formula corresponding to the Ethernet CRC32 calculation according to the multiple associated parameters and the calculation rules corresponding to the Ethernet CRC32 calculation; setting a second loop statement according to the data bit width variable, and writing the assignment formula into the second loop statement, and writing a preset data update formula into the second loop statement to obtain a target second loop statement, the data update formula is used to perform an assignment update according to the calculation result of the assignment formula, so as to execute the assignment formula according to the content after the assignment update in the next loop; according to the target second loop statement, obtaining the verification expression of the Ethernet CRC32 calculation.

[0010] In some embodiments of the present application, based on the above technical solution, the assignment formula corresponding to the Ethernet CRC32 calculation is obtained according to the multiple associated parameters and the calculation rules corresponding to the Ethernet CRC32 calculation, including: determining the polynomial of the Ethernet CRC32 calculation and the set data bit width corresponding to the data bit width variable according to the associated parameters; and performing XOR calculation on the bit width of the set data bit width and each item in the polynomial to obtain the assignment formula.

[0011] In some embodiments of the present application, based on the above technical solution, the verification expression of the Ethernet CRC32 calculation is obtained according to the target second loop statement, including: determining the verification expressions of different bit widths in the data bit width variable according to the calculation result of executing the Ethernet CRC32 calculation according to the target second loop statement; according to the verification expressions of different bit widths, simplifying the repeated calculation items in the verification expressions of different bit widths by using a preset simplification command to obtain a simplified verification expression of the Ethernet CRC32 calculation.

[0012] In some embodiments of the present application, based on the above technical solution, the check expressions of different bit widths are simplified by a preset simplification command for repeated calculation items in the check expressions of different bit widths to obtain a simplified check expression for the Ethernet CRC32 calculation, including: obtaining the number of repeated calculation items in the check expressions of different bit widths; if the remainder after dividing the number of repeated calculation items by 2 is not equal to 0, simplifying the check expressions of different bit widths by a preset simplification command to obtain a simplified check expression for the Ethernet CRC32 calculation.

[0013] According to one aspect of an embodiment of the present application, a Verilog code generation device for Ethernet cyclic redundancy check CRC32 calculation is provided, including: an acquisition module, used to obtain a target data bit width for Ethernet CRC32 calculation; a loading module, used to change a data bit width variable in a preset shell script according to the target data bit width to obtain a target shell script, wherein the preset shell script includes an execution code for generating the Verilog code; an execution module, used to execute the target shell script to generate a Verilog code of Ethernet CRC32 corresponding to the target data bit width through the execution code.

[0014] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor of a computer, the computer executes the Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation as described in the above embodiment.

[0015] According to one aspect of an embodiment of the present application, an electronic device is provided, comprising: one or more processors; a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the electronic device implements the Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation as described in the above embodiments.

[0016] In the technical solution of the embodiment of the present application, the above invention content can at least bring the following beneficial effects: The technical solution of the present application is provided with an execution code capable of generating Verilog codes according to different data bit widths in a preset shell script. By executing the preset shell script, Verilog codes for Ethernet CRC32 calculations of different data bit widths can be generated. When it is necessary to generate the Verilog code for Ethernet CRC32 calculations corresponding to the target data bit width, the data bit width variable in the preset shell script is changed by the target data bit width to obtain the target shell script. The corresponding required Verilog code can be generated by simply executing the target shell script, thereby realizing automatic generation of the Verilog code for Ethernet CRC32 calculations through the shell script, without the need to manually calculate the CRC to complete the Verilog code writing, thereby improving the generation efficiency and convenience of the Verilog code. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 The present invention is a flowchart of a Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation shown in an exemplary embodiment of the present application.

[0018] Figure 2 The present invention is a flowchart of a Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation shown in another exemplary embodiment of the present invention.

[0019] Figure 3 A flowchart of obtaining a check expression for Ethernet CRC32 calculation is shown in an exemplary embodiment of the present application.

[0020] Figure 4 This is a schematic diagram of the structure of executing code in the second loop statement shown in an exemplary embodiment of the present application.

[0021] Figure 5 This is a flow chart of an exemplary embodiment of the present application showing an assignment formula for obtaining Ethernet CRC32 calculation.

[0022] Figure 6 A flowchart of a simplified verification expression is shown in an exemplary embodiment of the present application.

[0023] Figure 7 A flowchart of a simplified verification expression is shown as another exemplary embodiment of the present application.

[0024] Figure 8 The block diagram of a Verilog code generation device for Ethernet cyclic redundancy check CRC32 calculation according to an embodiment of the present application is shown as an exemplary embodiment of the present application.

[0025] Fig. 9 The present invention is a schematic diagram of the structure of a computer system suitable for implementing an electronic device of an embodiment of the present invention, shown as an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose and implementation method of the present application clearer, the exemplary implementation method of the present application will be clearly and completely described below in conjunction with the drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0027] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their common and usual meanings.

[0028] The terms "first", "second", "third", etc. in the specification and claims of this application and the above drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise noted. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances.

[0029] The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to all the components expressly listed but may include other components not expressly listed or inherent to such product or device.

[0030] It should be noted that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0031] Figure 1 The following is a flowchart of a Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation shown in an exemplary embodiment of the present application. Figure 1 As shown, the present application discloses a Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation, which may at least include the following execution steps: S100, obtaining the target data bit width of Ethernet CRC32 calculation; S101, changing a data bit width variable in a preset shell script according to a target data bit width to obtain a target shell script, wherein the preset shell script includes an execution code for generating a Verilog code; S102, executing the target shell script to generate the Verilog code of Ethernet CRC32 corresponding to the target data bit width by executing the code.

[0032] Specifically, the target data bit width of the Ethernet CRC32 calculation can be determined according to the specific data processing content. Among them, the determination of the bit width data can comprehensively consider multiple factors, including technical specifications, hardware detection tools, application scenarios and requirements, etc. For example, some third-party hardware detection tools (such as CPU-Z, GPU-Z, etc.) can read detailed information of computer hardware, including bit width data.

[0033] It should be noted that for most computer hardware, including processors, memory, graphics cards, etc., you can find out their bit width data by looking at their technical specifications. Therefore, I will not go into details here.

[0034] Based on the target data bit width obtained above, the data bit width variable in the preset shell script is changed according to the target data bit width to obtain the target shell script. Wherein, the preset shell script includes an execution code for generating a Verilog code.

[0035] It should also be noted that Verilog code can be a hardware description language, which can be a language that describes the structure and behavior of digital system hardware in text form. Verilog code can be used to represent logic circuit diagrams, logic expressions, and the logic functions performed by digital logic systems. By obtaining the Verilog code after the machine is running, relevant fault simulation and timing analysis can be implemented.

[0036] In detail, in the technical solution of the present application, an input interface for setting the data bit width is provided in a pre-set shell script. When the shell script obtains the corresponding data bit width, that is, after obtaining the target data bit width, the preset shell script can adaptively set the execution code for generating the Verilog code according to the target data bit width, so that in the present application, the data bit width variable in the preset shell script is changed according to the target data bit width to obtain the target shell script, and the corresponding Ethernet cyclic redundancy check CRC32 calculation Verilog code can be generated according to the target data bit width.

[0037] Based on this, when executing the target shell script, the Verilog code for calculating Ethernet CRC32 of various bit widths is automatically generated through the target shell script.

[0038] It should be noted that a Shell script is a script program written for a Shell to automatically execute commands on an operating system. Shell is a command line interpreter that allows users to interact with the operating system.

[0039] At the same time, since Shell scripts are important tools for Linux and UNIX system administrators and system developers, Shell scripts can be executed on any Linux system without installing corresponding execution software or various libraries in advance. Therefore, this application uses Shell scripts to generate Verilog code for calculating Ethernet CRC32 checksum, which can make the corresponding Shell scripts easy to transplant and use.

[0040] In the above implementation, an execution code capable of generating Verilog codes according to different data bit widths is provided in the preset shell script. By executing the preset shell script, the Verilog codes for Ethernet CRC32 calculations of different data bit widths can be generated. When it is necessary to generate the Verilog code for Ethernet CRC32 calculations corresponding to the target data bit width, the data bit width variable in the preset shell script is changed by the target data bit width to obtain the target shell script. The corresponding required Verilog code can be generated by executing the target shell script, thereby realizing automatic generation of the Verilog code for Ethernet CRC32 calculations through the shell script, without the need to manually calculate the CRC to complete the Verilog code writing, thereby improving the generation efficiency and convenience of the Verilog code.

[0041] Based on the above embodiments, Figure 2 This is a flowchart of a Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation shown in another exemplary embodiment of the present application. Figure 2 As shown, in some embodiments of the present application, before changing the data bit width variable in the preset shell script according to the target data bit width to obtain the target shell script, the corresponding method may further include at least the following execution steps for setting the content of the target shell script: S200, writing the module definition in the execution code into the initial shell script, where the module definition is used to define multiple associated parameters for Ethernet CRC32 calculation, and the associated parameters include a data bit width variable; S201, according to a plurality of associated parameters and a calculation rule corresponding to the Ethernet CRC32 calculation, obtain a check expression for the Ethernet CRC32 calculation, write the check expression into a preset first loop statement, and write the first loop statement into an initial shell script; S202, writing the module end statement in the execution code into the initial shell script to obtain a preset shell script, wherein the module end statement is used to end the generation of the Verilog code.

[0042] In some embodiments of the present application, before writing the module definition in the execution code into the initial shell script, at least the following execution steps may be included: The module definition information required for generating the Verilog code is written into a preset Verilog file through a preset command for information input in an initial shell script, and the module definition in the execution code is obtained so that the associated parameters are defined according to the module definition information in the module definition.

[0043] Specifically, firstly, the module definition information required by the Verilog code is written into a blank Verilog file through the preset command of the shell script, wherein the preset command may be the echo command, which is a command line tool existing in most Unix / Linux systems, and is used to display a line of text or a string in the terminal (command line interface). The echo command is used in script programming and command line operations to output information to the user in a preset fixed format or pass the information to other commands.

[0044] For example, this application will generate the module definition information required by the Verilog code and write it into a blank Verilog file through the echo command of the shell script. Please refer to the following content: echo "function crc32_gen(input [31:0]ct, input [${data_width}-1:0]di);">crc32_new.v echo "reg [31:0] nt;">>crc32_new.v echo "begin" >> crc32_new.v By entering the above content through the echo command, the module definition of automatically generating Verilog code in Ethernet CRC32 calculation can be completed.

[0045] It should be noted that the initial shell script may include multiple blank files, which can be used to store template definitions, execution codes, and output codes. Based on this, the present application writes the module definition in the execution code into the blank file in the initial shell script through echo, so that the shell script can directly call and use the content of the template definition during the execution of the execution code, so as to define multiple associated parameters of Ethernet CRC32 calculation according to the called module definition, wherein the associated parameters include the data bit width variable shown in the above embodiment.

[0046] Exemplarily, the multiple associated parameters for Ethernet CRC32 calculation defined by the module definition in this application may include, but are not limited to, the following: In the technical solution of Ethernet CRC32 calculation of the present application, the polynomial corresponding to Ethernet CRC32 calculation can be x32+x26+x23+x22+x16+x12+x9+x10+x8+x7+x5+x4+x2+x1+1. And the corresponding data bit width variable is 16 as an example for explanation.

[0047] In the shell script, the associated parameters defined according to the module definition can be ct0, ct1, ct2...ct31, where ct0, ct1, ct2...ct31 correspond to x1, x2...x32 in the crc32 polynomial; the associated parameters defined according to the module definition can also be nt[31:0], where nt[31:0] corresponds to the 32-bit wide crc32 calculation result output of verdilog; the associated parameters defined according to the module definition can also be di0, di1...di15, where di0, di1...di15 correspond to the data data that needs to be verified in verilog; the associated parameters defined according to the module definition can also be nt_reg0, nt_reg1...nt_reg31, where the group of signals nt_reg0, nt_reg1...nt_reg31 are used as intermediate variables to store the values ​​calculated by crc32.

[0048] By way of example, in the above steps, according to multiple associated parameters and the calculation rules corresponding to the Ethernet CRC32 calculation, a check expression for the Ethernet CRC32 calculation is obtained. Specifically, the following contents may be included: According to the polynomial corresponding to the above-mentioned Ethernet CRC32 calculation, and according to the multiple associated parameters defined by the module, when calculating CRC32, each data bit width is calculated separately, and in the present application, it can be calculated according to the high-bit priority principle corresponding to the data bit width, and calculated one by one in order from high to low. Of course, it can also be calculated according to other orders, which is only used as an example here.

[0049] In the technical solution of the present application, the calculation formula corresponding to the calculation rule corresponding to a data bit width can be written into a shell script, and after obtaining the calculation result corresponding to a data bit width, the corresponding calculation formula is repeatedly executed by setting a loop statement to calculate the remaining other data bit widths. Thus, the Verilog code for CRC32 calculation is generated according to the output result.

[0050] For example, after generating the Verilog code, the present application terminates the execution of the execution code used to generate the Verilog code through the end statement in the shell script, and the specific end statement can refer to the following content: echo "crc32_gen=nt_r;">>crc32_new.v echo "end;" >>crc32_new.v echo "endfunction;">>crc32_new.v From the above content, it can be seen that in the technical solution of this application, taking the data bit width of 16 bits as an example, a Verilog code for calculating the Ethernet CRC32 data bit width of 16 bits can be generated by simply executing the corresponding shell script. At the same time, the parameter data bit width variable in the shell script can be changed to generate Verilog codes with other data bit widths.

[0051] Through the above implementation, the present application obtains a calculation formula represented by code based on the calculation rules of CRC32 calculation with the associated parameters defined by the module, and writes the calculation formula into a preset loop statement so that the shell script can generate the Verilog code corresponding to each data bit width when calculating CRC32.

[0052] Based on the above embodiments, Figure 3 The flowchart of the verification expression for obtaining Ethernet CRC32 calculation is shown in the exemplary embodiment of the present application. Figure 3 As shown, in some embodiments of the present application, according to multiple associated parameters and the calculation rules corresponding to the Ethernet CRC32 calculation, the check expression of the Ethernet CRC32 calculation is obtained, which may at least include the following execution steps: S300, obtaining a value assignment formula corresponding to Ethernet CRC32 calculation according to a plurality of associated parameters and a calculation rule corresponding to Ethernet CRC32 calculation; S301, setting a second loop statement according to the data bit width variable, and writing an assignment formula into the second loop statement, and writing a preset data update formula into the second loop statement to obtain a target second loop statement, wherein the data update formula is used to perform an assignment update according to a calculation result of the assignment formula, so that the assignment formula is executed according to the content after the assignment update in the next loop; S302. Obtain a check expression for Ethernet CRC32 calculation according to the target second loop statement.

[0053] Specifically, the calculation rules corresponding to the Ethernet CRC32 calculation correspond to the polynomial content exemplified in the above embodiment, and the assignment formula is generated by combining the associated parameters defined by the module with the polynomial, thereby realizing the execution code conversion of the calculation rules.

[0054] It should be noted that Figure 4 FIG. 1 is a schematic diagram of the structure of the execution code in the second loop statement shown in the exemplary embodiment of the present application. Figure 4As shown, the execution code corresponding to the assignment formula includes multiple assignment calculation formulas 401, and the execution code corresponding to the data update formula also includes multiple update calculation formulas 402, and the assignment formula is used for Ethernet CRC32 calculation of a data bit width. Taking the 16 data bit widths in the above example as an example, the 16 data bit widths need to be calculated one by one through the assignment formula. For example, through the setting of the second loop statement, the assignment formula is executed cyclically, and after each execution of the assignment formula, the calculation result of the assignment formula is updated through the data update formula, so that the assignment formula is executed according to the content after the assignment update in the next loop, thereby completing the Ethernet CRC32 calculation of 16 data bit widths.

[0055] Based on the above embodiments, Figure 5 FIG. 1 is a flow chart of an exemplary embodiment of the present application showing a formula for calculating the value of Ethernet CRC32. Figure 5 As shown, in some embodiments of the present application, according to the above embodiments, based on multiple associated parameters and the calculation rules corresponding to the Ethernet CRC32 calculation, the assignment formula corresponding to the Ethernet CRC32 calculation is obtained, which may at least include the following execution steps: S500, determining the set data bit width corresponding to the polynomial calculated by Ethernet CRC32 and the data bit width variable according to the associated parameters; S501, performing XOR calculation on the bit width of the set data bit width and each term in the polynomial respectively to obtain an assignment formula.

[0056] Specifically, based on the CRC32 calculation rules, the calculation of each bit of CRC32 should be the result obtained by XORing the previous bit, such as the example in the above embodiment, which is calculated with high-order priority. First, the highest bit of the input data, i.e., di15, is calculated according to the CRC32 polynomial, i.e., di15 and ct0~ct31 are XORed, thereby obtaining the following exemplary XOR calculation formula: nt_reg[0]=ct

[31] ^di

[15] nt_reg[1]=ct[0]^ct

[31] ^di

[15] nt_reg[2]=ct[1]^ ct

[31] ^di

[15] … nt_reg

[31] =ct

[30] A set of XOR calculation formulas in the above example is written into the initial shell script as an assignment formula, and is packaged through the second loop statement recorded in the above embodiment to obtain the CRC check formula corresponding to each data bit width.

[0057] Based on the above embodiments, Figure 6FIG. 1 is a flowchart of a simplified verification expression shown in an exemplary embodiment of the present application. Figure 6 As shown, in some embodiments of the present application, for the above embodiment, according to the target second loop statement, obtaining the check expression of Ethernet CRC32 calculation may at least include the following execution steps: S600, determining the check expressions of different bit widths in the data bit width variable according to the calculation result of executing the Ethernet CRC32 calculation according to the target second loop statement; S601. According to check expressions of different bit widths, repeated calculation items in the check expressions of different bit widths are simplified by a preset simplification command to obtain a simplified check expression for Ethernet CRC32 calculation.

[0058] It should be noted that when the shell script executes the second loop statement, the polynomial corresponding to nt_reg is the Verilog code for CRC32 calculation. However, at the same time, due to the large number of bits involved in the XOR, with each additional round of calculation, the number of ct and di in the expression corresponding to nt_reg will increase exponentially. The wider the di bit is, the more rounds of formula derivation are required, and the data of ct and di will become extremely large. Therefore, the technical solution of the present application also simplifies the expression of nt_reg by setting the execution steps as in this embodiment.

[0059] For example, take nt_reg_1[1] and nt_reg_1[0] as an example. After the first bit of the input data di is subjected to CRC32 calculation, the expressions of nt_reg_1[1] and nt_reg_1[0] are obtained as follows: nt_reg_1[0]=ct

[31] ^di

[15] nt_reg_1[1]=ct[0]^ct

[31] ^di

[15] When the second bit of the input data di is crc32-calculated, the expressions of nt_reg_1[1] and nt_reg_1[0] are obtained as follows: nt_reg_1[0]=ct

[30] ^di

[14] nt_reg_1[1]=ct

[30] ^ ct

[31] ^di

[15] ^di

[14] When all 16 bits of the input data di have completed the crc32 calculation, the expression of nt_reg_1[0] is obtained as follows: nt[0]=ct

[16] ^ct

[26] ^di

[10] ^ct

[25] ^ct

[31] ^di

[15] ^di[9]^ct

[22] ^ct

[31] ^di

[15] ^ct

[28] ^di

[12] ^di[6]^di[0] It can be seen that di

[15] participates in two XOR operations, so the corresponding polynomial can be simplified.

[0060] Based on this, an example is given to illustrate that the technical solution of the present application can obtain the number of corresponding parameters in the polynomial by inputting the corresponding query command.

[0061] For example, if you enter the command ct_cnt0=`echo ${nt_reg_1[n]} | grep -o `ct\[0\]` | wc -l`, you can get ct_cnt0=0, which means that the string expression of nt[0] does not contain ct0.

[0062] Similarly, the quantities of ct1-ct31 and di0-di15 in the formula can be calculated.

[0063] By using the number of ct1-ct31 and di0-di15 in the formula calculated by the above command, the calculation item of multiple XOR calculations of parameters in the XOR calculation expression corresponding to each bit is judged, so that it can be determined whether to simplify the corresponding XOR calculation expression according to the judgment result. In this way, the efficiency of generating the Verilog code for Ethernet CRC32 calculation corresponding to the target data bit width is improved to a certain extent.

[0064] Based on the above embodiments, Figure 7 FIG. 1 is a flowchart of another exemplary embodiment of the present application showing a simplified verification expression. Figure 7 As shown, in some embodiments of the present application, according to the check expressions of different bit widths, repeated calculation items in the check expressions of different bit widths are simplified by preset simplification commands to obtain a simplified check expression for Ethernet CRC32 calculation, which may at least include the following execution steps: S700, obtaining the number of repeated calculation items in the check expressions of different bit widths; S701: If the remainder after the number of repeated calculation items is divided by 2 is not equal to 0, simplify the check expressions of different bit widths by using a preset simplification command to obtain a simplified check expression for Ethernet CRC32 calculation.

[0065] Specifically, after calculating the number of ct1-ct31 and di0-di15 in the formula through the above embodiment, ct_cnt and di_cnt are divided by 2 to obtain the remainder. If the remainder obtained is 1, it is considered that the expression of nt_reg_1 should contain the corresponding ct and di. If the remainder obtained is 0, it is considered that the corresponding ct and di are not contained after simplification.

[0066] In the shell script, the method of calculating the remainder of ct_cnt and di_cnt is exemplarily described by the following execution code: ct0_odd=$(expr ${ct_cnt0} % 2) ct1_odd=$(expr ${ct_cnt1} % 2) … ct31_odd=$(expr ${ct_cnt6} % 2) The above method can be used to calculate the parity number of each bit of ct and di contained in the formula, so that the simplified formula can be obtained: if [ ${ct0_odd} -eq 1];then nt_r[n]=${nt_r[n]}^ct0 fi if [ ${ct1_odd} -eq 1];then nt_r[n]=${nt_r[n]}^ct1 fi … if [ ${ct31_odd} -eq 1];then nt_r[n]=${nt_r[n]}^ct31 fi if [ ${di0_odd} -eq 1];then nt_r[n]=${nt_r[n]}^di0 fi It should be noted that in the exemplary description of the execution code of this application, the meaning of each instruction and symbol can be explained by the default instructions and default symbols of the shell script language. Therefore, each instruction will not be described in detail, and the technical solution of this application will only be explained through part of the execution code.

[0067] Based on the simplified check expression of CRC32 calculation, write the simplified check expression into the first loop statement, and write the first loop statement into the corresponding Verilog file through the echo command. At this point, combined with the calculation process of the check expression, the target shell script for generating the execution code of the Verilog code is obtained.

[0068] Among them, after the simplified verification expression is written into the initial shell script, the content of the corresponding first loop statement in the target shell script is explained by the following exemplary code: for ((n=${data_width};n>=0;n--)) do echo "nt_r[${n}] = ${nt_r[n]};">>crc32_new.v done In order to more clearly disclose the Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation in this application, combined with the above embodiments, further comprehensive description is given, specifically as follows: First of all, it should be made clear that the Ethernet cyclic redundancy check CRC32 calculation of the present application is based on the polynomial disclosed in the above embodiment, and the polynomial is implemented through the assignment formula in the code.

[0069] Among them, the assignment formula is to calculate a data bit width. This application takes 16 data bit widths as an example for explanation. For all data bit widths, the updated data based on the last data bit width calculation result is calculated one by one through the second loop statement.

[0070] However, in the calculation process of the second loop statement, there will be repeated calculation content, so the content corresponding to the second loop statement is simplified to obtain the content corresponding to the first loop statement.

[0071] During use, the first loop statement is written into the initial shell script, and the target shell script is obtained according to the acquired target data bit width, so as to generate the Verilog code of Ethernet CRC32 calculation corresponding to the target data bit width by executing the code.

[0072] The following describes an apparatus embodiment of the present application, which can be used to execute the Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation in the above-mentioned embodiment of the present application. For details not disclosed in the apparatus embodiment of the present application, please refer to the embodiment of the Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation in the above-mentioned embodiment of the present application.

[0073] Figure 8 The block diagram of a Verilog code generation device for Ethernet cyclic redundancy check CRC32 calculation according to an embodiment of the present application is shown as an exemplary embodiment of the present application.

[0074] Reference Figure 8 As shown, according to an embodiment of the present application, a Verilog code generation device 800 for Ethernet cyclic redundancy check CRC32 calculation includes: an acquisition module 801, used to obtain a target data bit width for Ethernet CRC32 calculation; a loading module 802, used to change a data bit width variable in a preset shell script according to the target data bit width to obtain a target shell script, wherein the preset shell script includes an execution code for generating Verilog code; an execution module 803, used to execute the target shell script to generate a Verilog code for Ethernet CRC32 calculation corresponding to the target data bit width by executing the code.

[0075] In some embodiments of the present application, based on the aforementioned scheme, before changing the data bit width variable in the preset shell script according to the target data bit width to obtain the target shell script, the loading module 802 is further configured to: write the module definition in the execution code into the initial shell script, the module definition is used to define multiple associated parameters for Ethernet CRC32 calculation, and the associated parameters include the data bit width variable; obtain the verification expression of Ethernet CRC32 calculation according to the multiple associated parameters and the calculation rules corresponding to the Ethernet CRC32 calculation, and write the verification expression into the preset first loop statement, and write the first loop statement into the initial shell script; write the module end statement in the execution code into the initial shell script to obtain the preset shell script, and the module end statement is used to end the generation of the Verilog code.

[0076] In some embodiments of the present application, based on the aforementioned scheme, before writing the module definition in the execution code into the initial shell script, the loading module 802 is also configured to: write the module definition information required to generate the Verilog code into a preset Verilog file through the preset command for information input in the initial shell script, and obtain the module definition in the execution code, so that the associated parameters are defined according to the module definition information in the module definition.

[0077] In some embodiments of the present application, based on the aforementioned scheme, according to multiple associated parameters and the calculation rules corresponding to the Ethernet CRC32 calculation, a verification expression for the Ethernet CRC32 calculation is obtained, and the loading module 802 is also configured to: according to multiple associated parameters and the calculation rules corresponding to the Ethernet CRC32 calculation, obtain the assignment formula corresponding to the Ethernet CRC32 calculation; set a second loop statement according to the data bit width variable, and write the assignment formula into the second loop statement, and write a preset data update formula into the second loop statement to obtain a target second loop statement, the data update formula is used to perform an assignment update according to the calculation result of the assignment formula, so as to execute the assignment formula according to the content after the assignment update in the next loop; according to the target second loop statement, obtain the verification expression for the Ethernet CRC32 calculation.

[0078] In some embodiments of the present application, based on the aforementioned scheme, according to multiple associated parameters and the calculation rules corresponding to the Ethernet CRC32 calculation, the assignment formula corresponding to the Ethernet CRC32 calculation is obtained, and the loading module 802 is also configured to: determine the set data bit width corresponding to the polynomial and data bit width variable of the Ethernet CRC32 calculation according to the associated parameters; perform XOR calculation on the bit width of the set data bit width with each term in the polynomial to obtain the assignment formula.

[0079] In some embodiments of the present application, based on the aforementioned scheme, according to the target second loop statement, a check expression for Ethernet CRC32 calculation is obtained, and the loading module 802 is also configured to: determine the check expressions of different bit widths in the data bit width variable according to the calculation result of executing the Ethernet CRC32 calculation according to the target second loop statement; according to the check expressions of different bit widths, simplify the repeated calculation items in the check expressions of different bit widths through preset simplification commands to obtain a simplified check expression for Ethernet CRC32 calculation.

[0080] In some embodiments of the present application, based on the aforementioned scheme, according to check expressions of different bit widths, repeated calculation items in the check expressions of different bit widths are simplified by a preset simplification command to obtain a simplified check expression for Ethernet CRC32 calculation, and the loading module 802 is also configured to: obtain the number of repeated calculation items in the check expressions of different bit widths; if the remainder after dividing the number of repeated calculation items by 2 is not equal to 0, simplify the check expressions of different bit widths by a preset simplification command to obtain a simplified check expression for Ethernet CRC32 calculation.

[0081] It should be noted that the Verilog code generation device for Ethernet cyclic redundancy check CRC32 calculation provided in the above embodiment and the Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation provided in the above embodiment belong to the same concept, and the specific manner in which each module and unit performs the operation has been described in detail in the method embodiment and will not be repeated here.

[0082] An embodiment of the present application also provides an electronic device, including a processor and a memory, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation as described above is implemented.

[0083] Fig. 9 A schematic diagram of a computer system for implementing an electronic device of an embodiment of the present application, shown as an exemplary embodiment of the present application It should be noted that Fig. 9 The computer system 900 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0084] like Fig. 9 As shown, the computer system 900 includes a central processing unit (CPU) 901, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 902 or the program loaded from the storage part 908 to the random access memory (RAM) 903, such as executing the method described in the above embodiment. In the RAM 903, various programs and data required for system operation are also stored. The CPU 901, the ROM 902 and the RAM 903 are connected to each other through the bus 904. The input / output (I / O) interface 905 is also connected to the bus 904.

[0085] The following components are connected to the I / O interface 905: an input section 906 including a keyboard, a mouse, etc.; an output section 907 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 908 including a hard disk, etc.; and a communication section 909 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 909 performs communication processing via a network such as the Internet. A drive 910 is also connected to the I / O interface 905 as needed. A removable medium 911, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 910 as needed so that a computer program read therefrom is installed into the storage section 908 as needed.

[0086] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part 909, and / or installed from a removable medium 911. When the computer program is executed by a central processing unit (CPU) 901, various functions defined in the system of the present application are executed.

[0087] It should be noted that the computer-readable medium shown in the embodiment of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, device or device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier, which carries a computer-readable computer program. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which may send, propagate, or transmit programs for use by or in conjunction with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0088] The flowchart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. Wherein, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0089] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. The names of these units do not, in some cases, constitute limitations on the units themselves.

[0090] As another aspect, the present application also provides a computer-readable storage medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable storage medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation described in the above embodiment.

[0091] It should be noted that, although several modules or units of the equipment for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into being embodied by multiple modules or units.

[0092] Through the description of the above implementation methods, it is easy for those skilled in the art to understand that the example implementation methods described here can be implemented by software, or by combining software with necessary hardware. Therefore, the technical solution according to the implementation method of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to the implementation method of the present application.

[0093] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the embodiments disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not disclosed in the present application.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0095] For the convenience of explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are to better explain the principles and practical applications, so that those skilled in the art can better use the embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims

1. A Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation, characterized in that, include: Get the target data bit width for Ethernet CRC32 calculation; According to the target data bit width, a data bit width variable in a preset shell script is changed to obtain a target shell script, wherein the preset shell script includes an execution code for generating the Verilog code; The target shell script is executed to generate a Verilog code for Ethernet CRC32 calculation corresponding to the target data bit width through the execution code.

2. The Verilog code generation method of Ethernet cyclic redundancy check CRC32 according to claim 1 is characterized in that, Before changing the data bit width variable in the preset shell script according to the target data bit width to obtain the target shell script, the method further includes: Writing the module definition in the execution code into an initial shell script, wherein the module definition is used to define a plurality of associated parameters of the Ethernet CRC32 calculation, wherein the associated parameters include the data bit width variable; According to the plurality of associated parameters and the calculation rule corresponding to the Ethernet CRC32 calculation, a check expression for the Ethernet CRC32 calculation is obtained, and the check expression is written into a preset first loop statement, and the first loop statement is written into the initial shell script; The module end statement in the execution code is written into the initial shell script to obtain the preset shell script, wherein the module end statement is used to end the generation of the Verilog code.

3. The Verilog code generation method of Ethernet cyclic redundancy check CRC32 calculation according to claim 2, characterized in that, Before writing the module definition in the execution code into the initial shell script, it also includes: The module definition information required for generating the Verilog code is written into a preset Verilog file through a preset command for information input in the initial shell script, and the module definition in the execution code is obtained, so that the associated parameters are defined according to the module definition information in the module definition.

4. The Verilog code generation method of Ethernet cyclic redundancy check CRC32 calculation according to claim 2, characterized in that, The method of obtaining a check expression for the Ethernet CRC32 calculation based on the plurality of associated parameters and the calculation rule corresponding to the Ethernet CRC32 calculation comprises: According to the plurality of associated parameters and the calculation rule corresponding to the Ethernet CRC32 calculation, an assignment formula corresponding to the Ethernet CRC32 calculation is obtained; A second loop statement is set according to the data bit width variable, and the assignment formula is written into the second loop statement, and a preset data update formula is written into the second loop statement to obtain a target second loop statement, wherein the data update formula is used to perform assignment update according to the calculation result of the assignment formula, so as to execute the assignment formula according to the content after the assignment update in the next loop; According to the target second loop statement, a check expression for the Ethernet CRC32 calculation is obtained.

5. The Verilog code generation method of Ethernet cyclic redundancy check CRC32 according to claim 4 is characterized in that, The step of obtaining a value formula corresponding to the Ethernet CRC32 calculation based on the plurality of associated parameters and the calculation rule corresponding to the Ethernet CRC32 calculation comprises: Determine, according to the associated parameters, a polynomial for the Ethernet CRC32 calculation and a set data bit width corresponding to the data bit width variable; The bit width of the set data bit width is XOR-calculated with each term in the polynomial to obtain the assignment formula.

6. The Verilog code generation method of Ethernet cyclic redundancy check CRC32 calculation according to claim 4, characterized in that, The second loop statement according to the target obtains the check expression of the Ethernet CRC32 calculation, including: Determine the check expressions of different bit widths in the data bit width variable according to the calculation result of executing the Ethernet CRC32 calculation according to the target second loop statement; According to the check expressions of different bit widths, repeated calculation items in the check expressions of different bit widths are simplified by a preset simplification command to obtain a simplified check expression for the Ethernet CRC32 calculation.

7. The Verilog code generation method of Ethernet cyclic redundancy check CRC32 calculation according to claim 6 is characterized in that, The method of simplifying the repeated calculation items in the check expressions of different bit widths according to the check expressions of different bit widths by using a preset simplification command to obtain a simplified check expression of the Ethernet CRC32 calculation, includes: Obtain the number of repeated calculation items in the verification expressions of different bit widths; If the remainder after dividing the number of repeated calculation items by 2 is not equal to 0, the check expressions of different bit widths are simplified by a preset simplification command to obtain a simplified check expression for the Ethernet CRC32 calculation.

8. A Verilog code generation device for Ethernet cyclic redundancy check CRC32 calculation, characterized in that: include: An acquisition module is used to obtain the target data bit width for Ethernet CRC32 calculation; A loading module, used for changing a data width variable in a preset shell script according to the target data width to obtain a target shell script, wherein the preset shell script includes an execution code for generating the Verilog code; An execution module is used to execute the target shell script to generate a Verilog code for Ethernet CRC32 calculation corresponding to the target data bit width through the execution code.

9. A computer-readable storage medium, characterized in that: Computer-readable instructions are stored thereon, and when the computer-readable instructions are executed by a processor of a computer, the computer is caused to execute the Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation as described in any one of claims 1-7.

10. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, enables the electronic device to implement the Verilog code generation method for Ethernet cyclic redundancy check CRC32 calculation as described in any one of claims 1 to 7.

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