Power supply control circuit
By designing a power control circuit including a first enable control circuit and a second enable control circuit, the problem of poor compatibility of existing timing control chips is solved, and flexible adaptation and efficient timing control of different types of power supply are realized.
Patent Information
- Application Number
- CN202411612418.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-12
- Publication Date
- 2025-02-11
AI Technical Summary
When existing timing control chips realize up-down timing control between various power supply channels, they have poor compatibility and are difficult to adapt to different models of first-level power supply or PMIC.
A power control circuit is designed, including a first enable control circuit corresponding to the first stage power supply and a second enable control circuit corresponding to the second stage power supply. Through the indication pin and the buck circuit, flexible enable signal control is realized to adapt to different Model power supply.
This power control circuit can meet the timing control needs while being compatible with different models of primary and secondary power supplies, reducing verification and time costs and improving the efficiency of timing control.
Smart Images
Figure CN119420155A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of circuit technology, and in particular to a power supply control circuit. Background Art
[0002] In order to meet the requirements of L2 (partial autonomous driving) and higher-level assistance / autonomous driving functions, the computing power and complexity of the system-on-chip (SOC) used in the automotive autonomous driving domain controller products are becoming increasingly higher, and the complexity of the SOC power supply required will also increase. Based on this, the current SOC power supply is mostly provided by the Power Management Integrated Circuit (PMIC). Generally, PMIC contains multiple power outputs, and there are clear power-on and power-off timing requirements for each power supply, which ensures the stable operation of the SOC.
[0003] There are special timing control chips on the market for power-on and power-off timing control between various power supplies. The required timing can be achieved by controlling the enable pins of the primary power supply and PMIC. However, the time interval of each control signal of the existing timing control chip is mostly fixed (such as 10ms). For different types of primary power supplies or PMICs, it is often necessary to select timing control chips with different time intervals to meet the timing requirements. Therefore, the compatibility of the timing control chip is poor.
[0004] It can be seen that when achieving the control requirements of the power-on and power-off timings between various power supplies, how to improve the compatibility of the adaptation is a technical problem that people in this field need to solve urgently. Summary of the invention
[0005] The purpose of the present invention is to provide a power control circuit to solve the technical problem of poor compatibility of different types of primary power supplies or PMICs when using a timing control chip to realize the control requirements of the power-on and power-off timings between various power supplies.
[0006] In order to solve the above technical problems, the present invention provides a power supply control circuit, comprising: a first enabling control circuit corresponding to a primary power supply, and a second enabling control circuit corresponding to a secondary power supply; the primary power supply comprises an indication pin for indicating the output state of the primary power supply;
[0007] The first enabling control circuit includes a first switch, a second switch and a first buck circuit;
[0008] The second enabling control circuit includes a third switch and a second buck circuit;
[0009] The first input end of the first switch and the second input end of the second switch are both used to receive a control signal; the second input end of the first switch is used to receive a target output signal of the secondary power supply; the output end of the first switch and the output end of the second switch are both connected to the input end of the first step-down circuit, and output a first enable signal of the primary power supply; wherein the target output signal is an output signal corresponding to the last stage of all circuits closed during the power-off process of the secondary power supply; the control signal is used to control the conduction or closing of the first switch;
[0010] The first input end of the second switch and the first input end of the third switch are both used to receive a wake-up signal; the second input end of the third switch is connected to the indication pin, the output end of the third switch is connected to the second step-down circuit, and outputs a second enable signal of the secondary power supply; wherein the wake-up signal is used to control the conduction or closing of the second switch and the third switch.
[0011] Exemplarily, the first switch includes a first transistor and a second transistor; wherein the first transistor is an NPN transistor; and the second transistor is a PNP transistor;
[0012] The base of the first transistor is the first input terminal of the first switch, the emitter of the first transistor is grounded, the collector of the first transistor is connected to the base of the second transistor, the emitter of the second transistor is the second input terminal of the first switch, and the collector of the second transistor is the output terminal of the first switch.
[0013] Exemplarily, the second switch includes a third transistor and a fourth transistor; wherein the third transistor is an NPN transistor; and the fourth transistor is a PNP transistor;
[0014] The base of the third transistor is the first input terminal of the second switch, the emitter of the third transistor is grounded, the collector of the third transistor is connected to the base of the fourth transistor, the emitter of the fourth transistor is the second input terminal of the second switch, and the collector of the fourth transistor is the output terminal of the second switch.
[0015] Exemplarily, the third switch includes a fifth transistor and a sixth transistor; wherein the fifth transistor is an NPN transistor; and the sixth transistor is a PNP transistor;
[0016] The base of the fifth transistor is the first input terminal of the third switch, the emitter of the fifth transistor is grounded, the collector of the fifth transistor is connected to the base of the sixth transistor, the emitter of the sixth transistor is the second input terminal of the third switch, and the collector of the sixth transistor is the output terminal of the third switch.
[0017] Exemplarily, it also includes a first signal isolation circuit;
[0018] The first input end of the first signal isolation circuit is connected to the output end of the first switch, the second input end of the first signal isolation circuit is connected to the output end of the second switch, and the output end of the first signal isolation circuit is connected to the input end of the first buck circuit.
[0019] Exemplarily, a second signal isolation circuit is also included;
[0020] The input end of the second signal isolation circuit is used to receive the wake-up signal, and the output end of the second signal isolation circuit is connected to the first input end of the second switch and the first input end of the third switch respectively.
[0021] Exemplarily, it also includes a voltage protection circuit corresponding to the primary power supply;
[0022] The voltage protection circuit includes the first step-down circuit, a first voltage dividing circuit, a second voltage dividing circuit and a third voltage dividing circuit;
[0023] The first end of the first voltage divider circuit is connected to the emitter of the second transistor for receiving the target output signal; the second end of the first voltage divider circuit is connected to the base of the second transistor, and the third end of the first voltage divider circuit is connected to the collector of the first transistor;
[0024] The first end of the second voltage-dividing circuit is connected to the emitter of the first transistor, the second end of the second voltage-dividing circuit is connected to the base of the first transistor, and the third end of the second voltage-dividing circuit is used to receive the control signal;
[0025] The first end of the third voltage-dividing circuit is connected to the collector of the fourth transistor, and the second end of the third voltage-dividing circuit is connected to the input end of the first step-down circuit.
[0026] Exemplarily, it further includes a fourth voltage dividing circuit and a fifth voltage dividing circuit;
[0027] The first end of the fourth voltage-dividing circuit is connected to the emitter of the fourth triode for receiving the control signal; the second end of the fourth voltage-dividing circuit is connected to the base of the fourth triode, and the third end of the fourth voltage-dividing circuit is connected to the collector of the third triode;
[0028] The first end of the fifth voltage-dividing circuit is connected to the emitter of the third transistor, the second end of the fifth voltage-dividing circuit is connected to the base of the third transistor, and the third end of the fifth voltage-dividing circuit is used to receive the wake-up signal.
[0029] Exemplarily, it further includes a sixth voltage dividing circuit and a seventh voltage dividing circuit;
[0030] The first end of the sixth voltage-dividing circuit is connected to the emitter of the sixth transistor and the indication pin; the second end of the sixth voltage-dividing circuit is connected to the base of the sixth transistor, and the third end of the sixth voltage-dividing circuit is connected to the collector of the fifth transistor;
[0031] The first end of the seventh voltage-dividing circuit is connected to the emitter of the fifth transistor, the second end of the seventh voltage-dividing circuit is connected to the base of the fifth transistor, and the third end of the seventh voltage-dividing circuit is used to receive the wake-up signal.
[0032] Exemplarily, it further includes a first filter circuit corresponding to the first switch, a second filter circuit corresponding to the second switch, and a third filter circuit corresponding to the third switch;
[0033] The input end of the first filter circuit is connected to the base of the first transistor, and the output end of the first filter circuit is connected to the emitter of the first transistor and is grounded;
[0034] The input end of the second filter circuit is connected to the base of the third transistor, and the output end of the second filter circuit is connected to the emitter of the third transistor and is grounded;
[0035] The input end of the third filter circuit is connected to the base of the fifth transistor, and the output end of the third filter circuit is connected to the emitter of the fifth transistor and is grounded.
[0036] The power control circuit provided by the present invention includes: a first enabling control circuit corresponding to a primary power supply, and a second enabling control circuit corresponding to a secondary power supply; the primary power supply includes an indication pin for characterizing the output state of the primary power supply; the first enabling control circuit includes a first switch, a second switch and a first step-down circuit; the second enabling control circuit includes a third switch and a second step-down circuit. The first input end of the first switch and the second input end of the second switch are both used to receive a control signal; the second input end of the first switch is used to receive a target output signal of the secondary power supply; the output end of the first switch and the output end of the second switch are both connected to the input end of the first step-down circuit, and output the first enabling signal of the primary power supply; wherein the target output signal is the output signal corresponding to the last level of all circuits closed during the power-off process of the secondary power supply; the control signal is used to control the conduction or closing of the first switch; the first input end of the second switch and the first input end of the third switch are both used to receive a wake-up signal; the second input end of the third switch is connected to the indication pin, the output end of the third switch is connected to the second step-down circuit, and outputs the second enabling signal of the secondary power supply; wherein the wake-up signal is used to control the conduction or closing of the second switch and the third switch.
[0037] For the power control circuit, during the power-on process, when the wake-up signal is high, after the second switch and the third switch are controlled to be turned on, the control signal pulls up the first enable signal corresponding to the primary power supply through the second switch, thereby enabling the primary power supply. When the output voltage of the primary power supply is stable, the output state indication pin of the primary power supply will become a high level, and then the enable signal corresponding to the secondary power supply is pulled up through the third switch to enable the secondary power supply. The power-on process meets the requirement of turning on the secondary power supply after the output of the primary power supply is stable, and the secondary power supply is turned on by the indication of the signal of the indication pin used to characterize the output state of the primary power supply, which is suitable for various types of primary power supplies; during the power-off process, when the wake-up signal is low, the second switch and the third switch are both closed, and the enable signal corresponding to the secondary power supply will be pulled down under the action of the second step-down circuit, and the secondary power supply begins to execute the power-off process. At this time, although the second switch is closed, the first switch is still in the open state under the action of the control signal. At this time, the output signal corresponding to the circuit closed at the last level of the secondary power supply will continue to pull up the enable signal of the primary circuit, that is, the primary power supply remains on. When the secondary power supply executes the last power-off process, the output signal corresponding to the circuit closed at the last level of the secondary power supply becomes a low level. At this time, the enable signal corresponding to the primary power supply will be pulled down under the action of the first step-down circuit, and the primary power supply is turned off. This process realizes the requirement that the secondary power supply completes the power-off process and then turns off the primary power supply. For other types of secondary power supplies, it is only necessary to select the last level of power supply in the power-off sequence as the output signal of the secondary circuit, so it is suitable for various types of secondary power supplies. It can be seen that the power control circuit can be compatible with different types of primary power supplies and different types of secondary power supplies while meeting the timing control requirements. Since the timing control chip does not need to be replaced back and forth for different types of primary power supplies and different types of secondary power supplies, the verification and time costs are reduced and the efficiency of timing control is improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0039] FIG1 is a power supply topology diagram of a conventional automobile autonomous driving domain controller SOC provided by an embodiment of the present invention;
[0040] FIG2 is a schematic diagram of implementing timing control through a timing control chip according to an embodiment of the present invention;
[0041] FIG3 is a timing diagram of a power-on process provided by an embodiment of the present invention;
[0042] FIG4 is a timing diagram of a power-off process provided by an embodiment of the present invention;
[0043] FIG5 is a timing diagram of power on and off of a product provided by an embodiment of the present invention;
[0044] FIG6 is a schematic diagram of a timing control circuit provided in an embodiment of the present invention;
[0045] FIG7 is a schematic diagram of a power control circuit provided in an embodiment of the present invention;
[0046] FIG8 is a schematic diagram of a specific power supply control circuit provided by an embodiment of the present invention;
[0047] FIG. 9 is a power-on and power-off timing diagram after using the power control circuit provided by the present invention, provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0049] The core of the present invention is to provide a power control circuit to solve the technical problem of poor compatibility of different types of primary power supplies or PMICs when using a timing control chip to realize the control requirements of the power-on and power-off timings between various power supplies.
[0050] To meet the requirements of advanced assistance / autonomous driving functions at L2 and above, the SOC computing power and complexity used in automotive autonomous driving domain controller products are becoming increasingly higher, and at the same time, the complexity of the SOC power supply required will also increase. Based on this, the current SOC power supply is mostly provided by PMIC. Generally, PMIC contains multiple power outputs, and there are clear power-on and power-off timing requirements for each power supply, which ensures the stable operation of the SOC.
[0051] The PMICs currently used are all secondary power supplies, that is, they cannot be powered by KL30, and the primary power supply needs to be converted into a lower voltage (such as: 5V / 3.3V) and then provided to the PMIC. At this time, there is a clear requirement for the power timing between the primary power supply and the PMIC (such as the primary power supply output must be stable before turning on the PMIC; or the PMIC must complete the next point process before turning off the primary power supply). For this piece of power up and down timing control, there are special timing control chips on the market. By controlling the enable pins of the primary power supply and the PMIC, the required timing can be achieved. Figure 1 is a power supply topology diagram of an existing automotive autonomous driving domain controller SOC provided by an embodiment of the present invention. As shown in Figure 1, KL30 is connected to the VIN pin of 1ST_POWER (i.e., the primary power supply), and the VOUT (i.e., the output end) of 1ST_POWER is connected to the VIN pin of the PMIC (secondary power supply). The PMIC also includes multiple output ends (such as VOUT1, VOUT2, VOUT3 and VOUT4), and each output end is connected to the SOC. In addition, 1ST_POWER corresponds to 1ST_ENABLE (i.e., the enable signal of the primary power supply), and PMIC corresponds to PMIC_ENABLE (i.e., the secondary power supply enable signal).
[0052] 1ST_POWER converts KL30 into the input voltage required by PMIC, which is generally 3.3V or 5V, and then PMIC converts it into the various voltages required for SOC operation, where the timing of each output of PMIC is controlled by the PMIC itself. For timing control, it is actually to control the time interval between the jump of the primary power supply and the PMIC enable signal. The power is turned on when the enable signal is high, and the power is turned off when it is low. The timing control chip is mainly used in the relevant timing control to meet the timing control requirements. Figure 2 is a schematic diagram of realizing timing control through a timing control chip provided by an embodiment of the present invention. As shown in Figure 2, on the basis of Figure 1, a timing control chip and a timing control chip power supply for powering the timing control chip are added. The timing control chip generally does not support direct power supply from KL30, and requires a separate primary power supply. The timing control chip is turned on / off by the wake-up signal. The wake-up signal is generally the car ignition signal (KL15). When KL15 is high, the timing control chip is turned on, and then the control signal is output to enable the primary power supply and the PMIC power supply. Each control signal has a certain time interval to meet the power-on timing requirements; when KL15 is low, the timing control chip is turned off, and then the control signal is output to turn off the primary power supply and the PMIC power supply. Each control signal has a certain time interval to meet the power-off timing requirements. Figure 3 is a timing diagram of a power-on process provided by an embodiment of the present invention. Figure 4 is a timing diagram of a power-off process provided by an embodiment of the present invention. In Figures 3 and 4, the EN signal is the wake-up signal, FLAG1~3 is the control signal output by the timing control chip, and td1~6 is the time interval, which is generally a fixed time, such as 10ms. Through the above scheme, the power-on and power-off timing of the product that can be achieved is shown in Figure 5, which is a power-on and power-off timing diagram of the product provided by an embodiment of the present invention.
[0053] Power-on process: When the wake-up signal is high, the timing control chip turns on and then outputs the control signal. Then the control signal pulls up the first-level power enable (1ST_ENABLE) and PMIC enable (PMIC_ENABLE) at a fixed time interval. Obviously, t1+t2 is the fixed time interval when the timing control chip is powered on.
[0054] Furthermore, after the first-level power supply is enabled, it starts to have an output voltage (1ST_POWER_VOUT). The condition for PMIC to be turned on is that the output voltage of the first-level power supply must be stable (t1 is the time from the first-level power supply being enabled to the output voltage being stable). Therefore, the PMIC enable must be pulled high after the output voltage of the first-level power supply is stable, that is, t2 ≥ 0; here comes the shortcoming of the timing control chip: when different first-level power supplies are selected, their t1 times are not the same. When t1 exceeds the fixed time interval of the timing control chip, the timing control chip becomes unusable.
[0055] Furthermore, after the output of the first-level power supply is stabilized, the PMIC enable is pulled high, and the PMIC starts to output each power supply according to the set timing, and the entire time becomes t3.
[0056] Power-off process: When the wake-up signal is low, the timing control chip is turned off, and then the control signal is output. Then the control signal pulls down the first-level power enable (1ST_ENABLE) and PMIC enable (PMIC_ENABLE) at a fixed time interval. Considering that PMIC has its own power-off process (time: t4), the first-level power output can only be turned off after PMIC completes the power-off process. Therefore, the first-level power enable needs to be pulled down after t4, that is, t5 ≥ 0 (t4 + t5 is the fixed time interval of the timing control chip). Here comes another shortcoming of the timing control chip: when different PMICs are selected, the t4 time is not the same. When t4 exceeds the fixed time interval when the timing control chip is powered off, the timing control chip is unusable.
[0057] In order to improve the compatibility of power supplies at various levels during timing control, FIG6 is a schematic diagram of a timing control circuit provided in an embodiment of the present invention. Compared with FIG1 , FIG6 adds 1ST_PG (an output status indication pin of a primary power supply). The inventive circuit in FIG6 is the power supply control circuit described below.
[0058] It is worth noting that the power supply described below includes a primary power supply and a secondary power supply. When there are multiple power supplies, the power supply control circuit provided by the present invention is also applicable.
[0059] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. FIG7 is a schematic diagram of a power control circuit provided by an embodiment of the present invention. As shown in FIG7 , the power control circuit includes: a first enabling control circuit corresponding to a primary power supply, and a second enabling control circuit corresponding to a secondary power supply; the primary power supply includes an indication pin for characterizing the output state of the primary power supply;
[0060] The first enabling control circuit includes a first switch, a second switch and a first buck circuit;
[0061] The second enabling control circuit includes a third switch and a second buck circuit;
[0062] The first input end of the first switch and the second input end of the second switch are both used to receive a control signal; the second input end of the first switch is used to receive a target output signal of the secondary power supply; the output end of the first switch and the output end of the second switch are both connected to the input end of the first step-down circuit, and output a first enable signal of the primary power supply; wherein the target output signal is an output signal corresponding to the last circuit closed in all circuits during the power-off process of the secondary power supply; the control signal is used to control the conduction or closing of the first switch;
[0063] The first input end of the second switch and the first input end of the third switch are both used to receive a wake-up signal; the second input end of the third switch is connected to the indication pin, the output end of the third switch is connected to the second step-down circuit, and outputs a second enable signal of the secondary power supply; wherein the wake-up signal is used to control the conduction or closing of the second switch and the third switch.
[0064] There is no limitation on the specific structures of the first switch, the second switch, the third switch, the first buck circuit and the second buck circuit, which are determined according to actual conditions.
[0065] Fig. 8 is a schematic diagram of a specific power supply control circuit provided by an embodiment of the present invention. The first switch Q1 includes a first transistor O1 and a second transistor O2; wherein the first transistor O1 is an NPN transistor; the second transistor O2 is a PNP transistor;
[0066] The base of the first transistor O1 is the first input terminal of the first switch Q1, the emitter of the first transistor O1 is grounded, the collector of the first transistor O1 is connected to the base of the second transistor O2, the emitter of the second transistor O2 is the second input terminal of the first switch Q1, and the collector of the second transistor O2 is the output terminal of the first switch Q1.
[0067] The second switch Q2 includes a third transistor O3 and a fourth transistor O4; wherein the third transistor O3 is an NPN transistor; and the fourth transistor O4 is a PNP transistor;
[0068] The base of the third triode O3 is the first input terminal of the second switch Q2, the emitter of the third triode O3 is grounded, the collector of the third triode O3 is connected to the base of the fourth triode O4, the emitter of the fourth triode O4 is the second input terminal of the second switch Q2, and the collector of the fourth triode O4 is the output terminal of the second switch Q2.
[0069] The third switch Q3 includes a fifth transistor O5 and a sixth transistor O6; wherein the fifth transistor O5 is an NPN transistor; and the sixth transistor O6 is a PNP transistor;
[0070] The base of the fifth transistor O5 is the first input terminal of the third switch Q3, the emitter of the fifth transistor O5 is grounded, the collector of the fifth transistor O5 is connected to the base of the sixth transistor O6, the emitter of the sixth transistor O6 is the second input terminal of the third switch Q3, and the collector of the sixth transistor O6 is the output terminal of the third switch Q3.
[0071] In addition, in order to reduce interference between the control signal (KL30) and the target output signal (PMIC_VOUT1), the power control circuit further includes a first signal isolation circuit;
[0072] The first input end of the first signal isolation circuit is connected to the output end of the first switch Q1 , the second input end of the first signal isolation circuit is connected to the output end of the second switch Q2 , and the output end of the first signal isolation circuit is connected to the input end of the first buck circuit.
[0073] There is no limitation on the first signal isolation circuit. As shown in FIG8 , the first dual-path diode D1 is used to implement signal isolation between the KL30 and PMIC_VOUT1 signals.
[0074] When there are multiple wake-up signals, in order to avoid interference between different wake-up signals, the power control circuit further includes a second signal isolation circuit;
[0075] The input end of the second signal isolation circuit is used to receive the wake-up signal, and the output end of the second signal isolation circuit is connected to the first input end of the second switch Q2 and the first input end of the third switch Q3 respectively.
[0076] There is no limitation on the second signal isolation circuit. As shown in FIG8 , the second dual-path diode D2 is used to implement signal isolation between the WAKEUP1 signal and the WAKEUP1 signal; the third dual-path diode D3 is used to implement signal isolation between the WAKEUP3 signal and the KL15 signal.
[0077] In order to protect the second switch Q2, in implementation, the power control circuit further includes a fourth voltage dividing circuit and a fifth voltage dividing circuit;
[0078] A first end of the fourth voltage-dividing circuit is connected to the emitter of the fourth transistor O4 for receiving a control signal; a second end of the fourth voltage-dividing circuit is connected to the base of the fourth transistor O4; and a third end of the fourth voltage-dividing circuit is connected to the collector of the third transistor O3;
[0079] A first end of the fifth voltage-dividing circuit is connected to the emitter of the third transistor O3 , a second end of the fifth voltage-dividing circuit is connected to the base of the third transistor O3 , and a third end of the fifth voltage-dividing circuit is used to receive a wake-up signal.
[0080] The fourth voltage divider circuit and the fifth voltage divider circuit are not limited. As shown in FIG8 , the fourth voltage divider circuit includes two resistors between pin 4 and pin 5 of the second switch Q2, and the fifth voltage divider circuit includes two resistors between pin 1 and pin 2 of the second switch Q2.
[0081] Similarly, in order to protect the third switch Q3, the power control circuit further includes a sixth voltage dividing circuit and a seventh voltage dividing circuit;
[0082] The first end of the sixth voltage-dividing circuit is connected to the emitter of the sixth transistor O6 and the indication pin; the second end of the sixth voltage-dividing circuit is connected to the base of the sixth transistor O6, and the third end of the sixth voltage-dividing circuit is connected to the collector of the fifth transistor O5;
[0083] A first end of the seventh voltage-dividing circuit is connected to the emitter of the fifth transistor O5 , a second end of the seventh voltage-dividing circuit is connected to the base of the fifth transistor O5 , and a third end of the seventh voltage-dividing circuit is used to receive a wake-up signal.
[0084] The sixth voltage divider circuit and the seventh voltage divider circuit are not limited. As shown in FIG8 , the sixth voltage divider circuit includes two resistors between pins 4 and 5 of the third switch Q3, and the seventh voltage divider circuit includes two resistors between pins 1 and 2 of the third switch Q3.
[0085] In order to avoid noise at the control end of each switch combination circuit, the power supply control circuit further includes a first filter circuit corresponding to the first switch Q1, a second filter circuit corresponding to the second switch Q2, and a third filter circuit corresponding to the third switch Q3;
[0086] The input end of the first filter circuit is connected to the base of the first transistor O1, and the output end of the first filter circuit is connected to the emitter of the first transistor O1 and is grounded;
[0087] The input end of the second filter circuit is connected to the base of the third transistor O3, and the output end of the second filter circuit is connected to the emitter of the third transistor O3 and is grounded;
[0088] An input end of the third filtering circuit is connected to the base of the fifth transistor O5 , and an output end of the third filtering circuit is connected to the emitter of the fifth transistor O5 and is grounded.
[0089] As shown in FIG. 8 , the first filter circuit includes a first capacitor C1 , the second filter circuit includes a second capacitor C2 , and the third filter circuit includes a third capacitor C3 .
[0090] The following uses the power control circuit shown in FIG8 to illustrate that the power control circuit provided by the present invention can meet the timing control requirements.
[0091] Specific implementation method:
[0092] (1) The first switch Q1, the second switch Q2 and the third switch Q3 are a combination circuit of an NPN transistor and a PNP transistor, which can realize that when the input of pin 2 is high, the combination circuit is turned on, and pins 3 and 4 are connected; when the input of pin 2 is low, the combination circuit is turned off, and pins 3 and 4 are disconnected. The principle is the working principle of the transistor, which will not be repeated here.
[0093] (2) The wake-up signal is the control signal for turning the entire circuit on or off. When any one of the wake-up signals is high, the circuit is turned on; when all the wake-up signals are low, the circuit is turned off. The second dual-path diode D2 and the third dual-path diode D3 can prevent interference between different wake-up signals. For automotive autonomous driving domain controller products, the wake-up signal voltage is generally 9~16V, and the transistor combination circuit ensures that it can be turned on.
[0094] (3) Power-on process: When the wake-up signal is high, the second switch Q2 and the third switch Q3 will be turned on, and KL30 will pull up 1ST_ENABLE through the second resistor R2 and the first dual-path diode D1, thereby enabling the primary power supply. When the output voltage of the primary power supply is stable, the output status indication pin 1ST_PG of the primary power supply will become a high level (1ST_PG will output a low level when the output voltage is abnormal), thereby pulling up PMIC_ENABLE and enabling PMIC. This process can meet the requirement of turning on PMIC after the output of the primary power supply is stable, and is applicable to other models of primary power supplies.
[0095] For the first switch Q1, because the control source is KL30, the first switch Q1 is in the on state. After the PMIC is enabled, the PMIC_VOUT1 outputs high after the set timing, and then is connected in parallel with KL30 through the first dual-path diode D1 to jointly enable the first-level power supply. The PMIC_VOUT1 here must be the output that is turned off at the last level in the PMIC power-off process. The first dual-path diode D1 can prevent interference between KL30 and PMIC_VOUT1.
[0096] The third resistor R3 and the fourth resistor R4 are current limiting pull-down resistors and ensure that the first switch Q1 , the second switch Q2 , and the third switch Q3 are in a saturation region (one of the triode working regions).
[0097] (4) Power-off process: When all wake-up signals are low, the second switch Q2 and the third switch Q3 will be closed, and PMIC_ENABLE will be pulled low by the pull-down resistor (the fourth resistor R4). The PMIC starts to execute the power-off process. At this time, although the second switch Q2 is closed, the first switch Q1 is still turned on, and PMIC_VOUT1 will continue to pull up 1ST_ENABLE, that is, the first-level power supply remains on.
[0098] When the PMIC executes the last power-off process, PMIC_VOUT1 will be turned off, and 1ST_ENABLE will be pulled down by the pull-down resistor (third resistor R3), and the first-level power supply will be turned off. This process realizes the requirement that the PMIC completes the power-off process and then turns off the first-level power supply. For other types of PMIC, you only need to select the last-level power supply in the power-off sequence as PMIC_VOUT1, which is also applicable.
[0099] (5) C1, C2, and C3 are filter capacitors used to filter out noise at the control end of the transistor combination circuit.
[0100] Fig. 9 is a power-on and power-off timing diagram after using the power supply control circuit provided by the present invention, provided by an embodiment of the present invention. It can be seen from Fig. 9 that the requirements of timing control are met.
[0101] It can be seen that the above-mentioned power control circuit can flexibly adapt to different primary power supply / PMIC solutions with good compatibility, thus saving the time and verification cost caused by chip reselection.
[0102] The above describes that the timing control meets the requirements and has good compatibility. In practice, because the domain controller power supply is KL30 and the real vehicle environment is complex, power feeding or voltage mutation often occurs on KL30. In order to avoid abnormal operation of the domain controller due to undervoltage or circuit board / wiring harness burnout due to excessive current in these situations, the undervoltage protection function has also become a must for domain controller products. Currently, the undervoltage protection function on the market is mostly implemented by undervoltage protection chips, including voltage detection and power metal oxide semiconductor (MOS) tubes. When the voltage is lower than the threshold, the power MOS tube is turned off to shut down the product. Undervoltage protection and timing control need to select corresponding chips respectively, and then match the peripheral circuit to realize. Some timing control chips cannot be directly powered by KL30, and an additional primary power supply is required to power them. The design is complex and the total cost is high. As shown in Figure 2, the undervoltage protection chip monitors the KL30 voltage in real time. When KL30 is undervoltage, the power MOS tube is turned off, thereby disconnecting the path between KL30 and the primary power supply VIN.
[0103] In order to reduce the complexity and cost of the design, the power control circuit provided in the embodiment of the present invention further includes a voltage protection circuit corresponding to the primary power supply;
[0104] The voltage protection circuit includes a first step-down circuit, a first voltage dividing circuit, a second voltage dividing circuit and a third voltage dividing circuit;
[0105] The first end of the first voltage divider circuit is connected to the emitter of the second transistor O2 for receiving the target output signal; the second end of the first voltage divider circuit is connected to the base of the second transistor O2, and the third end of the first voltage divider circuit is connected to the collector of the first transistor O1;
[0106] A first end of the second voltage divider circuit is connected to the emitter of the first transistor O1, a second end of the second voltage divider circuit is connected to the base of the first transistor O1, and a third end of the second voltage divider circuit is used to receive a control signal;
[0107] A first end of the third voltage-dividing circuit is connected to the collector of the fourth transistor O4 , and a second end of the third voltage-dividing circuit is connected to the input end of the first step-down circuit.
[0108] As shown in FIG8 , the first voltage divider circuit includes two resistors between pin 4 and pin 5 of the first switch Q1 , the second voltage divider circuit includes two resistors between pin 1 and pin 2 of the first switch Q1 and the first resistor R1 , and the third voltage divider circuit includes a second resistor R2 and a third resistor R3 .
[0109] For undervoltage protection, it is actually to monitor the voltage of KL30 in real time. When KL30 is undervoltage, the path between KL30 and the primary power supply VIN is promptly shut down, or the enable signal (1ST_ENABLE) of the primary power supply is pulled down, thereby making the product enter a completely closed state. Still taking Figure 8 as an example, the implementation process of the undervoltage protection function provided by the invention is described. It is implemented by the internal resistor divider circuit of the second resistor R2, the third resistor R3, the first resistor R1, and the first switch Q1. Each primary power supply has a corresponding high-level threshold for enabling. It only needs to match the resistance values of the second resistor R2 and the first resistor R1 according to the undervoltage protection target threshold, so that when KL30 is undervoltage, the primary power supply can be turned off to shut down the product.
[0110] The calculation is as follows: KL30 is required to be undervoltage protected when it is lower than 4.5V, and the high level threshold of the primary power supply is 1.9V. Apply the following formula: (KL30 undervoltage threshold - Q2 voltage drop - D1 voltage drop) * R3 / (R2+R3) = primary power supply high level threshold.
[0111] Assuming that the voltage drop of the second switch Q2 = 0.2V, the voltage drop of the first dual-path diode D1 = 0.5V, it is calculated that R2 = 100K;
[0112] Then calculate the first resistor R1. When KL30 is undervoltage, the voltage is divided by the first resistor R1 to close the first switch Q1 path, thereby disconnecting the influence of PMIC_VOUT1 on 1ST_ENABLE (if it is not disconnected, even if KL30 is divided to below the high level threshold by the second resistor R2, PMIC_VOUT1 is still at a high level and the primary power supply is still turned on).
[0113] Apply the following formula: KL30 undervoltage threshold * 47K / (R1 + 2 * 47K) = NPN Vbe voltage when Q1 is turned on.
[0114] Assuming that the NPN Vbe voltage = 0.7V when the first switch Q1 is turned on, R1≈208K is calculated;
[0115] Through the above calculation, it can be achieved that when KL30 is lower than 4.5V, the 1ST_ENABLE voltage is lower than 1.9V and the first-level power supply is turned off.
[0116] It can be seen that the undervoltage protection function is achieved through the above undervoltage protection circuit. The circuit provided by the present invention is suitable for the automobile automatic driving domain controller, realizes the power-on and power-off timing control and undervoltage protection, and effectively reduces the cost by about 50% compared with the conventional chip solution.
[0117] The above is a detailed introduction to a power control circuit provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the present invention.
[0118] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.
Claims
1. A power control circuit, characterized in that: include: A first enabling control circuit corresponding to the primary power supply and a second enabling control circuit corresponding to the secondary power supply; the primary power supply includes an indication pin for indicating an output state of the primary power supply; The first enabling control circuit includes a first switch, a second switch and a first buck circuit; The second enabling control circuit includes a third switch and a second buck circuit; The first input end of the first switch and the second input end of the second switch are both used to receive a control signal; the second input end of the first switch is used to receive a target output signal of the secondary power supply; the output end of the first switch and the output end of the second switch are both connected to the input end of the first step-down circuit, and output a first enable signal of the primary power supply; wherein the target output signal is an output signal corresponding to the last stage of all circuits closed during the power-off process of the secondary power supply; the control signal is used to control the conduction or closing of the first switch; The first input end of the second switch and the first input end of the third switch are both used to receive a wake-up signal; the second input end of the third switch is connected to the indication pin, the output end of the third switch is connected to the second step-down circuit, and outputs a second enable signal of the secondary power supply; wherein the wake-up signal is used to control the conduction or closing of the second switch and the third switch.
2. The power control circuit according to claim 1, characterized in that: The first switch includes a first transistor and a second transistor; wherein the first transistor is an NPN transistor; and the second transistor is a PNP transistor; The base of the first transistor is the first input terminal of the first switch, the emitter of the first transistor is grounded, the collector of the first transistor is connected to the base of the second transistor, the emitter of the second transistor is the second input terminal of the first switch, and the collector of the second transistor is the output terminal of the first switch.
3. The power control circuit according to claim 2, characterized in that: The second switch includes a third transistor and a fourth transistor; wherein the third transistor is an NPN transistor; and the fourth transistor is a PNP transistor; The base of the third transistor is the first input terminal of the second switch, the emitter of the third transistor is grounded, the collector of the third transistor is connected to the base of the fourth transistor, the emitter of the fourth transistor is the second input terminal of the second switch, and the collector of the fourth transistor is the output terminal of the second switch.
4. The power control circuit according to claim 3, characterized in that: The third switch includes a fifth transistor and a sixth transistor; wherein the fifth transistor is an NPN transistor; and the sixth transistor is a PNP transistor; The base of the fifth transistor is the first input terminal of the third switch, the emitter of the fifth transistor is grounded, the collector of the fifth transistor is connected to the base of the sixth transistor, the emitter of the sixth transistor is the second input terminal of the third switch, and the collector of the sixth transistor is the output terminal of the third switch.
5. The power control circuit according to claim 1, characterized in that: Also included is a first signal isolation circuit; The first input end of the first signal isolation circuit is connected to the output end of the first switch, the second input end of the first signal isolation circuit is connected to the output end of the second switch, and the output end of the first signal isolation circuit is connected to the input end of the first buck circuit.
6. The power control circuit according to claim 1, characterized in that: Also included is a second signal isolation circuit; The input end of the second signal isolation circuit is used to receive the wake-up signal, and the output end of the second signal isolation circuit is connected to the first input end of the second switch and the first input end of the third switch respectively.
7. The power control circuit according to claim 3, characterized in that: Also includes a voltage protection circuit corresponding to the primary power supply; The voltage protection circuit includes the first step-down circuit, a first voltage dividing circuit, a second voltage dividing circuit and a third voltage dividing circuit; The first end of the first voltage divider circuit is connected to the emitter of the second transistor for receiving the target output signal; the second end of the first voltage divider circuit is connected to the base of the second transistor, and the third end of the first voltage divider circuit is connected to the collector of the first transistor; The first end of the second voltage-dividing circuit is connected to the emitter of the first transistor, the second end of the second voltage-dividing circuit is connected to the base of the first transistor, and the third end of the second voltage-dividing circuit is used to receive the control signal; The first end of the third voltage-dividing circuit is connected to the collector of the fourth transistor, and the second end of the third voltage-dividing circuit is connected to the input end of the first step-down circuit.
8. The power control circuit according to claim 3, characterized in that: Also includes a fourth voltage dividing circuit and a fifth voltage dividing circuit; The first end of the fourth voltage-dividing circuit is connected to the emitter of the fourth triode for receiving the control signal; the second end of the fourth voltage-dividing circuit is connected to the base of the fourth triode, and the third end of the fourth voltage-dividing circuit is connected to the collector of the third triode; The first end of the fifth voltage-dividing circuit is connected to the emitter of the third transistor, the second end of the fifth voltage-dividing circuit is connected to the base of the third transistor, and the third end of the fifth voltage-dividing circuit is used to receive the wake-up signal.
9. The power control circuit according to claim 4, characterized in that: Also includes a sixth voltage dividing circuit and a seventh voltage dividing circuit; The first end of the sixth voltage-dividing circuit is connected to the emitter of the sixth transistor and the indication pin; the second end of the sixth voltage-dividing circuit is connected to the base of the sixth transistor, and the third end of the sixth voltage-dividing circuit is connected to the collector of the fifth transistor; The first end of the seventh voltage-dividing circuit is connected to the emitter of the fifth transistor, the second end of the seventh voltage-dividing circuit is connected to the base of the fifth transistor, and the third end of the seventh voltage-dividing circuit is used to receive the wake-up signal.
10. The power control circuit according to claim 4, characterized in that: Also includes a first filter circuit corresponding to the first switch, a second filter circuit corresponding to the second switch, and a third filter circuit corresponding to the third switch; The input end of the first filter circuit is connected to the base of the first transistor, and the output end of the first filter circuit is connected to the emitter of the first transistor and is grounded; The input end of the second filter circuit is connected to the base of the third transistor, and the output end of the second filter circuit is connected to the emitter of the third transistor and is grounded; The input end of the third filter circuit is connected to the base of the fifth transistor, and the output end of the third filter circuit is connected to the emitter of the fifth transistor and is grounded.