Communication level adaptive circuit and communication level adaptive method

Abstract

The invention relates to a communication level self-adaption circuit and a communication level self-adaption method, the communication level self-adaption circuit comprises a level conversion circuit, the output end of the level conversion circuit is connected with the input communication interface of the circuit, and the input end of the level conversion circuit is connected with the output communication interface of a target circuit; the target circuit comprises a target level conversion circuit, the output end of the target level conversion circuit is connected with the input communication interface of the target circuit, and the input end is connected with the output communication interface of the circuit; the level conversion circuit can convert any level input signal into an input signal of a level required by the input communication interface of the circuit; the target level conversion circuit can convert any level input signal into the input signal of the level required by the input communication interface of the target circuit, so that any conversion of 1.8 V to 5.5 V levels is realized, the level self-adaptive matching of any two or more circuits is achieved, and the universality is particularly improved in the field of serial port communication.

Description

Technical Field

[0001] The invention relates to a communication level self-adaptation circuit and a communication level self-adaptation method, belonging to digital circuit design technology. Background Art

[0002] In the field of electronic engineering, communication or data transmission between circuits can only be carried out when their level signals are consistent. Take the microcontroller (MCU) as an example. As the core control unit, the microcontroller (MCU) is widely used in various intelligent devices and systems. However, in actual applications, the operating voltages of different microcontrollers (MCUs) or peripheral modules are often different. For example, some microcontrollers (MCUs) have an operating voltage of 5V, while others only have an operating voltage of 3.3V or 1.8V. This voltage difference may cause damage to low-voltage devices when directly connected, especially in serial communication.

[0003] Serial communication is a common data exchange method that allows devices to transmit data through serial data streams. However, different devices may use different level standards to represent data signals. Due to the differences in serial level standards between different devices, direct connection often leads to communication failure or data errors.

[0004] In the prior art, the solution to achieve mutual communication between two circuits is usually that both parties agree to use the circuits with the same level. However, in actual applications, one party often has a mature product, and the other party designs and produces it according to the digital level rules of the existing product to achieve matching, or designs signal level conversion circuits at the sending end and receiving end of the matching party's product to convert the sent level signal into the level signal corresponding to the other party's product, and convert the received level signal into the level signal corresponding to its own product. However, to implement this solution, it is necessary to add an additional power conversion module corresponding to the matched product in the matching party's product, or add a level matching pin from the matched product to the signal level conversion circuit of the matching product to provide the level corresponding to the matched product.

[0005] The problem with the above existing solutions is that adding a level conversion circuit or a level matching line to one circuit has poor adaptability because the level of each circuit is fixed; the additional level matching line may also have problems such as improper installation, aging and loosening, and poor contact caused by oxidation. To address the problem of poor adaptability, for example, circuit A is the matching party output level matching line, circuit B and circuit C are both matched parties, and the level matching line is used in different systems for level conversion. If circuit B wants to communicate with circuit C in another system design, the level matching cannot be completed. Summary of the invention

[0006] In order to solve the above problems in the prior art, the present invention proposes a communication level self-adaptation circuit and a communication level self-adaptation method.

[0007] The technical solution of the present invention is as follows:

[0008] In one aspect, the present invention provides a communication level adaptation method, which is used to connect a first circuit and a second circuit, wherein the output interface and the input interface of the first circuit and the second circuit have the same or different levels, and is characterized in that the first circuit includes a first level conversion circuit, and the second circuit includes a second level conversion circuit;

[0009] The output end of the first level conversion circuit is connected to the input communication interface of the first circuit, and the input end of the first level conversion circuit is connected to the output communication interface of the second circuit;

[0010] The output end of the second level conversion circuit is connected to the input communication interface of the second circuit, and the input end of the second level conversion circuit is connected to the output communication interface of the first circuit;

[0011] The first level conversion circuit is capable of converting an input signal into an input signal of a level required by an input communication interface of the first circuit;

[0012] The second level conversion circuit can convert the input signal into an input signal of a level required by the input communication interface of the second circuit.

[0013] As a preferred implementation, the level of the input signal input to the first level conversion circuit or the second level conversion circuit is 1.8V-5.5V.

[0014] As a preferred implementation, the first level conversion circuit or the second level conversion circuit is implemented by a single triode, specifically:

[0015] The level conversion circuit includes a third triode, and the emitter of the third triode serves as the input end of the level conversion circuit;

[0016] The base of the third transistor is connected to the power supply through the eighth resistor, the first capacitor is connected in parallel to both ends of the eighth resistor, and the collector of the third transistor serves as the output end of the level conversion circuit;

[0017] The second conversion level is connected to the output end of the level conversion circuit through a seventh resistor;

[0018] The second conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

[0019] As a preferred implementation, the first level conversion circuit or the second level conversion circuit is implemented by a dual MOS tube, specifically:

[0020] The level conversion circuit includes a thirteenth resistor, one end of the thirteenth resistor is connected to the gate of the first MOS tube, and the other end is used as the input end of the level conversion circuit, and the source of the first MOS tube is grounded; a fourteenth resistor is connected in parallel to the gate and source of the first MOS tube;

[0021] The drain of the first MOS tube is connected to the gate of the second MOS tube, one end of the fifteenth resistor is connected to the drain of the first MOS tube, and the other end is connected to the third conversion level;

[0022] The source of the second MOS tube is grounded, the drain of the second MOS tube serves as the output end of the level conversion circuit, one end of the eighteenth resistor is connected to the drain of the second MOS tube, and the other end is connected to the third conversion level;

[0023] The third conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

[0024] On the other hand, the present invention also provides a communication level adaptive circuit, which can be connected to a target circuit of any output and input level, and is characterized in that it includes a level conversion circuit, the output end of which is connected to the input communication interface of the circuit, and the input end is connected to the output communication interface of the target circuit;

[0025] The target circuit includes a target level conversion circuit, the output end of the target level conversion circuit is connected to the input communication interface of the target circuit, and the input end is connected to the output communication interface of the circuit;

[0026] The level conversion circuit can convert an input signal of any level into an input signal of the level required by the input communication interface of the circuit;

[0027] The target level conversion circuit can convert an input signal of any level into an input signal of a level required by an input communication interface of the target circuit.

[0028] As a preferred implementation, the level of the input signal input to the level conversion circuit or the target level conversion circuit is 1.8V-5.5V.

[0029] As a preferred implementation, the level conversion circuit is implemented by a dual triode, specifically:

[0030] The level conversion circuit includes a first resistor, one end of the first resistor is connected to the base of the first triode, and the other end is used as the input end of the level conversion circuit, and the emitter of the first triode is grounded; a second resistor is connected in parallel between the emitter and the base of the first triode;

[0031] The collector of the first triode is connected to the base of the second triode through a fifth resistor, one end of the third resistor is connected to the collector of the first triode, and the other end is connected to the first conversion level;

[0032] The emitter of the second triode is grounded, the collector of the second triode serves as the output end of the level conversion circuit, one end of the fourth resistor is connected to the collector of the second triode, and the other end is connected to the first conversion level;

[0033] The first conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

[0034] As a preferred implementation, the level conversion circuit is implemented by a single triode, specifically:

[0035] The level conversion circuit includes a third triode, and the emitter of the third triode serves as the input end of the level conversion circuit;

[0036] The base of the third transistor is connected to the power supply through the eighth resistor, the first capacitor is connected in parallel to both ends of the eighth resistor, and the collector of the third transistor serves as the output end of the level conversion circuit;

[0037] The second conversion level is connected to the output end of the level conversion circuit through a seventh resistor;

[0038] The second conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

[0039] As a preferred implementation, the level conversion circuit is implemented by dual MOS tubes, specifically:

[0040] The level conversion circuit includes a thirteenth resistor, one end of the thirteenth resistor is connected to the gate of the first MOS tube, and the other end is used as the input end of the level conversion circuit, and the source of the first MOS tube is grounded; a fourteenth resistor is connected in parallel to the gate and source of the first MOS tube;

[0041] The drain of the first MOS tube is connected to the gate of the second MOS tube, one end of the fifteenth resistor is connected to the drain of the first MOS tube, and the other end is connected to the third conversion level;

[0042] The source of the second MOS tube is grounded, the drain of the second MOS tube serves as the output end of the level conversion circuit, one end of the eighteenth resistor is connected to the drain of the second MOS tube, and the other end is connected to the third conversion level;

[0043] The third conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

[0044] As a preferred implementation, the level conversion circuit is implemented by a single MOS tube, specifically:

[0045] The level conversion circuit includes a third MOS tube, and the source of the third MOS tube serves as an input end of the level conversion circuit;

[0046] The gate of the third MOS tube is connected to the power supply, and the drain of the third MOS tube serves as the output end of the level conversion circuit;

[0047] The fourth conversion level is connected to the output end of the level conversion circuit through a twenty-second resistor;

[0048] The fourth conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

[0049] The present invention has the following beneficial effects:

[0050] The level conversion circuit of the present invention can receive input signals of any level in the range of 1.8V-5.5V and convert them into the level required by the input communication interface of the circuit. This adaptive characteristic enables the circuit to easily cope with devices of different voltage standards without worrying about communication barriers caused by level mismatch. Through the target level conversion circuit, the circuit can not only receive signals from the target circuit, but also send signals back to the target circuit, realizing true two-way communication. This capability is particularly important in communication systems that require complex interactions. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 This is an implementation diagram of the MCU serial port communication level conversion implemented by the present invention.

[0052] Figure 2 This is a connection diagram of a level conversion circuit implemented by a dual triode of the present invention.

[0053] Figure 3 This is a connection diagram of a level conversion circuit implemented by a single triode of the present invention.

[0054] Figure 4 This is a connection diagram of a level conversion circuit implemented by a dual MOS tube of the present invention.

[0055] Figure 5This is a connection diagram of a level conversion circuit implemented by a single MOS tube of the present invention. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] It should be understood that the step numbers used in this document are only for convenience of description and are not intended to limit the order in which the steps are executed.

[0058] It should be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0059] The terms “include” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0060] The term "and / or" means and includes any and all possible combinations of one or more of the associated listed items.

[0061] Embodiment 1:

[0062] In this embodiment, the third transistor is Figure 3 Q3, Figure 3 The VCC in the figure is the power supply (in this embodiment, the power supply VCC is 1.8V), and the first capacitor is Figure 3 As shown in C1, the eighth resistor is Figure 3 As shown in R8, the seventh resistor is Figure 3 As shown in R7, the second conversion level is Figure 3 VDD shown;

[0063] The thirteenth resistor is Figure 4 As shown in R13, the fourteenth resistor is Figure 4 As shown in R14, the fifteenth resistor is Figure 4 As shown in R15, the eighteenth resistor is Figure 4 As shown in R18, the first MOS tube is Figure 4 As shown in Q5, the second MOS tube is Figure 4As shown in Q6, the third conversion level is Figure 4 VDD shown.

[0064] See also Figure 1 , the present invention provides a communication level adaptation method, which is used to connect a first circuit and a second circuit, wherein the output interface and the input interface of the first circuit and the second circuit have the same or different levels, and is characterized in that the first circuit includes a first level conversion circuit, and the second circuit includes a second level conversion circuit;

[0065] The output end of the first level conversion circuit is connected to the input communication interface of the first circuit, and the input end of the first level conversion circuit is connected to the output communication interface of the second circuit;

[0066] The output end of the second level conversion circuit is connected to the input communication interface of the second circuit, and the input end of the second level conversion circuit is connected to the output communication interface of the first circuit;

[0067] The first level conversion circuit is capable of converting an input signal into an input signal of a level required by an input communication interface of the first circuit;

[0068] The second level conversion circuit can convert the input signal into an input signal of the level required by the input communication interface of the second circuit. In this way, the level of the present circuit and the level of the target circuit can be independent of each other, and the level adjustment of one party will not affect the actual communication. At the same time, the connection and communication between any two of multiple circuit systems with different levels can be realized, which can greatly improve the versatility.

[0069] As a preferred embodiment, the level of the input signal input to the first level conversion circuit or the second level conversion circuit is 1.8V-5.5V. The level conversion circuit can receive input signals of any level in the range of 1.8v-5.5v and convert them into the level required by the input communication interface of this circuit. This adaptive characteristic enables the circuit to easily cope with devices with different voltage standards without worrying about communication barriers caused by level mismatch.

[0070] See also Figure 3 As a preferred implementation, the first level conversion circuit or the second level conversion circuit is implemented by a single triode, specifically:

[0071] The level conversion circuit (the level conversion circuit described in this embodiment represents the first level conversion circuit or the second level conversion circuit) includes a third transistor, and the emitter of the third transistor serves as the input end of the level conversion circuit (refer to Figure 3 INPUT as shown);

[0072] The base of the third transistor is connected to a power supply (in this embodiment, the power supply VCC is 1.8V) through an eighth resistor, the first capacitor is connected in parallel to both ends of the eighth resistor, and the collector of the third transistor serves as the output end of the level conversion circuit;

[0073] The second conversion level is connected to the output terminal (reference Figure 3 OUTPUT) connection shown;

[0074] The second conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

[0075] When the input terminal INPUT of the level conversion circuit is at high level 1 (any level between 1.8V and 5.5V), transistor Q3 V BE is less than 0.7V, the transistor Q3 works in the cut-off state, and the collector level of the transistor Q3 is equal to the second conversion level VDD voltage, that is, high level 1;

[0076] When the input terminal INPUT of the level conversion circuit is low level 0, the transistor Q3 V BE When the voltage is greater than 0.7V, the transistor Q3 works in a saturated conduction state, and the voltage value at the output terminal OUTPUT of the level conversion circuit approaches the voltage value at the input terminal INPUT of the level conversion circuit, that is, a low level 0.

[0077] See also Figure 4 As a preferred implementation, the first level conversion circuit or the second level conversion circuit is implemented by a dual MOS tube, specifically:

[0078] The level conversion circuit (the level conversion circuit described in this embodiment represents the first level conversion circuit or the second level conversion circuit) includes a thirteenth resistor, one end of the thirteenth resistor is connected to the gate of the first MOS tube, and the other end is used as the input end of the level conversion circuit (refer to Figure 4 The source of the first MOS tube is grounded; the fourteenth resistor is connected in parallel between the gate and the source of the first MOS tube;

[0079] The drain of the first MOS tube is connected to the gate of the second MOS tube, one end of the fifteenth resistor is connected to the drain of the first MOS tube, and the other end is connected to the third conversion level;

[0080] The source of the second MOS tube is grounded, and the drain of the second MOS tube serves as the output end of the level conversion circuit (refer to Figure 3 OUTPUT shown), one end of the eighteenth resistor is connected to the drain of the second MOS tube, and the other end is connected to the third conversion level;

[0081] The third conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

[0082] When the input terminal INPUT of the level conversion circuit is 1 (any level between 1.8V and 5.5V), the MOS tube Q5 is in the on working state, the drain and source of the MOS tube Q5 are turned on, the gate of the MOS tube Q6 is at 0 level, and in the off working state, it is not turned on, and the level of the output terminal OUTPUT of the level conversion circuit is the third conversion level VDD value, that is, the output terminal OUTPUT of the level conversion circuit is 1.

[0083] When the input terminal INPUT of the level conversion circuit is 0, the MOS tube Q5 is in the cut-off working state and is not conducting, the voltage of the drain D of the MOS tube Q5 is the third conversion level VDD, the MOS tube Q6 is in the conducting working state, the drain of Q6 is connected to the ground, and the output terminal OUTPUT of the level conversion circuit is 0.

[0084] Embodiment 2:

[0085] In this embodiment, the first resistor is Figure 2 The second resistor is shown as R1. Figure 2 The third resistor is R2 shown as Figure 2 The fourth resistor is R3 shown as Figure 2 The fifth resistor is R4 shown as Figure 2 As shown in R5, the first transistor is Figure 2 The second transistor is Q1 shown Figure 2 As shown for Q2, the first transition level is Figure 2 VDD shown;

[0086] The third transistor is Figure 3 Q3, Figure 3 The VCC in the figure is the power supply (in this embodiment, the power supply VCC is 1.8V), and the first capacitor is Figure 3 As shown in C1, the eighth resistor is Figure 3 As shown in R8, the seventh resistor is Figure 3 As shown in R7, the second conversion level is Figure 3 VDD shown;

[0087] The thirteenth resistor is Figure 4 As shown in R13, the fourteenth resistor is Figure 4 As shown in R14, the fifteenth resistor is Figure 4 As shown in R15, the eighteenth resistor is Figure 4 As shown in R18, the first MOS tube is Figure 4 As shown in Q5, the second MOS tube is Figure 4As shown in Q6, the third conversion level is Figure 4 VDD shown;

[0088] Figure 5 The VCC shown is a power supply (in this embodiment, the power supply VCC is 1.8V), and the third MOS tube is Figure 4 As shown in Q7, the fourth conversion level is Figure 5 The VDD shown, the twenty-second resistor is Figure 5 R22 shown.

[0089] See also Figure 1 , the present invention also provides a communication level adaptive circuit, which can be connected to a target circuit of any output and input level, characterized in that it includes a level conversion circuit, the output end of which is connected to the input communication interface of the circuit, and the input end is connected to the output communication interface of the target circuit;

[0090] The target circuit includes a target level conversion circuit, the output end of the target level conversion circuit is connected to the input communication interface of the target circuit, and the input end is connected to the output communication interface of the circuit;

[0091] The level conversion circuit can convert an input signal of any level into an input signal of the level required by the input communication interface of the circuit;

[0092] The target level conversion circuit can convert an input signal of any level into an input signal of the level required by the input communication interface of the target circuit. In this way, the level of the circuit and the level of the target circuit are independent of each other, and the level adjustment of one party will not affect the actual communication. At the same time, the connection and communication between any two of multiple circuit systems with different levels can be realized, which can greatly improve the versatility.

[0093] As a preferred embodiment, the level of the input signal input to the level conversion circuit or the target level conversion circuit is 1.8V-5.5V. The level conversion circuit can receive input signals of any level in the range of 1.8v-5.5v and convert them into the level required by the input communication interface of this circuit. This adaptive characteristic enables the circuit to easily cope with devices with different voltage standards without worrying about communication barriers caused by level mismatch.

[0094] See also Figure 2 As a preferred implementation, the level conversion circuit is implemented by a dual triode, specifically:

[0095] The level conversion circuit includes a first resistor, one end of the first resistor is connected to the base of the first transistor, and the other end of the first resistor is used as the input end of the level conversion circuit (reference Figure 2The emitter of the first transistor is grounded; the second resistor is connected in parallel between the emitter and the base of the first transistor;

[0096] The collector of the first triode is connected to the base of the second triode through a fifth resistor, one end of the third resistor is connected to the collector of the first triode, and the other end is connected to the first conversion level;

[0097] The emitter of the second transistor is grounded, and the collector of the second transistor serves as the output end of the level conversion circuit (reference Figure 2 OUTPUT shown), one end of the fourth resistor is connected to the collector of the second transistor, and the other end is connected to the first conversion level;

[0098] The first conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

[0099] When the input terminal INPUT of the level conversion circuit is 1 (any level between 1.8V and 5.5V), transistor Q1 V BE The voltage is greater than the transistor conduction voltage 0.7V, the transistor works in saturation state, that is, conduction state, the voltage of the collector C of the transistor Q1 is close to the emitter E, that is, 0, then the collector of the transistor Q2 is 0, the transistor Q2 works in the cut-off state, not conducting, and the level of the output terminal OUTPUT of the level conversion circuit is the value of the first conversion level VDD, that is, 1;

[0100] When the input terminal INPUT of the level conversion circuit is 0, the transistor Q1 V BE The voltage is less than the transistor conduction voltage 0.7V, the transistor works in the cut-off state, the transistor is not conducting, the voltage of the collector C of the transistor Q1 is equal to the first conversion level VDD, then the transistor Q2 V BE Greater than the on-state voltage 0.7V, transistor Q2 works in saturated conduction state, the transistor is on, Q2 V CE is very small, close to 0, then the output terminal OUTPUT of the level conversion circuit is 0.

[0101] See also Figure 3 As a preferred implementation, the level conversion circuit is implemented by a single triode, specifically:

[0102] The level conversion circuit includes a third transistor, and the emitter of the third transistor serves as the input end of the level conversion circuit (reference Figure 3 INPUT as shown);

[0103] The base of the third transistor is connected to a power supply (in this embodiment, the power supply VCC is 1.8V) through an eighth resistor, the first capacitor is connected in parallel to both ends of the eighth resistor, and the collector of the third transistor serves as the output end of the level conversion circuit;

[0104] The second conversion level is connected to the output terminal (reference Figure 3 OUTPUT) connection shown;

[0105] The second conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

[0106] When the input terminal INPUT of the level conversion circuit is at high level 1 (any level between 1.8V and 5.5V), transistor Q3 V BE is less than 0.7V, the transistor Q3 works in the cut-off state, and the collector level of the transistor Q3 is equal to the second conversion level VDD voltage, that is, high level 1;

[0107] When the input terminal INPUT of the level conversion circuit is low level 0, the transistor Q3 V BE When the voltage is greater than 0.7V, the transistor Q3 works in a saturated conduction state, and the voltage value at the output terminal OUTPUT of the level conversion circuit approaches the voltage value at the input terminal INPUT of the level conversion circuit, that is, a low level 0.

[0108] See also Figure 4 As a preferred implementation, the level conversion circuit is implemented by a dual MOS tube, specifically:

[0109] The level conversion circuit includes a thirteenth resistor, one end of the thirteenth resistor is connected to the gate of the first MOS tube, and the other end is used as the input end of the level conversion circuit (reference Figure 4 The source of the first MOS tube is grounded; the fourteenth resistor is connected in parallel between the gate and the source of the first MOS tube;

[0110] The drain of the first MOS tube is connected to the gate of the second MOS tube, one end of the fifteenth resistor is connected to the drain of the first MOS tube, and the other end is connected to the third conversion level;

[0111] The source of the second MOS tube is grounded, and the drain of the second MOS tube serves as the output end of the level conversion circuit (refer to Figure 4 OUTPUT shown), one end of the eighteenth resistor is connected to the drain of the second MOS tube, and the other end is connected to the third conversion level;

[0112] The third conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

[0113] When the input terminal INPUT of the level conversion circuit is 1 (any level between 1.8V and 5.5V), the MOS tube Q5 is in the on working state, the drain and source of the MOS tube Q5 are turned on, the gate of the MOS tube Q6 is at 0 level, and in the off working state, it is not turned on, and the level of the output terminal OUTPUT of the level conversion circuit is the third conversion level VDD value, that is, the output terminal OUTPUT of the level conversion circuit is 1.

[0114] When the input terminal INPUT of the level conversion circuit is 0, the MOS tube Q5 is in the cut-off working state and is not conducting, the voltage of the drain D of the MOS tube Q5 is the third conversion level VDD, the MOS tube Q6 is in the conducting working state, the drain of Q6 is connected to the ground, and the output terminal OUTPUT of the level conversion circuit is 0.

[0115] See also Figure 5 As a preferred implementation, the level conversion circuit is implemented by a single MOS tube, specifically:

[0116] The level conversion circuit includes a third MOS tube, and the source of the third MOS tube serves as the input end of the level conversion circuit (reference Figure 5 INPUT as shown);

[0117] The gate of the third MOS tube is connected to a power supply (in this embodiment, the power supply VCC is 1.8V), and the drain of the third MOS tube serves as the output end of the level conversion circuit;

[0118] The fourth conversion level is connected to the output terminal (reference Figure 5 OUTPUT) connection shown;

[0119] The fourth conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

[0120] When the input terminal INPUT of the level conversion circuit is at a high level 1 (any level between 1.8V and 5.5V), the MOS tube Q7 is in a cut-off working state, and the drain level of the MOS tube Q7 is the fourth conversion level VDD voltage, that is, the high level 1;

[0121] When INPUT is at a low level of 0 and the MOS tube Q7 is in the on working state, the drain and source of the MOS tube Q7 are turned on, and the level of the output terminal OUPUT of the level conversion circuit is equal to the level of the input terminal INPUT of the level conversion circuit, that is, low level 0.

[0122] In the embodiments of the present application, the present patent is not limited to serial communication, such as SPI, parallel port, and other communication protocol interfaces based on the combination of multiple IO ports all belong to the protection scope of this patent. "At least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, c can be single or multiple.

[0123] Those of ordinary skill in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented in a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0124] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0125] In several embodiments provided in the present application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory; hereinafter referred to as: ROM), random access memory (Random Access Memory; hereinafter referred to as: RAM), disk or optical disk, and other media that can store program codes.

[0126] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A communication level adaptive method, used to connect a first circuit and a second circuit, wherein the output interface and the input interface of the first circuit and the second circuit have the same or different levels, characterized in that: The first circuit includes a first level conversion circuit, and the second circuit includes a second level conversion circuit; The output end of the first level conversion circuit is connected to the input communication interface of the first circuit, and the input end of the first level conversion circuit is connected to the output communication interface of the second circuit; The output end of the second level conversion circuit is connected to the input communication interface of the second circuit, and the input end of the second level conversion circuit is connected to the output communication interface of the first circuit; The first level conversion circuit is capable of converting an input signal into an input signal of a level required by an input communication interface of the first circuit; The second level conversion circuit can convert the input signal into an input signal of a level required by the input communication interface of the second circuit.

2. The communication level adaptive method according to claim 1, characterized in that: The level of the input signal input to the first level conversion circuit or the second level conversion circuit is 1.8V-5.5V.

3. The communication level adaptive method according to claim 1 or 2, characterized in that: The first level conversion circuit or the second level conversion circuit is implemented by a single triode, specifically: The level conversion circuit includes a third triode, and the emitter of the third triode serves as the input end of the level conversion circuit; The base of the third transistor is connected to the power supply through the eighth resistor, the first capacitor is connected in parallel to both ends of the eighth resistor, and the collector of the third transistor serves as the output end of the level conversion circuit; The second conversion level is connected to the output end of the level conversion circuit through a seventh resistor; The second conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

4. The communication level adaptive method according to claim 1 or 2, characterized in that: The first level conversion circuit or the second level conversion circuit is implemented by a dual MOS tube, specifically: The level conversion circuit includes a thirteenth resistor, one end of the thirteenth resistor is connected to the gate of the first MOS tube, and the other end is used as the input end of the level conversion circuit, and the source of the first MOS tube is grounded; a fourteenth resistor is connected in parallel to the gate and source of the first MOS tube; The drain of the first MOS tube is connected to the gate of the second MOS tube, one end of the fifteenth resistor is connected to the drain of the first MOS tube, and the other end is connected to the third conversion level; The source of the second MOS tube is grounded, the drain of the second MOS tube serves as the output end of the level conversion circuit, one end of the eighteenth resistor is connected to the drain of the second MOS tube, and the other end is connected to the third conversion level; The third conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

5. A communication level adaptive circuit, capable of connecting to a target circuit of any output or input level, characterized in that: A level conversion circuit is included, wherein the output end of the level conversion circuit is connected to the input communication interface of the circuit, and the input end is connected to the output communication interface of the target circuit; The target circuit includes a target level conversion circuit, the output end of the target level conversion circuit is connected to the input communication interface of the target circuit, and the input end is connected to the output communication interface of the circuit; The level conversion circuit can convert an input signal of any level into an input signal of the level required by the input communication interface of the circuit; The target level conversion circuit can convert an input signal of any level into an input signal of a level required by an input communication interface of the target circuit.

6. The communication level adaptive circuit according to claim 5, characterized in that: The level of the input signal input to the level conversion circuit or the target level conversion circuit is 1.8V-5.5V.

7. The communication level adaptive circuit according to claim 5 or 6, characterized in that: The level conversion circuit is implemented by a dual triode, specifically: The level conversion circuit includes a first resistor, one end of the first resistor is connected to the base of the first triode, and the other end is used as the input end of the level conversion circuit, and the emitter of the first triode is grounded; a second resistor is connected in parallel between the emitter and the base of the first triode; The collector of the first triode is connected to the base of the second triode through a fifth resistor, one end of the third resistor is connected to the collector of the first triode, and the other end is connected to the first conversion level; The emitter of the second triode is grounded, the collector of the second triode serves as the output end of the level conversion circuit, one end of the fourth resistor is connected to the collector of the second triode, and the other end is connected to the first conversion level; The first conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

8. The communication level adaptive circuit according to claim 5 or 6, characterized in that: The level conversion circuit is implemented by a single triode, specifically: The level conversion circuit includes a third triode, and the emitter of the third triode serves as the input end of the level conversion circuit; The base of the third transistor is connected to the power supply through the eighth resistor, the first capacitor is connected in parallel to both ends of the eighth resistor, and the collector of the third transistor serves as the output end of the level conversion circuit; The second conversion level is connected to the output end of the level conversion circuit through a seventh resistor; The second conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

9. The communication level adaptive circuit according to claim 5 or 6, characterized in that: The level conversion circuit is implemented by dual MOS tubes, specifically: The level conversion circuit includes a thirteenth resistor, one end of the thirteenth resistor is connected to the gate of the first MOS tube, and the other end is used as the input end of the level conversion circuit, and the source of the first MOS tube is grounded; a fourteenth resistor is connected in parallel to the gate and source of the first MOS tube; The drain of the first MOS tube is connected to the gate of the second MOS tube, one end of the fifteenth resistor is connected to the drain of the first MOS tube, and the other end is connected to the third conversion level; The source of the second MOS tube is grounded, the drain of the second MOS tube serves as the output end of the level conversion circuit, one end of the eighteenth resistor is connected to the drain of the second MOS tube, and the other end is connected to the third conversion level; The third conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

10. The communication level adaptive circuit according to claim 5 or 6, characterized in that: The level conversion circuit is implemented by a single MOS tube, specifically: The level conversion circuit includes a third MOS tube, and the source of the third MOS tube serves as an input end of the level conversion circuit; The gate of the third MOS tube is connected to the power supply, and the drain of the third MOS tube serves as the output end of the level conversion circuit; The fourth conversion level is connected to the output end of the level conversion circuit through a twenty-second resistor; The fourth conversion level uses the digital logic power supply of the circuit to which it belongs, and reaches a voltage value equal to the voltage value of the level required by the input communication interface of the circuit to which the level conversion circuit belongs.

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