Semiconductor structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and provides a semiconductor structure and a preparation method thereof.The semiconductor structure comprises a plurality of semiconductor block structures arranged in the first direction and signal line leading-out structures located on at least one side end area of the semiconductor block structures; the signal line leading-out structure comprises a plurality of signal lines which extend in the second direction and are arranged at intervals in the third direction. The signal line comprises a main body extension part and a leading-out end part positioned at at least one end of the main body extension part; in the signal line leading-out structure, the orthographic projections of the leading-out end parts of any two signal lines on the substrate are not overlapped, and the orthographic projections of the main body extension parts of any two signal lines on the substrate are overlapped; and in the third direction and in the direction from the side close to the substrate to the side far away from the substrate, the lengths of the signal lines are sequentially reduced or sequentially increased. The semiconductor structure disclosed by the invention is relatively short in process flow and relatively low in manufacturing cost, and is convenient for leading out each signal line.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for preparing the same. Background Art

[0002] Memory is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high degree of integration and fast transmission speed. For example, the two-transistor capacitor-free dynamic random access memory (2Transistor 0Capacitor, 2T0C) uses two vertical structure transistors as the unit structure, in which the drain of one transistor is connected to the gate of the other transistor, and the gate capacitance is used to store charge and change the transistor transconductance to store information. This structure can increase the storage density by continuously increasing the number of stacked layers in the vertical direction without reducing the critical size. However, each layer of devices needs to be completed before the next layer of devices can be made. The process is long, the cost is high, and the signal line is difficult to lead out.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The present disclosure provides a semiconductor structure and a preparation method thereof, which can shorten the process flow, reduce the manufacturing cost, and facilitate the lead-out of various signal lines.

[0005] According to one aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure is prepared on a substrate. The semiconductor structure includes a plurality of semiconductor block structures arranged at intervals along a first direction. The semiconductor block structure includes two side end regions in the first direction. At least one side end region of the semiconductor block structure is provided with a signal line lead-out structure. The signal line lead-out structure includes:

[0006] A plurality of signal lines extending along a second direction and arranged at intervals along a third direction, wherein the first direction and the second direction are both parallel to the plane where the substrate is located, the first direction intersects with the second direction, and the third direction is perpendicular to the plane where the substrate is located; the signal line comprises a main extension portion and a lead-out end portion located at at least one end of the main extension portion; in the signal line lead-out structure, the orthographic projections of any two lead-out ends of the signal lines on the substrate do not overlap, and the orthographic projections of any two main extension portions of the signal lines on the substrate overlap; in the third direction and in a direction from a side close to the substrate to a side away from the substrate, the length of each of the signal lines decreases or increases in sequence.

[0007] In an exemplary embodiment of the present disclosure, the signal line lead-out structure further includes:

[0008] A connecting line connected to the lead-out end of the signal line, the connecting line extending along the third direction, and two adjacent connecting lines being insulated from each other;

[0009] When the lengths of the signal lines decrease in sequence in the third direction from the side close to the substrate to the side away from the substrate, the connecting line is connected to a side of the lead-out end portion away from the substrate; or, when the lengths of the signal lines increase in sequence in the third direction from the side close to the substrate to the side away from the substrate, the connecting line is connected to a side of the lead-out end portion close to the substrate.

[0010] In an exemplary embodiment of the present disclosure, the signal line lead-out structure is provided at two side end regions of the semiconductor block structure; each of the signal lines includes two lead-out end portions located at both ends of the main body extension portion, and each of the lead-out end portions has the same size in the second direction.

[0011] In an exemplary embodiment of the present disclosure, the material of the signal line includes polysilicon, and a metal silicide layer is provided on a lead-out surface of at least the lead-out end portion of the signal line.

[0012] In an exemplary embodiment of the present disclosure, a metal silicide layer is provided on a side of the lead-out end portion away from the center of the semiconductor block structure along the second direction.

[0013] In an exemplary embodiment of the present disclosure, a metal silicide layer is provided on a side of the signal line away from the center of the semiconductor block structure along the first direction.

[0014] In an exemplary embodiment of the present disclosure, the signal line is a word line, and the material of the metal silicide layer is CoSi2, TiSi2 or NiSi.

[0015] According to one aspect of the present disclosure, a method for preparing a semiconductor structure is provided, comprising the following steps:

[0016] providing a substrate;

[0017] Preparing a plurality of semiconductor block structures spaced apart along a first direction on the substrate, wherein the semiconductor block structure comprises two side end regions in the first direction, and at least one side end region of the semiconductor block structure is provided with a signal line lead-out structure;

[0018] Wherein, the method for preparing the signal line lead-out structure comprises:

[0019] A stacked structure is formed in the signal line lead-out structure region of the substrate, the stacked structure comprising insulating material layers and conductive material layers that are alternately stacked multiple times along a third direction; wherein the projections of the signal line lead-out structure region of the substrate and the side end region of the semiconductor block structure on the substrate overlap, the insulating material layers and the conductive material layers both extend along a second direction, the first direction and the second direction are both parallel to the plane where the substrate is located, the first direction intersects with the second direction, and the third direction is perpendicular to the plane where the substrate is located;

[0020] The stacked structure is processed by a trimming etching process to form a plurality of signal lines extending along the second direction and arranged at intervals along the third direction, wherein the signal lines include a main extension portion and a lead-out end portion located at at least one end of the main extension portion; in the signal line lead-out structure, the orthographic projections of any two of the lead-out ends of the signal lines on the substrate do not overlap, and the orthographic projections of any two of the main extension portions of the signal lines on the substrate do overlap; in the third direction and in a direction from a side close to the substrate to a side away from the substrate, the length of each of the signal lines decreases successively.

[0021] In an exemplary embodiment of the present disclosure, the number of the conductive material layers is n, the number of the insulating material layers is n+1, and n>2; in the third direction, the conductive material layers are defined as the 1st to nth conductive material layers from top to bottom, and the insulating material layers are defined as the 1st to n+1th insulating material layers from top to bottom; the stacked structure is processed by a trimming etching process to form a plurality of signal lines extending along the second direction and arranged at intervals along the third direction, including the following steps:

[0022] S1, forming a first graphic mask layer on the stacked structure, wherein the length of the first graphic mask layer in the second direction is less than the length of the first conductive material layer, and the orthographic projection of the first graphic mask layer on the stacked structure does not overlap with at least one end of the first conductive material layer;

[0023] S2, using the first graphic mask layer as a mask to etch the first insulating material layer and the first conductive material layer to expose at least one end of the second insulating material layer to form a first graphic stacked structure;

[0024] S3, forming a second graphic mask layer on the first graphic stacked structure, wherein the length of the second graphic mask layer in the second direction is less than the length of the first layer of the conductive material layer remaining after the last etching, and the orthographic projection of the second graphic mask layer on the substrate does not overlap with at least one end of the first layer of the conductive material layer remaining after the last etching;

[0025] S4, etching the exposed second insulating material layer and the second conductive material layer using the second graphic mask layer as a mask to expose at least one end of the next insulating material layer to form a second graphic stacked structure;

[0026] Repeat steps S3-S4 until at least one end of the nth insulating material layer is exposed to form an n-1th graphical stacked structure; each of the conductive material layers remaining after etching is used as a signal line, at least one end exposed in the signal line is used as the lead-out end, and the portion of the signal line that is not the lead-out end is used as a main body extension.

[0027] In an exemplary embodiment of the present disclosure, the method for preparing the signal line lead-out structure further includes:

[0028] forming a covering layer on a side of each of the lead-out ends away from the substrate;

[0029] Etching the cover layer to form a plurality of connection holes penetrating the cover layer along the third direction, wherein orthographic projections of different connection holes on the substrate at least partially overlap with orthographic projections of different lead-out ends on the substrate;

[0030] A conductive material is deposited in the connection hole to form a connection line.

[0031] In an exemplary embodiment of the present disclosure, the material of the signal line includes polysilicon, the surface of the lead-out end away from the substrate is a lead-out surface, and the method for preparing the signal line lead-out structure further includes:

[0032] removing the insulating material layer covering each of the lead-out ends in the n-1th patterned stacked structure to expose the lead-out surface of the lead-out end in the signal line and the side surface of the signal line away from the center of the semiconductor block structure along the second direction;

[0033] A metal silicide layer is formed on the lead-out surface of the lead-out end portion and the side surface away from the center of the semiconductor block structure along the second direction.

[0034] In an exemplary embodiment of the present disclosure, the material of the signal line includes polysilicon, the surface of the lead-out end away from the substrate is a lead-out surface, and the space between two adjacent semiconductor block structures is filled with insulating material. The method for preparing the signal line lead-out structure further includes:

[0035] Removing the insulating material layer covering the lead-out surface of each lead-out end portion and the insulating material between two adjacent semiconductor block structures in the n-1th patterned stacked structure to expose each lead-out surface, the side surface of the signal line away from the center of the semiconductor block structure along the second direction, and the side surface of each signal line away from the center of the semiconductor block structure along the first direction;

[0036] A metal silicide layer is formed on a lead-out surface of the lead-out end portion, a side surface of the signal line away from the center of the semiconductor block structure along the second direction, and a side surface of the signal line away from the center of the semiconductor block structure along the first direction.

[0037] The semiconductor structure and preparation method disclosed herein, multiple semiconductor block structures can be distributed laterally on the substrate surface along a first direction parallel to the substrate, and multiple semiconductor block structures can be formed simultaneously during the manufacturing process. In this process, there is no need to wait for the previous semiconductor block structure to be completed before forming another semiconductor block structure, and the manufacturing process flow is short and the manufacturing cost is low. At the same time, in the signal line lead-out structure of each semiconductor block structure, since the orthographic projections of the lead-out ends of any two signal lines on the substrate do not overlap, the orthographic projections of the main extension parts of any two signal lines on the substrate overlap; in the third direction and in the direction from the side close to the substrate to the side away from the substrate, the length of each signal line decreases or increases successively, so that each signal line arranged along the third direction is in a step shape, and the step-shaped signal line structure extends along the second direction and is arranged at intervals along the first direction, thereby realizing the signal line lead-out of multiple semiconductor block structures arranged at intervals along the first direction. In addition, the lead-out ends of each signal line are exposed, which can facilitate the subsequent preparation of connecting wires for electrically leading out the signal lines on each lead-out end through the same process, which helps to further shorten the process flow and reduce the manufacturing cost. In addition, the stepped design allows signal lines to be arranged more closely in the third direction, helping to improve space utilization.

[0038] In the semiconductor structure and its preparation method, the material of the signal line in the signal line lead-out structure includes polysilicon, thereby avoiding the problem of defects or metal residues that are easily generated when a step-shaped signal line structure is formed by etching using a metal material (such as tungsten / titanium nitride); a metal silicide layer is formed on at least the lead-out surface of the lead-out end, thereby reducing the contact resistance between the signal line and the connecting line, thereby achieving a low-resistance connection.

[0039] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0041] Figure 1 Schematic diagram of a semiconductor structure in an embodiment of the present disclosure.

[0042] Figure 2 Schematic diagram of a semiconductor shared unit structure in an embodiment of the present disclosure.

[0043] Figure 3 It is a schematic diagram of a lead-out end surface of a lead-out terminal portion covered by a metal silicide layer in an embodiment of the present disclosure.

[0044] Figure 4 It is a schematic diagram of a metal silicide layer covering a lead-out end surface of the lead-out end portion and two side surfaces of the lead-out end portion distributed along the second direction in an embodiment of the present disclosure.

[0045] Figure 5 It is a schematic diagram of a metal silicide layer covering a lead-out end surface of the lead-out end, two side surfaces of the lead-out end distributed along the second direction, and a side surface of the signal line away from the center of the semiconductor block structure along the first direction in an embodiment of the present disclosure.

[0046] Figure 6 It is a schematic diagram of the structure after completing step S1201 in the embodiment of the present disclosure.

[0047] Figure 7 Schematic diagram of the insulating filling layer in the embodiment of the present disclosure.

[0048] Figure 8 Schematic diagram of a sub-pattern in an embodiment of the present disclosure.

[0049] Fig. 9 FIG. 4 is a schematic diagram of a first opening and a signal line accommodating groove in an embodiment of the present disclosure.

[0050] Fig.10 For along Fig. 9 Cross-sectional view taken along the AA direction.

[0051] Fig.11 Schematic diagram of insulating material in an embodiment of the present disclosure.

[0052] Fig.12 It is a schematic diagram after completing step S220 in the embodiment of the present disclosure.

[0053] Fig.13 Schematic diagram of the Xth graphic mask layer during the Xth etching in an embodiment of the present disclosure.

[0054] Fig.14 Schematic diagram of the covering layer in an embodiment of the present disclosure.

[0055] Fig.15 Schematic diagram of the connection hole in the embodiment of the present disclosure.

[0056] Fig.16 2 is a cross-sectional view of a connecting line in an embodiment of the present disclosure.

[0057] Description of reference numerals:

[0058] 1. substrate; 100. semiconductor block structure; 2. first storage unit; 3. second storage unit; 4. source-drain layer; 410. source-drain unit layer; 10. first transistor; 101. first gate; 102. first gate dielectric layer; 103. first semiconductor layer; 20. second transistor; 201. second gate; 202. second gate dielectric layer; 203. second semiconductor layer; 5. signal line; 51. main extension; 52. lead-out end; 53. metal silicide layer; 510. conductive material layer; 6. first bit line; 7. second bit line; 8. Insulating material; 9, protective layer; 1030, stacked structure; 301, insulating material layer; 302, semiconductor material layer; 303, insulating filling layer; 30, connecting line; 40, patterned film layer stacking structure; 401, first pattern; 402, second pattern; 4021, sub-pattern; 403, first opening; 404, first transistor accommodating groove; 405, signal line accommodating groove; 50, etching stop layer; 60, covering layer; 61, connecting hole; 70, Xth graphic mask layer; x, first direction; y, second direction; z, third direction. DETAILED DESCRIPTION

[0059] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0060] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0061] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second", "third" ... "nth", etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0062] With the rapid development of the semiconductor industry, the storage density requirements for memory are increasing. However, the traditional 1T1C (i.e., one transistor and one capacitor) structure faces severe challenges in improving storage density. The reduction of its key dimensions is limited by the lithography capability limit of the lithography machine, and it is difficult to continue to shrink. At the same time, it is difficult to achieve three-dimensional stacking in the 1T1C structure, and the improvement of storage density is therefore severely restricted by the key dimensions. In order to break through this bottleneck, those skilled in the art will turn their research focus to the 2T0C (i.e., two transistors, no capacitor) structure. In the existing vertically structured 2T0C DRAM memory, the transistor channel in the storage unit is perpendicular to the substrate, and a significant improvement in storage density is achieved by stacking the storage function layers in sequence. However, the process flow of the stacked storage function layers is long and the manufacturing cost is high.

[0063] The present disclosure provides a semiconductor structure, which is prepared on a substrate 1. Figure 1 A schematic diagram of a semiconductor structure of the present disclosure is shown, Figure 1 As shown, the semiconductor structure includes a plurality of semiconductor block structures 100 arranged at intervals along a first direction x, the semiconductor block structure 100 includes two side end regions in the first direction x, at least one side end region of the semiconductor block structure 100 is provided with a signal line lead-out structure, and the signal line lead-out structure includes:

[0064] A plurality of signal lines 5 extending along a second direction y and arranged at intervals along a third direction z, wherein the first direction x and the second direction y are both parallel to the plane where the substrate 1 is located, the first direction x intersects with the second direction y, and the third direction z is perpendicular to the plane where the substrate 1 is located; the signal line 5 comprises a main body extension portion 51 and a lead-out end portion 52 located at at least one end of the main body extension portion 51; in the signal line lead-out structure, the orthographic projections of the lead-out ends 52 of any two signal lines 5 on the substrate 1 do not overlap, and the orthographic projections of the main body extension portions 51 of any two signal lines 5 on the substrate 1 do overlap; in the third direction z and in a direction from a side close to the substrate 1 to a side away from the substrate 1, the lengths of the signal lines 5 decrease or increase in sequence.

[0065] It should be noted that the signal line lead-out structure is set according to the side end area structure of the semiconductor block structure 100. If both side end areas of the semiconductor block structure 100 have signal line structures that need to be led out, it is necessary to set a signal line lead-out structure in each of the two side end areas; if only one side end area of ​​the semiconductor block structure 100 has a signal line structure that needs to be led out, it is only necessary to set one signal line lead-out structure.

[0066] In the semiconductor structure disclosed in the present invention, multiple semiconductor block structures 100 can be distributed on the surface of the substrate 1 in a horizontal direction x parallel to the substrate 1. During the manufacturing process, multiple semiconductor block structures 100 can be formed simultaneously. In this process, there is no need to wait for the previous semiconductor block structure 100 to be completed before forming another semiconductor block structure 100. The manufacturing process is short and the manufacturing cost is low. At the same time, since the orthographic projections of the lead-out ends 52 of any two signal lines 5 on the substrate 1 do not overlap, the orthographic projections of the main extension parts 51 of any two signal lines 5 on the substrate 1 do overlap; in the third direction z and in the direction from the side close to the substrate 1 to the side away from the substrate 1, the length of each signal line 5 decreases or increases in sequence, so that each signal line 5 arranged along the third direction z is in a step shape, and the step-shaped signal line structure extends along the second direction y and is arranged at intervals along the first direction x, realizing the signal line lead-out of multiple semiconductor block structures arranged at intervals along the first direction x. Furthermore, the lead-out end 52 of each signal line 5 is exposed, which facilitates the subsequent preparation of the connection line 30 for electrically leading out the signal line 5 on each lead-out end 52 through the same process, which helps to further shorten the process flow and reduce the manufacturing cost. In addition, the stepped design allows the signal lines 5 to be arranged more closely in the third direction z, which helps to improve space utilization.

[0067] The following is a description of the various parts of the semiconductor structure disclosed herein and their specific details:

[0068] In an exemplary embodiment of the present disclosure, the semiconductor block structure 100 may include a plurality of semiconductor common unit structures located on a substrate 1, wherein: the substrate 1 may be a flat plate structure, for example, it may be a flat plate structure. The substrate 1 may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, for example, its material may be silicon, but is not limited to silicon or other semiconductor materials, and the shape and material of the substrate 1 are not specifically limited herein. Figure 2 As shown, the semiconductor shared unit structure may include a first storage unit 2 and a second storage unit 3, the first storage unit 2 and the second storage unit 3 may be formed on a substrate 1, the first storage unit 2 and the second storage unit 3 may both be 2T0C (i.e., including two transistors and no capacitor) structures, the first storage unit 2 may be distributed side by side with the second storage unit 3 in a mirror-like manner along a first direction x, the first direction x may be parallel to the surface of the substrate 1, and the first storage unit 2 may share the same source-drain unit layer 410 with the second storage unit 3, which may reduce the area of ​​the region where the first storage unit 2 and the second storage unit 3 are located, thereby improving the device integration and thereby improving the storage density of the memory.

[0069] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 2 As shown, the first storage unit 2 and the second storage unit 3 both include a first transistor 10 and a second transistor 20, wherein:

[0070] The first transistor 10 is located above the top surface of the substrate 1. The first transistor 10 may be a CAA (Channel-All-Around) structure transistor and the channel is parallel to the plane where the substrate 1 is located and may extend along the first direction x. The first transistor 10 may include: a first gate 101, a first gate dielectric layer 102 and a first semiconductor layer 103. The first gate 101 may be in a strip shape and may extend along the first direction x. The material of the first gate 101 may be a conductive material, for example, the material of the first gate 101 may be indium zinc oxide (IZO) or polysilicon. The first gate dielectric layer 102 may conformally cover the sidewall and one end of the first gate 101. The material of the first gate dielectric layer 102 may be a material with a high dielectric constant, for example, it may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide or a mixture thereof. Of course, it may also be other materials, which are not listed here one by one. The first semiconductor layer 103 may conformally cover the surface of the first gate dielectric layer 102, and the first semiconductor layer 103 may include a first source and drain region, a first channel region, and a second source and drain region sequentially distributed along the first direction x, wherein the first source and drain region is located on a side of the first channel region away from the source and drain unit layer 410, and the second source and drain region is located on a side of the first channel region close to the source and drain unit layer 410. The material of the first semiconductor layer 103 and the material of the first gate 101 may be matched with each other; for example, when the material of the first semiconductor layer 103 may be indium gallium zinc oxide (IGZO), the material of the first gate 101 may be indium zinc oxide (IZO) or polysilicon.

[0071] Optionally, the material of the first semiconductor layer 103 of the present invention is indium gallium zinc oxide (IGZO). Compared with the traditional method of using single crystal silicon as the material of the first semiconductor layer 103, the present invention uses indium gallium zinc oxide (IGZO) as the material of the first semiconductor layer 103. This is because the off-state current of the IGZO thin film transistor (Thin Film Transistor-TFT) is extremely small, and its use in 2T0C DRAM storage cells can significantly reduce the leakage rate, help reduce device power consumption, and improve device reliability.

[0072] The second transistor 20 may also be located above the top surface of the substrate 1. The second transistor 20 may be a CAA structure transistor and the channel is parallel to the plane where the substrate 1 is located, and may extend along the first direction x. The second transistor 20 may be arranged side by side with the first transistor 10 along the first direction x, that is, the second transistor 20 and the first transistor 10 are laterally arranged on the surface of the substrate 1. The second transistor 20 may include a second gate 201, a second gate dielectric layer 202, and a second semiconductor layer 203. The second gate 201 may be in a strip shape and may extend along the first direction x. For example, the second gate 201 and the first gate 101 may be arranged in sequence along the first direction x. The material of the second gate 201 may be a conductive material, for example, it may be indium zinc oxide (IZO) or polysilicon. The material of the second gate 201 may be the same as or different from that of the first gate 101. For example, the materials of the second gate 201 and the first gate 101 may both be polysilicon; or, the material of the second gate 201 is indium zinc oxide (IZO), and the material of the first gate 101 is polysilicon. The second gate dielectric layer 202 can conformally cover the sidewalls of the second gate 201 and the end of the second gate 201 away from the first transistor 10. The material of the second gate dielectric layer 202 can be a material with a high dielectric constant, for example, it can be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide or a mixture thereof, and of course, it can also be other materials, which are not listed here. It should be noted that the material of the second gate dielectric layer 202 can be the same as that of the first gate dielectric layer 102. The second semiconductor layer 203 may conformally cover the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 includes a third source-drain region, a second channel region, and a fourth source-drain region sequentially distributed along the first direction x, wherein the third source-drain region is located on a side of the second channel region away from the source-drain unit layer 410, and the fourth source-drain region is located on a side of the second channel region close to the source-drain unit layer 410; the material of the second semiconductor layer 203 and the material of the second gate 201 may be matched with each other; for example, when the material of the second gate 201 is indium zinc oxide (IZO), the material of the second semiconductor layer 203 may be indium gallium zinc oxide (IGZO); when the material of the second gate 201 is polycrystalline silicon, the material of the second semiconductor layer 203 may be single crystal silicon. In some embodiments of the present disclosure, the material of the second semiconductor layer 203 may be the same as that of the first semiconductor layer 103, for example, the material of the second semiconductor layer 203 and the material of the first semiconductor layer 103 may both be indium gallium zinc oxide.

[0073] In an exemplary embodiment of the present disclosure, the first transistor 10 may be a write transistor, and the second transistor 20 may be a read transistor. The second source and drain region of the first transistor 10 may be conductively connected to the second gate 201 of the second transistor 20 through a semiconductor material (e.g., indium zinc oxide). The charge in the gate capacitance of the second transistor 20 (i.e., the read transistor) is changed by the first transistor 10 (i.e., the write transistor), thereby affecting the resistance state between the source and drain of the second transistor 20 (i.e., the read transistor), thereby achieving the distinction between "0" and "1".

[0074] In an exemplary embodiment of the present disclosure, the source-drain unit layer 410 may extend in a direction perpendicular to the substrate 1, that is, the plane where the source-drain unit layer 410 is located is perpendicular to the first direction x, and the fourth source-drain region in the first storage unit 2 and the fourth source-drain region in the second storage unit 3 are respectively connected to two opposite surfaces of the source-drain unit layer 410 distributed along the first direction x. Such a design can ensure that the signal paths and conditions received by the first storage unit 2 and the second storage unit 3 are consistent, which helps to reduce reading errors and data inconsistencies caused by differences in signal transmission.

[0075] In some embodiments of the present disclosure, multiple semiconductor common unit structures may be arranged along the second direction y and the third direction z. For example, multiple semiconductor common unit structures may form multiple common unit structure groups arranged along the third direction z, and each common unit structure group may include multiple semiconductor common unit structures arranged along the second direction y.

[0076] The second direction y is parallel to the substrate 1 and intersects with the first direction x. For example, the second direction y may be perpendicular to the first direction x, and the third direction z is perpendicular to the first direction x and the second direction y. It should be noted that parallel can be absolutely parallel or approximately parallel; similarly, perpendicular can be absolutely perpendicular or approximately perpendicular. Deviations are inevitable in the manufacturing process. In the present disclosure, the angle deviation may be caused by the limitation of the manufacturing process, so that the angle between the first direction x (or the second direction y) and the surface of the substrate 1 has a certain deviation, or the angle between the third direction z and the first direction x (or the second direction y) shows a certain deviation. As long as the angle deviation is within the preset range, the first direction x (or the second direction y) can be considered to be parallel to the substrate 1; or, the third direction z can be considered to be perpendicular to the first direction x (or the second direction y). For example, the preset range may be 10°, that is, when the angle between the first direction x (or the second direction y) and the surface of the substrate 1 is less than or equal to 10°, the first direction x (or the second direction y) may be considered to be parallel to the surface of the substrate 1; when the angle between the third direction z and the first direction x (or the second direction y) is greater than or equal to 80° and less than or equal to 100°, the third direction z may be considered to be perpendicular to the first direction x (or the second direction y).

[0077] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 1 As shown, the semiconductor block structure 100 may also include a plurality of first bit lines 6 extending along a third direction z and arranged along a first direction x and a second direction y, and a plurality of second bit lines 7 extending along a third direction z and arranged along a first direction x and a second direction y, each first bit line 6 being wrapped around the periphery of a row of first source and drain regions arranged along the third direction z in the same plane; each second bit line 7 being wrapped around the periphery of a row of third source and drain regions arranged along the third direction z in the same plane.

[0078] For example, the semiconductor common block structure may include a plurality of bit line groups spaced along the second direction y, each bit line group may include two first bit lines 6, the two first bit lines 6 may be spaced along the first direction x, one of the first bit lines 6 may be wrapped around the periphery of a row of first source and drain regions arranged along the third direction z in each first storage unit 2 in a plurality of common unit structure groups arranged along the third direction z; the other first bit line 6 may be wrapped around the periphery of a row of first source and drain regions arranged along the third direction z in each second storage unit 3 in a plurality of common unit structure groups arranged along the third direction z. It should be noted that different semiconductor common unit structures arranged along the second direction y are respectively provided with a corresponding bit line group, and each first bit line 6 in different bit line groups may be spaced and distributed in parallel along the second direction y.

[0079] Please continue to see Figure 1 As shown, each bit line group may further include two second bit lines 7, and the two second bit lines 7 may be spaced apart along the first direction x, wherein one second bit line 7 may be wrapped around the periphery of a row of third source and drain regions arranged along the third direction z in each first storage unit 2 in a plurality of shared unit structure groups arranged along the third direction z; the other second bit line 7 may be wrapped around the periphery of a row of third source and drain regions arranged along the third direction z in each second storage unit 3 in a plurality of shared unit structure groups arranged along the third direction z. It should be noted that each second bit line 7 in different bit line groups may be spaced apart and distributed in parallel along the second direction y.

[0080] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 1As shown, the semiconductor block structure 100 includes two side end regions in the first direction x, and both of the two side end regions have signal line structures that need to be led out, so the two side end regions are provided with signal line lead-out structures, and the signal line lead-out structures include a plurality of signal lines 5 extending along the second direction y and arranged at intervals along the third direction z, that is, the region where the signal lines 5 in the semiconductor block are located is the side end region. For example, each common unit structure group may include two signal lines 5, and the two signal lines 5 may be arranged at intervals along the first direction x, wherein one signal line 5 may be contacted and connected with all ends of a row of first gate electrodes 101 arranged along the second direction y in all first storage cells 2 in the same common unit structure group that are not covered by the first gate dielectric layer 102; and the other signal line 5 may be contacted and connected with all ends of a row of first gate electrodes 101 arranged along the second direction y in all second storage cells 3 in the same common unit structure group that are not covered by the first gate dielectric layer 102. The signal lines 5 connected to the first storage cells 2 in the multiple common unit structure groups arranged along the third direction z may be arranged at intervals along the third direction z. For example, the signal line 5 may be a word line. The material of the signal line 5 may be at least one of tungsten, copper, aluminum, tungsten nitride, titanium, titanium nitride or polysilicon. Of course, the material of the signal line 5 may also be other materials with good conductivity, which are not listed here one by one.

[0081] In some embodiments of the present disclosure, the signal line 5 may include a main extension portion 51 and a lead-out end portion 52 located at at least one end of the main extension portion 51; in the signal line lead-out structure, the orthographic projections of the lead-out ends 52 of any two signal lines 5 on the substrate 1 do not overlap, and the orthographic projections of the main extension portions 51 of any two signal lines 5 on the substrate 1 overlap; in the third direction z and in the direction from the side close to the substrate 1 to the side away from the substrate 1, the length of each signal line 5 decreases or increases in sequence. That is, at least one end of the plurality of signal lines 5 arranged along the third direction z is in a step shape; at this time, the lead-out ends 52 of each signal line 5 are exposed.

[0082] In an exemplary embodiment of the present disclosure, the two side end regions of the semiconductor block structure 100 are provided with signal line lead-out structures, and each signal line lead-out structure includes two lead-out end portions 52 located at both ends of the main body extension portion 51 in the second direction y, and each lead-out end portion 52 has the same size in the second direction y. For example, the two lead-out end portions 52 in the same signal line 5 have the same size in the second direction y, and the lead-out end portions 52 in different signal lines 5 also have the same size in the second direction y.

[0083] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 1As shown, the signal line lead-out structure further includes a connecting line 30, which is connected to the lead-out end 52 of the signal line 5, that is, each lead-out end 52 is correspondingly provided with a connecting line 30. The material of the connecting line 30 may be a conductive material, for example, the material may be titanium nitride or a combined film structure of titanium nitride and tungsten, and the signal may be transmitted to the lead-out end 52 of the signal line 5 through the connecting line 30. For example, the connecting line 30 may extend along the third direction z, and two adjacent connecting lines 30 are insulated. When the signal line 5 includes two lead-out ends 52, the two lead-out ends 52 are provided with a connecting line 30.

[0084] In an exemplary embodiment of the present disclosure, the signal line 5 can be electrically led out at the same time through two connecting lines 30. During the signal transmission process, the two connecting lines 30 can make the signal more evenly distributed, which helps to reduce the reflection and attenuation of the signal during the transmission process, thereby improving the integrity and stability of the signal transmission. At the same time, the design of providing connecting lines 30 at both ends can balance the electromagnetic field distribution around the signal line 5 to a certain extent, reduce the impact of external electromagnetic interference on signal transmission, and improve the anti-interference ability of the circuit.

[0085] In an exemplary embodiment of the present disclosure, when the lengths of the signal lines 5 decrease in sequence in the third direction z from the side close to the substrate 1 to the side away from the substrate 1, the connection line 30 is connected to the side of the lead-out end 52 away from the substrate 1. Alternatively, when the lengths of the signal lines 5 increase in sequence in the third direction z from the side close to the substrate 1 to the side away from the substrate 1, the connection line 30 is connected to the side of the lead-out end 52 close to the substrate 1. Different connection lines 30 may be distributed in parallel and all extend along the third direction z.

[0086] In an exemplary embodiment of the present disclosure, the materials of the first gate 101 and the signal line 5 are both polysilicon, and a metal silicide layer 53 (such as Figure 3 As shown in FIG. 1 , a metal silicide layer 53 may be provided on the lead-out surface of the lead-out end portion 52 of the signal line 5 (i.e., the side of the lead-out end portion 52 connected to the connection line 30), and the connection line 30 may be in contact with and connected to the surface of the metal silicide layer 53 away from the lead-out surface. The design of the metal silicide layer 53 may help reduce the contact resistance between the connection line 30 and the lead-out end portion 52, achieve low-resistance connection, and improve signal transmission efficiency. The material of the metal silicide layer 53 may be CoSi2, TiSi2, or NiSi, etc.

[0087] In an exemplary embodiment of the present disclosure, Figure 4 As shown, a metal silicide layer 53 is provided on the side of the lead-out end portion 52 away from the center of the semiconductor block structure 100 along the second direction y; or Figure 5As shown, a metal silicide layer 53 is provided on the side of the signal line 5 away from the center of the semiconductor block structure 100 along the first direction x. The provision of the metal silicide layer 53 helps to reduce the resistance of the signal line 5 itself and the contact resistance between the signal line 5 and the surrounding structure, improve the transmission efficiency of the current in the signal line 5, and reduce energy loss.

[0088] In an exemplary embodiment of the present disclosure, the lead-out surface of the lead-out end portion 52 of the signal line 5, the side of the lead-out end portion 52 away from the center of the semiconductor block structure 100 along the second direction y, and the side of the signal line 5 away from the center of the semiconductor block structure 100 along the first direction x are all provided with a metal silicide layer 53. Such a design can greatly reduce the resistance of the signal line 5 itself and the contact resistance between the signal line 5 and other surrounding structures, improve the transmission efficiency of the signal in the transmission line, and reduce power consumption.

[0089] The reading and writing process of the semiconductor structure disclosed in the present invention is described below:

[0090] In the process of writing "1", a positive voltage (greater than the threshold voltage Vth) can be applied to the write word line WWL (i.e., signal line 5) through the connection line 30 to turn on the first transistor 10 (i.e., the write transistor), and a positive voltage can be applied to the write bit line WBL to inject charge into the gate capacitance (i.e., storage node) of the second transistor 20 (i.e., the read transistor); after the charge injection, the positive voltage applied to the write word line WWL and the positive voltage applied to the write bit line WBL are removed to save the "1" state. In the process of reading "1", a read voltage is applied to the drain of the second transistor 20 (i.e., the read transistor). Since a certain amount of charge is stored in the gate capacitance, the second transistor 20 (i.e., the read transistor) is in a relatively low resistance state, and a relatively large current is obtained, which is then amplified and identified by the peripheral circuit to complete the process of reading "1". In the process of writing "0", a positive voltage (greater than the threshold voltage Vth) is applied to the write word line WWL through the connection line 30 to turn on the first transistor 10 (i.e., the write transistor), and a negative voltage is applied to the write bit line WBL to extract charge from the gate capacitance (i.e., the storage node) of the second transistor 20 (i.e., the read transistor); after the charge is extracted, the positive voltage applied to the write word line WWL and the negative voltage applied to the write bit line WBL are removed to save the "0" state. In the process of reading "0", a read voltage is applied to the drain of the second transistor 20 (i.e., the read transistor). Since there is no charge in the gate capacitance, the second transistor 20 (i.e., the read transistor) is in a higher resistance state, and a smaller current is obtained, which is then amplified and identified by the peripheral circuit to complete the process of reading "0".

[0091] The present disclosure also provides a method for preparing a semiconductor structure. The method is used to prepare the semiconductor structure in any of the above embodiments. The method may include steps S110 and S120, wherein:

[0092] Step S110, providing a substrate 1;

[0093] Step S120, preparing a plurality of semiconductor block structures 100 arranged at intervals along a first direction x on a substrate 1, wherein the semiconductor block structure 100 includes two side end regions in the first direction x, and at least one side end region of the semiconductor block structure 100 is provided with a signal line lead-out structure;

[0094] The method for preparing the signal line lead-out structure (ie, step S120) includes:

[0095] Step S210, forming a stacked structure in the signal line lead-out structure region of the substrate 1, the stacked structure comprising insulating material layers and conductive material layers alternately stacked multiple times along the third direction z; wherein the projections of the signal line lead-out structure region of the substrate 1 and the side end region of the semiconductor block structure 100 on the substrate 1 overlap, the insulating material layers and the conductive material layers both extend along the second direction y, the first direction x and the second direction y are both parallel to the plane where the substrate 1 is located, the first direction x intersects with the second direction y, and the third direction z is perpendicular to the plane where the substrate 1 is located;

[0096] Step S220, the stacked structure is processed by a trimming etching process to form a plurality of signal lines 5 extending along the second direction y and arranged at intervals along the third direction z, the signal line 5 comprising a main extension portion 51 and a lead-out end portion 52 located at at least one end of the main extension portion 51; in the signal line lead-out structure, the orthographic projections of the lead-out ends 52 of any two signal lines 5 on the substrate 1 do not overlap, and the orthographic projections of the main extension portions 51 of any two signal lines 5 on the substrate 1 do overlap; in the third direction z and in a direction from the side close to the substrate 1 to the side away from the substrate 1, the length of each signal line 5 decreases successively.

[0097] The method for preparing the semiconductor structure disclosed in the present invention can form multiple semiconductor block structures 100 at the same time. In this process, there is no need to wait for the previous semiconductor block structure 100 to be completed before forming another semiconductor block structure 100. The process flow is short and the manufacturing cost is low. At the same time, since the orthographic projections of the lead-out ends 52 of any two signal lines 5 on the substrate 1 do not overlap, the orthographic projections of the main extension parts 51 of any two signal lines 5 on the substrate 1 do overlap; in the third direction z and in the direction from the side close to the substrate 1 to the side away from the substrate 1, the length of each signal line 5 decreases or increases in sequence, so that each signal line 5 arranged along the third direction z is in a step shape, and the step-shaped signal line structure extends along the second direction y and is arranged at intervals along the first direction x, realizing the signal line lead-out of multiple semiconductor block structures arranged at intervals along the first direction x. Furthermore, the lead-out end portion 52 of each signal line 5 is exposed, which can facilitate the subsequent preparation of the connection line 30 for electrically leading out the signal line 5 on each lead-out end portion 52 through the same process, which helps to further shorten the process flow and reduce manufacturing costs.

[0098] The steps and specific details of the method for preparing the semiconductor structure disclosed in the present invention are described in detail below:

[0099] In step S110 , a substrate 1 is provided.

[0100] The substrate 1 may be a flat plate structure, for example, it may be a flat plate structure. The substrate 1 may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, for example, its material may be silicon, but is not limited to silicon or other semiconductor materials, and the shape and material of the substrate 1 are not particularly limited here.

[0101] In step S120 , a plurality of semiconductor block structures 100 arranged at intervals along a first direction x are prepared on a substrate 1 . The semiconductor block structure 100 includes two side end regions in the first direction x, and at least one side end region of the semiconductor block structure 100 is provided with a signal line lead-out structure.

[0102] In some embodiments of the present disclosure, forming the semiconductor block structure 100 may include steps S1201 to S1207, wherein:

[0103] In step S1201, insulating material layers 301 and semiconductor material layers 302 are alternately deposited on substrate 1 in sequence, and a protective layer 9 may be formed on the surface of the topmost insulating material layer 301. The material of the insulating material layer 301 may be silicon oxide, and the material of the protective layer 9 may be silicon nitride. The structure formed by the insulating material layer 301, the semiconductor material layer 302 and the protective layer 9 may be defined as a film layer stack structure. The film layer stack structure may be patterned to form a patterned film layer stack structure 40. The pattern of the patterned film layer stack structure 40 includes a plurality of first patterns 401 extending along a first direction x and spaced apart along a second direction y, and a plurality of second patterns 402 extending along a second direction y and spaced apart along the first direction x; the first pattern 401 overlaps the second pattern 402. In the embodiment of the present disclosure, the structure after completing step S1201 is as follows: Figure 6 shown.

[0104] In an exemplary embodiment of the present disclosure, Figure 7 As shown, the insulating material can be filled in the patterned film layer stack structure 40, and the insulating material can fill the gaps in the patterned film layer stack structure 40, and the insulating material and the insulating material layer 301 together constitute the insulating filling layer 303. After the insulating filling layer 303 is formed, a protective material can be deposited on the surface of the insulating filling layer 303 and the patterned film layer stack structure 40, and the newly deposited protective material can form a new protective layer 9 together with the original protective layer 9.

[0105] In step S1202, a plurality of first openings 403 are formed along the third direction z, penetrating the patterned film layer stack structure 40, the protective layer 9 and the insulating filling layer 303. The first openings 403 are arranged in a one-to-one correspondence with the second pattern 402. The first openings 403 divide the corresponding second pattern 402 into two sub-patterns 4021 that are distributed side by side in a mirror-image manner along the first direction x. Figure 8 as shown; Fig. 9 and Fig.10 As shown, part of the semiconductor material layer 302 is etched away laterally on both sides through the first opening 403 to form a plurality of first transistor and signal line accommodating grooves, the first transistor and signal line accommodating grooves comprising a row of first transistor accommodating grooves 404 extending along the first direction x and arranged along the second direction y, and a signal line accommodating groove 405 extending along the second direction y and connecting the row of first transistor accommodating grooves 404.

[0106] In step S1203, a first semiconductor layer 103, a first gate dielectric layer 102 and a first gate material layer (not shown in the figure) are sequentially deposited in the first transistor and signal line accommodating groove; the first semiconductor layer 103 covers the sidewalls and bottom surface of the first transistor and signal line accommodating groove, the first gate dielectric layer 102 conformally covers the surface of the first semiconductor layer 103, and the first gate material layer fills the remaining space of the first transistor and signal line accommodating groove; in this process, in order to facilitate the process and ensure that the first gate material layer can fill the first transistor and signal line accommodating groove, the first semiconductor layer 103 can cover the surface of the protective layer 9 at the same time, and the first gate material layer After filling the first opening 403, the first semiconductor layer 103, the first gate dielectric layer 102 and the first gate material layer located on the top of the protective layer 9 and in the first opening 403 can be removed. The first gate material layer in the signal line accommodating groove 405 can be used as the conductive material layer 510, and the first gate material layer in the first transistor accommodating groove 404 can be used as the first gate 101. The first gate 101, the first gate dielectric layer 102 and the first semiconductor layer 103 together constitute the first transistor 10. The first semiconductor layer 103 on the first gate 101 in the first transistor 10 includes a first source and drain region, a first channel region and a second source and drain region sequentially distributed along the first direction x.

[0107] In an exemplary embodiment of the present disclosure, Fig.11 As shown, after the first transistor 10 , the second transistor 20 and the conductive material layer 510 are formed, the insulating material 8 may be filled into the first opening 403 to close the first opening 403 .

[0108] In an exemplary embodiment of the present disclosure, forming the semiconductor block structure 100 further includes:

[0109] In step S1204 , a plurality of second openings are formed along the third direction z penetrating the patterned film layer stack structure 40 . The second openings are located in the middle between two adjacent first openings 403 . The second openings are parallel to the plane where the second direction y and the third direction z are located.

[0110] In step S1205, part of the insulating filling layer 303 is etched away laterally on both sides through the second opening to form the second gate 201 of the second transistor 20, and then the second gate dielectric layer 202 and the second semiconductor layer 203 are deposited in sequence. The second gate dielectric layer 202 conformally covers the side walls of the second gate 201 and the end of the second gate 201 away from the first transistor 10, the second semiconductor layer 203 covers the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 includes a third source and drain region, a second channel region and a fourth source and drain region distributed in sequence along the first direction x.

[0111] In step S1206, the insulating material is filled between adjacent second transistors 20 to close the second openings; a plurality of third openings are formed along the third direction z through the insulating material, the third openings are located in the second openings, and the third openings expose the fourth source and drain regions in the second transistors 20, and the source and drain layers 4 can be formed in the third openings. The third openings are parallel to the plane where the second direction y and the third direction z are located.

[0112] In an exemplary embodiment of the present disclosure, forming the semiconductor block structure 100 further includes:

[0113] In step S1207, a plurality of first bit line accommodating holes and second bit line accommodating holes extending along the third direction z are formed, a first bit line 6 is formed in the first bit line accommodating hole, and a second bit line 7 is formed in the second bit line accommodating hole; each first bit line 6 is coated on the periphery of a row of first source and drain regions arranged along the third direction z in the same plane, and each second bit line 7 is coated on the periphery of a row of third source and drain regions arranged along the third direction z in the same plane.

[0114] In an exemplary embodiment of the present disclosure, a method for preparing a signal extraction structure may include steps S210 and S220, wherein:

[0115] Step S210, forming a stacked structure 1030 in the signal line lead-out structure region of the substrate 1 (please continue to refer to Figure 8 As shown), the stacked structure 1030 includes insulating material layers 301 and conductive material layers 510 that are alternately stacked multiple times along a third direction z; wherein, the projections of the signal line lead-out structure region of the substrate 1 and the side end region of the semiconductor block structure 100 on the substrate 1 overlap, the insulating material layers 301 and the conductive material layers 510 both extend along the second direction y, the first direction x and the second direction y are both parallel to the plane where the substrate 1 is located, the first direction x intersects with the second direction y, and the third direction z is perpendicular to the plane where the substrate 1 is located.

[0116] The area where the conductive material layer 510 and the insulating material layer 301 are stacked in the stacked structure 1030 is the side end area of ​​the semiconductor block structure 100, and this area can also be named as the signal line lead-out structure area. The structure in which the insulating material layer 301 and the conductive material layer 510 are alternately stacked along the third direction z formed in the process of step S1201-step S1203 can be used as the stacked structure 1030 in step S210. It should be noted that when a protective layer 9 is formed on the surface of the insulating material layer 301 located at the top, the protective layer 9 can also be used as a part of the stacked structure 1030. That is, the preparation details of the stacked structure 1030 in step S210 can refer to steps S1201-step S1203, and will not be repeated here.

[0117] Step S220, the stacked structure 1030 is processed by a trimming etching process to form a plurality of signal lines 5 extending along the second direction y and arranged at intervals along the third direction z, the signal line 5 comprising a main extension portion 51 and a lead-out end portion 52 located at at least one end of the main extension portion 51; in the signal line lead-out structure, the orthographic projections of the lead-out ends 52 of any two signal lines 5 on the substrate 1 do not overlap, and the orthographic projections of the main extension portions 51 of any two signal lines 5 on the substrate 1 do overlap; in the third direction z and in a direction from the side close to the substrate 1 to the side away from the substrate 1, the length of each signal line 5 decreases successively.

[0118] The stacked structure 1030 may be processed cyclically by a trim-etch process, thereby converting the plurality of conductive material layers 510 extending along the second direction y and arranged along the third direction z into a plurality of signal lines 5 extending along the second direction y and arranged at intervals along the third direction z. In the third direction z, the ends of the plurality of signal lines 5 may be stepped, and in the direction from the side close to the substrate 1 to the side away from the substrate 1, the signal line 5 located in the upper layer exposes the lead-out end 52 of the signal line 5 located in the lower layer. In the present disclosure, the structure after completing step S220 is as follows: Fig.12 shown.

[0119] In an exemplary embodiment of the present disclosure, the number of conductive material layers 510 in the semiconductor block structure 100 is n, and the number of insulating material layers 301 is n+1, where n>2; in the third direction z, each conductive material layer 510 can be defined as the first to nth conductive material layers 510 from top to bottom, and each insulating material layer 301 can be defined as the first to n+1th insulating material layers 301 from top to bottom; processing the stacked structure 1030 by a trimming etching process to form a plurality of signal lines 5 extending along the second direction y and arranged at intervals along the third direction z (i.e., step S120) may include the following steps:

[0120] S1, forming a first graphic mask layer on the stacked structure 1030, wherein the length of the first graphic mask layer in the second direction y is less than the length of the first conductive material layer 510, and the orthographic projection of the first graphic mask layer on the stacked structure 1030 does not overlap with at least one end of the first conductive material layer 510.

[0121] In an exemplary embodiment of the present disclosure, before forming the first graphic mask layer, an etch stop layer 50 may be formed on the surface of the stacked structure 1030, and a mask material layer may be formed on the surface of the etch stop layer 50, the mask material layer including a plurality of mask patterns extending along the second direction y and spaced apart along the first direction x, the orthographic projection of the mask pattern on the substrate 1 completely coincides with the orthographic projection of the stacked structure 1030 on the substrate 1, and the mask material layer having the mask pattern may be used to etch the etch stop layer 50 (when the stacked structure 1030 further includes a protective layer 9, the protective layer 9 is etched at the same time) to form an opening exposing the first insulating material layer 301. Subsequently, the mask material layer may be removed, and then the first graphic mask layer may be formed on the surface of the etch stop layer 50. In the second direction y, the length of the first graphic mask layer is less than the length of the conductive material layer 510, and the orthographic projection of the first graphic mask layer on the stacked structure does not overlap with at least one end of the first conductive material layer 510. For example, in the second direction y, the first pattern mask layer may be located in the middle area of ​​the stacked structure 1030 , and the orthographic projection of the first pattern mask layer on the stacked structure does not overlap with both ends of the first conductive material layer 510 .

[0122] S2, using the first pattern mask layer as a mask to etch the first insulating material layer 301 and the first conductive material layer 510 to expose at least one end of the second insulating material layer 301, thereby forming a first patterned stacked structure.

[0123] In some embodiments of the present disclosure, the material of the first gate 101 and the conductive material layer 510 may be polysilicon, and the first insulating material layer 301 and the first conductive material layer 510 may be etched by an anisotropic etching process using the first graphic mask layer as a mask to expose at least one end of the second insulating material layer 301, and the etched structure may be defined as a first graphic stacked structure. Compared with the conventional solution in which the conductive material layer 510 is made of tungsten and silicon nitride, the polysilicon in the present application is easy to etch away, and the process difficulty is relatively low; and after the etching is completed, no metal residues and defects will appear, and the device reliability is relatively high.

[0124] It should be noted that, during the anisotropic etching process, the film layer structure in the semiconductor block structure 100 except for the stacked structure 1030 can be protected by the etching stop layer 50 and the protection layer 9 to prevent damage to other structures during the etching process.

[0125] S3, forming a second graphic mask layer on the first graphic stacking structure, wherein the length of the second graphic mask layer in the second direction y is less than the length of the first layer of conductive material layer 510 remaining after the last etching, and the orthographic projection of the second graphic mask layer on the substrate 1 has no overlap with at least one end of the first layer of conductive material layer 510 remaining after the last etching.

[0126] In some embodiments of the present disclosure, the first graphic mask layer may be removed before forming the second graphic mask layer, thereby exposing the surface of the first graphic stacking structure, and then forming the second graphic stacking structure on the first graphic stacking structure. In the second direction y, the length of the second graphic stacking structure may be less than the length of the first layer of conductive material layer 510 in the first graphic stacking structure, and the orthographic projection of the second graphic mask layer on the substrate 1 does not overlap with at least one end of the first layer of conductive material layer 510 of the first graphic stacking structure. For example, in the second direction y, the second graphic mask layer may be located in the middle area on the first graphic stacking structure, and the orthographic projection of the second graphic mask layer on the first graphic stacking structure does not overlap with both ends of the first layer of conductive material layer 510.

[0127] In other embodiments of the present disclosure, the first graphic mask layer does not need to be removed before forming the second graphic mask layer, and the edge of the first graphic mask layer in the second direction y can be etched so that the length of the first graphic mask layer in the second direction y is less than the length of the first conductive material layer 510 in the first graphic stacking structure, and the orthographic projection of the first graphic mask layer on the substrate 1 does not overlap with at least one end of the first conductive material layer 510 of the first graphic stacking structure. The first graphic mask layer after edge etching can be defined as the second graphic mask layer.

[0128] S4, using the second pattern mask layer as a mask to etch the exposed second insulating material layer 301 and the second conductive material layer 510 to expose at least one end of the next insulating material layer 301, thereby forming a second patterned stacked structure.

[0129] During etching of the second insulating material layer 301 and the second conductive material layer 510 , the film layer structure in the semiconductor block structure 100 except for the stacked structure 1030 can still be protected by the etching stop layer 50 and the protective layer 9 to prevent damage to other structures during the etching process.

[0130] Repeat steps S3-S4 until at least one end of the nth insulating material layer 301 is exposed to form an n-1th graphic stacking structure; each conductive material layer 510 remaining after etching is used as a signal line 5, and the area of ​​each signal line 5 that does not overlap with other signal lines 5 is used as a lead-out end 52. After forming the n-1th graphic stacking structure, the insulating material layer 301 located on the lead-out end 52 of each signal line 5 can be removed, and the lead-out end 52 of each signal line 5 is exposed, and the portion of the signal line 5 that is not the lead-out end 52 can be used as the main body extension 51. Fig.13 FIG. 4 is a schematic diagram showing an Xth pattern mask layer 70 deposited during an Xth etching in an embodiment of the present disclosure.

[0131] In the present disclosure, the insulating material layer 301 and the conductive material layer 510 are etched down layer by layer by repeating steps S3 and S4 until at least one end of the nth insulating material layer 301 is exposed. Each repetition of steps S3 and S4 forms a new patterned stacked structure, and in each repetition of steps S3 and S4, the ends of each conductive material layer 510 that has been etched before are etched again, so that the ends of each conductive material layer 510 are synchronously retracted inwards in each etching process, and each conductive material layer 510 in the n-1th patterned stacked structure can be used as a signal line 5, and the ends of each signal line 5 are arranged in a step-like shape.

[0132] In an exemplary embodiment of the present disclosure, the method for preparing the signal line lead-out structure further includes steps S310 to S330, wherein:

[0133] In step S310 , a covering layer 60 is formed on a side of each lead-out end portion 52 away from the substrate 1 .

[0134] The material of the cover layer 60 is the same as that of the insulating material layer 301. For example, the material of the cover layer 60 and the material of the insulating material layer 301 are both silicon oxide. The cover layer 60 can be formed on the side of the lead-out end 52 away from the substrate 1 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. In the embodiment of the present disclosure, the structure after completing step S310 is as follows: Fig.14 shown.

[0135] Step S320 , etching the cover layer 60 to form a plurality of connection holes 61 penetrating the cover layer 60 along the third direction z, wherein the orthographic projections of different connection holes 61 on the substrate 1 at least partially overlap with the orthographic projections of different lead-out ends 52 on the substrate 1 .

[0136] A mask layer may be formed on the covering layer 60, and the mask layer may be etched to form a plurality of mask holes penetrating the covering layer 60 along a third direction z. The covering layer 60 may be etched at the mask holes by a non-isotropic etching process to form a plurality of connection holes 61 penetrating the covering layer 60 along the third direction z. The connection holes 61 may be distributed in a one-to-one correspondence with the lead-out ends 52. For example, each connection hole 61 may expose each lead-out end 52, respectively. The shape of the cross section of the connection hole 61 may be circular, elliptical, rectangular, polygonal or irregular, and is not particularly limited herein. It should be noted that after the connection hole 61 is formed, the mask layer may be removed to expose the etching stop layer or protective layer 9 on the top of the stacked structure 1030. In the embodiment of the present disclosure, the structure after completing step S320 is as follows: Fig.15 shown.

[0137] Step S330 , depositing a conductive material in the connection hole 61 to form a connection line 30 .

[0138] The conductive material may be a material with strong conductive properties, which may include one material or two materials. For example, the conductive material may be titanium nitride and / or tungsten. For example, the conductive material may include titanium nitride and tungsten, and a titanium nitride layer that conformally covers the sidewalls and bottom of the connection hole 61 may be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this process, for the convenience of the process, the titanium nitride layer may simultaneously cover the etching stop layer or protective layer 9 at the top of the stacked structure 1030. Subsequently, tungsten may be filled in the connection hole 61 having the titanium nitride layer by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The tungsten may fill the connection hole 61. In this process, for the convenience of the process, tungsten may simultaneously cover the surface of the titanium nitride layer at the top of the stacked structure 1030. It should be noted that after the connection hole 61 is filled with tungsten, the titanium carbide layer, tungsten and etching stop layer at the top of the stacked structure can be removed by back etching or grinding, and the ends of the titanium carbide layer and tungsten in the connection hole 61 away from the substrate 1 are made flush with the surface of the protective layer 9 away from the substrate 1, and the remaining titanium carbide layer and tungsten in the connection hole 61 can be used as the connection line 30. In the embodiment of the present disclosure, the structure after completing step S330 is as follows: Fig.16 shown.

[0139] In an exemplary embodiment of the present disclosure, the surface of the lead-out end portion 52 away from the substrate 1 can be used as the lead-out surface; in the n-1th patterned stacked structure, the surface of each lead-out surface is covered with an insulating material layer 301. After forming the n-1th patterned stacked structure and before forming the covering layer 60, the method for preparing the signal line lead-out structure of the present disclosure further includes steps S410 and S420, wherein:

[0140] In step S410 , the insulating material layer 301 covering each lead-out end 52 in the (n−1)th patterned stacked structure is removed to expose the lead-out surface of the lead-out end 52 in the signal line 5 and the side surface of the signal line 5 away from the center of the semiconductor block structure 100 along the second direction y.

[0141] The insulating material layers 301 on the lead surfaces can be removed by wet etching or dry etching to expose the lead surfaces. Meanwhile, the side surfaces of the signal lines 5 away from the center of the semiconductor block structure 100 along the second direction y are also exposed.

[0142] Step S420 , forming a metal silicide layer 53 on the lead-out surface of the lead-out end portion 52 and on the side surface away from the center of the semiconductor block structure 100 along the second direction y.

[0143] The material of the metal silicide layer 53 may be CoSi2, TiSi2 or NiSi, etc. The material of the connecting wire 30 is a metal material, for example, a composite structure of a tungsten core shaft coated with a titanium nitride layer, and the titanium nitride layer is used as an electron blocking layer. The metal layer can be formed on the lead-out surface and the side of the signal line 5 away from the center of the semiconductor block structure 100 along the second direction y by chemical vapor deposition, physical vapor deposition or atomic layer deposition, and the metal layer can be treated by a thermal annealing process so that the metal ions in the metal layer diffuse into the signal line 5, thereby forming a metal silicide layer 53 at the junction of the metal layer and the signal line 5. Subsequently, the unreacted metal layer can be removed, while the metal silicide layer 53 formed on the lead-out surface of the lead-out end 52 and the side of the signal line 5 away from the center of the semiconductor block structure 100 along the second direction y is retained.

[0144] Taking the material of the metal silicide layer 53 as CoSi2 as an example, a cobalt material layer can be formed on the lead-out surface and the side surface away from the center of the semiconductor block structure 100 along the second direction y, and the cobalt ions can be diffused into the lead-out end portion 52 through a thermal annealing process. At this time, the cobalt ions can combine with the silicon in the signal line 5 to form a silicon-cobalt bond, thereby forming a CoSi2 layer at the junction of the cobalt material layer and the signal line 5. The unreacted cobalt material layer can be removed later.

[0145] In an exemplary embodiment of the present disclosure, the surface of the lead-out end portion 52 away from the substrate 1 can be used as the lead-out surface; in the n-1th patterned stacked structure, the surface of each lead-out surface is covered with an insulating material layer 301. And the insulating material 8 is filled between two adjacent semiconductor blocks, and the insulating material 8 can fill the gap between the two adjacent semiconductor blocks. After forming the n-1th patterned stacked structure and before forming the covering layer 60, the method for preparing the signal line lead-out structure of the present disclosure further includes steps S510 and S520, wherein:

[0146] In step S510, the insulating material layer 301 covering the lead-out surface of each lead-out end portion 52 in the n-1th patterned stacked structure and the insulating material 8 between two adjacent semiconductor blocks are removed to expose each lead-out surface, the side surface of the signal line 5 away from the center of the semiconductor block structure 100 along the second direction y, and the side surface of each signal line 5 away from the center of the semiconductor block structure 100 along the first direction x.

[0147] In some embodiments of the present disclosure, the insulating material 8 filled between two adjacent semiconductor blocks is the same as the material of the insulating material layer 301 on the lead-out surface, and the insulating material 8 covering the insulating material layer 301 on each lead-out surface and the semiconductor block structure 100 in the n-1th patterned stacked structure can be removed simultaneously by the same etching process, thereby exposing the side surfaces of each lead-out surface and the signal line 5 away from the center of the semiconductor block structure 100 along the second direction y. For example, the insulating material layer 301 on the lead-out surface of the insulating material 8 and the insulating material 8 between the semiconductor block structure 100 can be removed by wet etching.

[0148] In step S520 , a metal silicide layer 53 is formed on the lead-out surface of the lead-out end portion 52 , the side surface of the signal line 5 away from the center of the semiconductor block structure 100 along the second direction y, and the side surface of the signal line 5 away from the center of the semiconductor block structure 100 along the first direction x.

[0149] The material of the connecting wire 30 is a metal material, for example, a composite structure of a titanium nitride layer covering a tungsten core shaft, and the titanium nitride layer is used as an electron blocking layer. A metal layer can be formed on the lead-out surface, the side of the signal line 5 away from the center of the semiconductor block structure 100 along the second direction y, and the side of the signal line 5 away from the center of the semiconductor block structure 100 along the first direction x by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The metal layer can be treated by a thermal annealing process to diffuse metal ions in the metal layer into the signal line 5, thereby forming a metal silicide layer 53 at the junction of the metal layer and the signal line 5. Subsequently, the unreacted metal layer can be removed, while the metal silicide layer 53 formed on the lead-out surface of the lead-out end 52, the side of the signal line 5 away from the center of the semiconductor block structure 100 along the second direction y, and the side of the signal line 5 away from the center of the semiconductor block structure 100 along the first direction x is retained. For example, when the material of the metal silicide layer 53 is CoSi2, the material of the metal layer may be cobalt; when the material of the metal silicide layer 53 is TiSi2, the material of the metal layer may be titanium; when the material of the metal silicide layer 53 is NiSi, the material of the metal layer may be nickel.

[0150] After the metal silicide layer 53 is formed, step S310 may be performed, that is, after the metal silicide layer 53 is formed, a covering layer 60 may be formed. When step S320 is performed, the formed connection hole 61 may expose the metal silicide layer 53 on the lead-out surface, and the end of the connection line 30 formed when step S330 is close to the substrate 1 is in contact with the metal silicide layer 53 on the lead-out surface. The metal silicide layer 53 on the lead-out surface may help reduce the resistance between the connection line 30 and the lead-out end 52, thereby improving the signal transmission efficiency; at the same time, the metal silicide layer 53 on the side of the lead-out end 52 away from the center of the semiconductor block structure 100 along the second direction y and the metal silicide layer 53 on the side of the signal line 5 away from the center of the semiconductor block structure 100 along the first direction x may help reduce the resistance of the signal line 5 itself and the contact resistance between the signal line 5 and the surrounding structure, thereby improving the transmission efficiency of the current in the signal line 5 and reducing energy loss.

[0151] It should be noted that, although the steps of the method for preparing a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0152] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A semiconductor structure, wherein the semiconductor structure is prepared on a substrate, characterized in that: The semiconductor structure comprises a plurality of semiconductor block structures arranged at intervals along a first direction, wherein the semiconductor block structure comprises two side end regions in the first direction, and at least one side end region of the semiconductor block structure is provided with a signal line lead-out structure, wherein the signal line lead-out structure comprises: A plurality of signal lines extending along a second direction and arranged at intervals along a third direction, wherein the first direction and the second direction are both parallel to the plane where the substrate is located, the first direction intersects with the second direction, and the third direction is perpendicular to the plane where the substrate is located; the signal line comprises a main extension portion and a lead-out end portion located at at least one end of the main extension portion; in the signal line lead-out structure, the orthographic projections of any two lead-out ends of the signal lines on the substrate do not overlap, and the orthographic projections of any two main extension portions of the signal lines on the substrate overlap; in the third direction and in a direction from a side close to the substrate to a side away from the substrate, the length of each of the signal lines decreases or increases in sequence.

2. The semiconductor structure according to claim 1, characterized in that: The signal line lead-out structure further includes: A connecting line connected to the lead-out end of the signal line, the connecting line extending along the third direction, and two adjacent connecting lines being insulated from each other; When the lengths of the signal lines decrease in sequence in the third direction from the side close to the substrate to the side away from the substrate, the connecting line is connected to a side of the lead-out end portion away from the substrate; or, when the lengths of the signal lines increase in sequence in the third direction from the side close to the substrate to the side away from the substrate, the connecting line is connected to a side of the lead-out end portion close to the substrate.

3. The semiconductor structure according to claim 1, characterized in that: The signal line lead-out structure is provided at two side end regions of the semiconductor block structure; each of the signal lines includes two lead-out end portions located at two ends of the main body extension portion, and each of the lead-out end portions has the same size in the second direction.

4. The semiconductor structure according to claim 1, characterized in that The material of the signal line includes polysilicon, and a metal silicide layer is provided on at least the lead-out surface of the lead-out end portion of the signal line.

5. The semiconductor structure according to claim 4, characterized in that: A metal silicide layer is provided on a side of the lead-out end portion away from the center of the semiconductor block structure along the second direction.

6. The semiconductor structure according to claim 4, characterized in that: A metal silicide layer is disposed on a side of the signal line away from the center of the semiconductor block structure along the first direction.

7. The semiconductor structure according to any one of claims 4 to 6, characterized in that: The signal line is a word line, and the material of the metal silicide layer is CoSi2, TiSi2 or NiSi.

8. A method for preparing a semiconductor structure, characterized in that: The following steps are involved: providing a substrate; Preparing a plurality of semiconductor block structures spaced apart along a first direction on the substrate, wherein the semiconductor block structure comprises two side end regions in the first direction, and at least one side end region of the semiconductor block structure is provided with a signal line lead-out structure; Wherein, the method for preparing the signal line lead-out structure comprises: A stacked structure is formed in the signal line lead-out structure region of the substrate, the stacked structure comprising insulating material layers and conductive material layers that are alternately stacked multiple times along a third direction; wherein the projections of the signal line lead-out structure region of the substrate and the side end region of the semiconductor block structure on the substrate overlap, the insulating material layers and the conductive material layers both extend along a second direction, the first direction and the second direction are both parallel to the plane where the substrate is located, the first direction intersects with the second direction, and the third direction is perpendicular to the plane where the substrate is located; The stacked structure is processed by a trimming etching process to form a plurality of signal lines extending along the second direction and arranged at intervals along the third direction, wherein the signal lines include a main extension portion and a lead-out end portion located at at least one end of the main extension portion; in the signal line lead-out structure, the orthographic projections of any two of the lead-out ends of the signal lines on the substrate do not overlap, and the orthographic projections of any two of the main extension portions of the signal lines on the substrate do overlap; in the third direction and in a direction from a side close to the substrate to a side away from the substrate, the length of each of the signal lines decreases successively.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The number of the conductive material layers is n, the number of the insulating material layers is n+1, and n>2; in the third direction, the conductive material layers are defined as the 1st to nth conductive material layers from top to bottom, and the insulating material layers are defined as the 1st to n+1th insulating material layers from top to bottom; the stacked structure is processed by a trimming etching process to form a plurality of signal lines extending along the second direction and arranged at intervals along the third direction, including the following steps: S1, forming a first graphic mask layer on the stacked structure, wherein the length of the first graphic mask layer in the second direction is less than the length of the first conductive material layer, and the orthographic projection of the first graphic mask layer on the stacked structure does not overlap with at least one end of the first conductive material layer; S2, using the first graphic mask layer as a mask to etch the first insulating material layer and the first conductive material layer to expose at least one end of the second insulating material layer to form a first graphic stacked structure; S3, forming a second graphic mask layer on the first graphic stacked structure, wherein the length of the second graphic mask layer in the second direction is less than the length of the first layer of the conductive material layer remaining after the last etching, and the orthographic projection of the second graphic mask layer on the substrate does not overlap with at least one end of the first layer of the conductive material layer remaining after the last etching; S4, etching the exposed second insulating material layer and the second conductive material layer using the second graphic mask layer as a mask to expose at least one end of the next insulating material layer to form a second graphic stacked structure; Repeating steps S3-S4 until at least one end of the nth insulating material layer is exposed, thereby forming an n-1th patterned stacked structure; The conductive material layers remaining after etching are respectively used as signal lines, at least one end exposed in the signal line is used as the lead-out end, and the portion of the signal line other than the lead-out end is used as a main body extension portion.

10. The method for preparing a semiconductor structure according to claim 8, characterized in that: The method for preparing the signal line lead-out structure further includes: forming a covering layer on a side of each of the lead-out ends away from the substrate; Etching the cover layer to form a plurality of connection holes penetrating the cover layer along the third direction, wherein orthographic projections of different connection holes on the substrate at least partially overlap with orthographic projections of different lead-out ends on the substrate; A conductive material is deposited in the connection hole to form a connection line.

11. The method for preparing a semiconductor structure according to claim 9, characterized in that: The material of the signal line includes polysilicon, the surface of the lead-out end away from the substrate is a lead-out surface, and the method for preparing the signal line lead-out structure further includes: removing the insulating material layer covering each of the lead-out ends in the n-1th patterned stacked structure to expose the lead-out surface of the lead-out end in the signal line and the side surface of the signal line away from the center of the semiconductor block structure along the second direction; A metal silicide layer is formed on the lead-out surface of the lead-out end portion and the side surface away from the center of the semiconductor block structure along the second direction.

12. The method for preparing a signal line lead-out structure according to claim 9, characterized in that: The material of the signal line includes polysilicon, the surface of the lead-out end away from the substrate is a lead-out surface, and the space between two adjacent semiconductor block structures is filled with insulating material. The method for preparing the signal line lead-out structure also includes: Removing the insulating material layer covering the lead-out surface of each lead-out end portion and the insulating material between two adjacent semiconductor block structures in the n-1th patterned stacked structure to expose each lead-out surface, the side surface of the signal line away from the center of the semiconductor block structure along the second direction, and the side surface of each signal line away from the center of the semiconductor block structure along the first direction; A metal silicide layer is formed on a lead-out surface of the lead-out end portion, a side surface of the signal line away from the center of the semiconductor block structure along the second direction, and a side surface of the signal line away from the center of the semiconductor block structure along the first direction.

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