Silicon carbide step groove MOSFET and manufacturing method thereof

Abstract

The invention discloses a silicon carbide step groove MOSFET and a manufacturing method thereof. The MOSFET comprises a semiconductor drain region, a semiconductor drift region, a second conductive type semiconductor well region, a first conductive type semiconductor source region, a second conductive type semiconductor contact region, a first groove, a first conductive type carrier diffusion layer, a second groove, a second conductive type semiconductor shielding region, a gate dielectric layer, a gate electrode, an interlayer dielectric layer and a contact hole. And a source end metal electrode and a drain end metal electrode. A first conductive type semiconductor carrier diffusion layer (CSL) is prepared in a local region of the bottom and the side wall of a first groove, so that the specific on-resistance (Ron, sp) of the device is reduced; second conductive type semiconductor shielding regions short-circuited with the source end metal electrode are prepared in all regions of the bottom and the side wall of the second groove, so that the gate-oxide electric field can be remarkably reduced compared with a shielding region introduced only at the bottom of the groove, and the reliability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and in particular to a silicon carbide stepped trench MOSFET and a manufacturing method thereof. Background Art

[0002] The band gap width of silicon carbide is about three times that of silicon, the breakdown field strength is about 10 times that of silicon, the thermal conductivity is about 3 times that of silicon, and its electron saturation drift velocity is about one order of magnitude higher than that of silicon. These excellent properties of silicon carbide make it an ideal material for power electronic devices.

[0003] For silicon carbide MOSFET, researchers first developed a planar structure. With the continuous pursuit of excellent electrical performance, it was found that the JFET resistance and low channel mobility of planar MOSFET restricted the continued improvement of the performance of silicon carbide planar MOSFET, causing researchers to gradually turn to the development of silicon carbide trench MOSFET. Trench MOSFET eliminates JFET resistance, and the mobility of its vertical channel is about twice that of the horizontal channel. Therefore, silicon carbide trench MOSFET greatly alleviates the contradiction between device breakdown voltage (BV) and specific on-resistance (Ron,sp) compared to silicon carbide planar MOSFET.

[0004] A key problem of silicon carbide trench MOSFET is that when the device is working in a blocking state, the gate oxide electric field gathers at the corner position of the bottom of the trench. The high gate oxide electric field will affect the reliability of the device. The present invention prepares a surrounding semiconductor shielding area around the second trench, which can significantly reduce the gate oxide electric field. The surrounding semiconductor shielding area is prepared by a self-alignment process without adding an additional mask.

[0005] The information disclosed in this background technology section is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as acknowledging or suggesting in any form that the information constitutes the prior art already known to those skilled in the art. Summary of the invention

[0006] In view of the problems existing in the prior art, the object of the present invention is to provide a silicon carbide step trench MOSFET and a manufacturing method thereof, so as to solve the problem of gate oxide electric field at the bottom corner of the high trench of the silicon carbide trench MOSFET in the blocking state.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions: A silicon carbide stepped trench MOSFET, comprising: a semiconductor drain region, which is a semiconductor material heavily doped with a first conductivity type; a semiconductor drift region, which is a semiconductor material lightly doped with a first conductivity type; A second conductive type semiconductor well region located at the top of the semiconductor drift region; A first conductive type semiconductor source region located at a middle position of a top end of the second conductive type semiconductor well region; A second conductive type semiconductor contact region, which is located at the top of the second conductive type semiconductor well region and away from the middle position; A first trench, located in the middle of the semiconductor drift region, extending from the semiconductor source region into the semiconductor drift region; A first conductive type carrier diffusion layer, which is located between the second conductive type semiconductor well region and the second conductive type semiconductor shielding region; a second groove disposed directly below the first groove; The second conductive type semiconductor shielding region surrounds the second trench; A gate dielectric layer, which is located on inner walls of the first trench and the second trench; A gate electrode, which is located on the gate dielectric layer of the first trench and the second trench; An interlayer dielectric layer, which is located above the gate electrode; a contact hole is provided in the interlayer dielectric layer; A source-end metal electrode, which is located above the interlayer dielectric layer and forms an ohmic contact with the semiconductor source region and the semiconductor contact region through the contact hole; The drain metal electrode is located below the semiconductor drain region and forms an ohmic contact with the semiconductor drain region.

[0008] Furthermore, the first trench has a width of W1 and a depth of T1, and the depth T1 is greater than the sum of the thickness of the semiconductor well region and the thickness of the gate dielectric.

[0009] Furthermore, the width of the first conductive type carrier diffusion layer is W2, which is prepared by adjusting the ion implantation angle and the rotation angle, and its doping concentration is less than the doping concentration of the semiconductor well region, and the ion implantation is performed in self-alignment with the first trench without adding an additional mask.

[0010] Furthermore, the width of the second trench is W3, and the depth thereof is T3, and the sum of T1 and T3 is not greater than the thickness of the drift region.

[0011] Furthermore, the width of the second conductive type semiconductor shielding region is W4, which is prepared by adjusting the ion implantation angle and the rotation angle, surrounds the second groove, and is short-circuited with the source metal. Its doping concentration is 1 to 100 times the concentration of the semiconductor well region, and the ion implantation is carried out in self-alignment with the second groove without adding an additional mask.

[0012] Furthermore, the width W1 of the first trench is greater than the sum of the width W3 of the second trench and twice the width W4 of the shielding region, that is, W1>W3+2×W4.

[0013] Furthermore, the gate electrode is isolated from the adjacent SIC epitaxy by a gate dielectric layer, and the material of the gate electrode is heavily doped polysilicon or metal.

[0014] Further, for an N-channel silicon carbide trench MOSFET, the first conductivity type refers to N-type, and the second conductivity type is P-type; for a P-channel silicon carbide trench MOSFET, the first conductivity type refers to P-type, and the second conductivity type is N-type.

[0015] A method for manufacturing a silicon carbide stepped trench MOSFET comprises the following steps: S1. Prepare a semiconductor drain region heavily doped with a semiconductor material of the first conductive type, wherein the concentration of impurity atoms in the crystal is 1×10 19 Pieces / cm 3 -3×10 20 Pieces / cm 3 A low-doped semiconductor drift region is formed on the heavily doped semiconductor drain region, wherein the doping concentration of the semiconductor drift region is 1.5×10 15 Pieces / cm 3 -9.5×10 16 Pieces / cm 3 ; S2, implanting aluminum atoms into the top of the semiconductor drift region to form a second conductivity type semiconductor well region, with an implantation dose of 5×10 11 Pieces / cm 2 -5×10 14 Pieces / cm 2 Then, nitrogen atoms are implanted at the middle of the top of the second conductive type semiconductor well region, with an implantation dose of 1×10 15 Pieces / cm 2 -9×10 15 Pieces / cm 2 A first conductive type semiconductor source region is formed between the first conductive type semiconductor source region and the second conductive type semiconductor well region is formed by injecting high concentration aluminum atoms at the top and away from the middle position to form a second conductive type semiconductor body contact region; S3, depositing a layer of silicon oxide or a combination of silicon oxide and polysilicon as a hard mask layer HM1 on the active area, then etching a window on the hard mask, and then etching the semiconductor drift region by dry coupled plasma etching, or reactive ion etching, or a combination of the two, to form a first trench with a width of W1 and a depth of T1, wherein the depth T1 is greater than the sum of the thickness of the semiconductor well region and the thickness of the gate dielectric; S4, forming a carrier diffusion layer with a width of W2 outside the first groove by adjusting the ion implantation angle and the rotation angle, wherein the ion implantation is performed with the first groove as a self-alignment, so no additional mask is introduced in the preparation of the carrier diffusion layer; defining the lead-out position area of ​​the semiconductor shielding area by photoresist, and then preparing the lead-out end of the second conductive type semiconductor shielding area by adjusting the ion implantation angle and the rotation angle; S5, preparing a second hard mask layer HM2 on the hard mask layer HM1 and the carrier diffusion layer, and then using the first trench as a self-aligned etching window on the hard mask layer HM2 to form a HM2 sidewall, so that no additional MASK is added to the window opening of the hard mask layer HM2; S6, etching the semiconductor drift region in the window area defined by the hard mask layer HM2 by dry coupled plasma etching, reactive ion etching, or a combination of the two, to produce a second trench with a width of W3 and a depth of T3, wherein the sum of T1 and T3 is not greater than the thickness of the drift region; S7, using the hard mask layer as a barrier, by adjusting the ion implantation angle and the rotation angle, a second conductive type semiconductor shielding region with a width of W4 is prepared, which surrounds the second trench and is short-circuited with the source metal. The semiconductor shielding region is 1 to 100 times the concentration of the semiconductor well region. The high doping concentration of the semiconductor shielding region compounds the carrier diffusion layer in contact with the second trench, thereby ensuring that the second trench is surrounded by the semiconductor shielding region; the semiconductor shielding region needs to be connected to the source metal, either the entire semiconductor shielding region is connected to the source metal, or the semiconductor shielding region distributed in stages is connected to the source metal; S8, removing the hard mask, forming a gate dielectric layer by deposition or oxidation, wherein the gate dielectric layer is a silicon oxide, silicon nitride, aluminum oxide or hafnium oxide dielectric, or a combination of several materials, and has a thickness of 0.02-1µm, and then forming a gate electrode on the gate dielectric layer, wherein the gate electrode is heavily doped polysilicon or metal; S9, depositing a certain thickness of non-doped silicon oxide and borophosphosilicate glass above the gate electrode to form an interlayer dielectric layer with a thickness of 0.4-1µm, and then etching a through hole in the interlayer dielectric layer to form a contact hole; S10, depositing and etching a front metal on the interlayer dielectric to form a source metal electrode; depositing a conductive metal under the semiconductor drain region to form a drain metal electrode, and both the source and drain metals form ohmic contacts with the semiconductor.

[0016] Further, taking the strip cell as an example, there are three ways to short-circuit the second conductive type semiconductor shielding area (9) with the source metal: The first one is that when the device is in the on state, the conductive channels on the left and right sides of the first trench are turned on; The second is that the semiconductor shielding area on the right side of the first trench is distributed in a single-side phase, that is, the conductive channel on the right side of the first trench is phase-conducted, while the left channel is fully conductive; The third type is: a whole semiconductor shielding region is prepared on the right side of the first trench, that is, the conductive channel on the right side of the first trench is completely non-conductive, while the channel on the left side is completely conductive.

[0017] Further, based on step S2, a first conductive type carrier diffusion layer (16) is prepared by high energy injection, and then steps S3-S10 are repeated to finally form a primitive cell structure. By introducing a long strip of the first conductive type carrier diffusion layer (16) below the semiconductor well region, the specific on-resistance of the device is further reduced.

[0018] By adopting the above technical solution, the present invention has the following beneficial effects: The present application designs a silicon carbide stepped trench MOSFET and a manufacturing method thereof. The structure is designed with a semiconductor shielding area surrounding the second trench, so that the new structure can achieve a lower gate oxide electric field at the corner of the bottom of the trench in a blocking state, so as to improve the reliability of the device; at the same time, the characteristic of the semiconductor shielding area being connected to the source end metal enables the surrounding shielding area to eliminate the entire second trench and reduce the gate-drain overlap area in the local area of ​​the bottom of the first trench, so as to reduce the gate-drain capacitance (Cgd) and reduce the switching power consumption; further, the carrier diffusion layer at the step position can reduce the specific on-resistance (Ron,sp); further, the step position where the first trench contacts the second trench introduces a new electric field peak, which can improve the breakdown voltage (BV) of the device; further, the second layer of hard mask HM2 window opening, carrier diffusion layer preparation, and semiconductor shielding area all adopt self-alignment process without adding additional mask plates. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 is a schematic diagram of the three-dimensional structure of the primitive cell of Example 1 of the present application; Figure 2 is a schematic diagram of a two-dimensional cross-section unit cell along line BB' of Example 1 of the present application; Figure 3 This is a schematic diagram of a two-dimensional cross-section primitive cell along line AA' of Example 1 of the present application; Figure 4 This is a schematic diagram of the initial structure of Example 1 of the present application; Figure 5 is a schematic diagram of the structure of forming an active area in Example 1 of the present application; Figure 6 is a schematic structural diagram of forming a first groove in Example 1 of the present application; Figure 7 is a schematic diagram of the structure of forming a carrier diffusion layer in Example 1 of the present application; Figure 8 This is a schematic diagram of the structure of forming the semiconductor shielding region lead-out terminal in Embodiment 1 of the present application; Fig. 9 is a schematic structural diagram of forming a window of a hard mask HM2 in Embodiment 1 of the present application; Fig.10 is a schematic structural diagram of forming a second groove in Example 1 of the present application; Fig.11 is a schematic structural diagram of a semiconductor shielding region formed in Embodiment 1 of the present application; Fig.12 is a schematic diagram of forming a gate structure in Example 1 of the present application; Fig.13 is a schematic diagram of the structure of forming a contact hole in Embodiment 1 of the present application; Fig.14 is a schematic diagram of the structure of forming a metal electrode in Example 1 of the present application; Fig.15 is a schematic top view of the structure of three semiconductor shielding regions formed in Example 2 of the present application; Fig.16 This is a schematic diagram of a two-dimensional cross-section primitive cell formed in Example 3 of the present application; Figures 1 to 16 The regions in the figure are marked as follows: (1) - semiconductor drain region, (2) - semiconductor drift region, (3) - second conductivity type semiconductor well region, (4) - first conductivity type semiconductor source region, (5) - second conductivity type semiconductor body contact region, (6) - first trench, (7) - first conductivity type carrier diffusion layer, (8) - second trench, (9) - second conductivity type semiconductor shielding region, (10) - gate dielectric layer, (11) - gate electrode, (12) - interlayer dielectric layer, (13) - contact hole, (14) - source metal electrode, (15) - drain metal electrode, (16) - first conductivity type carrier diffusion layer. DETAILED DESCRIPTION

[0021] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] The specific implementation of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention. Example 1

[0023] Figure 1-3 and Fig.14 An embodiment shown in the figure comprises: a semiconductor drain region 1, which is a semiconductor material heavily doped with a first conductivity type; a semiconductor drift region 2, which is a semiconductor material lightly doped with the first conductivity type; a second conductivity type semiconductor well region 3, which is located at the top of the semiconductor drift region; a first conductivity type semiconductor source region 4, which is located at the middle position of the top of the second conductivity type semiconductor well region; a second conductivity type semiconductor contact region 5, which is located at the top of the second conductivity type semiconductor well region and away from the middle position; a first trench 6, which is located in the middle position of the semiconductor drift region and extends from the semiconductor source region into the semiconductor drift region; a first conductivity type carrier diffusion layer 7, which is located at the second conductivity type type semiconductor well region and a second conductive type semiconductor shield region; a second trench 8 is placed directly below the first trench; a second conductive type semiconductor shield region 9 surrounds the second trench; a gate dielectric layer 10 is located on the inner walls of the first and second trenches; a gate electrode 11 is located on the gate dielectric layer of the first and second trenches; an interlayer dielectric layer 12 is located above the gate electrode; a contact hole 13 is provided in the interlayer dielectric layer; a source metal electrode 14 is located above the interlayer dielectric and forms an ohmic contact with the semiconductor source region and the semiconductor body contact region through the contact hole; a drain metal electrode 15 is located below the semiconductor drain region and forms an ohmic contact with the semiconductor drain region.

[0024] In the present application, the gate dielectric layer in the first and second grooves can be formed by thermal growth or by deposition. The gate dielectric layer can be silicon oxide, or a high dielectric constant dielectric such as silicon nitride, aluminum oxide, hafnium oxide, or a combination of several materials. The new structure needs to sacrifice part of the conductive channel so as to connect the semiconductor shielding area to the source metal. The entire semiconductor shielding area can be connected to the source metal, or the semiconductor shielding area distributed in stages can be connected to the source metal. If the semiconductor shielding area is not connected to the source metal, it will increase the power consumption of the device on the one hand, and reduce the reliability of the device on the other hand.

[0025] In this specific embodiment, a first conductive type carrier diffusion layer is formed in the first groove by adjusting the ion injection angle and the rotation angle, and then a second groove is etched out. Subsequently, a second conductive type semiconductor shielding region is formed at the bottom and sidewall of the second groove by adjusting the ion injection angle and the rotation angle, wherein the ion injection of the carrier diffusion layer and the semiconductor shielding region are performed by a self-alignment process without adding an additional mask.

[0026] exist Figure 4 In the embodiment shown, the semiconductor drain region 1 is a semiconductor material heavily doped with the first conductivity type, such as a crystal with an impurity atom concentration of 1×10 19 Pieces / cm 3 -3×10 20 Pieces / cm 3 A low-doped semiconductor drift region 2 is formed on the heavily doped semiconductor drain region, wherein the doping concentration of the semiconductor drift region is 1.5×10 15 Pieces / cm 3 -9.5×10 16 Pieces / cm 3 .

[0027] exist Figure 5 In the embodiment shown, aluminum atoms are implanted at the top of the semiconductor drift region to form a second conductivity type semiconductor well region 3, and the implantation dose is 5×10 11 Pieces / cm 2 -5×10 14 Pieces / cm 2 Then, nitrogen atoms are implanted at the middle position of the top of the second conductive type semiconductor well region, with an implantation dose of 1×10 15 Pieces / cm 2 -9×10 15 Pieces / cm 2 A first conductive type semiconductor source region 4 is formed between the two regions, and then a second conductive type semiconductor contact region 5 is formed by implanting high concentration aluminum atoms at the top of the second conductive type semiconductor well region and away from the middle position.

[0028] exist Figure 6 In the illustrated embodiment, a layer of silicon oxide or a combination of silicon oxide and polysilicon is deposited above the active area as a hard mask layer (HM1), and then a window is etched on the hard mask. Subsequently, etching is performed in the semiconductor drift region by dry coupled plasma etching, reactive ion etching, or a combination of the two to form a first trench 6 with a width of W1 and a depth of T1, wherein the depth T1 is greater than the sum of the thickness of the semiconductor well region and the thickness of the gate dielectric.

[0029] exist Figure 7 In the illustrated embodiment, a carrier diffusion layer 7 with a width of W2 is formed outside the first trench by adjusting the ion implantation angle and the rotation angle, wherein the ion implantation is performed using the first trench as a self-alignment, so no additional mask is introduced in the preparation of the carrier diffusion layer.

[0030] exist Figure 8 In the embodiment shown, the lead-out position area of ​​the semiconductor shielding region is defined by photoresist, and then the lead-out end of the second conductive type semiconductor shielding region is prepared by adjusting the ion implantation angle and the rotation angle, such as Figure 8 (a) shows that the area covered by the photoresist is removed as shown in Figure 8 (b) shows that Figure 7 Be consistent.

[0031] exist Fig. 9 In the illustrated embodiment, a second hard mask layer HM2 is prepared on the hard mask layer HM1 and the carrier diffusion layer, and then a window is self-alignedly etched on the hard mask layer HM2 using the first trench as a self-aligned etching method to form a HM2 sidewall. Therefore, the window opening of the hard mask layer HM2 does not add an additional MASK.

[0032] exist Fig.10 In the embodiment shown, the semiconductor drift region is etched in the window area defined by the hard mask HM2 by dry coupled plasma etching, reactive ion etching or a combination of the two to produce a second trench 8 with a width of W3 and a depth of T3, wherein the sum of T1 and T3 is not greater than the thickness of the drift region.

[0033] exist Fig.11 In the illustrated embodiment, a second conductive type semiconductor shielding region 9 with a width of W4 is prepared by adjusting the ion implantation angle and the rotation angle with a hard mask layer as a barrier, which surrounds the second trench and is short-circuited with the source metal. The semiconductor shielding region can be 1 to 100 times the concentration of the semiconductor well region. The high doping concentration of the semiconductor shielding region compounds the carrier diffusion layer in contact with the second trench, thereby ensuring that the second trench is surrounded by the semiconductor shielding region. Furthermore, the semiconductor shielding region needs to be connected to the source metal. The entire semiconductor shielding region can be connected to the source metal, or the semiconductor shielding region distributed in stages can be connected to the source metal. If the semiconductor shielding region is not connected to the source metal, it will increase the turn-on power consumption of the device on the one hand, and reduce the reliability of the device on the other hand. exist Fig.12 In the embodiment shown, the hard mask is removed and a gate dielectric layer 10 is formed by deposition or oxidation. The gate dielectric layer can be silicon oxide, or a high dielectric constant dielectric such as silicon nitride, aluminum oxide, hafnium oxide, or a combination of several materials. The thickness can be 0.02-1µm. Then, a gate electrode 11 is prepared on the gate dielectric layer, wherein the gate electrode can be heavily doped polysilicon or metal.

[0034] exist Fig.13 In the embodiment shown, a certain thickness of non-doped silicon oxide and borophosphosilicate glass is deposited above the gate electrode to form an interlayer dielectric layer 12, whose thickness is generally 0.4-1µm, and then a through hole is etched in the interlayer dielectric layer to form a contact hole 13.

[0035] exist Fig.14In the embodiment shown, a front metal is deposited and etched on the interlayer dielectric to form a source metal electrode 14. A conductive metal is deposited under the semiconductor drain region to form a drain metal electrode 15. Both the source and drain metals form ohmic contacts with the semiconductor. Example 2

[0036] exist Fig.15 In the embodiment shown, taking the strip cell as an example, there are three ways to short-circuit the semiconductor shielding region (9) surrounding the second groove with the source metal. Fig.15 As shown in (a), when the device is in the on state, the conductive channels on the left and right sides of the first trench are staged; the semiconductor shielding area (9) on the right side of the first trench can also be distributed on one side in stages, as shown in a top view. Fig.15 As shown in (b), the conductive channel on the right side of the first trench is partially conductive, while the left side channel is fully conductive; further, a whole semiconductor shielding region (9) can be prepared on the right side of the first trench, as shown in the top view. Fig.15 (c) That is, the conductive channel on the right side of the first trench is completely non-conductive, while the channel on the left side is completely conductive. Example 3

[0037] exist Fig.16 In the embodiment shown, in Example 1 Figure 5 On the basis of, a first conductive type carrier diffusion layer (16) is prepared by high energy injection, and its structure is as follows Fig.16 (a), then Example 3 repeats Example 1 Figures 6 to 13 Process steps, the final cell structure is as follows Fig.16 (b) It not only inherits the advantages of the structure in embodiment 1, but also the structure in embodiment 3 introduces a long first conductive type carrier diffusion layer (16) under the semiconductor well region, which helps to further reduce the specific on-resistance of the device.

[0038] In summary, the present application discloses a silicon carbide stepped trench MOSFET and a manufacturing method thereof, wherein a first conductive type semiconductor carrier diffusion layer (CSL) is prepared at a local area of ​​the bottom and sidewall of the first trench to reduce the device's specific on-resistance (Ron,sp); further, a second conductive type semiconductor shielding region short-circuited with a source metal electrode is prepared in the entire area of ​​the bottom and sidewall of the second trench, which can significantly reduce the gate oxide electric field compared to the shielding region introduced only at the bottom of the trench, so as to improve the device reliability; further, the shielding region connected to the source metal can eliminate the second trench's entire The gate-drain overlap area of ​​the local area at the bottom of the first trench is reduced to reduce the gate-drain capacitance (Cgd), thereby reducing the switching power consumption of the device; further, the first conductive type semiconductor carrier diffusion layer and the second conductive type semiconductor shielding area are respectively prepared by the trench self-aligned ion implantation process, and no additional mask is added; further, the step position where the first trench contacts the second trench introduces a new electric field peak, which can improve the breakdown voltage (BV) of the device; therefore, the present invention not only optimizes the static and dynamic electrical performance parameters of the device, but also optimizes the reliability of the device.

[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A silicon carbide step trench MOSFET, characterized in that: include: A semiconductor drain region (1), which is a heavily doped semiconductor material of a first conductivity type; A semiconductor drift region (2), which is a lightly doped semiconductor material of a first conductivity type; A second conductive type semiconductor well region (3), which is located at the top of the semiconductor drift region (2); A first conductive type semiconductor source region (4), which is located at a middle position at the top of the second conductive type semiconductor well region (3); A second conductive type semiconductor contact region (5), which is located at the top of the second conductive type semiconductor well region (3) and away from the middle; A first trench (6) located in the middle of the semiconductor drift region (2) and extending from the semiconductor source region into the semiconductor drift region; A first conductive type carrier diffusion layer (7), which is located between the second conductive type semiconductor well region (3) and the second conductive type semiconductor shielding region (9); a second groove (8) disposed directly below the first groove (6); The second conductive type semiconductor shielding region (9) surrounds the second trench (8); A gate dielectric layer (10), which is located on the inner walls of the first trench (6) and the second trench (8); A gate electrode (11) located on the gate dielectric layer of the first trench (6) and the second trench (8); An interlayer dielectric layer (12) located on the gate electrode (11); a contact hole (13) is provided in the interlayer dielectric layer (12); A source-end metal electrode (14), which is located above the interlayer dielectric layer (12) and forms an ohmic contact with the semiconductor source region and the semiconductor contact region through the contact hole (13); A drain-end metal electrode (15) is located below the semiconductor drain region (1) and forms an ohmic contact with the semiconductor drain region (1).

2. The silicon carbide step trench MOSFET according to claim 1, characterized in that: The first trench (6) has a width of W1 and a depth of T1, and the depth T1 is greater than the sum of the thickness of the semiconductor well region and the thickness of the gate dielectric.

3. The silicon carbide step trench MOSFET according to claim 1, characterized in that: The width of the first conductive type carrier diffusion layer (7) is W2, and it is prepared by adjusting the ion implantation angle and the rotation angle, and its doping concentration is less than the doping concentration of the semiconductor well region, and the ion implantation is performed in self-alignment with the first trench, without adding an additional mask.

4. The silicon carbide step trench MOSFET according to claim 1, characterized in that: The width of the second trench (8) is W3, and the depth thereof is T3, and the sum of T1 and T3 is not greater than the thickness of the drift region.

5. The silicon carbide step trench MOSFET according to claim 1, characterized in that: The width of the second conductive type semiconductor shielding region (9) is W4, which is prepared by adjusting the ion implantation angle and the rotation angle, surrounds the second groove (8), and is short-circuited with the source metal. Its doping concentration is 1 to 100 times the concentration of the semiconductor well region, and the ion implantation is performed in self-alignment with the second groove (8) without adding an additional mask.

6. The silicon carbide step trench MOSFET according to claim 1, characterized in that: The width W1 of the first groove (6) is greater than the sum of the width W3 of the second groove (8) and twice the width W4 of the shielding area, that is, W1>W3+2×W4.

7. The silicon carbide step trench MOSFET according to claim 1, characterized in that: The gate electrode (11) is isolated from the adjacent SIC epitaxy by a gate dielectric layer, and the material of the gate electrode (11) is heavily doped polysilicon or metal; For an N-channel silicon carbide trench MOSFET, the first conductivity type refers to N-type and the second conductivity type is P-type; for a P-channel silicon carbide trench MOSFET, the first conductivity type refers to P-type and the second conductivity type is N-type.

8. A method for manufacturing a silicon carbide step trench MOSFET according to any one of claims 1 to 7, characterized in that: The steps include: S1. Prepare a semiconductor drain region (1) heavily doped with a semiconductor material of the first conductivity type, wherein the concentration of impurity atoms in the crystal is 1×10 19 Pieces / cm 3 -3×10 20 Pieces / cm 3 A low-doped semiconductor drift region (2) is formed on the heavily-doped semiconductor drain region, wherein the doping concentration of the semiconductor drift region is 1.5×10 15 Pieces / cm 3 -9.5×10 16 Pieces / cm 3 ; S2, implanting aluminum atoms at the top of the semiconductor drift region (2) to form a second conductive type semiconductor well region (3), with an implantation dose of 5×10 11 Pieces / cm 2 -5×10 14 Pieces / cm 2 Then, nitrogen atoms are implanted into the middle of the top of the second conductive type semiconductor well region (3) at a dose of 1×10 15 Pieces / cm 2 -9×10 15 Pieces / cm 2 A first conductive type semiconductor source region (4) is formed between the two regions, and then a high concentration of aluminum atoms is injected at the top of the second conductive type semiconductor well region (3) and away from the middle position to form a second conductive type semiconductor body contact region (5); S3, depositing a layer of silicon oxide or a combination of silicon oxide and polysilicon as a hard mask layer HM1 above the active region, then etching a window on the hard mask, and then etching the semiconductor drift region by dry coupled plasma etching, reactive ion etching, or a combination of the two, to form a first trench (6) with a width of W1 and a depth of T1, wherein the depth T1 is greater than the sum of the thickness of the semiconductor well region and the thickness of the gate dielectric; S4, forming a carrier diffusion layer (7) with a width of W2 outside the first trench by adjusting the ion implantation angle and the rotation angle, wherein the ion implantation is performed using the first trench as a self-alignment, so that no additional mask is introduced in the preparation of the carrier diffusion layer; defining the lead-out position area of ​​the semiconductor shielding region by photoresist, and then preparing the lead-out end of the second conductive type semiconductor shielding region by adjusting the ion implantation angle and the rotation angle; S5, preparing a second hard mask layer HM2 on the hard mask layer HM1 and the carrier diffusion layer, and then using the first trench as a self-aligned etching window on the hard mask layer HM2 to form a HM2 sidewall, so that no additional MASK is added to the window opening of the hard mask layer HM2; S6, etching the semiconductor drift region in the window area defined by the hard mask layer HM2 by dry coupled plasma etching, reactive ion etching or a combination of the two, to produce a second trench (8) with a width of W3 and a depth of T3, wherein the sum of T1 and T3 is not greater than the thickness of the drift region; S7, using the hard mask layer as a barrier, adjusting the ion implantation angle and the rotation angle to prepare a second conductive type semiconductor shielding region (9) with a width of W4, which surrounds the second trench (8) and is short-circuited with the source metal. The semiconductor shielding region is 1 to 100 times the concentration of the semiconductor well region. The high doping concentration of the semiconductor shielding region compounds the carrier diffusion layer in contact with the second trench, thereby ensuring that the second trench is surrounded by the semiconductor shielding region. The semiconductor shielding region needs to be connected to the source metal, and the entire semiconductor shielding region is connected to the source metal, or the semiconductor shielding region distributed in stages is connected to the source metal. S8, removing the hard mask, forming a gate dielectric layer (10) by deposition or oxidation, wherein the gate dielectric layer is a silicon oxide, silicon nitride, aluminum oxide or hafnium oxide dielectric, or a combination of several materials, and has a thickness of 0.02-1µm, and then forming a gate electrode (11) on the gate dielectric layer, wherein the gate electrode is heavily doped polysilicon or metal; S9, depositing a certain thickness of non-doped silicon oxide and borophosphosilicate glass above the gate electrode to form an interlayer dielectric layer (12) with a thickness of 0.4-1µm, and then etching a through hole in the interlayer dielectric layer to form a contact hole (13); S10, depositing and etching a front metal on the interlayer dielectric to form a source metal electrode (14); depositing a conductive metal below the semiconductor drain region to form a drain metal electrode (15), and both the source and drain metals form ohmic contacts with the semiconductor.

9. The method for manufacturing a silicon carbide step trench MOSFET according to claim 8, characterized in that: Taking the strip cell as an example, there are three ways to short-circuit the second conductive type semiconductor shielding area (9) with the source metal: The first one is that when the device is in the on state, the conductive channels on the left and right sides of the first trench are turned on; The second is that the semiconductor shielding area on the right side of the first trench is distributed in a single-side phase, that is, the conductive channel on the right side of the first trench is phase-conducted, while the left channel is fully conductive; The third type is: a whole semiconductor shielding region is prepared on the right side of the first trench, that is, the conductive channel on the right side of the first trench is completely non-conductive, while the channel on the left side is completely conductive.

10. The method for manufacturing a silicon carbide step trench MOSFET according to claim 8, characterized in that: On the basis of step S2, a first conductive type carrier diffusion layer (16) is prepared by high energy injection, and then steps S3-S10 are repeated to finally form a primitive cell structure. By introducing a long strip of the first conductive type carrier diffusion layer (16) below the semiconductor well region, the specific on-resistance of the device is further reduced.

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