Edge contact type field effect transistor and preparation method thereof

Abstract

The invention belongs to the related technical field of semiconductor devices, and discloses an edge contact type field effect transistor and a preparation method thereof.The transistor comprises a substrate layer and a gate layer arranged on the surface of the substrate layer in a protruding mode, and a channel layer is arranged above the gate layer; the channel layer strides over the gate layer and is provided with a channel region located over the gate layer, two electrode regions located on the two opposite sides of the gate layer and a rising region connected between the electrode regions and the channel region, the channel layer is made of transition metal chalcogenide, and the electrode regions are used for conducting induced phase change through a lithium embedding method; therefore, edge contact of the metal phase and the semiconductor phase is realized. According to the invention, lithium embedding is limited by utilizing stress, and local stress is additionally introduced into the channel layer by utilizing a step formed by the gate layer and the substrate layer, so that the diffusion behavior of lithium ions is blocked and limited at a stress existence position, namely a rising region, preparation of a sharper phase transformation interface can be realized, and the method has high consistency and is convenient for large-scale integration.

Description

Technical Field

[0001] The present invention belongs to the technical field related to semiconductor devices, and more specifically, relates to an edge contact type field effect transistor and a preparation method thereof. Background Art

[0002] As semiconductor feature sizes gradually shrink, silicon technology is rapidly approaching its fundamental limit at nodes below 10 nanometers. Field effect transistors require new channel materials. Two-dimensional (2D) semiconductors have outstanding advantages such as atomic-level thickness, no surface dangling bonds, and high carrier mobility, which make two-dimensional semiconductor transistors have better electrostatic control and conduction performance, making them a strong competitor for the next generation of channel materials. Internationally, the Institute of Electrical and Electronics Engineers (IEEE) has long listed two-dimensional materials as key materials for further improving transistor integration density in its annual technology roadmap (IRDS).

[0003] In traditional silicon-based transistors, heavy doping of the source and drain is used to achieve ohmic contact between the metal electrode and the semiconductor at the source and drain, thereby reducing contact resistance. At the same time, the polysilicon gate above the channel is used as an ion diffusion barrier in the channel region during heavy doping. In this way, high-quality metal-semiconductor contact at the source and drain can be achieved while ensuring the self-alignment effect between the source and drain active regions and the gate. However, the atomically thin nature of two-dimensional materials makes it difficult for them to withstand the structural damage caused by traditional doping methods, and it is impossible to achieve ohmic contact between metal and semiconductor by high-concentration doping of the source and drain. Therefore, the low-quality contact interface between the metal and the semiconductor in two-dimensional transistor devices limits further performance improvements.

[0004] Based on the unique 2H / 1T structure of transition metal dichalcogenides (TMDCs) and the associated semiconductor / metallic transition, a new idea for realizing a new homologous edge-type metal-semiconductor contact through phase change engineering is provided. In 2014, the team of Professor Chhowalla.M of Rutgers University in the United States used the Li embedding method to induce MoS2 to transform from the 2H phase to the 1T phase, and for the first time used phase change engineering to prepare edge-contact transistors, transforming the metal-semiconductor surface contact into a homologous edge contact of the in-plane metal phase-semiconductor phase, which greatly improved the on-state current of the MoS2 semiconductor transistor.

[0005] However, the Li embedding method is based on the embedding of lithium ions between TMDCs layers and inducing their phase change. The disordered diffusion of lithium ions within the layers causes the phase change interface to be rough and the precision is not ideal. The existing photoresist barrier process cannot achieve the precise preparation of atomic-level sharp phase change interfaces, which leads to potential interface defects and pinning effects, and even causes device short circuits, limiting the performance of transistors. The uncontrollable position of the phase change interface will also lead to poor uniformity in device preparation and the inability to align the gate with the source and drain regions of the phase change, limiting the further array integration of two-dimensional transistors and hindering their application.

[0006] In summary, in two-dimensional semiconductor transistor devices, under the existing process, when the Li embedding method is used to prepare edge contacts, it is difficult to achieve atomic-level sharpness of the phase change interface and controllable preparation of the phase change interface position, which greatly limits the further improvement of the performance of two-dimensional transistors and array integration. Summary of the invention

[0007] In response to the above defects or improvement needs of the prior art, the present invention provides an edge contact field effect transistor and a method for preparing the same, which is used to solve the problem that in a two-dimensional semiconductor transistor device, the existing process of preparing edge contacts by Li embedding method is difficult to achieve controllable preparation of the phase change interface position. The phase change interface can be controlled in the prepared two-dimensional transistor, thereby obtaining a high-quality metal-semiconductor contact interface with high consistency for large-scale integration.

[0008] To achieve the above-mentioned purpose, according to one aspect of the present invention, there is provided an edge contact field effect transistor, comprising a substrate layer and a gate layer protruding from the surface of the substrate layer, a channel layer being provided above the gate layer, the channel layer being arranged across the gate layer so that the channel layer has a channel region located directly above the gate layer, two electrode regions located on opposite sides of the gate layer, and a rising region connected between any of the electrode regions and the channel region, the material of the channel layer is a transition metal sulfide compound, the electrode region is used to induce phase change through a lithium embedding method and then transform into a metal phase, so as to achieve edge contact between the metal phase and the semiconductor phase.

[0009] The edge contact field effect transistor provided by the present invention further comprises an insulating layer provided between the gate layer and the channel layer, wherein the gate layer and the channel layer are separated by the insulating layer;

[0010] And / or, the electrode region is connected to a metal electrode.

[0011] According to the edge contact field effect transistor provided by the present invention, when the transistor is a floating gate field effect transistor structure for storage, the gate layer is a floating gate layer.

[0012] According to the edge contact field effect transistor provided by the present invention, the floating gate layer is a graphene layer; the channel layer is a molybdenum sulfide layer; and the substrate layer is a silicon wafer with a silicon oxide layer.

[0013] According to the edge contact field effect transistor provided by the present invention, the electrode region is specifically exposed to n-butyl lithium solution for lithium embedding at least in a local portion, and lithium ions are embedded in the electrode region to induce a phase change in the electrode region into a metal phase.

[0014] According to the edge contact field effect transistor provided by the present invention, the height of the gate layer protruding from the substrate layer is 10-20nm; the concentration of the n-butyl lithium solution is 2-3M; and the time for which the electrode region is exposed to the n-butyl lithium solution is 1-3h.

[0015] According to another aspect of the present invention, a method for preparing an edge contact field effect transistor is provided, which is used to prepare the edge contact field effect transistor described in any one of the above items, and the preparation method comprises:

[0016] Performing cleaning pretreatment on the substrate layer;

[0017] Preparing the gate layer on the surface of the substrate layer, wherein the gate layer is obtained by mechanical stripping;

[0018] The channel layer is prepared on the surface of the substrate layer, and the channel layer is arranged across the gate layer, so that the channel layer has a channel region located directly above the gate layer, two electrode regions located on opposite sides of the gate layer, and a rising region connected between any of the electrode regions and the channel region, wherein the channel layer is obtained by mechanical stripping;

[0019] Disposing a protective layer on the surface of the channel layer, wherein the protective layer covers the channel region and the rising region, and at least a partial portion of the electrode region is exposed;

[0020] The device after the protective layer is set is immersed in a lithium solution for lithium insertion induction, and is taken out after a preset induction time to obtain a transistor in which the electrode region is transformed into a metal phase to achieve edge contact between the metal phase and the semiconductor phase.

[0021] According to the method for preparing an edge contact field effect transistor provided by the present invention, after preparing the gate layer on the surface of the substrate layer and before preparing the channel layer, the method further comprises:

[0022] Preparing an insulating layer above the gate layer, wherein the insulating layer is obtained by mechanical stripping;

[0023] Accordingly, the channel layer is prepared above the insulating layer.

[0024] According to the method for preparing an edge contact field effect transistor provided by the present invention, after the substrate layer is cleaned and pretreated and before the gate layer is prepared, the method further comprises:

[0025] A cross mark is prepared on the surface of the substrate layer to mark the position of the gate layer when preparing the gate layer.

[0026] According to the method for preparing an edge contact field effect transistor provided by the present invention, after obtaining the transistor in which the electrode region is transformed into a metal phase, the method further comprises:

[0027] A metal electrode is prepared on the electrode region by adopting a metal thermal evaporation process.

[0028] In general, compared with the prior art, the edge contact field effect transistor and the preparation method thereof provided by the present invention are as follows:

[0029] 1. A transistor structure and preparation process for stress-limited lithium embedding phase change are proposed. The steps with a sudden height difference formed by the gate layer material and the substrate layer are used to introduce additional local stress in the transition metal chalcogenide channel layer, so that the material produces local deformation in the stress area, that is, forms a rising area, resulting in a smaller interlayer spacing here, and increasing the diffusion energy barrier, thereby blocking the diffusion behavior of lithium ions at the stress location, that is, the rising area, that is, the physical edge of the gate layer. The phase change induced by lithium ions also ends here. Compared with the traditional method of only using photolithography mask protection, the contact interface is greatly optimized, the defect state density is reduced, and a sharper phase change interface can be prepared, avoiding the problem of irregular expansion of the phase change interface; at the same time, the position of lithium embedding phase change can be accurately limited, and the uniformity of device preparation is improved. It is particularly significant in improving the uniformity and success rate of arrayed device preparation, which is convenient for large-scale integrated manufacturing;

[0030] 2. The transistor structure and preparation process of stress-limited lithium-embedded phase change can also achieve the self-alignment effect between the edge of the floating gate material and the edge of the semiconductor channel, which not only avoids the parasitic capacitance caused by the overlap of the source, drain and floating gate parts, but also avoids the problem of the channel part being unadjustable due to the floating gate area being smaller than the semiconductor channel area, significantly improving the transistor performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the structure of constructing a gate layer on the surface of a substrate layer provided by the present invention;

[0032] Figure 2 It is a schematic diagram of the structure of preparing an insulating layer by transferring materials on a gate layer provided by the present invention;

[0033] Figure 3It is a schematic diagram of the structure of preparing a channel layer by transfer based on a gate layer and an insulating layer provided by the present invention;

[0034] Figure 4 It is a schematic diagram of the structure of protecting the surface of a device with an inert material provided by the present invention;

[0035] Figure 5 It is a schematic diagram of the structure after the electrode region of the to-be-intercalated channel layer is exposed provided by the present invention;

[0036] Figure 6 It is a schematic structural diagram of lithium embedding / intercalation treatment of a device provided by the present invention;

[0037] Figure 7 It is a schematic diagram of the structure of a complete transistor unit device obtained by depositing Cr / Au metal on the exposed area to prepare source and drain electrodes after the lithium embedding / intercalation treatment provided by the present invention;

[0038] Figure 8 This is a light microscopic image of an edge contact field effect transistor with a self-alignment effect that is actually prepared by the present invention;

[0039] Fig. 9 It is a structure and optical microscope comparison diagram of the edge contact field effect transistor provided by the present invention;

[0040] Fig.10 It is a flow chart of a method for preparing an edge contact field effect transistor provided by the present invention;

[0041] Fig.11 The diagram is a back gate transfer characteristic curve showing the change of the source-drain current of the field effect transistor provided by the present invention with different back gate scanning voltages, and a diagram showing the change of the extracted storage window size with the back gate scanning voltage;

[0042] Fig.12 It is a graph of source-drain current level changes after a -15V back gate pulse writing voltage of different widths is applied to the field effect transistor provided by the present invention, and a graph of the source-drain current ratio before and after the pulse is extracted, wherein a constant bias voltage of 0.1V is applied to the source and drain;

[0043] Fig.13 It is a graph of source-drain current level changes after a 15V back gate pulse erase voltage of different widths is applied to the field effect transistor provided by the present invention, and a graph of the source-drain current ratio before and after the pulse is extracted, wherein a 0.1V constant bias voltage is applied to the source and drain;

[0044] Fig.14 It is a comparison diagram of an edge contact field effect transistor prepared by a conventional photoresist blocking method and a self-aligned edge contact field effect transistor prepared by a stress limiting process according to the present invention;

[0045] Throughout the drawings, the same reference numerals are used to denote the same elements or structures, wherein:

[0046] 201 - substrate layer, 202 - gate layer, 203 - insulating layer, 204 - channel layer, 205 - protection layer, 206 - exposed area, 207 - lithium ions, 208 - metal electrode. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0048] See also Figures 1 to 7 The first embodiment provides an edge contact type field effect transistor, which includes a substrate layer 201 and a gate layer 202 protruding from the surface of the substrate layer 201. Figure 1 As shown; a channel layer 204 is provided above the gate layer 202, and the channel layer 204 is arranged across the gate layer 202, so that the channel layer 204 has a channel region located directly above the gate layer 202, two electrode regions located on opposite sides of the gate layer 202, and a rising region connected between any of the electrode regions and the channel region, as shown Figure 3 shown.

[0049] refer to Figure 6 and Figure 7 , the material of the channel layer 204 is a transition metal sulfide compound, and the electrode region is used to induce phase change through lithium embedding method and then transform into a metal phase to achieve edge contact between the metal phase and the semiconductor phase. Due to the step limitation of the gate layer 202, the channel layer 204 forms a channel region and an electrode region with a height difference when it is set, and the rising region is connected between the electrode region and the channel region. The channel layer 204 is an integrated structure, so that the rising region will be squeezed and connected between the electrode region and the channel region, resulting in an increase in the material interlayer pressure in the rising region, so that when the electrode region is induced to change phase by lithium embedding method, the material interlayer pressure in the rising region can block the diffusion of lithium ions 207, so that when the lithium ions 207 diffuse from the electrode region to the rising region, they will stop continuing to diffuse due to resistance, thereby being able to control the phase change interface at the rising region, that is, to control the position of the phase change interface.

[0050] That is, the rising region is used to block the diffusion of lithium ions 207 from the electrode region to the channel region during the lithium embedding process, so that the channel region maintains the semiconductor phase, thereby achieving edge contact between the metal phase and the semiconductor phase; and the phase change interface can be controlled in the rising region, achieving precise preparation of atomic-level sharp phase change interfaces, and at the same time achieving a self-alignment effect between the phase change interface and the edge of the gate layer 202, which is convenient for large-scale integrated manufacturing.

[0051] This embodiment takes into account that in the prior art, when edge-contact floating-gate transistors are prepared by lithium embedding / intercalation methods, the phase change interface is rough and the position cannot be precisely controlled due to the disordered diffusion of lithium ions 207, which limits the further improvement of transistor performance and subsequent array integration. This embodiment proposes a stress limiting process to improve the lithium embedding / intercalation phase change method, based on which an edge-contact field effect transistor that can achieve a self-alignment effect is prepared, which can achieve fast erasing when used for storage and has the potential for array integration.

[0052] This embodiment proposes a new edge contact field effect transistor structure, which realizes the precise preparation of sharp phase change interfaces at the atomic level, thereby significantly reducing interface defects and improving the performance of unit transistor devices. Through structural design, the position of the phase change contact interface is precisely controlled to achieve self-alignment with the edge of the floating gate layer, facilitating large-scale integrated manufacturing.

[0053] The above edge contact is achieved by inducing the transition metal chalcogenide compound in the electrode region to change into a metal phase by a lithium embedding method. The transition metal chalcogenide compound in the electrode region is exposed to a lithium solution such as an n-butyl lithium solution for lithium embedding, and lithium ions 207 are embedded in the interlayer of the transition metal chalcogenide compound and diffuse inward. The transition metal chalcogenide compound at the position where the lithium ions 207 are embedded is induced to change into a metal phase, and the position where the lithium ions 207 are not embedded still maintains a semiconductor phase, and finally the edge contact between the transition metal chalcogenide compounds in the metal phase on both sides and the semiconductor phase channel region in the middle that has not changed is achieved.

[0054] By utilizing the characteristics of different phase structures of transition metal chalcogenides, the rough surface contact between the traditional electrode and the two-dimensional semiconductor is transformed into an edge contact between the metal phase and the semiconductor phase within the same two-dimensional material surface through phase change. This enables more efficient carrier injection and realizes high-speed operation of the transistor. For example, high-speed erasing and writing is achieved when the transistor is used as a memory.

[0055] The above-mentioned atomic-level sharp phase change interface and self-alignment effect are achieved through structural design. The step with a sudden height difference formed by the physical edge of the gate layer 202 material and the substrate layer 201 is used to introduce additional local stress in the surface of the transition metal sulfide channel layer 204 (that is, the force exerted by the gate layer 202 on the channel layer 204 when the channel layer 204 is set), so that the material produces local deformation in the stress area (that is, forms a rising area), resulting in a smaller interlayer spacing here, thereby increasing the diffusion energy barrier, thereby blocking the diffusion behavior of lithium ions 207 at the position where the stress exists, namely the rising area, that is, the physical edge position of the gate layer 202, and the phase change induced by the lithium ions 207 also ends here, ultimately achieving the atomic-level sharp phase change interface and the self-alignment effect of the edge contact position and the physical edge of the floating gate.

[0056] Further, refer to Figure 2 The edge contact field effect transistor further includes an insulating layer 203 disposed between the gate layer 202 and the channel layer 204, and the gate layer 202 and the channel layer 204 are separated by the insulating layer 203; the insulating layer 203 should completely separate the gate layer 202 and the channel layer 204 so that there is no contact between the two. The insulating layer 203 is also disposed in contact with the upper surface and side surface of the gate layer 202, and has a stress deformation region at the side surface of the gate layer 202.

[0057] refer to Figure 7 The electrode regions are connected to metal electrodes 208. The metal electrode 208 connected to one of the electrode regions is a source, and the metal electrode 208 connected to the other electrode region is a drain.

[0058] In some specific embodiments, when the transistor is a floating gate field effect transistor structure for storage, the gate layer 202 is a floating gate layer. Specifically, the floating gate layer is a few-layer graphene; the channel layer 204 is molybdenum sulfide; and the substrate layer 201 is a silicon wafer with a silicon oxide layer.

[0059] refer to Figure 7 The transistor uses a silicon wafer with a silicon oxide layer as a substrate layer 201, and from the substrate layer 201 upwards are a floating gate layer, an insulating layer 203, a transition metal chalcogenide compound as a channel layer 204, and a source and a drain electrode prepared by an electrode evaporation process on the channel layer 204. The transition metal chalcogenide compound of the channel layer 204 is phase-changed to a metal phase near the contact area with the metal electrode 208, while the middle is a semiconductor phase, thereby achieving edge contact, and the phase-changed edge is self-aligned with the edge of the few-layer graphene as the floating gate layer.

[0060] Specifically, the physical edge of the floating gate layer material and the substrate layer 201 together form a structure with a sudden height difference, and stress deformation is introduced between the insulating layer 203 and the transition metal sulfide compound as the channel layer 204, and the lithium embedding diffusion position in the transition metal sulfide compound of the channel layer 204 is further limited to the stress deformation position, that is, the material edge of the floating gate layer. Finally, the self-alignment effect of the semiconductor channel and the floating gate layer position is achieved. The transistor is formed by stacking each layer of material on the substrate layer 201 in sequence by mechanically peeling and transferring the material.

[0061] In some specific embodiments, the electrode region is specifically exposed to an n-butyl lithium solution for lithium embedding, and the electrode region is induced to undergo a phase change to a metal phase by embedding lithium ions 207 into the electrode region. That is, the electrode region is provided with an exposed region 206, and the exposed region 206 is a local portion of the electrode region or the entire electrode region. Optionally, the exposed region 206 is located at the edge of the electrode region, that is, the edge of the electrode region is the exposed region 206, so that the lithium ions in the lithium solution are embedded into the channel layer material through the edge of the electrode region.

[0062] For the channel layer 204 of the transistor, a lithium embedding method is used to induce a phase change in the transition metal chalcogenide in the electrode region. During the process, lithium ions 207 are embedded in the transition metal chalcogenide layers and diffuse internally, so that the transition metal chalcogenide at the position where the lithium ions 207 are embedded is transformed from a semiconductor phase to a metal phase, and then forms an edge contact with the semiconductor phase transition metal chalcogenide in the middle that has not undergone a phase change.

[0063] In some specific embodiments, the height of the floating gate layer protruding from the substrate layer 201 is 10-20nm; the concentration of the n-butyl lithium solution is 2-3M; and the time for which the electrode region is exposed to the n-butyl lithium solution is 1-3h. This embodiment comprehensively considers that the height of the floating gate layer, the concentration of the lithium solution, and the exposure time of the electrode region in the lithium solution will affect the degree of diffusion of lithium ions 207 from the electrode region to the inside. Through research, it is found that within the above parameter range, the phase change interface can be better controlled in the rising region to achieve a better phase change interface.

[0064] The second embodiment provides a method for preparing an edge contact field effect transistor, which is used to prepare the edge contact field effect transistor described in any one of the above items, and the preparation method comprises:

[0065] The substrate layer 201 is cleaned and pre-treated; specifically, the substrate layer 201 is selected; a silicon wafer with a 300nm silicon oxide layer on the surface is selected as the substrate layer 201, and the substrate layer 201 is cleaned by acetone, ethanol, and deionized water respectively through an ultrasonic cleaner, and the surface moisture is blown dry.

[0066] The gate layer 202 is prepared on the surface of the substrate layer 201, wherein the gate layer 202 is obtained by mechanical stripping; the specific location of the construction of the gate layer 202 is as follows: a single crystal as a gate material is taken, thinned by mechanical stripping, and then transferred to the substrate layer 201, and a material with a suitable shape and thickness is selected under an optical microscope as the gate layer 202.

[0067] The channel layer 204 is prepared on the surface of the substrate layer 201, referring to Figure 3 and Figure 8 , the channel layer 204 is arranged across the gate layer 202, so that the channel layer 204 has a channel region located directly above the gate layer 202, two electrode regions located on opposite sides of the gate layer 202, and a rising region connected between any of the electrode regions and the channel region, wherein the channel layer 204 is obtained by mechanical stripping; the construction of the channel layer 204 is specifically as follows: a two-dimensional material as the channel layer 204 is taken, and a material of a suitable shape and thickness is selected after mechanical stripping and thinning, and is transferred to the substrate layer 201 at a suitable angle according to the required structural requirements, that is, it is necessary to cross the gate layer 202, so that the channel layer 204 has two electrode regions located on opposite sides of the gate layer 202, a channel region located above the gate layer 202, and a rising region.

[0068] A protective layer 205 is disposed on the surface of the channel layer 204, wherein the protective layer 205 covers the channel region and the rising region, and at least a partial portion of the electrode region is exposed; Figure 5 and Figure 6 The protection of the deformation area, i.e., the rising area, and the non-phase change area, i.e., the channel area, and the exposure of the remaining phase change areas, i.e., the electrode areas, are specifically as follows: according to the characteristics of the phase change material, the non-phase change channel area directly above the gate layer 202 and the rising area near the step are protected by inert materials such as photoresist and oxide, and the channel material on both sides of the gate layer 202, i.e., the area near the edge of the electrode area, is exposed.

[0069] The device after the protective layer 205 is provided is immersed in a lithium solution for lithium insertion induction, and is taken out after a preset induction time to obtain a transistor in which the electrode region is transformed into a metal phase to achieve edge contact between the metal phase and the semiconductor phase. Figure 6 and Figure 7 , Implementation of self-aligned phase change edge contact: Using the Li intercalation / embedding phase change method, the device that has gone through the above steps together with the substrate is immersed in an n-butyl lithium solution, taken out after a certain period of time, and rinsed with n-hexane and anhydrous ethanol in turn and blown dry.

[0070] Furthermore, after the gate layer 202 is prepared on the surface of the substrate layer 201 and before the channel layer 204 is prepared, the method further includes:

[0071] An insulating layer 203 is prepared on the gate layer 202, wherein the insulating layer 203 is obtained by mechanical stripping; accordingly, the channel layer 204 is prepared on the insulating layer 203. That is, the two-dimensional materials used as the insulating layer 203 and the channel layer 204 are taken, and after mechanical stripping and thinning, materials of suitable shape and thickness are selected, and are sequentially transferred to the gate layer 202 at a suitable angle according to the required structural requirements.

[0072] After the substrate layer 201 is cleaned and pre-treated and before the gate layer 202 is prepared, the method further includes:

[0073] A cross mark is prepared on the surface of the substrate layer 201 to mark the position of the gate layer 202 when preparing the gate layer 202. A cross mark is prepared on the substrate surface; after spin coating of photoresist, photoresist baking, ultraviolet lithography, development, fixing, and metal thermal evaporation processes, a cross mark and digital marking are prepared on the substrate surface to form a coordinate system for later material point transfer. For example, when constructing the gate layer 202, the gate layer 202 is transferred to the above-mentioned marked substrate, and a material with a suitable shape and thickness is selected as the gate layer 202 under a light microscope, and the coordinates are recorded. The insulating layer 203 and the channel layer 204 can be transferred at a fixed point according to the coordinates of the gate layer 202.

[0074] Further, after obtaining the transistor in which the electrode region is transformed into a metal phase, the method further comprises:

[0075] A metal electrode 208 is prepared on the electrode region by using a metal thermal evaporation process. Figure 7 , electrode construction; for the device after phase change treatment, a metal thermal evaporation process is used to cover the exposed areas on both sides of the electrode area with metal electrodes 208, which serve as source and drain electrodes respectively, and further patterning processing methods such as photolithography are combined to lead out the electrodes, such as Figure 8 and Fig. 9 shown.

[0076] The following are specific embodiments:

[0077] Example 1

[0078] like Figures 1 to 7 As shown, in this embodiment, a few-layer graphene is used as the floating gate layer material, hexagonal boron nitride is used as the insulating layer 203 material, and molybdenum sulfide is used as the channel layer 204 material to achieve the construction of an edge contact field effect transistor unit device with a self-aligned effect, referring to Fig.10 , which may include the following steps:

[0079] Step S1, selection and treatment of substrate silicon wafer; in this embodiment, an oxide silicon wafer with an oxide layer thickness of 300nm is selected as the unit device substrate, and then the surface impurities are removed by cleaning to obtain a substrate with a clean surface. The cleaning method is as follows: immerse the silicon wafer in beakers containing acetone, ethanol, and deionized water in turn, and put them into an ultrasonic cleaning machine for ultrasonic cleaning for 5 minutes respectively. After cleaning, take it out with tweezers and immediately blow off the surface deionized water with a nitrogen gun, and then store it in a vacuum environment for later use.

[0080] Step S2, preparation of a cross mark on the substrate surface; spin-coat AR-P 5350 type ultraviolet photoresist on the clean substrate surface, the spin-coating machine speed is 4000r / min, the spin-coating time is 1min, and then placed on a 150°C heating plate for 5min to evaporate the solvent. Select a suitable mark mask, use an ultraviolet photolithography machine for contact exposure, and use the corresponding AR300-26 developer for development after exposure. After successful development, use a high vacuum coating machine to evaporate Cr (10nm) / Au (40nm), and then use acetone to remove the photoresist and the Cr / Au metal above the photoresist, leaving the mark metal mark of the exposure area on the substrate surface. At this point, the preparation of the cross mark on the substrate surface is completed.

[0081] Step S3, construction of floating gate layer: select a small piece of graphite single crystal, place it on a highly transparent tape, and thin it through repeated mechanical peeling to obtain a suitable few-layer graphene as the floating gate layer. Use a plasma cleaner to perform O2 Plasma hydrophilic treatment on the substrate, then stick the tape covered with few-layer graphene on the substrate, press it gently and peel it off, and the material will be transferred to the substrate silicon wafer. Find the few-layer graphene with suitable thickness and shape under the optical microscope and record the coordinates as the floating gate layer of the device, such as Figure 1 shown.

[0082] Step S4, construction of the insulating layer 203 and the channel layer 204; the insulating layer 203 and the channel layer 204 are constructed by mechanical stripping and fixed-point transfer, and the specific process is as follows: the thin layer of h-BN, i.e. the insulating layer 203 and the MoS2 material are respectively obtained by the above-mentioned mechanical stripping method, the tape with the thin layer of material is attached to the block of polydimethylsiloxane (PDMS), and it is peeled off after gently pressing, and the material is transferred to the PDMS, and the material of suitable thickness and shape is found under the optical microscope, and it is transferred to the top of the graphene floating gate layer in step S3 in sequence by using the two-dimensional material transfer platform as the insulating layer 203 and the channel layer 204, which are sequentially constructed. Figure 2 and Figure 3The structure shown. During the construction process, the physical edge of the few-layer graphene material in the floating gate layer forms a step stress structure together with the substrate, and external stress is introduced into the surface of the h-BN and MoS2 materials on it. The stress position is the edge position of the graphene material. The MoS2 directly above the graphene material is the adjustable channel area, and the two sides of it are the electrode areas that need to undergo phase change treatment.

[0083] Step S5, protection of the deformation zone and the non-phase change zone and exposure of the remaining phase change zones; in this embodiment, the protection of the deformation zone and the non-phase change zone is achieved by spin coating PMMA, such as Figure 4 As shown, the PMMA protective layer 205 in the area near the edge of MoS2 on both sides of the source and drain is removed by EBL treatment and development, forming Figure 5 The exposed area 206 shown is exposed in this area. However, the present invention is not limited thereto, and other inert materials such as photoresists and oxides, as well as other reasonable protective material removal methods can be used according to the characteristics of the intercalation material, as long as the protection of the deformation area and the non-intercalation area and the exposure of the remaining phase change areas can be achieved.

[0084] Step S6, realization of self-aligned phase change edge contact; adopt Li intercalation / embedding phase change method, select 2.5M n-butyl lithium solution, immerse the device after the above steps together with the substrate silicon wafer into the n-butyl lithium solution in the inert gas environment of the glove box, and the lithium ions 207 begin to embed from the edges of the MoS2 on both sides of the exposed source and drain, diffuse along the material layer to the middle step position, and change the MoS2 at the path from the semiconductor phase to the metal phase, and stop at the physical edge of the floating gate material where there is step stress, such as Figure 6 As shown. After 2 hours, the silicon wafer was taken out and rinsed with n-hexane and anhydrous ethanol in turn to remove the residual reagents on the surface. However, the present invention is not limited to this. According to the material thickness, temperature and other conditions, the organic lithium solution with a suitable concentration can be selected, the phase change treatment time can be adjusted, and the appropriate rinsing reagent can be selected, as long as the lithium ion 207 intercalation of the material can be achieved and the diffusion behavior can be successfully limited under the action of the step stress.

[0085] Step S7, electrode construction; after the phase change treatment and cleaning of the phase change reagent, Cr (10nm) / Au (40nm) is thermally evaporated using a high vacuum coating apparatus, and then the photoresist and the Cr / Au metal thereon are removed using acetone, leaving the Cr / Au metal in the exposed area 206 in step S5 as the source and drain of the device, and at the same time plays a protective role in the intercalation start area, such as Figure 7 After that, referring to the process flow in step S5, the source and drain electrodes of the device are respectively led out through the processes of spin coating PMMA, EBL treatment, development, and thermal evaporation of Cr (10nm) / Au (40nm), so as to facilitate the subsequent electrical testing using a probe station, see Figure 8 and Fig. 9 .

[0086] Step S8, performance test: using a probe station test system and a semiconductor analyzer, the transistor unit device constructed is tested for transistor-related performance. Fig.11 , Fig.12 , Fig.13 As shown. Fig.11 It can be concluded that the transistor has an on-state current as high as microamperes and an off-state current as low as picoamperes, and has a large storage window. Under a back gate scan voltage of plus or minus 20V, the storage window is about 30V, and it further increases with the increase of the scan voltage. Fig.12 and Fig.13 The following are the changes in the source-drain current level after applying back-gate pulse voltages of different widths, and the extracted source-drain current ratio before and after the pulse. A constant bias of 0.1V is applied to the source and drain, and the back-gate pulse voltages are -15V and 15V respectively. This reflects the write / erase speed of the transistor when it is used for storage, which is the core performance indicator of the memory. From the results, it can be seen that the transistor memory can achieve a write speed of nearly 10 at a write voltage of 10ns. 4 The on / off ratio can reach 10 with a write / erase pulse of 1μs. 8 The complete write / erase ratio of the switch has an extremely excellent erase speed.

[0087] Comparative Example 1

[0088] like Fig.14 , is a comparison between an edge contact field effect transistor prepared by a conventional photoresist blocking method and a self-aligned edge contact field effect transistor prepared by the stress limiting process of the present invention. Fig.14 (a)(c)(e) are data graphs of edge-contact field effect transistors prepared by the traditional photoresist blocking method, and (b)(d)(f) are data graphs of self-aligned edge-contact field effect transistors prepared by the stress limiting process of the present invention. Among them, (a)(b) is a comparison of two optical microscope images after the transfer of each layer of material is completed and the area to be intercalated is exposed. (c)(d) are data graphs obtained by Raman mapping the device after phase change induction treatment using Li embedding / intercalation method. (e)(f) are respectively the changes in the source-drain current of the two prepared field effect transistors with the floating gate voltage, that is, the floating gate transfer characteristic curves.

[0089] Depend on Fig.14It can be seen from (a) and (b) that when the edge contact transistor is prepared by the traditional photoresist blocking method, the source, drain and channel are at the same height, all directly above the floating gate layer. When the self-aligned edge contact transistor is prepared by the stress limiting process, the step structure formed by the physical edge of the floating gate material and the substrate is used. There is only a semiconductor phase channel directly above the floating gate layer, and the two sides of the floating gate layer, i.e., the two sides of the step, are the source and drain regions to be phase-changed. During the phase change process, lithium ions 207 are embedded in MoS2 from the exposed window and diffuse from the interlayer to the surrounding area.

[0090] Fig.14 (c) and (d) in the figure are data graphs obtained by Ramanmapping characterization of the device after phase change induction treatment using Li embedding / intercalation method. The characteristic peak area of ​​semiconductor phase MoS2 is used as a reference. The brighter position indicates that MoS2 is a semiconductor phase here, and the darker position indicates that there is no semiconductor phase MoS2 here, that is, the lithium ion 207 has induced the phase change of MoS2 here to a metal phase, and the interface between the metal phase and the semiconductor phase has been represented by a white dotted line in the figure. It is not difficult to conclude from the figure that the traditional method of using only photoresist blocking cannot effectively limit the diffusion of lithium ions 207. Lithium ions 207 have diffused across the photoresist blocking position to diffuse into the middle channel area, and the metal phases on both sides tend to connect together, and the phase change interface is very rough. On the contrary, Fig.14 The phase change interface in (d) is very sharp and achieves self-alignment with the edge of the floating gate layer material below, which indicates that the stress limiting process can effectively limit the diffusion of lithium ions 207, prepare a sharp phase change interface, and achieve self-alignment between the semiconductor phase channel and the floating gate layer in the field effect transistor structure.

[0091] Fig.14 (e) and (f) in the figure are the floating gate transfer characteristic curves of the two transistors prepared, that is, the source-drain current changes with the floating gate voltage. The horizontal axis is the voltage applied to the floating gate layer, and the vertical axis is the source-drain current, which shows the regulation effect of the floating gate layer on the intermediate semiconductor phase channel region. It can be concluded that the self-aligned edge contact transistor prepared based on the stress limiting process has a lower off-state current, a lower subthreshold swing, and can achieve a higher switching ratio, which reflects its high-quality contact interface and better channel regulation effect. The edge contact transistor prepared by the traditional photoresist blocking method is the opposite, which is consistent with the rough phase change interface and the metal phase phase change of the channel part in (c).

[0092] In summary, the structure constructed in this embodiment is a self-aligned edge contact field effect transistor of molybdenum disulfide / hexagonal boron nitride / few-layer graphene, and the molybdenum disulfide near the source and drain is subjected to phase change induction treatment by lithium embedding / intercalation method, so that its phase changes to a metal phase, and the phase change behavior is precisely limited by means of the step structure formed by the physical edge of the floating gate layer material and the substrate, thereby achieving high-quality metal-semiconductor contact on the basis of preparing a sharp phase change interface, and the prepared transistor has a high storage window (storage window of 30V under ±20V back gate scanning), high erase speed (10ns write, 1μs erase), and high switching ratio (10 6 -10 8 ), low subthreshold swing (floating gate subthreshold swing is about 80mv / dec), and at the same time, self-alignment of the semiconductor channel and the floating gate layer is achieved, which improves the uniformity of device preparation and facilitates array integration.

[0093] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An edge contact field effect transistor, characterized in that: It includes a substrate layer and a gate layer protruding from the surface of the substrate layer, a channel layer is provided above the gate layer, and the channel layer is arranged across the gate layer, so that the channel layer has a channel region located directly above the gate layer, two electrode regions located on opposite sides of the gate layer, and a rising region connected between any of the electrode regions and the channel region, the material of the channel layer is a transition metal sulfide compound, and the electrode region is used to induce phase change through a lithium embedding method and then transform into a metal phase to achieve edge contact between the metal phase and the semiconductor phase.

2. The edge contact field effect transistor according to claim 1, characterized in that: Also comprising an insulating layer disposed between the gate layer and the channel layer, the gate layer and the channel layer being separated by the insulating layer; And / or, the electrode region is connected to a metal electrode.

3. The edge contact field effect transistor according to claim 1, characterized in that: When the transistor is a floating gate field effect transistor structure for storage, the gate layer is a floating gate layer.

4. The edge contact field effect transistor according to claim 3, characterized in that: The floating gate layer is a graphene layer; the channel layer is a molybdenum sulfide layer; and the substrate layer is a silicon wafer with a silicon oxide layer.

5. The edge contact field effect transistor according to any one of claims 1 to 4, characterized in that: The electrode region is specifically exposed to an n-butyllithium solution at least partially for lithium insertion, and the electrode region is induced to undergo a phase change into a metal phase by the insertion of lithium ions into the electrode region.

6. The edge contact field effect transistor according to claim 5, characterized in that: The height of the gate layer protruding from the substrate layer is 10-20 nm; the concentration of the n-butyl lithium solution is 2-3 M; and the time for which the electrode region is exposed to the n-butyl lithium solution is 1-3 hours.

7. A method for preparing an edge contact field effect transistor, characterized in that: For preparing an edge contact field effect transistor according to any one of claims 1 to 6, the preparation method comprises: Performing cleaning pretreatment on the substrate layer; Preparing the gate layer on the surface of the substrate layer, wherein the gate layer is obtained by mechanical stripping; The channel layer is prepared on the surface of the substrate layer, and the channel layer is arranged across the gate layer, so that the channel layer has a channel region located directly above the gate layer, two electrode regions located on opposite sides of the gate layer, and a rising region connected between any of the electrode regions and the channel region, wherein the channel layer is obtained by mechanical stripping; Disposing a protective layer on the surface of the channel layer, wherein the protective layer covers the channel region and the rising region, and at least a partial portion of the electrode region is exposed; The device after the protective layer is set is immersed in a lithium solution for lithium insertion induction, and is taken out after a preset induction time to obtain a transistor in which the electrode region is transformed into a metal phase to achieve edge contact between the metal phase and the semiconductor phase.

8. The method for preparing an edge contact field effect transistor according to claim 7, characterized in that: After preparing the gate layer on the surface of the substrate layer and before preparing the channel layer, the method further includes: Preparing an insulating layer above the gate layer, wherein the insulating layer is obtained by mechanical stripping; Accordingly, the channel layer is prepared above the insulating layer.

9. The method for preparing an edge contact field effect transistor according to claim 7, characterized in that: After the substrate layer is cleaned and pre-treated and before the gate layer is prepared, the method further includes: A cross mark is prepared on the surface of the substrate layer to mark the position of the gate layer when preparing the gate layer.

10. The method for preparing an edge contact field effect transistor according to claim 7, characterized in that: After obtaining the transistor in which the electrode region is transformed into a metal phase, the method further includes: preparing a metal electrode on the electrode region by using a metal thermal evaporation process.

Images