Display panel and display device

Abstract

The invention discloses a display panel and a display device, and relates to the technical field of display, the display panel comprises a substrate, an active layer located on one side of the substrate and multiple metal layers located on the side, away from the substrate, of the active layer, and the multiple metal layers comprise the first metal layer and the second metal layer; the display panel comprises a first shielding area, and at least part of an active layer is located in the first shielding area; the first shielding area is arranged in the direction perpendicular to the plane where the substrate base plate is located, and at least one of the entity part of the first metal layer and the entity part of the second metal layer covers the first shielding area, so that the active layer in the first shielding area is covered, and the active layer in the first shielding area is prevented from being affected when a light emitting diode is bonded through laser; and meanwhile, a plurality of openings are formed in the first metal layer, and a plurality of openings are formed in the second metal layer, so that the areas of the entity part of the first metal layer and the entity part of the second metal layer are reduced, the overlapping area of the two is reduced, and the short-circuit risk of the two is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Light Emitting Diode (LED) display panels, such as Micro LED display panels and Mini-LED display panels, have many advantages such as self-luminescence, low driving voltage, high luminous efficiency, short response time, high clarity and contrast, and have gradually become a research hotspot in the field of display technology.

[0003] When preparing a light-emitting diode display panel, the light-emitting diode needs to be fixed to the array substrate by laser bonding technology. However, the array substrate includes an active layer, and when laser bonding the light-emitting diode, it is easy to affect at least part of the active layer, thereby affecting the performance of the thin film transistor including at least part of the active layer. Summary of the invention

[0004] To solve the above technical problems, the embodiments of the present application provide a display panel and a display device to avoid affecting at least part of the active layer in the array substrate when laser bonding light-emitting diodes, thereby avoiding affecting the performance of the thin film transistor including at least part of the active layer.

[0005] To achieve the above objectives, the present application provides the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a display panel, the display panel comprising:

[0007] substrate substrate;

[0008] An active layer located on one side of the substrate base;

[0009] A multi-layer metal layer located on a side of the active layer away from the substrate, the multi-layer metal layer comprising a first metal layer and a second metal layer, the first metal layer comprising a solid portion and a plurality of openings, the second metal layer comprising a solid portion and a plurality of openings;

[0010] The display panel comprises a first shielding area, and at least a part of the active layer is located in the first shielding area;

[0011] In a direction perpendicular to the plane where the substrate is located, at least one of the solid portion of the first metal layer and the solid portion of the second metal layer covers the first shielding area.

[0012] In a second aspect, based on the same inventive concept, an embodiment of the present application further provides a display device, which includes the above-mentioned display panel.

[0013] Compared with the prior art, the above technical solution has the following advantages:

[0014] The display panel provided by the embodiment of the present application includes a base substrate, an active layer located on one side of the base substrate, and a multi-layer metal layer located on the side of the active layer away from the base substrate, the multi-layer metal layer includes a first metal layer and a second metal layer; the display panel includes a first shielding area, and at least part of the active layer is located in the first shielding area; by being arranged in a direction perpendicular to the plane where the base substrate is located, at least one of the solid part of the first metal layer and the solid part of the second metal layer covers the first shielding area, thereby covering the active layer in the first shielding area, so as to avoid affecting the active layer in the first shielding area when laser bonding the light-emitting diode, thereby avoiding affecting the performance of the thin film transistor including the active layer in the first shielding area.

[0015] Furthermore, considering that in actual processes, arc discharge is prone to occur when a large area of ​​metal is placed in a vacuum machine for patterning, the area of ​​the solid part of the first metal layer and the area of ​​the solid part of the second metal layer are subject to certain restrictions; furthermore, considering that in a direction perpendicular to the plane where the substrate is located, if the overlapping area of ​​the solid part of the first metal layer and the solid part of the second metal layer is large, a short circuit between the first metal layer and the second metal layer may be easily caused when the insulating layer between the first metal layer and the second metal layer is damaged. Therefore, a plurality of openings are opened in the first metal layer to reduce the area of ​​the solid part of the first metal layer, and a plurality of openings are opened in the second metal layer to reduce the area of ​​the solid part of the second metal layer, thereby reducing the risk of arc discharge when the first metal layer and the second metal layer are placed in a vacuum machine for patterning, and the overlapping area of ​​the solid part of the first metal layer and the solid part of the second metal layer in a direction perpendicular to the plane where the substrate is located may also be reduced, thereby reducing the risk of a short circuit between the first metal layer and the second metal layer when the insulating layer between the first metal layer and the second metal layer is damaged. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic diagram of a partial cross-sectional structure of an array substrate in a display panel provided in an embodiment of the present application;

[0018] Figure 2 A schematic diagram of a partial layout structure of a display panel provided in an embodiment of the present application;

[0019] Figure 3 for Figure 2 Schematic diagram of the layout structure of the active layer q;

[0020] Figure 4 for Figure 2 Schematic diagram of the layout structure of the first metal layer M3;

[0021] Figure 5 for Figure 2 A schematic diagram of the layout structure of the second metal layer M4;

[0022] Figure 6 A schematic diagram of a short circuit between the first metal layer M3 and the second metal layer M4 caused by damage to the insulating layer PLN between the two metal layers;

[0023] Figure 7 A schematic diagram of a circuit structure of a pixel circuit 110 in a display panel provided in an embodiment of the present application;

[0024] Figure 8 for Figure 7 A timing diagram of the pixel circuit 110 is shown;

[0025] Fig. 9 A partial cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0026] Fig.10 A schematic diagram of a partial layout structure of another display panel provided in an embodiment of the present application;

[0027] Fig.11 for Fig.10 Schematic diagram of the layout structure of the active layer q;

[0028] Fig.12 for Fig.10 Schematic diagram of the layout structure of the first metal layer M3;

[0029] Fig.13 for Fig.10 A schematic diagram of the layout structure of the second metal layer M4;

[0030] Fig.14 for Figure 4 The layout structure of the first metal layer M3 and Figure 5 A schematic diagram of the stacking structure of the second metal layer M4;

[0031] Fig.15 A partially enlarged schematic diagram of an area CC1 in a first shielding area CC in a display panel provided in an embodiment of the present application;

[0032] Fig.16Another partially enlarged schematic diagram of a region CC1 in a first shielding region CC in a display panel provided in an embodiment of the present application;

[0033] Fig.17 A schematic diagram of a partial layout structure of another display panel provided in an embodiment of the present application;

[0034] Fig.18 for Fig.17 Schematic diagram of the layout structure of the active layer q;

[0035] Fig.19 for Fig.17 Schematic diagram of the layout structure of the first metal layer M3;

[0036] Fig. 20 for Fig.17 A schematic diagram of the layout structure of the second metal layer M4;

[0037] Fig.21 A schematic diagram of a partial cross-sectional structure of a first metal layer M3 and a second metal layer M4 in a display panel provided in an embodiment of the present application;

[0038] Fig.22a A schematic cross-sectional structure diagram of a design pattern of the first metal layer M3 and the second metal layer M4 in the display panel provided in an embodiment of the present application;

[0039] Figure 22b A schematic cross-sectional structure diagram of an actual pattern of the first metal layer M3 and the second metal layer M4 in the display panel provided in the embodiment of the present application;

[0040] Fig.23a A schematic cross-sectional structure diagram of another design pattern of the first metal layer M3 and the second metal layer M4 in the display panel provided in an embodiment of the present application;

[0041] Figure 23b A schematic cross-sectional structure diagram of another actual pattern of the first metal layer M3 and the second metal layer M4 in the display panel provided in an embodiment of the present application;

[0042] Fig.24 A schematic diagram of a partial layout stacking of an active layer q, a metal layer M1 and a metal layer M2 in a display panel provided in an embodiment of the present application;

[0043] Fig.25 A partial enlarged schematic diagram of the first metal layer M3 and the second metal layer M4 in the wiring area FF in the display panel provided in the embodiment of the present application;

[0044] Fig.26 A schematic diagram of a partial layout structure of another display panel provided in an embodiment of the present application;

[0045] Fig. 27 for Fig.26 Schematic diagram of the layout structure of the active layer q;

[0046] Fig.28 for Fig.26 Schematic diagram of the layout structure of the first metal layer M3;

[0047] Fig.29 for Fig.26 A schematic diagram of the layout structure of the second metal layer M4;

[0048] Fig.30 A schematic diagram of the structure of a display device provided in an embodiment of the present application;

[0049] Fig.31 A schematic diagram of the structure of another display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0051] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0052] As described in the background technology section, when preparing a light-emitting diode display panel, the light-emitting diode needs to be fixed to the array substrate by laser bonding technology. However, the array substrate includes an active layer, and when laser bonding the light-emitting diode, it is easy to affect at least part of the active layer, thereby affecting the performance of the thin film transistor including at least part of the active layer.

[0053] In view of this, an embodiment of the present application provides a display panel, which includes an array substrate and light emitting diodes located on the array substrate. Figure 1 FIG. 1 is a schematic diagram showing a partial cross-sectional structure of an array substrate 100 in a display panel provided in an embodiment of the present application. Figure 1As shown, the array substrate 100 in the display panel includes a base substrate sub, an active layer q located on one side of the base substrate sub, and a multi-layer metal layer located on the side of the active layer q away from the base substrate sub. The multi-layer metal layers are, for example, a metal layer M1, a metal layer M2, a metal layer M3 and a metal layer M4 arranged in sequence along a direction away from the base substrate sub. A metal layer, such as a metal layer M0, may also be provided on the side of the active layer q facing the base substrate sub. The multi-layer metal layers on the side of the active layer q away from the base substrate sub include a first metal layer M3 and a second metal layer M4. The first metal layer M3 includes a solid portion 10 and a plurality of openings 11. The second metal layer M4 also includes a solid portion 20 and a plurality of openings 21.

[0054] Figure 2 FIG. 1 is a schematic diagram of a partial layout structure of a display panel provided in an embodiment of the present application. For the sake of clarity, Figure 2 Only the layout structure of the active layer q, the layout structure of the first metal layer M3 and the layout structure of the second metal layer M4 are shown. Figure 3 Shows Figure 2 Schematic diagram of the layout structure of the active layer q, Figure 4 Shows Figure 2 Schematic diagram of the layout structure of the first metal layer M3, Figure 5 Shows Figure 2 Schematic diagram of the layout structure of the second metal layer M4. Figure 2-Figure 5 As shown, the display panel includes a first blocking area CC, at least a portion of the active layer q is located in the first blocking area CC, and, in a direction perpendicular to the plane where the substrate sub is located, at least one of the physical part 10 of the first metal layer M3 and the physical part 20 of the second metal layer M4 covers the first blocking area CC, that is, at least one of the physical part 10 of the first metal layer M3 and the physical part 20 of the second metal layer M4 completely blocks the first blocking area CC.

[0055] It can be understood that, in a direction perpendicular to the plane where the substrate sub is located, at least one of the physical part 10 of the first metal layer M3 and the physical part 20 of the second metal layer M4 covers the first shielding area CC, that is, optionally, the physical part 10 of the first metal layer M3 covers the first shielding area CC, or, the physical part 20 of the second metal layer M4 covers the first shielding area CC, or, the physical part 10 of the first metal layer M3 and the physical part 20 of the second metal layer M4 jointly cover the first shielding area CC.

[0056] In the display panel provided in the embodiment of the present application, since at least part of the active layer q is located in the first blocking area CC, and the first metal layer M3 and the second metal layer M4 are located on the side of the active layer q away from the substrate sub, the first blocking area CC is covered by at least one of the physical portion 10 of the first metal layer M3 and the physical portion 20 of the second metal layer M4, so that the active layer q in the first blocking area CC is covered by at least one of the physical portion 10 of the first metal layer M3 and the physical portion 20 of the second metal layer M4, thereby avoiding affecting the active layer q in the first blocking area CC when laser bonding the light-emitting diode, and further avoiding affecting the performance of the thin film transistor including the active layer q in the first blocking area CC.

[0057] Furthermore, considering that in the actual process, arc discharge is prone to occur when a large area of ​​metal is patterned in a vacuum machine, the area of ​​the entity part 10 of the first metal layer M3 and the area of ​​the entity part 20 of the second metal layer M4 are subject to certain restrictions; furthermore, considering that in the direction perpendicular to the plane where the substrate sub is located, if the overlapping area of ​​the entity part 10 of the first metal layer M3 and the entity part 20 of the second metal layer M4 is large, then Figure 6 As shown, when the insulating layer PLN between the first metal layer M3 and the second metal layer M4 is damaged, it is easy to cause a short circuit between the two metal layers; Figure 1 , Figure 2 as well as Figure 4-Figure 5 As shown, a plurality of openings 11 are opened in the first metal layer M3 to reduce the area of ​​the entity part 10 of the first metal layer M3, and a plurality of openings 21 are opened in the second metal layer M4 to reduce the area of ​​the entity part 20 of the second metal layer M4, thereby reducing the risk of arc discharge when the first metal layer M3 and the second metal layer M4 are subjected to patterning in a vacuum machine, and can also reduce the overlapping area of ​​the entity part 10 of the first metal layer M3 and the entity part 20 of the second metal layer M4 in a direction perpendicular to the plane where the substrate sub is located, thereby reducing the risk of short circuit between the first metal layer M3 and the second metal layer M4 when the insulating layer between the first metal layer M3 and the second metal layer M4 is damaged.

[0058] Different metal layers in the display panel are isolated by an insulating layer, which not only isolates but also protects and supports them. Figure 1 As shown, there is an insulating layer PLN between the first metal layer M3 and the second metal layer M4, and the insulating layer PLN is an organic material layer, that is, the insulating layer PLN is an organic insulating layer. Alternatively, the insulating layer PLN may also be an inorganic material layer.

[0059] Compared with an inorganic material layer as an insulating layer, an organic material layer as an insulating layer usually has a lower manufacturing cost; moreover, the organic material layer usually has good chemical stability and physical properties, can resist the erosion of environmental factors such as moisture and oxygen, and is beneficial to extending the service life of the display panel; the organic material layer also has good flexibility and customization. However, the organic insulating layer will volatilize gas in some high-temperature processes, and exhaust design is required. In the display panel provided in the embodiment of the present application, a plurality of openings 11 are opened in the first metal layer M3, and a plurality of openings 21 are opened in the second metal layer M4, which is beneficial to the exhaust of the organic insulating layer between the first metal layer M3 and the second metal layer M4.

[0060] It is understandable that if Figure 2 As shown, the array substrate 100 in the display panel includes a plurality of pixel circuits 110, and the pixel circuits 110 are used to drive the light emitting diodes 200 to emit light. Figure 7 A schematic diagram of a circuit structure of a pixel circuit 110 is shown. Figure 7 As shown, the pixel circuit 110 may include a pulse width module 111 controlled by PWM (Pulse Width Modulation) and an amplitude module 112 controlled by PAM (Pulse Amplitude Modulation) so as to achieve the best luminous efficiency and viewing angle color bias of the driven light emitting diode 200. The pulse width module 111 in the pixel circuit 110 may include 6 thin film transistors (T1-T6) and a capacitor (C1), which receives scan signals WS1 and WS2, data signal Vdata1, light control signal Emit1, reference signal Vref1, off voltage Voff and pulse width control voltage Sweep, and is used to control the light emission duration of the light emitting diode 200; the amplitude module 112 in the pixel circuit 110 may include 6 thin film transistors (T7-T12) and a capacitor (C2), which receives scan signals AS1 and AS2, data signal Vdata2, light control signal Emit2, reference signal Vref2, first power supply voltage VPVDD and second power supply voltage VPVEE, and is used to control the light emission intensity of the light emitting diode 200. The connection mode of each thin film transistor in the pixel circuit 110 and the access signal are as follows: Figure 7 As shown, no further details are given.

[0061] Obviously, Figure 7 The pixel circuit 110 shown is only one type of pixel circuit in the light emitting diode display panel. In practical applications, the implementation method of the pixel circuit can be selected based on the needs and is not limited to Figure 7 The circuit structure shown.

[0062] In order to better understand this application, Figure 7 The thin film transistors T1 - T12 are all P-type transistors, and are turned on under a low-level signal as an example to illustrate the working process of the pixel circuit 110 .

[0063] refer to Figure 8 , first, in the first stage S1011 of the signal generation stage S101, also referred to as the initialization stage, for the pulse width module 111, the scan signal WS1 is at a low level, and the scan signal WS2 and the light-emitting control signal Emit1 are at a high level, so that the transistor T2 is turned on, and the reference signal Vref1 is transmitted to the gate of the transistor T5, so that the gate T5 of the transistor is initialized; similarly, for the amplitude module 112, the scan signal AS1 is at a low level, and the scan signal AS2 and the light-emitting control signal Emit2 are at a high level, so that the transistor T7 is turned on, and the reference signal Vref2 is transmitted to the gate of the transistor T10, so that the gate of the transistor T10 is initialized.

[0064] Secondly, in the second stage S1012 of the signal generation stage S101, for the pulse width module 111, the scanning signal WS2 is at a low level, the scanning signal WS1 and the light emitting control signal Emit1 are at a high level, at this time, the transistor T3, the transistor T5 and the transistor T6 are all turned on, forming a path from the data signal Vdata1 to the gate of the transistor T5, so as to pull up the voltage of the lower electrode of the capacitor C1, until the voltage of the lower plate of the capacitor C1 is pulled up to the point where the transistor T5 cannot be turned on, so that the first end of the transistor T1 is in a high impedance state and connected to the floating Empty signal; similarly, for the amplitude module 112, the scanning signal AS2 is at a low level, the scanning signal AS1 and the light control signal Emit2 are at a high level, at this time, the transistors T8, T9 and T10 are turned on, forming a path from the data signal Vdata2 to the gate of the transistor T10, so as to pull up the voltage of the lower plate of the capacitor C2 until the voltage of the lower electrode of the capacitor C2 is pulled up to the point where the transistor T10 cannot be kept turned on, and at this time, the voltage of the lower plate of the capacitor C2 is the corresponding voltage for controlling the light intensity of the light-emitting diode 200.

[0065] Next, in the control processing stage S102, for the pulse width module 111, the light control signal Emit1 is a low level signal, and the transistor T1 transmits the floating signal to the gate of the transistor T10 of the amplitude module 112; for the amplitude module 112, the light control signal Emit2 is still high level, so the transistors T11 and T12 are in the off state, so that the transistor T10 cannot be turned on, so as to avoid the fluctuation stage in which the transistor T1 initially transmits the floating signal to the gate of the transistor T10. In addition, due to the control of the pulse width control voltage Sweep at this time, the voltage of the lower electrode of the capacitor C1 still cannot control the transistor T5 to be turned on, and the path from the off voltage Voff to the transistor T10 remains in the off state.

[0066] Then, in the light-emitting control stage S103, for the amplitude module 112, the light-emitting control signal Emit2 is a low-level signal, and the transistors T11, T10, and T12 are all turned on, forming a path from the first power supply voltage VPVDD to the light-emitting diode 200 and the second power supply voltage VPVEE. The transistor T10 outputs a corresponding driving current to the light-emitting diode 200 according to the signal of its gate and the signal of its first terminal, and the light-emitting diode 200 emits light in response to the driving current. At this time, for the pulse width module 111, due to the control of the pulse width control voltage Sweep, the voltage of the lower electrode of the capacitor C1 still cannot control the transistor T5 to turn on, and the path from the off voltage Voff to the transistor T10 remains in the off state.

[0067] Afterwards, in the light-emitting cut-off stage S104, since the pulse width control voltage Sweep is a linearly decreasing voltage, in this stage the pulse width control voltage Sweep decreases to a voltage at the lower plate of the capacitor C1 that can control the transistor T5 to turn on, thereby forming a path for the off voltage Voff to the transistor T10, and the off voltage Voff is transmitted to the gate of the transistor T10 to control the T10 transistor to turn off, thereby turning off the light-emitting diode 200.

[0068] like Figure 1 As shown, the thin film transistor Tx (for example, any one of T1-T12) in the pixel circuit 110 includes an active portion b1, a gate g1, a source electrode s1, and a drain electrode d1, wherein the active portion b1 of the thin film transistor Tx is located in the active layer q. Figure 2 and Figure 3As shown, the active layer q of the display panel includes a first active portion q1, and the pixel circuit 110 includes the first active portion q1, the first active portion q1 includes the active portion of each thin film transistor in the pixel circuit 110, and the first active portion q1 is located in the first blocking area CC, that is, the active portion of each thin film transistor in the pixel circuit 110 is located in the first blocking area CC. In this way, since at least one of the entity portion 10 of the first metal layer M3 and the entity portion 20 of the second metal layer M4 covers the first blocking area CC, that is, covers the active portion of each thin film transistor in the pixel circuit 110 in the direction perpendicular to the plane where the substrate sub is located, it can avoid affecting the active portion of each thin film transistor in the pixel circuit 110 when laser bonding the light emitting diode, thereby avoiding affecting the performance of the pixel circuit 110 and ensuring the normal light emission of the light emitting diode.

[0069] It should be noted that in this application, for the sake of clarity, some drawings such as Figure 2 and Figure 3 The first active portion q1 in the pixel circuit 110 represents the pixel circuit 110 . It is understandable that the pixel circuit 110 also includes other film layer structures, which will not be described in detail.

[0070] It should also be noted that, in the present application, it is not limited to which metal layer the first metal layer M3 is located among the multiple metal layers on the side of the active layer q away from the substrate sub, nor is it limited to which metal layer the second metal layer M4 is located among the multiple metal layers on the side of the active layer q away from the substrate sub, nor is it limited to whether the first metal layer M3 and the second metal layer M4 are adjacent metal layers.

[0071] Optional, combined Figure 4 and Figure 7 As shown, the entity portion 10 of the first metal layer M3 includes a first power structure PVDD, and the first power structure PVDD is used to provide a first power voltage VPVDD; Figure 5 and Figure 7 As shown, the physical part 20 of the second metal layer M4 includes a second power structure PVEE, which is used to provide a second power voltage VPVEE; in this way, in a direction perpendicular to the plane where the substrate sub is located, at least one of the first power structure PVDD and the second power structure PVEE can be used to cover the first shielding area CC, that is, to cover the first active part q1 of the pixel circuit 110.

[0072] It is understood that the display panel includes a plurality of light emitting diodes 200. Figure 4 and Figure 7As shown, the first power structure PVDD (used to provide the first power voltage VPVDD) is electrically connected to the pixel circuit 110, and then the pixel circuit 110 is electrically connected to the first electrode 201 of the light emitting diode 200; Figure 5 and Figure 7 As shown, the second power structure PVEE (used to provide a second power voltage VPVEE) is electrically connected to the second electrode 202 of the light emitting diode 200 .

[0073] For example, Fig. 9 A partial cross-sectional schematic diagram of a display panel provided in an embodiment of the present application is shown. Fig. 9 As shown, the light-emitting diode 200 includes a first semiconductor layer 203, a quantum well layer 204 and a second semiconductor layer 205 which are stacked. The first semiconductor layer 203 is electrically connected to the first electrode 201, and the second semiconductor layer 205 is electrically connected to the second electrode 202. The first power structure PVDD located in the first metal layer M3 is electrically connected to the pixel circuit 110, and the pixel circuit 110 is further electrically connected to the first electrode 201 of the light-emitting diode 200. The second power structure PVEE located in the metal layer M4 is electrically connected to the second electrode 202 of the light-emitting diode 200.

[0074] It should be noted that, in the present application, the electrical connection between the two may be direct electrical connection or indirect electrical connection. Fig. 9 As shown, the second power structure PVEE located on the metal layer M4 is electrically connected to the second electrode 202 of the light-emitting diode 200 through the bonding layer 206, and the pixel circuit 110 is electrically connected to the first electrode 201 of the light-emitting diode 200 through the auxiliary electrode located on the metal layer M3, the auxiliary electrode located on the metal layer M4 and the bonding layer.

[0075] It should also be noted that Fig. 9 The example in which the first electrode 201 and the second electrode 202 of the light-emitting diode 200 are both facing the array substrate 100 is used for demonstration. In this case, the light-emitting diode 200 is a flip-chip structure. Alternatively, the first electrode 201 and the second electrode 202 of the light-emitting diode 200 may also be both away from the array substrate 100, in which case the light-emitting diode 200 is a normal structure; the first electrode 201 and the second electrode 202 of the light-emitting diode 200 may also have one facing the array substrate 100 and the other away from the array substrate 100, in which case the light-emitting diode 200 is a vertical structure. When the light-emitting diode 200 is a normal structure and a vertical structure, the electrical connection relationship of the light-emitting diode 200 is not affected, that is, the first power structure PVDD located in the first metal layer M3 is still electrically connected to the pixel circuit 110, and the pixel circuit 110 is electrically connected to the first electrode 201 of the light-emitting diode 200, and the second power structure PVEE located in the metal layer M4 is electrically connected to the second electrode 202 of the light-emitting diode 200.

[0076] In existing light-emitting diode display panels, the first power structure PVDD usually adopts a grid line distribution, and due to process limitations, the thickness of the metal layer where the first power structure PVDD is located is limited to a certain extent, resulting in a large impedance of the first power structure PVDD and a large difference in IR drop across the entire surface of the first power structure PVDD, which easily affects the brightness uniformity of the display panel.

[0077] Similarly, in existing light-emitting diode display panels, the second power structure PVEE also usually adopts a grid line distribution, and due to process limitations, the thickness of the metal layer where the second power structure PVDD is located is also limited to a certain extent, resulting in a larger impedance of the second power structure PVEE. The IR drop of the entire surface of the second power structure PVEE varies greatly, which easily affects the brightness uniformity of the display panel.

[0078] In the display panel provided in the embodiment of the present application, in the direction perpendicular to the plane where the substrate sub is located, if at least one of the first power structure PVDD and the second power structure PVEE is to be used to cover the first shielding area CC, it is necessary to increase the area of ​​the first power structure PVDD and / or the area of ​​the second power structure PVEE to ensure that at least one of the first power structure PVDD and the second power structure PVEE covers the first shielding area CC. When the area of ​​the first power structure PVDD is increased, the impedance of the first power structure PVDD can be reduced, thereby improving the display brightness uniformity of the display panel. When the area of ​​the second power structure PVEE is increased, the impedance of the second power structure PVEE can be reduced, thereby improving the display brightness uniformity of the display panel. When the area of ​​the first power structure PVDD and the area of ​​the second power structure PVEE are increased at the same time, the impedance of the first power structure PVDD can be reduced, and the impedance of the second power structure PVEE can also be reduced, thereby improving the display brightness uniformity of the display panel.

[0079] refer to Figure 7 As shown, in the display panel, the pixel circuits 110 and the light emitting diodes 200 are arranged in a one-to-one correspondence. Figure 2 and Figure 5 The partial layout structure of the display panel shown in FIG. 1 also shows a schematic diagram of the bonding position of the first electrode 201 and the second electrode 202 of the light-emitting diode 200. For the convenience of notation, the bonding position of the first electrode 201 and the second electrode 202 of the light-emitting diode 200 is used to represent the light-emitting diode 200. Figure 2 and Figure 5 As shown, in the display panel, at least two light emitting diodes 200 form a light emitting element group 210. Figure 2 and Figure 3As shown, at least two pixel circuits 110 form a pixel circuit group 120 , and the first active portion q1 of each pixel circuit 110 in the pixel circuit group 120 is located in the first blocking area CC.

[0080] Optional, such as Figure 2 and Figure 5 As shown, the light emitting diode 200 includes a first light emitting diode 211, a second light emitting diode 212 and a third light emitting diode 213. The first light emitting diode 211 can be used to emit red light, the second light emitting diode 212 can be used to emit green light, and the third light emitting diode 213 can be used to emit blue light. A group of light emitting elements 210 includes a first light emitting diode 211, a second light emitting diode 212 and a third light emitting diode 213. Accordingly, as Figure 2 and Figure 3 As shown, a pixel circuit group 120 includes a pixel circuit 110 that drives a first light emitting diode 211 to emit light, a pixel circuit 110 that drives a second light emitting diode 212 to emit light, and a pixel circuit 110 that drives a third light emitting diode 213 to emit light.

[0081] On this basis, optional Figure 2 and Figure 4 As shown, in a direction perpendicular to the plane where the substrate sub is located, the first power structure PVDD at least partially overlaps with a group of pixel circuit groups 120, and the second power structure PVEE at least partially overlaps with a group of pixel circuit groups 120. Further optionally, as Figure 2 and Figure 4 As shown, the first power structure PVDD covers the orthographic projection area of ​​a group of pixel circuit groups 120 on the plane where the substrate sub is located in the orthographic projection area of ​​the plane where the substrate sub is located, and the second power structure PVEE covers the orthographic projection area of ​​a group of pixel circuit groups 120 on the plane where the substrate sub is located in the orthographic projection area of ​​the plane where the substrate sub is located.

[0082] Another option, Fig.10 A schematic diagram of a partial layout structure of another display panel provided in an embodiment of the present application is shown, similar to Figure 2 For clarity of illustration, Fig.10 Only the layout structure of the active layer q, the layout structure of the first metal layer M3, the layout structure of the second metal layer M4, and the bonding positions of the first electrode 201 and the second electrode 202 of the light emitting diode 200 are shown. Fig.11 Shows Fig.10 Schematic diagram of the layout structure of the active layer q, Fig.12 Shows Fig.10 Schematic diagram of the layout structure of the first metal layer M3, Fig.13 Shows Fig.10Schematic diagram of the layout structure of the second metal layer M4. Fig.10 and Fig.13 As shown, the light emitting element groups 210 are arranged in a row along the first direction X, and multiple rows of light emitting element groups 210 are arranged along the second direction Y, wherein the first direction X and the second direction Y intersect, and the first direction X and the second direction Y are parallel to the plane where the substrate sub is located. Optionally, the first direction X and the second direction Y are perpendicular, that is, the light emitting element groups 210 are arranged in an array along the first direction X and the second direction Y. Accordingly, as Fig.10 and Fig.11 As shown, the pixel circuit groups 120 are arranged in a row along the first direction X, and multiple rows of pixel circuit groups 120 are arranged along the second direction Y, that is, the pixel circuit groups 120 can also be arranged in an array in the first direction X and the second direction Y.

[0083] like Figure 10-13 As shown, in a direction perpendicular to the plane where the substrate sub is located, the first power structure PVDD overlaps at least partially with four groups of pixel circuit groups 120 overlapping two adjacent rows of pixel circuit groups 120 and two adjacent columns of pixel circuit groups 120; further optionally, as Figure 10-13 As shown, the orthographic projection area of ​​the first power structure PVDD on the plane where the substrate sub is located covers the orthographic projection area of ​​the 2*2 pixel circuit group 120 on the plane where the substrate sub is located.

[0084] like Figure 10-13 As shown, in a direction perpendicular to the plane where the substrate sub is located, the second power structure PVEE overlaps at least partially with four groups of pixel circuit groups 120 overlapping two adjacent rows of pixel circuit groups 120 and two adjacent columns of pixel circuit groups 120; further optionally, as Figure 10-13 As shown, the orthographic projection area of ​​the second power structure PVEE on the plane where the substrate sub is located covers the orthographic projection area of ​​the 2*2 pixel circuit group 120 on the plane where the substrate sub is located.

[0085] By analogy, the orthographic projection area of ​​the first power structure PVDD on the plane where the substrate sub is located can also cover 3*3, 3*4, 4*3, 4*4... and other different matrix pixel circuit groups 120 and the orthographic projection areas of all pixel circuit groups 120 on the plane where the substrate sub is located, and even the orthographic projection area of ​​the first power structure PVDD on the plane where the substrate sub is located can cover the entire display area of ​​the display panel; and, as the orthographic projection area of ​​the first power structure PVDD on the plane where the substrate sub is located increases, the area of ​​the first power structure PVDD increases, and the impedance of the first power structure PVDD decreases, the more conducive it is to improving the display brightness uniformity of the display panel.

[0086] Similarly, the orthographic projection area of ​​the second power supply structure PVEE on the plane where the substrate sub is located can also cover 3*3, 3*4, 4*3, 4*4... and other different matrix pixel circuit groups 120 and the orthographic projection areas of all pixel circuit groups 120 on the plane where the substrate sub is located, and even the orthographic projection area of ​​the second power supply structure PVEE on the plane where the substrate sub is located can cover the entire display area of ​​the display panel; and, as the orthographic projection area of ​​the second power supply structure PVEE on the plane where the substrate sub is located increases, the area of ​​the second power supply structure PVEE increases, and the impedance of the second power supply structure PVEE decreases, which is more conducive to improving the display brightness uniformity of the display panel.

[0087] It should be noted that a group of pixel circuit groups 120 and a group of light emitting element groups 210 constitute a pixel unit pixel. Figure 2-Figure 5 It shows a pixel unit. Figure 10-13 Four pixel units are shown schematically, and the four pixel units form a matrix of two rows and two columns (ie, 2*2) along a first direction X and a second direction Y. In order to clearly distinguish different pixel units, Figure 10-13 In the figure, horizontal lines and vertical lines are used to indicate the boundaries of adjacent pixel unit regions along the first direction X and the second direction Y. It can be understood that the boundaries are only for the convenience of explanation and are not intended to limit the present invention.

[0088] like Figure 7 As shown, the pixel circuit 110 includes a pulse width module 111 and an amplitude module 112. From the above analysis of the pixel circuit 110, it can be seen that although the pulse width module 111 in the pixel circuit 110 is also connected to the off voltage Voff, the off voltage Voff is similar to the first power supply voltage VPVDD, but because the amplitude module 112 directly drives the light emitting diode 200, the first power supply structure PVDD is electrically connected to the amplitude module 112 of the pixel circuit 110, that is, the first power supply structure PVDD provides the first power supply voltage VPVDD to the amplitude module 112 of the pixel circuit 110. In this way, by increasing the area of ​​the first power supply structure PVDD, the brightness uniformity of the display panel can be more directly improved.

[0089] Although the first shielding area CC can be covered in a direction perpendicular to the plane of the substrate sub by increasing the area of ​​the first power structure PVDD and the area of ​​the second power structure PVEE, and the impedance of the first power structure PVDD and the impedance of the second power structure PVEE can be reduced, thereby improving the brightness uniformity of the display panel, but, firstly, in the actual process, arc discharge is prone to occur when a large area of ​​metal is introduced into a vacuum machine for patterning, so that the area of ​​the first power structure PVDD and the area of ​​the second power structure PVEE are subject to certain restrictions; secondly, after the area of ​​the first power structure PVDD and the area of ​​the second power structure PVEE are increased, if the overlapping area of ​​the first power structure PVDD and the second power structure PVEE is large, the short circuit of the two metal layers may be easily caused when the insulating layer between the first metal layer M3 and the second metal layer M4 is damaged; thirdly, when the insulating layer between the first metal layer M3 and the second metal layer M4 is an organic material layer, openings are also required in the first metal layer M3 and the second metal layer M4 to meet the exhaust requirements.

[0090] In summary, it is necessary to open a plurality of openings 11 in the first metal layer M3 to reduce the area of ​​the first power structure PVDD, and to open a plurality of openings 21 in the second metal layer M4 to reduce the area of ​​the second power structure PVEE, thereby reducing the risk of arc discharge when the first metal layer M3 and the second metal layer M4 enter the vacuum machine for patterning; it is also possible to reduce the overlapping area of ​​the first power structure PVDD and the second power structure PVEE in a direction perpendicular to the plane where the substrate sub is located, thereby reducing the risk of short circuit between the first power structure PVDD and the second power structure PVEE when the insulating layer between the first metal layer M3 and the second metal layer M4 is damaged; and, opening a plurality of openings 11 in the first metal layer M3 and opening a plurality of openings 21 in the second metal layer M4 is conducive to the exhaust of the organic insulating layer between the first metal layer M3 and the second metal layer M4.

[0091] The opening design of the first metal layer M3 and the second metal layer M4 is described in detail below.

[0092] Optional, such as Figure 4 As shown, the opening 11 of the first metal layer M3 includes a plurality of first openings K1; Figure 5 As shown, the opening 21 of the second metal layer M4 includes a plurality of second openings K2; Figure 4 , Figure 5 as well as Fig.14 As shown, Fig.14 For the general Figure 4 The layout structure of the first metal layer M3 and Figure 5The schematic diagram of the stacking diagram shows that the layout structure of the second metal layer M4 is stacked together. In the first blocking area CC, in the direction perpendicular to the plane of the substrate, the first opening K1 and the second opening K2 do not overlap, that is, the first opening K1 and the second opening K2 are arranged in an alternating and complementary manner, and the first opening K1 of the first metal layer M3 is blocked by the entity part 20 of the second metal layer M4, and the second opening K2 of the second metal layer M4 is blocked by the entity part 10 of the first metal layer M3, thereby avoiding affecting the active layer q in the first blocking area CC when laser bonding the light-emitting diode, and further avoiding affecting the performance of the thin film transistor including the active layer q in the first blocking area CC.

[0093] Optional, such as Figure 4 As shown, in at least a partial area CC1 in the first shielding area CC, the first openings K1 are arranged in a row along the second direction Y, a plurality of rows of first openings K1 are arranged along the first direction X, the first openings K1 of alternate rows overlap along the first direction X, and the first openings K1 of adjacent rows at least partially do not overlap along the first direction X. Further optionally, as Figure 4 As shown, in at least a partial area CC1 of the first shielding area CC, the first openings K1 of alternate columns are arranged identically along the first direction X, and the first openings K1 of adjacent columns are arranged alternately along the first direction X.

[0094] and / or, if Figure 5 As shown, in at least a partial area CC1 of the first shielding area CC, the second openings K2 are arranged in a row along the second direction Y, a plurality of rows of second openings K2 are arranged along the first direction X, the second openings K2 of alternate rows overlap along the first direction X, and the second openings K2 of adjacent rows at least partially do not overlap along the first direction X. Further optionally, as Figure 5 As shown, in at least a partial area CC1 of the first shielding area CC, the second openings K2 of alternate columns are arranged identically along the first direction X, and the second openings K2 of adjacent columns are arranged alternately along the first direction X.

[0095] It can be understood that, since in the first shielding area CC, in the direction perpendicular to the plane where the substrate is located, the first opening K1 and the second opening K2 do not overlap, and in at least a partial area CC1 of the first shielding area CC, the first openings K1 of the alternate columns are arranged in the same manner along the first direction X, and the first openings K1 of adjacent columns are arranged in a staggered manner along the first direction X, and at the same time, the second openings K2 of the alternate columns are arranged in the same manner along the first direction X, and the second openings K2 of adjacent columns are arranged in a staggered manner along the first direction X, therefore, in combination with Figure 4 , Figure 5 , Fig.14 as well as Fig.15 As shown, Fig.15A partial enlarged schematic diagram of the area CC1 in the first shielding area CC is shown, and it can be seen that the first opening K1 and the second opening K2 are arranged in an alternating and complementary manner on the orthographic projection of the first metal layer M3. Similarly, the first opening K1 and the second opening K2 are arranged in an alternating and complementary manner on the orthographic projection of the second metal layer M4. The first opening K1 of the first metal layer M3 is blocked by the entity 20 of the second metal layer M4, and the second opening K2 of the second metal layer M4 is blocked by the entity 10 of the first metal layer M3. In this way, not only the entity 10 of the first metal layer M3 and the entity 20 of the second metal layer M4 jointly shield the first shielding area CC, but also the overlapping area of ​​the entity 10 of the first metal layer M3 and the entity 20 of the second metal layer M4 in the direction perpendicular to the plane of the substrate is smaller, thereby reducing the risk of short circuit between the first metal layer M3 and the second metal layer M4 when the insulating layer between the first metal layer M3 and the second metal layer M4 is damaged.

[0096] Another option, such as Fig.16 As shown, in at least a partial area CC1 in the first shielding area CC, the first openings K1 are arranged in a row along the second direction Y, a plurality of rows of first openings K1 are arranged along the first direction X, the first openings K1 in adjacent rows overlap along the first direction X, and the first openings K1 in alternate rows overlap along the first direction X. Further optionally, as Fig.15 As shown, in at least a partial area CC1 of the first shielding area CC, the first openings K1 of adjacent columns are arranged the same along the first direction X, and the first openings K1 of alternate columns are arranged the same along the first direction X.

[0097] and / or, if Fig.16 As shown, in at least a partial area CC1 of the first shielding area CC, the second openings K2 are arranged in a row along the second direction Y, multiple rows of second openings K2 are arranged along the first direction X, the second openings K2 in adjacent rows overlap along the first direction X, and the second openings K2 in alternate rows overlap along the first direction X. Further optionally, as Fig.16 As shown, in at least a partial area CC1 of the first shielding area CC, the second openings K2 in adjacent columns are arranged identically along the first direction X, and the second openings K2 in alternate columns are arranged identically along the first direction X.

[0098] It can be understood that, since in the first shielding area CC, in the direction perpendicular to the plane where the substrate is located, the first opening K1 and the second opening K2 do not overlap, and in at least a partial area CC1 of the first shielding area CC, the first openings K1 of adjacent columns are arranged in the same manner along the first direction X, and the first openings K1 of alternate columns are arranged in the same manner along the first direction X, and at the same time, the second openings K2 of adjacent columns are arranged in the same manner along the first direction X, and the second openings K2 of alternate columns are arranged in the same manner along the first direction X, therefore, as Fig.16As shown, the first opening K1 and the second opening K2 are arranged in an alternating and complementary manner on the orthographic projection of the first metal layer M3. Similarly, the first opening K1 and the second opening K2 are arranged in an alternating and complementary manner on the orthographic projection of the second metal layer M4. The first opening K1 of the first metal layer M3 is blocked by the entity part 20 of the second metal layer M4, and the second opening K2 of the second metal layer M4 is blocked by the entity part 10 of the first metal layer M3. In this way, not only the entity part 10 of the first metal layer M3 and the entity part 20 of the second metal layer M4 jointly block the first blocking area CC, but also the overlapping area of ​​the entity part 10 of the first metal layer M3 and the entity part 20 of the second metal layer M4 in the direction perpendicular to the plane where the substrate is located is smaller, thereby reducing the risk of short circuit between the first metal layer M3 and the second metal layer M4 when the insulating layer between the first metal layer M3 and the second metal layer M4 is damaged.

[0099] Optional, such as Fig.15 and Fig.16 As shown, the shape of the first opening K1 and the shape of the second opening K2 can be the same, which facilitates the layout design of the first metal layer M3 and the second metal layer M4, but the present application is not limited to this. Alternatively, the shape of the first opening K1 can also be different from the shape of the second opening K2, depending on the specific situation.

[0100] Optional, such as Fig.15 and Fig.16 As shown, the shape of the first opening K1 and the shape of the second opening K2 can be polygonal. Fig.15 As shown, the shape of the first opening K1 and the shape of the second opening K2 are arc-angled rectangles; for another example, Fig.16 As shown, the shape of the first opening K1 and the shape of the second opening K2 are octagons. Fig.15 and Fig.16 It can be seen that compared with the octagonal shape of the first opening K1 and the octagonal shape of the second opening K2, when the shape of the first opening K1 and the shape of the second opening K2 are square, the overlapping area of ​​the solid part 10 of the first metal layer M3 and the solid part 20 of the second metal layer M4 in the direction perpendicular to the plane of the substrate is relatively smaller, which can further reduce the risk of short circuit between the first metal layer M3 and the second metal layer M4 when the insulating layer between the first metal layer M3 and the second metal layer M4 is damaged.

[0101] Optional, such as Figure 5 and Fig.14As shown, the entity part 20 of the second metal layer M4 further includes a first auxiliary electrode R1, and a third opening K3 is provided between the first auxiliary electrode R1 and the second power structure PVDD, so that the first auxiliary electrode R1 and the second power structure PVDD are insulated from each other. Since the entity part 10 of the first metal layer M3 and the entity part 20 of the second metal layer M4 jointly cover the first shielding area CC in a direction perpendicular to the plane where the substrate is located, at least the portion of the third opening K3 located in the first shielding area CC is shielded by the entity part 10 of the first metal layer M3.

[0102] Combination Figure 3 , Figure 5 and Fig. 9 As shown, the first auxiliary electrode R1 is electrically connected to the pixel circuit 110, and the first auxiliary electrode R1 is electrically connected to the first electrode 201 of the light emitting diode 200, that is, the pixel circuit 110 is electrically connected to the first electrode 201 of the light emitting diode 200 through the first auxiliary electrode R1. It can be understood that one pixel circuit 110 needs to be provided with one first auxiliary electrode R1, so as to be electrically connected to the first electrode 201 of the corresponding light emitting diode 200 through the first auxiliary electrode R1.

[0103] As is known above, at least two pixel circuits 110 form a pixel circuit group 120, and one pixel circuit group 120 corresponds to one pixel unit pixel. Optionally, Figure 2 and Figure 3 As shown, three pixel circuits 110 form a pixel circuit group 120, so in a pixel unit pixel, a first auxiliary electrode R1 is required to be respectively provided for the three pixel circuits 110 to be electrically connected to the first electrode 201 of the light emitting diode 200 corresponding to each of them. Figure 5 and Fig.14 As shown, a plurality of fourth openings K4 are provided in the second power structure PVEE between the first auxiliary electrode R1 and two adjacent first auxiliary electrodes R1. Since the area of ​​the second power structure PVEE between the first auxiliary electrode R1 and two adjacent first auxiliary electrodes R1 is relatively small, the area of ​​the fourth openings K4 provided in the second power structure PVEE between the first auxiliary electrode R1 and two adjacent first auxiliary electrodes R1 also needs to be relatively small. Optionally, the area of ​​the fourth opening K4 is smaller than the area of ​​the second opening K2.

[0104] It should be noted that the area of ​​the first opening K1 in the first metal layer M3 and the area of ​​the second opening K2 in the second metal layer M4 can be relatively large. In this way, on the one hand, the area of ​​the entity part 10 of the first metal layer M3 and the area of ​​the entity part 20 of the second metal layer M4 can be reduced, which is convenient for patterning in a vacuum machine; on the other hand, the overlapping area of ​​the entity part 10 of the first metal layer M3 and the entity part 20 of the second metal layer M4 in the direction perpendicular to the plane of the substrate can also be reduced; on the other hand, it is conducive to sufficient exhaust. Of course, the more openings are opened in the first metal layer M3 and the second metal layer M4, for example, a plurality of fourth openings K4 are provided in the second power structure PVEE between the first auxiliary electrode R1 and the two adjacent first auxiliary electrodes R1, the effects of these three aspects can also be improved.

[0105] Since a fourth opening K4 different from the second opening K2 is provided in the first auxiliary electrode R1 and the second power structure PVEE between two adjacent first auxiliary electrodes R1, the overlapped portion of the first power structure PVDD and the first auxiliary electrode R1 and the second power structure PVEE between two adjacent first auxiliary electrodes R1 in a direction perpendicular to the plane where the substrate is located may also adopt a design different from the first opening K1. Figure 4 , Figure 5 and Fig.14 As shown, the area where the first auxiliary electrode R1 and the second power structure PVEE between two adjacent first auxiliary electrodes R1 are located is set as area CC2, then in the direction perpendicular to the plane where the substrate is located, the part where the first power structure PVDD overlaps with the first auxiliary electrode R1 and the second power structure PVEE between two adjacent first auxiliary electrodes R1, that is, the part where the first active structure PVDD is located in area CC2 can be provided with a plurality of fifth openings K5, and the arrangement of the fifth openings K5 can be different from the arrangement of the first openings K1.

[0106] Optional, such as Figure 4 As shown, the fifth openings K5 are arranged in a row along the second direction Y, multiple rows of fifth openings K5 are arranged along the first direction X, the fifth openings K5 in adjacent rows overlap along the first direction X, and the fifth openings K5 in alternate rows overlap along the first direction X. Further optionally, as Figure 4 As shown, in the region CC2 , the fifth openings K5 in adjacent columns are arranged identically along the first direction X, and the fifth openings K5 in alternate columns are arranged identically along the first direction X.

[0107] Optional, combined Figure 4 , Figure 5 and Fig.14As shown, the orthographic projection of the fourth opening K4 on the first metal layer M3 and the fifth opening K5 are arranged alternately along the second direction Y. That is to say, the orthographic projection of the fourth opening K4 on the first metal layer M3 and the fifth opening K5 are arranged alternately and complementary, the fifth opening K5 of the first metal layer M3 is blocked by the entity part 20 of the second metal layer M4, and the fourth opening K4 of the second metal layer M4 is blocked by the entity part 10 of the first metal layer M3, so that not only the entity part 10 of the first metal layer M3 and the entity part 20 of the second metal layer M4 jointly block the first blocking area CC, but also the overlapping area of ​​the entity part 10 of the first metal layer M3 and the entity part 20 of the second metal layer M4 in the direction perpendicular to the plane where the substrate is located is small, thereby reducing the risk of short circuit between the first metal layer M3 and the second metal layer M4 when the insulating layer between the first metal layer M3 and the second metal layer M4 is damaged.

[0108] It is understandable that, since a local area of ​​the second metal layer M4 needs to be bonded to the light-emitting diode, the area of ​​the second metal layer M4 that needs to be bonded to the light-emitting diode cannot be provided with an opening, but this does not affect the provision of an opening in the overlapping portion of the first metal layer M3 and the second metal layer M4 that needs to be bonded to the light-emitting diode in the direction perpendicular to the plane where the substrate is located. Figure 4 , Figure 5 and Fig.14 As shown, in a direction perpendicular to the plane where the substrate is located, a plurality of fifth openings K5 are provided at overlapping portions of the first metal layer M3 and the second metal layer M4 where regions to be bonded with light emitting diodes are required.

[0109] In the first metal layer M3 , the fifth opening K5 may be equal to the first opening K1 in shape and area, but the arrangement of the fifth opening K5 and the first opening K1 may be different.

[0110] As is known above, the first auxiliary electrode R1 located in the second metal layer M4 is electrically connected to the pixel circuit 110. Optionally, as Fig. 9 As shown, the first metal layer M3 and the second metal layer M4 are located on the side of the pixel circuit 110 away from the substrate sub, and the second metal layer M4 is located on the side of the first metal layer M3 away from the substrate sub. Figure 4 , Figure 5 , Fig. 9 as well as Fig.14As shown, the physical portion 10 of the first metal layer M3 also includes a second auxiliary electrode R2, and a sixth opening K6 is provided between the second auxiliary electrode R2 and the first power structure PVDD, so that the second auxiliary electrode R2 and the first power structure PVDD are insulated from each other; in a direction perpendicular to the plane where the substrate is located, the first auxiliary electrode R1 at least partially overlaps with the second auxiliary electrode R2, the first auxiliary electrode R1 and the second auxiliary electrode R2 are electrically connected through a via between the first metal layer M3 and the second metal layer M4, and the second auxiliary electrode R2 is electrically connected to the pixel circuit 110.

[0111] It can be understood that, in the first metal layer M3, the second auxiliary electrode R2 and the first power structure PVDD are insulated from each other by the sixth opening K6; in the second metal layer M4, the first auxiliary electrode R1 and the second power structure PVEE are insulated from each other by the third opening K3; and, in a direction perpendicular to the plane where the substrate is located, the first auxiliary electrode R1 at least partially overlaps with the second auxiliary electrode R2, so that the first auxiliary electrode R1 is electrically connected to the second auxiliary electrode R2, so that in a direction perpendicular to the plane where the substrate is located, the third opening K3 and the sixth opening K6 may at least partially overlap, that is, the first metal layer M3 and the second metal layer M4 may be hollowed out in the part where the third opening K3 and the sixth opening K6 overlap, if this part of the hollowed-out area overlaps with the active layer q, then when the light-emitting diode is laser bonded, it may affect the active layer q that overlaps with this part of the hollowed-out area.

[0112] Based on this, optional, such as Figure 4 , Figure 5 and Fig.14 As shown, the first auxiliary electrode R1 can be extended to the outside of the first shielding area CC and electrically connected to the second auxiliary electrode R2, that is, the sixth opening K6 opened in the first metal layer M3 is located outside the first shielding area CC, so that in the direction perpendicular to the plane of the substrate, the hollow area where the third opening K3 and the sixth opening K6 overlap will not overlap with the active layer q, so that when the light-emitting diode is laser bonded, the active layer q will not be affected by the hollow area where the third opening K3 and the sixth opening K6 overlap.

[0113] Alternatively, the sixth opening K6 may be located in the first shielding area CC, but in a direction perpendicular to the plane of the substrate, the sixth opening K6 does not overlap with the active layer q. Thus, in a direction perpendicular to the plane of the substrate, the hollow area where the third opening K3 and the sixth opening K6 overlap will not overlap with the active layer q. Therefore, when laser bonding the light-emitting diode is performed, the active layer q will not be affected by the hollow area where the third opening K3 and the sixth opening K6 overlap.

[0114] As is known above, a group of pixel circuit groups 120 is electrically connected to a group of light emitting element groups 210 to form a pixel unit pixel. Since the pixel circuit 110 is located in the array substrate 100, as shown in FIG. Fig. 9 As shown, the pixel circuit 110 is usually composed of an active layer q, a metal layer M1 and a metal layer M2, and the light emitting diode 200 is located on the array substrate 100. Therefore, in a direction perpendicular to the plane where the substrate is located, the pixel circuit group 120 and the electrically connected light emitting element group 210 may at least partially overlap or at least partially not overlap. Regardless of whether the pixel circuit group 120 and the electrically connected light emitting element group 210 overlap, the sixth opening K6 is set outside the first shielding area CC, or even if the sixth opening K6 is located in the first shielding area CC, but in a direction perpendicular to the plane where the substrate is located, the sixth opening K6 is set not to overlap with the active layer q, which can avoid the active layer q being affected by the hollow area where the third opening K3 and the sixth opening K6 overlap.

[0115] It is understandable that when the pixel circuit group 120 and the electrically connected light emitting element group 210 at least partially do not overlap in a direction perpendicular to the plane where the substrate is located, optionally, as Figure 17-Figure 20 As shown, Fig.17 FIG. 1 is a schematic diagram showing a partial layout stacking of an active layer q, a first metal layer M3 and a second metal layer M4 in another display panel provided by an embodiment of the present application. For the sake of clarity, Fig.18 Show Fig.17 Schematic diagram of the layout structure of the active layer q, Fig.19 Show Fig.17 Schematic diagram of the layout structure of the first metal layer M3, Fig. 20 Show Fig.17 In the schematic diagram of the layout structure of the second metal layer M4, it can be seen that in the direction perpendicular to the plane where the substrate is located, the pixel circuit group 120 does not overlap with the electrically connected light emitting element group 210. In other words, a column of pixel circuit groups includes n pixel circuit groups 120, and a column of light emitting element groups includes n light emitting element groups 210. For a corresponding column of pixel circuit groups 120 and a column of light emitting element groups 210 that are electrically connected, in the direction perpendicular to the plane where the substrate is located, the i-th pixel circuit group 120 is electrically connected to the i-th light emitting element group 210, and the i+1-th pixel circuit group 120 and the light emitting element group 210 electrically connected to the i-th pixel circuit group 120 (i.e., the i-th light emitting element group 210) at least partially overlap.

[0116] like Figure 17-Figure 20As shown, in the direction perpendicular to the plane where the substrate is located, the first auxiliary electrode R1 and the second auxiliary electrode R2 overlap in a partial area CC3 in the first blocking area CC, and the second auxiliary electrode R2 and the sixth opening K6 extend at least partially from the first blocking area CC to outside the first blocking area CC, that is, the second auxiliary electrode R2 needs to be wound, so that in a corresponding electrically connected column of pixel circuit groups 120 and a column of light-emitting element groups 210, the i-th light-emitting element group 210 is electrically connected to the pixel circuit group 120 (i.e., the i+1-th pixel circuit group 120) that overlaps the i+1-th light-emitting element group 210 in the direction perpendicular to the plane where the substrate is located in sequence through the first auxiliary electrode R1 and the second auxiliary electrode R2. Wherein, Fig.19 In FIG. 1 , the arrow of the straight line extending along the second auxiliary electrode R2 represents the direction from the light emitting element to the pixel circuit.

[0117] At this point, it can be understood that since the sixth opening K6 at least partially extends from the first shielding area CC to outside the first shielding area CC, the sixth opening K6 does not overlap with the active layer q in a direction perpendicular to the plane of the substrate, so as to avoid affecting the active layer q when laser bonding the light-emitting diode.

[0118] It should be noted that by being arranged in a direction perpendicular to the plane of the substrate, the pixel circuit group 120 and the electrically connected light-emitting element group 210 at least partially do not overlap, thereby compressing the area occupied by the pixel circuit group 120 in the display area of ​​the display panel, so that the driving circuit VSR (including a multi-stage cascaded shift register circuit) that drives the pixel circuit 110 to work can also be placed in the display area of ​​the display panel, which is conducive to realizing a borderless, full-screen design of the display panel and can be applied to spliced ​​display devices.

[0119] like Figure 7 and Fig. 9 As shown, the first power structure PVDD is electrically connected to the pixel circuit 110. Specifically, the first power structure PVDD includes a first connection portion L1, and the first connection portion L1 is electrically connected to the pixel circuit 110. It can be understood that, referring to Figure 4 As shown, since a plurality of openings 11 are provided in the first metal layer M3, the first connection portion L1 may overlap with the opening 11 in a direction perpendicular to the plane of the substrate. At this time, the first connection portion L1 needs to protrude toward the opening 11 in the first metal layer M3, that is, at least a portion of the first connection portion L1 protrudes toward the opening 11 in the first metal layer M3. In this way, the opening 11 in the first metal layer M3 adjacent to the first connection portion L1 has a different shape from other openings in the first metal layer M3. For example, the area of ​​the opening 11 in the first metal layer M3 adjacent to the first connection portion L1 is smaller than the area of ​​other openings in the first metal layer M3.

[0120] As is known from the foregoing, in the first shielding area CC, in a direction perpendicular to the plane where the substrate is located, the opening 11 in the first metal layer M3 and the opening 21 in the second metal layer M4 are arranged in a staggered and complementary manner, the opening 11 in the first metal layer M3 is shielded by the entity portion 20 of the second metal layer M4, and the opening 21 in the second metal layer M4 is shielded by the entity portion 10 of the first metal layer M3, so that the entity portion 10 of the first metal layer M3 and the entity portion 20 of the second metal layer M4 jointly cover the first shielding area CC. It can be understood that, as Fig.21 As shown, considering the process error, in the first shielding area CC, the opening 21 of the second metal layer M4 needs to have a minimum distance d between the orthographic projection of the first metal layer M3 and the opening 11 of the first metal layer M3, that is, the edge of the entity part 10 of the first metal layer M3 and the edge of the entity part 20 of the second metal layer M4 overlap. The inventors have found that the minimum distance d between the orthographic projection of the opening 21 of the second metal layer M4 and the opening 11 of the first metal layer M3 needs to satisfy:

[0121]

[0122] Among them, Fig.21 As shown, H is the thickness of the insulating layer PLN between the first metal layer M3 and the second metal layer M4;

[0123] X1 is the line width difference between the design pattern of the first metal layer M3 and the actual pattern, and X2 is the line width difference between the design pattern of the second metal layer M4 and the actual pattern. For ease of understanding, Fig.22a A schematic cross-sectional structure diagram of a design pattern of the first metal layer M3 and the second metal layer M4 is shown. Figure 22b A schematic diagram of a cross-sectional structure of an actual pattern of the first metal layer M3 and the second metal layer M4 is shown. The line width of the design pattern of the first metal layer M3 is W1, and the line width of the actual pattern of the first metal layer M3 is W1'. Then the line width difference between the design pattern of the first metal layer M3 and the actual pattern is X1 = W1-W1'. Similarly, the line width of the design pattern of the second metal layer M4 is W2, and the line width of the actual pattern of the second metal layer M4 is W2'. Then the line width difference between the design pattern of the second metal layer M4 and the actual pattern is X2 = W2-W2'.

[0124] Y is the fitting accuracy between the first metal layer M3 and the second metal layer M4, Fig.23a FIG. 4 is a schematic cross-sectional structure diagram of another design pattern of the first metal layer M3 and the second metal layer M4. Figure 23b Another schematic diagram of the cross-sectional structure of the first metal layer M3 and the second metal layer M4 is shown. Fig.23a and Figure 23bIt can be seen that due to process errors, the actual manufacturing patterns of the first metal layer M3 and the second metal layer M4 will deviate from the design patterns, so that there is a fitting accuracy Y between the first metal layer M3 and the second metal layer M4.

[0125] It should be noted that, the setting of the minimum distance d between the orthographic projection of the opening 21 of the second metal layer M4 on the first metal layer M3 and the opening 11 of the first metal layer M3 mainly considers the line width difference between the design graphics and the actual production graphics of the first metal layer M3 and the second metal layer M4 in the process, the fitting accuracy between the first metal layer M3 and the second metal layer M4, and the thickness of the insulating layer PLN between the first metal layer M3 and the second metal layer M4, and these three factors affect the effect of the opening 11 in the first metal layer M3 and the opening 21 in the second metal layer M4 interlaced and complementary to shield the active layer q.

[0126] The above embodiment mainly illustrates how to design the opening 11 of the first metal layer M3 and the opening 21 of the second metal layer M4 in the first shielding area CC.

[0127] like Figure 2-Figure 5 as well as Fig.14 As shown, at least one side of the pixel circuit group 120 along the first direction X is provided with a wiring area FF. Optionally, both sides of the pixel circuit group 120 along the first direction X are provided with a wiring area FF. Fig.24 A schematic diagram of the local layout stacking of an active layer q, a metal layer M1 and a metal layer M2 in a display panel provided in an embodiment of the present application is shown. It can be seen that the routing area FF includes a signal line 30 extending along the second direction Y, for example, a data signal line for transmitting a data signal to the pixel circuit 110, and a signal line for transmitting a driving signal to a driving circuit (driving the pixel circuit to work, including a multi-stage cascaded shift register circuit).

[0128] Different from the first shielding area CC, the routing area FF is not provided with an active layer q, therefore, the routing area FF is not required to be completely covered by the entity part 10 of the first metal layer M3 and the entity part 20 of the second metal layer M4, that is, in the routing area FF, in a direction perpendicular to the plane where the substrate is located, the opening 11 of the first metal layer M3 and the opening 21 of the second metal layer M3 can overlap. Optionally, as Figure 4 As shown, the opening 11 of the first metal layer M3 further includes a plurality of seventh openings K7 , and the area of ​​the seventh openings K7 is greater than that of the first openings K1 ; in the routing area FF, the seventh openings K7 are arranged along the second direction Y.

[0129] This is because, when the first metal layer M3 and the second metal layer M4 are set in the entire display area, due to the limitations of the actual process, such as the arc discharge that is prone to occur when a large area of ​​metal is patterned in a vacuum machine, the area of ​​the entity part 10 of the first metal layer M3 and the area of ​​the entity part 20 of the second metal layer M4 will be subject to certain restrictions. In the first shielding area CC, in order to shield the active layer q, the opening 11 of the first metal layer M3 and the opening 21 of the second metal layer M4 are staggered and complementary in a direction perpendicular to the plane where the substrate is located, so that the area of ​​the entity part 10 of the first metal layer M3 and the entity part 20 of the second metal layer M4 are The area is still large, and in the direction perpendicular to the plane of the substrate, the overlapping area of ​​the entity part 10 of the first metal layer M3 and the entity part 20 of the second metal layer M4 is large, which is prone to short circuit. The first metal layer M3 sets some seventh openings K7 with an area larger than the first openings K1 in the routing area FF, which can reduce the area of ​​the entity part 10 of the first metal layer M3 and the overlapping area of ​​the entity part 10 of the first metal layer M3 and the entity part 20 of the second metal layer M4. Moreover, it can also reduce the coupling between the entity part 10 of the first metal layer M3 (such as the first power structure PVDD) and the signal line in the routing area FF.

[0130] Optional, such as Figure 4 As shown, along the second direction Y, the seventh opening K7 and the plurality of first openings K1 are alternately arranged, that is, the first metal layer M3 is in the routing area FF, and a plurality of first openings K1 are also provided between the seventh openings K7 adjacent to each other along the second direction Y. Thus, not only are some seventh openings K7 with an area larger than the first openings K1 provided in the routing area FF, but the plurality of first openings K1 are also retained, so that the pattern density of the first metal layer M3 in the routing area FF and the pattern density in the first shielding area CC are relatively uniform, which is beneficial to improving the etching uniformity of the display panel and the uniformity of the reflection effect.

[0131] It should be noted that if Figure 4As shown, the seventh opening K7 is larger than the area of ​​the first opening K1. Optionally, the length of the seventh opening K7 along the first direction X is larger than the length of the first opening K1 along the first direction X. Thus, along the first direction X, the seventh opening K7 overlaps with the plurality of first openings K1. Alternatively, the width of the seventh opening K7 along the second direction Y is larger than the width of the first opening K1 along the second direction Y. Thus, along the second direction Y, the seventh opening K7 overlaps with the plurality of first openings K1. Alternatively, the length of the seventh opening K7 along the first direction X is larger than the length of the first opening K1 along the first direction X, and the width of the seventh opening K7 along the second direction Y is larger than the width of the first opening K1 along the second direction Y. Thus, along the first direction X and the second direction Y, the seventh opening K7 overlaps with the plurality of first openings K1. In summary, along the first direction X and / or the second direction Y, the seventh opening K7 overlaps with the plurality of first openings K1.

[0132] Similarly, optional, such as Figure 5 As shown, the opening 21 of the second metal layer M4 also includes a plurality of eighth openings K8, and the area of ​​the eighth opening K8 is larger than the area of ​​the second opening K2; in the routing area FF, the eighth openings K8 are arranged along the second direction Y; that is, the second metal layer M4 is provided with some eighth openings K8 with an area larger than the second opening K2 in the routing area FF, which can reduce the area of ​​the entity part 20 of the second metal layer M4, and reduce the overlapping area between the entity part 10 of the first metal layer M3 and the entity part 20 of the second metal layer M4, and also can reduce the coupling between the entity part 20 of the second metal layer M4 (such as the second power structure PVEE) and the signal line in the routing area FF.

[0133] Optional, such as Figure 5 As shown, along the second direction Y, the eighth opening K8 and the plurality of second openings K2 are alternately arranged, that is, the second metal layer M4 is in the routing area FF, and a plurality of second openings K2 are also provided between the eighth openings K8 adjacent to each other along the second direction Y. Thus, not only are some eighth openings K8 with an area larger than the second openings K2 provided on the second metal layer M4 in the routing area FF, but a plurality of second openings K2 are also retained, so that the pattern density of the second metal layer M4 in the routing area FF is relatively uniform with that in the first shielding area CC, which is beneficial to improving the etching uniformity of the display panel and the uniformity of the reflection effect.

[0134] It should be noted that if Figure 5As shown, the eighth opening K8 is larger than the area of ​​the second opening K2. Optionally, the length of the eighth opening K8 along the first direction X is larger than the length of the second opening K2 along the first direction X. Thus, along the first direction X, the eighth opening K8 overlaps with multiple second openings K2. Alternatively, the width of the eighth opening K8 along the second direction Y is larger than the width of the second opening K2 along the second direction Y. Thus, along the second direction Y, the eighth opening K8 overlaps with multiple second openings K2. Alternatively, the length of the eighth opening K8 along the first direction X is larger than the length of the second opening K2 along the first direction X, and the width of the eighth opening K8 along the second direction Y is larger than the width of the second opening K2 along the second direction Y. Thus, along the first direction X and the second direction Y, the eighth opening K8 overlaps with multiple second openings K2. In summary, along the first direction X and / or the second direction Y, the eighth opening K8 overlaps with multiple second openings K2.

[0135] Optional, combined Figure 4 , Figure 5 and Fig.14 As shown, the seventh opening K7 can be opened in the first metal layer M3 while the eighth opening K8 can be opened in the second metal layer M4, that is, the opening 11 of the first metal layer M3 also includes a plurality of seventh openings K7, and the area of ​​the seventh opening K7 is larger than the area of ​​the first opening K1; in the routing area FF, the seventh opening K7 is arranged along the second direction Y; and the opening 21 of the second metal layer M4 also includes a plurality of eighth openings K8, and the area of ​​the eighth opening K8 is larger than the area of ​​the second opening K2; in the routing area FF, the eighth opening K8 is arranged along the second direction Y; optionally, the orthographic projection of the eighth opening K8 on the first metal layer M3 is alternately arranged with the seventh opening K7 along the second direction Y. In this way, the area of ​​the physical part 10 of the first metal layer M3 and the area of ​​the physical part 20 of the second metal layer M4 can be reduced at the same time, and the overlapping area of ​​the physical part 10 of the first metal layer M3 and the physical part 20 of the second metal layer M4 can be reduced. The coupling between the physical part 10 of the first metal layer M3 (such as the first power structure PVDD) and the signal line in the routing area FF, and the coupling between the physical part 20 of the second metal layer M4 (such as the second power structure PVEE) and the signal line in the routing area FF can also be reduced.

[0136] Further optional, combined Figure 4 , Figure 5 and Fig.14As shown, in the routing area FF, along the second direction Y, the seventh opening K7 and the multiple first openings K1 are alternately arranged; along the second direction Y, the eighth opening K8 and the multiple second openings K2 are alternately arranged; optionally, the orthographic projection of the eighth opening K8 on the first metal layer M3 overlaps with the multiple first openings K1 between two adjacent seventh openings K7; another optional option, the orthographic projection of the seventh opening K7 on the second metal layer M4 overlaps with the multiple second openings K2 between two adjacent eighth openings K8; yet another optional option, the orthographic projection of the eighth opening K8 on the first metal layer M3 overlaps with the multiple first openings K1 between two adjacent seventh openings K7, and the orthographic projection of the seventh opening K7 on the second metal layer M4 overlaps with the multiple second openings K2 between two adjacent eighth openings K8.

[0137] For better understanding, Fig.25 A local enlarged schematic diagram of the first metal layer M3 and the second metal layer M4 in the routing area FF is shown. It can be seen that in the routing area FF, the orthographic projection of the eighth opening K8 on the first metal layer M3 and the seventh opening K7 are arranged in an alternating and complementary manner, the orthographic projection of the eighth opening K8 on the first metal layer M3 overlaps with the multiple first openings K1 between two adjacent seventh openings K7, and the orthographic projection of the seventh opening K7 on the second metal layer M4 overlaps with the multiple second openings K2 between two adjacent eighth openings K8.

[0138] It can be understood that the orthographic projection of the eighth opening K8 on the first metal layer M3 overlaps with the multiple first openings K1 between two adjacent seventh openings K7, and / or the orthographic projection of the seventh opening K7 on the second metal layer M4 overlaps with the multiple second openings K2 between two adjacent eighth openings K8, which can further reduce the overlapping area between the physical part 10 of the first metal layer M3 and the physical part 20 of the second metal layer M4, and can also further reduce the coupling between the physical part 10 of the first metal layer M3 (such as the first power structure PVDD) and the signal line in the routing area FF, and the coupling between the physical part 20 of the second metal layer M4 (such as the second power structure PVEE) and the signal line in the routing area FF; and the pattern density of the first metal layer M3 in the routing area FF is relatively uniform with the pattern density in the first shielding area CC, and the pattern density of the second metal layer M4 in the routing area FF is also relatively uniform with the pattern density in the first shielding area CC, which is beneficial to improving the etching uniformity of the display panel and the uniformity of the reflection effect.

[0139] The above embodiment has explained how to design the opening 11 of the first metal layer M3 and the opening 21 of the second metal layer M4 in the first shielding area CC and the wiring area FF. As we know, the display panel includes a display area, and the first shielding area CC and the wiring area FF are both located in the display area. When the entity part 10 of the first metal layer M3 (such as the first power structure PVDD) and the entity part 20 of the second metal layer M4 (such as the second power structure) are set in the entire display area, such as Figure 4 and Figure 5 As shown, in other areas of the display area except the first shielding area CC and the wiring area FF, the first metal layer M3 and the second metal layer M4 may also be provided with openings to further reduce the area of ​​the entity part 10 of the first metal layer M3 and the area of ​​the entity part 20 of the second metal layer M4, and further reduce the overlapping area of ​​the entity part 10 of the first metal layer M3 and the entity part 20 of the second metal layer M4, thereby reducing the risk of short circuit between the entity part 10 of the first metal layer M3 and the entity part 20 of the second metal layer M4. It can be understood that, similar to the wiring area FF, in the area where the thin film transistor is not provided in the display area, the opening 11 of the first metal layer M3 and the opening of the second metal layer M4 may overlap in the direction perpendicular to the plane where the substrate substrate is located.

[0140] Moreover, in other areas of the display area except the first shielding area CC and the routing area FF, the openings 11 of the first metal layer M3 and the openings of the second metal layer M4 can be evenly arranged, which is beneficial to improving the etching uniformity and the uniformity of the reflection effect of the display panel.

[0141] Optionally, in other areas of the display area except the first shielding area CC and the wiring area FF, the opening of the first metal layer M3 can be the first opening K1, which is arranged the same as the first opening K1 in the first shielding area CC and the wiring area FF; the opening of the second metal layer M4 can be the second opening K2, which is arranged the same as the second opening K2 in the first shielding area CC and the wiring area FF. In this way, in the entire display area, the pattern density of the openings of the first metal layer M3 is relatively uniform, and the pattern density of the openings of the second metal layer M4 is also relatively uniform, which can improve the etching uniformity of the display panel and the uniformity of the reflection effect.

[0142] It can be understood that, although the present application opens a plurality of openings 11 in the first metal layer M3 to reduce the area of ​​the entity portion 10 of the first metal layer M3, and opens a plurality of openings 21 in the second metal layer M4 to reduce the area of ​​the entity portion 20 of the first metal layer M4, and in a direction perpendicular to the plane where the substrate is located, the openings 11 of the first metal layer M3 and the openings 21 of the second metal layer M4 are arranged in an interlaced and complementary manner as a whole to reduce the overlapping area of ​​the entity portion 10 of the first metal layer M3 and the entity portion 20 of the first metal layer M4, however, due to the first metal The physical part 10 of the metal layer M3 can be set on the entire display area, and the physical part 20 of the second metal layer can also be set on the entire display area. Therefore, most of the physical part 10 of the first metal layer M3 serves as the first power structure PVDD, which still increases the area of ​​the first power structure PVDD, and most of the physical part 20 of the second metal layer M4 serves as the second power structure PVEE, which still increases the area of ​​the second power structure PVEE, thereby greatly reducing the impedance of the first power structure PVDD and the impedance of the second power structure PVEE, and greatly improving the brightness uniformity of the display panel.

[0143] Optionally, the area of ​​the entity part 10 of the first metal layer M3 accounts for a proportion of the area of ​​the display area in the range of 50%-70%, including the endpoint values; the area of ​​the entity part 20 of the second metal layer M4 accounts for a proportion of the area of ​​the display area in the range of 50%-70%, including the endpoint values. It can be understood that compared with the first power structure PVDD using a grid line distribution and the second power structure PVEE using a grid line distribution in the prior art, the area of ​​the entity part 10 of the first metal layer M3 is larger, so as to increase the area of ​​the first power structure PVDD. Similarly, the area of ​​the entity part 20 of the second metal layer M4 is larger, so as to increase the area of ​​the second power structure PVEE and improve the brightness uniformity of the display panel.

[0144] The above embodiment is mainly described by taking the first blocking area CC including the pixel circuit 110 and the first active portion q1 of the pixel circuit group 120 as an example.

[0145] like Figure 26-Figure 29 As shown, Fig.26 FIG. 1 is a schematic diagram showing a partial layout stacking of an active layer q, a first metal layer M3 and a second metal layer M4 in another display panel provided in an embodiment of the present application. For clarity of illustration, Fig. 27 Show Fig.26 Schematic diagram of the layout structure of the active layer q, Fig.28 Show Fig. 27 Schematic diagram of the layout structure of the first metal layer M3, Fig.29 Show Fig. 27From the schematic diagram of the layout structure of the second metal layer M4, it can be seen that the display panel includes a driving circuit VSR, the driving circuit VSR includes a multi-stage cascaded shift register circuit VSR1, the shift register circuit VSR1 also includes at least one thin film transistor, and the active part of the thin film transistor in the shift register circuit VSR1 also needs to be shielded to prevent the active part of the thin film transistor in the shift register circuit VSR1 from being affected when the laser bonding of the light emitting diode is performed.

[0146] Based on this, Fig. 27 As shown, the active layer q includes a second active portion q2, the shift register circuit VSR1 includes the second active portion q2, the second active portion q2 includes the active portions of each thin film transistor in the shift register circuit VSR1, and the second active portion q2 is also located in the first blocking area CC, that is, the active portion of each thin film transistor in the shift register circuit VSR1 is located in the first blocking area CC, so that, in a direction perpendicular to the plane where the substrate sub is located, at least one of the entity portion 10 of the first metal layer M3 and the entity portion 20 of the second metal layer M4 covers the first blocking area CC, that is, covers the first active portion q1 of the pixel circuit 110 while also covering the second active portion q2 of the shift register circuit VSR1, thereby avoiding affecting the first active portion q1 of the pixel circuit 110 and the second active portion q2 of the shift register circuit VSR1 when laser bonding the light emitting diode.

[0147] It should be noted that in this application, for the sake of clarity, some drawings such as Fig. 27 The second active portion q2 in the shift register circuit VSR1 represents the shift register circuit VSR1. It can be understood that the shift register circuit VSR1 also includes other film layer structures, which will not be described in detail.

[0148] It can be understood that the designs of the openings of the first metal layer M3 and the openings of the second metal layer M4 in the first shielding area CC including the first active part q1 of the pixel circuit 110 in the aforementioned embodiments are also applicable to the first shielding area CC including the second active part q2 of the bit register circuit VSR1. Therefore, for the first shielding area CC including the second active part q2 of the bit register circuit VSR1, the designs of the openings of the first metal layer M3 and the openings of the second metal layer M4 can refer to the aforementioned embodiments and will not be repeated here.

[0149] Based on the above embodiment, optionally, Fig. 27 As shown, the shift register circuit VSR1 can be located between the pixel circuits 110. That is, by compressing the local pixel circuits 110 in the display area and setting the shift register circuit VSR1 in the display area, it is beneficial to realize a borderless, full-screen design of the display panel and can be applied to a spliced ​​display device.

[0150] Alternatively, similar to the pixel circuit 110, the shift register circuit VSR1 is also typically disposed in the array substrate, and is composed of an active layer q, a metal layer M1, and a metal layer M2, and the light-emitting diode 200 is located on the array substrate 100. Therefore, even if the driving circuit VSR including a multi-stage cascaded shift register circuit VSR1 is disposed on one or both sides of the display area along the first direction X, the shift register circuit VSR1 and the light-emitting diode 200 may be arranged to overlap in a direction perpendicular to the plane of the substrate. At this time, the light-emitting diode overlapping with the shift register circuit VSR1 may not overlap with the electrically connected pixel circuit 110. In this way, a borderless, full-screen design of the display panel may be realized, and it may be applied to a spliced ​​display device.

[0151] It can be understood that in the display panel provided in the embodiment of the present application, as long as the thin film transistor is in the display area, it is necessary to be covered by at least one of the physical part 10 of the first metal layer M3 and the physical part 20 of the second metal layer M4 to prevent the active part of the thin film transistor from being affected when the laser is bonded to the light emitting diode. Therefore, in addition to the first active part q1 of the pixel circuit 110 and the second active part q2 of the shift register circuit VSR1, the first shielding area CC may also include active layers in circuits such as an electrostatic discharge circuit (ESD circuit) and a multiplexing circuit (Demux circuit), which are not described one by one.

[0152] The present application also provides a display device, such as Fig.30 and Fig.31 As shown, the display device 400 includes the display panel 300 provided in any of the above embodiments. Since the display panel 300 has been described in detail in the above embodiments, it will not be described again here.

[0153] The display device 400 can be any electronic device with a display function, such as a touch screen, a mobile phone, a tablet computer, a notebook computer, an e-reader, or a television.

[0154] It should be noted that, since the driving circuit VSR is set in the display area in the aforementioned embodiment, a borderless, full-screen design of the display panel 300 can be achieved, therefore, the display device provided in the embodiment of the present application can be a spliced ​​display device, including multiple borderless display units (ie, the display panel 300).

[0155] The various parts in this manual are described in a combination of parallel and progressive ways. Each part focuses on the differences from other parts, and the same or similar parts between the various parts can be referenced to each other.

[0156] With respect to the above description of the disclosed embodiments, the features described in the embodiments in this specification may be replaced or combined with each other, so that professionals in the field can implement or use the present application. Various modifications to these embodiments will be apparent to professionals in the field, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: substrate substrate; An active layer located on one side of the substrate; A multi-layer metal layer located on a side of the active layer away from the base substrate, the multi-layer metal layer comprising a first metal layer and a second metal layer, the first metal layer comprising a solid portion and a plurality of openings, the second metal layer comprising a solid portion and a plurality of openings; The display panel comprises a first shielding area, and at least a portion of the active layer is located in the first shielding area; In a direction perpendicular to the plane where the base substrate is located, at least one of the solid part of the first metal layer and the solid part of the second metal layer covers the first shielding area.

2. The display panel according to claim 1, characterized in that: An insulating layer is provided between the first metal layer and the second metal layer, and the insulating layer is an organic material layer.

3. The display panel according to claim 1, characterized in that: The display panel includes a plurality of pixel circuits, the active layer includes a first active portion, the pixel circuit includes the first active portion, and the first active portion is located in the first shielding area.

4. The display panel according to claim 3, characterized in that: The entity portion of the first metal layer includes a first power supply structure, and the first power supply structure is used to provide a first power supply voltage; The entity portion of the second metal layer includes a second power supply structure, and the second power supply structure is used to provide a second power supply voltage; The display panel includes a plurality of light emitting diodes, the first power supply structure is electrically connected to the pixel circuit, the pixel circuit is electrically connected to the first electrode of the light emitting diode, and the second power supply structure is electrically connected to the second electrode of the light emitting diode.

5. The display panel according to claim 4, characterized in that: The pixel circuit includes a pulse width module and an amplitude module, and the first power supply structure is electrically connected to the amplitude module of the pixel circuit.

6. The display panel according to claim 4, characterized in that: At least two of the pixel circuits form a pixel circuit group, and the first active portion of the pixel circuit group is located in the first shielding area; The pixel circuit groups are arranged in a row along a first direction, and a plurality of rows of the pixel circuit groups are arranged along a second direction, the first direction and the second direction intersect, and the first direction and the second direction are parallel to the plane where the substrate is located; In a direction perpendicular to the plane where the substrate is located, the first power supply structure at least partially overlaps with four groups of pixel circuit groups overlapping two adjacent rows of pixel circuit groups and two adjacent columns of pixel circuit groups; In a direction perpendicular to the plane where the substrate is located, the second power supply structure at least partially overlaps with four groups of pixel circuit groups overlapping two adjacent rows of pixel circuit groups and two adjacent columns of pixel circuit groups.

7. The display panel according to claim 6, characterized in that: The openings of the first metal layer include a plurality of first openings, and the openings of the second metal layer include a plurality of second openings; In the first shielding area, in a direction perpendicular to the plane where the substrate is located, the first opening and the second opening do not overlap.

8. The display panel according to claim 7, characterized in that: In at least a portion of the first shielding area, the first openings are arranged in a row along the second direction, a plurality of rows of the first openings are arranged along the first direction, the first openings in alternate rows overlap along the first direction, and the first openings in adjacent rows at least partially do not overlap along the first direction; And / or, in at least a portion of the first shielding area, the second openings are arranged in a row along the second direction, multiple rows of the second openings are arranged along the first direction, the second openings in alternate rows overlap along the first direction, and the second openings in adjacent rows do not overlap at least partially along the first direction.

9. The display panel according to claim 7, characterized in that: In at least a portion of the first shielding area, the first openings are arranged in a row along the second direction, a plurality of rows of the first openings are arranged along the first direction, the first openings in adjacent rows overlap along the first direction, and the first openings in alternate rows overlap along the first direction; And / or, in at least a portion of the first shielding area, the second openings are arranged in a row along the second direction, multiple rows of the second openings are arranged along the first direction, the second openings in adjacent rows overlap along the first direction, and the second openings in alternate rows overlap along the first direction.

10. The display panel according to claim 7, characterized in that: The shape of the first opening is the same as the shape of the second opening.

11. The display panel according to claim 7, characterized in that: The shapes of the first opening and the second opening are polygonal.

12. The display panel according to claim 7, characterized in that: The entity portion of the second metal layer further includes a first auxiliary electrode, and a third opening is provided between the first auxiliary electrode and the second power structure; The first auxiliary electrode is electrically connected to the pixel circuit, and the first auxiliary electrode is electrically connected to the first electrode of the light emitting diode; The first auxiliary electrode and the second power structure between two adjacent first auxiliary electrodes are provided with a plurality of fourth openings, and an area of ​​the fourth openings is smaller than an area of ​​the second openings.

13. The display panel according to claim 12, characterized in that: In a direction perpendicular to the plane where the base substrate is located, a plurality of fifth openings are provided at a portion where the first power structure overlaps with the first auxiliary electrode and the second power structure between two adjacent first auxiliary electrodes; The fifth openings are arranged in a row along the second direction, a plurality of rows of the fifth openings are arranged along the first direction, the fifth openings in adjacent rows overlap along the first direction, and the fifth openings in alternate rows overlap along the first direction; The orthographic projection of the fourth opening on the first metal layer is alternately arranged with the fifth opening along the second direction.

14. The display panel according to claim 12, characterized in that: The entity portion of the first metal layer further includes a second auxiliary electrode, and a sixth opening is provided between the second auxiliary electrode and the first power structure; In a direction perpendicular to the plane where the base substrate is located, the first auxiliary electrode and the second auxiliary electrode at least partially overlap, the first auxiliary electrode and the second auxiliary electrode are electrically connected, and the second auxiliary electrode is electrically connected to the pixel circuit.

15. The display panel according to claim 14, characterized in that: The sixth opening is located outside the first shielding area; Alternatively, the sixth opening is located in the first shielding area, and in a direction perpendicular to the plane where the substrate is located, the sixth opening does not overlap with the active layer.

16. The display panel according to claim 14, characterized in that: The display panel comprises a plurality of light emitting diodes, at least two of the light emitting diodes constitute a light emitting element group, and a group of the pixel circuit groups is electrically connected to a group of the light emitting element groups; In a direction perpendicular to the plane where the base substrate is located, the pixel circuit group and the electrically connected light emitting element group at least partially do not overlap along the second direction; In a direction perpendicular to the plane of the substrate, the first auxiliary electrode and the second auxiliary electrode overlap in the first shielding area, the second auxiliary electrode and the sixth opening are at least partially located outside the first shielding area, and the sixth opening does not overlap with the active layer.

17. The display panel according to claim 4, characterized in that: The first power supply structure includes a first connection portion, the first connection portion being electrically connected to the pixel circuit; At least a portion of the first connecting portion protrudes toward the opening of the first metal layer.

18. The display panel according to claim 1, characterized in that: In the first shielding area, the minimum distance d between the orthographic projection of the opening of the second metal layer on the first metal layer and the opening of the first metal layer satisfies: Among them, X1 is the line width difference between the design pattern and the actual production pattern of the first metal layer, X2 is the line width difference between the design pattern and the actual production pattern of the second metal layer, Y is the fitting accuracy between the first metal layer and the second metal layer, and H is the thickness of the insulating layer between the first metal layer and the second metal layer.

19. The display panel according to claim 7, characterized in that: A wiring area is provided on at least one side of the pixel circuit group along the first direction, and the wiring area includes a signal line extending along the second direction; The openings of the first metal layer further include a plurality of seventh openings, and the area of ​​the seventh openings is greater than the area of ​​the first openings; in the routing area, the seventh openings are arranged along the second direction.

20. The display panel according to claim 19, characterized in that: Along the second direction, the seventh opening and the plurality of first openings are arranged alternately.

21. The display panel according to claim 20, characterized in that: Along the first direction and / or the second direction, the seventh opening overlaps with the plurality of first openings.

22. The display panel according to claim 7, characterized in that: A wiring area is provided on at least one side of the pixel circuit group along the first direction, and the wiring area includes a signal line extending along the second direction; The openings of the second metal layer further include a plurality of eighth openings, and the area of ​​the eighth openings is greater than the area of ​​the second openings; in the routing area, the eighth openings are arranged along the second direction.

23. The display panel according to claim 22, characterized in that: Along the second direction, the eighth opening and a plurality of the second openings are arranged alternately.

24. The display panel according to claim 23, characterized in that: Along the first direction and / or the second direction, the eighth opening overlaps with a plurality of the second openings.

25. The display panel according to claim 7, characterized in that: A wiring area is provided on at least one side of the pixel circuit group along the first direction, and the wiring area includes a signal line extending along the second direction; The openings of the first metal layer further include a plurality of seventh openings, the area of ​​the seventh openings being greater than the area of ​​the first openings; in the routing area, the seventh openings are arranged along the second direction; The openings of the second metal layer further include a plurality of eighth openings, and the area of ​​the eighth openings is greater than the area of ​​the second openings; In the routing area, the eighth openings are arranged along the second direction; The orthographic projection of the eighth opening on the first metal layer is arranged alternately with the seventh opening along the second direction.

26. The display panel according to claim 25, characterized in that: Along the second direction, the seventh opening and the plurality of the first openings are arranged alternately; Along the second direction, the eighth opening and a plurality of the second openings are arranged alternately; The orthographic projection of the eighth opening on the first metal layer overlaps with a plurality of the first openings between two adjacent seventh openings, and / or the orthographic projection of the seventh opening on the second metal layer overlaps with a plurality of the second openings between two adjacent eighth openings.

27. The display panel according to claim 1, characterized in that: The display panel includes a driving circuit, and the driving circuit includes a multi-stage cascaded shift register circuit; The active layer includes a second active portion, the shift register circuit includes the second active portion, and the second active portion is located in the first shielding area.

28. The display panel according to claim 27, characterized in that: The display panel includes a plurality of pixel circuits, and the shift register circuit is located between the pixel circuits.

29. The display panel according to claim 27, characterized in that: The display panel includes a plurality of light emitting diodes, and the shift register circuit and the light emitting diodes overlap in a direction perpendicular to a plane where the base substrate is located.

30. The display panel according to claim 1, characterized in that: The display panel includes a plurality of pixel circuits, at least two of the pixel circuits form a pixel circuit group, the pixel circuit groups are arranged in a row along a first direction, and a plurality of rows of the pixel circuit groups are arranged along a second direction, the first direction and the second direction intersect, and the first direction and the second direction are parallel to the plane where the substrate is located; A wiring area is provided on at least one side of the pixel circuit group along the first direction, and the wiring area includes a signal line extending along the second direction; The display panel comprises a display area, and in other areas of the display area except the first shielding area and the routing area, the openings of the first metal layer are evenly arranged, and the openings of the second metal layer are evenly arranged.

31. The display panel according to claim 1, characterized in that: The display panel comprises a display area, and the area of ​​the solid portion of the first metal layer accounts for a proportion of 50% to 70% of the area of ​​the display area, including end points; The ratio of the area of ​​the solid portion of the second metal layer to the area of ​​the display region is in the range of 50%-70%, including end points.

32. A display device, characterized in that: A display panel comprising any one of claims 1-31.

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