Capacitive storage and calculation integrated processing system, method and equipment and storage medium

Abstract

The invention discloses a capacitive storage and calculation integrated processing system, method and device and a storage medium, and relates to the technical field of integrated circuits, and the system comprises the steps: carrying out the digital-to-analog conversion processing of digital input data, obtaining a plurality of analog effective input signals and effective weight data, and obtaining reference voltages of different values; the data calculation sub-module obtains a plurality of analog output voltages, sets a screening threshold value, obtains a numerical value obtained by multiplying the reference voltage by the screening threshold value, screens out the analog output voltages which are greater than or equal to the numerical value obtained by multiplying the reference voltage by the screening threshold value, accumulates the plurality of screened analog output voltages and solves an average value; and then the target analog output voltage is transmitted to the output module for analog-to-digital conversion processing to obtain output data. The system combines the characteristics of high energy efficiency of analog calculation and easy expansion of digital calculation, and then introduces reference voltage, so that the precision of output data can be improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a capacitive storage and computing integrated processing system, method, device and storage medium. Background Art

[0002] In the field of integrated circuit technology, data-intensive applications have increased dramatically in demand for computing power and storage efficiency. The storage wall and power consumption wall problems caused by frequent data exchange between storage and computing units in the traditional von Neumann architecture have become increasingly prominent. Computing in memory (CIM) technology, as an effective means to break through the von Neumann bottleneck, integrates computing power directly into the memory to achieve on-site data processing, greatly reducing data migration and improving system performance and energy efficiency.

[0003] At present, the integrated storage and computing solutions are mainly divided into digital processing and analog processing. The digital type performs calculations by coupling storage units with near-memory logic, but the energy efficiency and computing power are limited. The analog type maps matrix-vector multiplication by utilizing the capacitor charge redistribution mechanism, which significantly improves speed and energy efficiency. However, the SRAM-based analog storage and computing circuit requires changes to the internal circuit of the SRAM unit, and the layout implementation workload is large. It is not easy to adjust according to demand, and it is difficult to combine high-performance or high-density SRAM. It is difficult to expand the circuit scale, resulting in small data being ignored in the output data, resulting in low accuracy. Summary of the invention

[0004] The present application provides a capacitive storage and computing integrated processing system, method, device and storage medium, which can improve the accuracy of output data by combining the high energy efficiency of analog computing and the easy scalability of digital computing, and introducing a reference voltage.

[0005] In order to achieve the above purpose, this application adopts the following technical solutions: In a first aspect, the present application provides a capacitive storage and computing integrated processing system, the system comprising: an acquisition module, a data calculation module and an output module; The acquisition module includes a plurality of acquisition submodules for acquiring the first effective weight data, the first analog effective input signal, the second effective weight data, and the second analog effective input signal; A data calculation module, comprising a reference voltage generation submodule and a plurality of data calculation submodules, wherein the data calculation submodule comprises a plurality of calculation units and a plurality of switch selection units, the reference voltage generation submodule is used to generate a first reference voltage and a second reference voltage, the calculation unit is used to obtain a first analog output voltage according to the first analog valid input signal and the first valid weight data, the switch selection unit sets a screening threshold, obtains a value obtained by multiplying the first reference voltage and the screening threshold, screens out a first analog output voltage that is greater than or equal to the value obtained by multiplying the first reference voltage and the screening threshold, and accumulates and averages the plurality of first analog output voltages obtained by the screening to obtain a first target analog output voltage; The calculation unit is used to obtain a second analog output voltage according to the second analog valid input signal and the second valid weight data, the switch selection unit sets a screening threshold, obtains a value obtained by multiplying the second reference voltage and the screening threshold, screens out a second analog output voltage that is greater than or equal to the value obtained by multiplying the second reference voltage and the screening threshold, and accumulates and averages multiple second analog output voltages to obtain a second target analog output voltage; The output module is used to process the first target analog output voltage and the second target analog output voltage to obtain first output data and second output data, and output the first output data and the second output data.

[0006] In some possible implementations, the reference voltage generating submodule is specifically used to calculate the first reference voltage and the second reference voltage, and the calculation process is as follows: A first reference voltage is obtained by averaging the differences between a plurality of the first analog valid input signals and the ground voltage, and is outputted by the reference voltage generating submodule, wherein the plurality of the first analog valid input signals are obtained by a plurality of obtaining submodules; The second reference voltage is obtained by averaging the differences between multiple second analog valid input signals and the ground voltage, and is output by the reference voltage generation submodule. Multiple second analog valid input signals are obtained by multiple acquisition submodules.

[0007] In some possible implementations, the acquisition module includes an SRAM array, a data buffer module, and a data preprocessing module; The SRAM array is used to store multiple sets of digital input data and multiple sets of digital weight data; The data buffer module includes a plurality of data buffer submodules, which are used to buffer a plurality of groups of the digital input data and a plurality of groups of the digital weight data, and transmit the plurality of groups of the digital input data and the plurality of groups of the digital weight data to the data preprocessing module; The data preprocessing module includes multiple data preprocessing sub-modules, which are used to preprocess multiple groups of digital input data and multiple groups of digital weight data to obtain multiple groups of valid input data and multiple groups of valid weight data, and transmit the multiple groups of valid input data to the digital-to-analog converter to obtain multiple groups of analog valid input signals. The multiple groups of analog valid input signals include a first analog valid input signal and a second analog valid input signal. The first analog valid input signal contains multiple analog valid input signals, and the second analog valid input signal contains multiple analog valid input signals.

[0008] In some possible implementations, the output module includes an analog-to-digital conversion module and a data post-processing module; The analog-to-digital conversion module is used to convert the first target analog output voltage and the second target analog output voltage to obtain first valid output data and second valid output data; The data post-processing module is used to post-process the first valid output data and the second valid output data to obtain first output data and second output data, and output the first output data and the second output data.

[0009] In some possible implementations, the data calculation submodule is specifically used to multiply the first analog effective input signal and the first effective weight data to obtain a first analog output voltage; and to multiply the second analog effective input signal and the second effective weight data to obtain a second analog output voltage.

[0010] In a second aspect, the present application provides a capacitive storage and computing integrated processing method, the method comprising: Acquire first weight data, a first analog valid input signal, second weight data, a second analog valid input signal, a first reference voltage, and a second reference voltage; Obtain a first analog output voltage according to the first analog valid input signal and the first valid weight data, set a screening threshold, obtain a value obtained by multiplying the first reference voltage and the screening threshold, screen out first analog output voltages that are greater than or equal to the value obtained by multiplying the first reference voltage and the screening threshold, and accumulate and average the multiple first analog output voltages obtained by screening to obtain a first target analog output voltage; Obtain a second analog output voltage according to the second analog valid input signal and the second valid weight data, set a screening threshold, obtain a value obtained by multiplying the second reference voltage and the screening threshold, screen out a second analog output voltage that is greater than or equal to the value obtained by multiplying the second reference voltage and the screening threshold, and accumulate and average the multiple second analog output voltages obtained by screening to obtain a second target analog output voltage; The first target analog output voltage and the second target analog output voltage are processed to obtain first output data and second output data, and the first output data and the second output data are output.

[0011] In some possible implementations, the method further includes: The first reference voltage is obtained by averaging the differences between a plurality of the first analog valid input signals and the ground voltage; the second reference voltage is obtained by averaging the differences between a plurality of the second analog valid input signals and the ground voltage.

[0012] In some possible implementations, the method further includes: The first analog effective input signal and the first effective weight data are multiplied to obtain a first analog output voltage.

[0013] In a third aspect, the present application provides a computing device, including a memory and a processor; One or more computer programs are stored in the memory, and the one or more computer programs include instructions; when the instructions are executed by the processor, the computing device executes the method as described in any one of the first aspects.

[0014] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium is used to store a computer program, and the computer program is used to execute the method as described in any one of the first aspects.

[0015] It can be seen from the above technical solution that the present application has at least the following beneficial effects: In the present application, a capacitive storage and computing integrated processing system is provided, which includes: performing digital-to-analog conversion processing on digital input data through an acquisition module to obtain multiple analog valid input signals and multiple valid weight data, and sending them to a data calculation module; a reference voltage generation submodule in the data calculation module generates a reference voltage according to the multiple analog valid input signals and the ground voltage; the data calculation submodule multiplies the analog valid input signal and the valid weight data to obtain multiple analog output voltages; and then, according to the reference voltage, the multiple analog output voltages are screened, and the analog output voltages that are consistent with the reference voltage accuracy are screened out to obtain a value obtained by multiplying the reference voltage and the screening threshold, and the analog output voltages that are greater than or equal to the value obtained by multiplying the reference voltage and the screening threshold are screened out, and the multiple analog output voltages obtained by the screened are summed and averaged to obtain a target analog output voltage, and the target analog output voltage is transmitted to the output module for analog-to-digital conversion processing to obtain output data, and then the output data is sent. In the present application, the system is used to process each group of input data, and different reference voltages can be obtained according to the analog input signal. This ensures that the analog output voltage obtained in each group has higher accuracy, and does not ignore the lower analog output voltage due to the high reference voltage value, resulting in a lower-precision target analog output voltage. It can be seen that the present application can improve the accuracy of the output data by combining the high energy efficiency of analog computing and the easy scalability of digital computing, and then introducing a reference voltage.

[0016] It should be understood that the description of technical features, technical solutions, beneficial effects or similar language in this application does not imply that all features and advantages can be realized in any single embodiment. On the contrary, it is understood that the description of features or beneficial effects means that specific technical features, technical solutions or beneficial effects are included in at least one embodiment. Therefore, the description of technical features, technical solutions or beneficial effects in this specification does not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions and beneficial effects described in the present embodiment can also be combined in any appropriate manner. Those skilled in the art will understand that the embodiment can be realized without one or more specific technical features, technical solutions or beneficial effects of a specific embodiment. In other embodiments, additional technical features and beneficial effects can also be identified in a specific embodiment that does not embody all embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a capacitor-type integrated storage and computing processing system provided in an embodiment of the present application; Figure 2 A schematic diagram of the internal distribution of a data module provided in an embodiment of the present application; Figure 3 A schematic diagram of a switch selection unit provided in an embodiment of the present application; Figure 4 A schematic diagram of the output of effective weight data provided by an embodiment of the present application; Figure 5 A flowchart of a capacitor-type storage-computing integrated processing method provided in an embodiment of the present application; Figure 6 A schematic diagram of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] The terms "first", "second", "third", etc. in the specification of this application and the accompanying drawings are used to distinguish different objects rather than to limit a specific order.

[0019] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0020] At present, storage and computing integrated processing solutions are mainly divided into two types: digital and analog. The digital solution performs computing tasks by directly coupling storage units with near-memory logic, but its energy efficiency and computing power improvements are relatively limited. The analog solution uses a capacitor charge redistribution mechanism to achieve matrix-vector multiplication mapping, which can significantly improve computing speed and energy efficiency.

[0021] However, there are some challenges in the analog storage-computing integrated circuit based on SRAM. Specifically, this solution requires changing the internal circuit structure of the SRAM cell, which results in a large workload for layout implementation. At the same time, this solution is not easy to adjust according to specific needs and is difficult to combine with high-performance or high-density SRAM. Therefore, there are difficulties in expanding the scale of the circuit, which may cause smaller values ​​in the output data to be ignored, leading to the problem of reduced accuracy.

[0022] In view of this, an embodiment of the present application provides a capacitive storage and computing integrated processing system, in which a plurality of analog valid input signals and a plurality of valid weight data are obtained by performing digital-to-analog conversion processing on digital input data through an acquisition module, and the digital-to-analog conversion processing is performed on the digital input data, and the digital-to-analog conversion processing is performed on the digital input data, and the digital-to-analog conversion processing is performed on the digital input data, and the digital-to-analog conversion processing is performed on the digital input data, and the digital-to-analog conversion processing is performed on the digital input data, and the digital-to-analog conversion processing is performed on the digital input data, and the digital-to-analog conversion processing is performed on the digital input data, and the digital-to-analog conversion processing is performed on the digital input data, and the digital-to-analog conversion processing is performed on the digital input data, and the digital-to-analog conversion processing is performed on the digital input data, and the digital-to-analog conversion processing is performed on the digital output ... In the present application, the system is used to process each group of input data, and different reference voltages can be obtained according to the analog input signal. This ensures that the analog output voltage obtained in each group has higher accuracy, and does not ignore the lower analog output voltage due to the high reference voltage value, resulting in a lower-precision target analog output voltage. It can be seen that the present application can improve the accuracy of the output data by combining the high energy efficiency of analog computing and the easy scalability of digital computing, and then introducing a reference voltage.

[0023] In order to make the technical solution of the present application clearer and easier to understand, the following describes a capacitive storage and computing integrated processing system provided by an embodiment of the present application in conjunction with the accompanying drawings. Figure 1 As shown, this figure is a schematic diagram of a capacitive storage and computing integrated processing system provided in an embodiment of the present application. The system includes: an SRAM array 1, a data buffer module 2, a data preprocessing module 3, a data calculation module 104, an analog-to-digital conversion module 5 and a data post-processing module 6.

[0024] Specifically, Figure 1As shown, an SRAM array 1 is used to store multiple groups of digital input data and multiple groups of digital weight data; a data buffer module 2 is used to buffer multiple groups of digital input data and multiple groups of digital weight data, and transmit multiple digital input data and multiple digital weight data to the data preprocessing module; a data preprocessing module 3 is used to preprocess multiple digital input data and multiple digital weight data to obtain multiple valid input data and multiple valid weight data, and transmit multiple valid input data to a digital-to-analog converter to obtain multiple analog valid input signals; a data calculation module 4 is used to calculate an analog output voltage based on the analog valid input signal and the valid weight data using C-2C and a binary hybrid capacitor array, and then screen the analog target voltage based on a reference voltage to obtain a target analog output voltage; an analog-to-digital conversion module 5 is used to digitize the target analog output voltage to obtain valid output data; a data post-processing module 6 is used to post-process the valid output data, determine the output data, and output the output data.

[0025] Among them, the data buffer module 2 includes n data buffer sub-modules, the data preprocessing module 3 includes n data buffer sub-modules, and the data calculation module 4 includes 1 reference voltage generation sub-module and n data calculation sub-modules, where n is an integer greater than 1. In the embodiment of the present application, n is 7.

[0026] In the embodiment of the present application, the capacitive storage and computing integrated processing system supports the SRAM array 1 to output n groups of digital weight data and n groups of digital input data to the data buffer module 2, and obtains the multiplication and accumulation operation results of the n groups of data through a series of calculations. A group of digital weight data and digital input data includes a digital weight data and a digital input data.

[0027] In actual situations, the SRAM array can select different types of SRAM provided by the foundry according to needs, which can be density-based, speed-based, or low-power-based.

[0028] In an embodiment of the present application, each data buffer submodule is connected to a data preprocessing submodule, and each data preprocessing submodule is connected to a data calculation submodule, which are used to jointly complete the multiplication operation of a set of digital weight data and digital input data.

[0029] In the embodiment of the present application, the first reference voltage obtained according to the first group of analog valid input signals and the ground voltage is set to be 15V, the second reference voltage obtained according to the second group of analog valid input signals and the ground voltage is set to be 13V, the screening threshold is 0.9, the value obtained by multiplying the first reference voltage and the screening threshold is 13.5V, and the value obtained by multiplying the second reference voltage and the screening threshold is 11.7V. The first analog output voltage values ​​are set to 15.0V, 16.2V, 15.8V, 15.9V, 15.5V, 15.7V, and 13.2V, and the second group of analog output voltage values ​​are set to 16.0V, 16.2V, 15.8V, 12.9V, 11.5V, 14.7V, and 11.2V. The first analog output voltage is screened according to the value obtained by multiplying the first reference voltage and the screening threshold value, and the second analog output voltage is screened according to the value obtained by multiplying the second reference voltage and the screening threshold value. The first analog output voltage values ​​are 15.0V, 16.2V, 15.8V, 15.9V, 15.5V, and 15.7V, and the second group of analog output voltage values ​​are 16.0V, 16.2V, 15.8V, 12.9V, and 14.7V. The first analog output voltage and the second analog output voltage obtained by screening are calculated to obtain: The first target analog output voltage value is 13.44V The second target analog output voltage value is 10.8V According to the first reference voltage obtained from the first group, 6 analog output voltages can be obtained, which are added and averaged to obtain the first target analog output voltage, and then the first target analog output voltage is sent to the analog-to-digital conversion module 5; according to the second reference voltage obtained from the second group, 5 analog output voltages can be obtained, which are added and averaged to obtain the second target analog output voltage, and then the second target analog output voltage is sent to the analog-to-digital conversion module 5, wherein a setting is made for the numerical value of the reference voltage in the embodiment of the present application, and the actual situation requires calculation by simulating a valid input signal.

[0030] If the reference voltage value is not adjusted dynamically, when calculating the 7 analog output voltages obtained from the second set of input data, the value obtained by multiplying the first reference voltage and the screening threshold is used for screening, and only 4 values ​​can be screened out for calculating the second target analog output voltage. The second target analog output voltage value obtained in this way has a low accuracy and cannot fully reflect the output data. Therefore, the system of the present application can dynamically adjust the reference voltage according to the analog effective input signal to improve the accuracy of the target analog output voltage so that the output data can be fully presented.

[0031] Below, taking a group of input buffer sub-modules, data preprocessing sub-modules, and data calculation sub-modules, namely, data buffer sub-module 21, data preprocessing sub-module 31, and data calculation sub-module 41 as examples, a capacitive storage and computing integrated processing system provided in an embodiment of the present application is introduced in detail.

[0032] The present application embodiment provides a schematic diagram of the internal distribution of a data module, such as Figure 2 As shown, this figure is a schematic diagram of the internal distribution of a data module provided in an embodiment of the present application. It can be seen from the figure that in the embodiment of the present application, the data buffer submodule 21 includes an input buffer unit 211 and a weight buffer unit 212. The input buffer unit 211 supports 8-bit wide data input, and the weight buffer unit 212 supports 8-bit wide data input.

[0033] In the embodiment of the present application, the data preprocessing submodule 31 includes an input conversion adjustment unit 311, an XOR unit 312, a weight conversion adjustment unit 313, a data buffer synchronization unit 314 and a digital-to-analog conversion unit 315.

[0034] Specifically, the input conversion adjustment unit 311 is used to receive all 8-bit data output by the input buffer unit 211 and the result output by the XOR unit 312, and output valid input data with a width of 8 bits; The weight conversion adjustment unit 313 is used to receive all 8-bit data output by the weight buffer unit 212 and the result output by the XOR unit 312, and output effective weight data with a width of 7 bits.

[0035] An XOR unit 312 is used to perform an XOR operation on the highest bit output by the input buffer unit 211 and the highest bit output by the weight buffer unit 212, and output the result to the input conversion adjustment unit 311 and the weight conversion adjustment unit 312; The data buffer synchronization unit 314 is used to synchronize the n data preprocessing sub-modules in the data preprocessing module. When the input conversion adjustment unit and the weight conversion adjustment unit of each data preprocessing sub-module complete the data output, the n data buffer synchronization units will synchronously output the valid input data and the valid weight data.

[0036] The digital-to-analog conversion unit 315 is used to perform digital-to-analog conversion on the valid input data output by the data buffer synchronization unit 314, and output an analog valid input signal.

[0037] In an embodiment of the present application, the data buffer synchronization unit 314 of the data preprocessing submodule 41 outputs the effective weight data from the highest bit to the lowest bit, respectively, the 7th bit, the 6th bit, the 5th bit, the 4th bit, the 3rd bit, the 2nd bit and the 1st bit.

[0038] Among them, the digital-to-analog converter (DAC) is a device that converts digital quantities into analog quantities. In the embodiment of the present application, the digital-to-analog converter is connected to the data preprocessing module to convert the digital input data in the SRAM array into analog valid input signals, and converts discrete quantities into continuous quantities. After the digital data is converted into analog signals, the continuous change trend of the original data can be simulated, which is crucial for signal processing. The analog effective input signal has a wider dynamic range and can represent smaller signal changes and larger signal amplitudes, which is particularly important for systems that need to process weak signals or large-scale signal changes. Moreover, the analog effective input signal is continuous in time, which can achieve a smooth transition of the signal and avoid the step changes that may exist in the digital signal, thereby reducing signal distortion and noise.

[0039] In the embodiment of the present application, each data calculation submodule includes 1 C-2C and binary hybrid capacitor array, 7 switch selection units, 1 reset control unit, 1 reference voltage bootstrap unit and 1 input signal bootstrap unit.

[0040] Specifically, a C-2C and binary hybrid capacitor array, including capacitor C00, capacitor C01, capacitor C02, capacitor C03, capacitor C04, capacitor C05, capacitor C06, capacitor C07, capacitor C08, capacitor C09, capacitor C10, for outputting an analog output voltage; 7 switch selection units, including a 1st switch selection unit 4101, a 2nd switch selection unit 4102, a 3rd switch selection unit 4103, a 4th switch selection unit 4104, a 5th switch selection unit 4105, a 6th switch selection unit 4106, and a 7th switch selection unit 4107, for selecting a reference voltage, an analog valid input signal, and a ground voltage according to effective weight data and a reset signal output by a reset control unit; 7 switch selection units The units all include PMOS transistor PM1, PMOS transistor PM2, NMOS transistor NM1, NMOS transistor NM2, NMOS transistor NM3, NMOS transistor NM4, NMOS transistor NM5, and inverter INV. It can be understood that the internal structures of the 7 switch selection units are consistent; 1 input signal bootstrap unit 4108, used to output bootstrap analog valid input signals for the 7 switch selection units; 1 reset control unit 4109, used to output reset signals, control the reset of the 7 switch selection units, and connect the outputs of the 7 switch selection units to the ground voltage through the NMOS transistor NM5; 1 reference voltage bootstrap unit 4110, used to output bootstrap reference voltages for the 7 switch selection units.

[0041] The following is a more detailed introduction to the internal structure of the data calculation submodule 41.

[0042] The lower plate of capacitor C00 is connected to the ground voltage, the upper plate of capacitor C00 is connected to the upper plate of capacitor C01, the lower plate of capacitor C01 is connected to the output end of the first switch selection unit 4101, the lower plate of capacitor C02 is connected to the output end of the second switch selection unit 4102, the lower plate of capacitor C03 is connected to the output end of the third switch selection unit 4103, the lower plate of capacitor C04 is connected to the output end of the fourth switch selection unit 4104, the upper plate of capacitor C04 is connected to the upper plate of capacitor C05, the lower plate of capacitor C05 is connected to the output end of the fifth switch selection unit 4105, the upper plate of capacitor C05 is connected to the upper plate of capacitor C06, and the lower plate of capacitor C06 is connected to the output end of the fifth switch selection unit 4105. The electrode plate is connected to the output end of the 6th switch selection unit 4106, the upper electrode plate of capacitor C06 is connected to the upper electrode plate of capacitor C07, the lower electrode plate of capacitor C07 is connected to the output end of the 7th switch selection unit 4107, the lower electrode plate of capacitor C08 is connected to the upper electrode plate of capacitor C01, the upper electrode plate of capacitor C08 is connected to the upper electrode plate of capacitor C02, the lower electrode plate of capacitor C09 is connected to the upper electrode plate of capacitor C02, the upper electrode plate of capacitor C09 is connected to the upper electrode plate of capacitor C03, the lower electrode plate of capacitor C10 is connected to the upper electrode plate of capacitor C03, the upper electrode plate of capacitor C10 is connected to the upper electrode plate of capacitor C04, and the upper electrode plate of capacitor C07 is connected to the multiplication and accumulation signal output end of the data calculation submodule 41. Among them, the capacitance values ​​of capacitors C00, C01, C02, C03, and C04 are unit capacitance C, the capacitance values ​​of capacitors C05, C08, C09, and C10 are 2C, the capacitance value of capacitor C06 is 4C, and the capacitance value of capacitor C06 is 8C.

[0043] like Figure 3As shown, the figure is a schematic diagram of a switch selection unit provided in an embodiment of the present application. Taking the first switch selection unit 4101 as an example, the substrate of the PMOS transistor PM1 is connected to the source of the PMOS transistor PM1, the source of the PMOS transistor PM1 is connected to the bootstrap reference voltage output by the reference voltage bootstrap unit 4110, the drain of the PMOS transistor PM1 is connected to the gate of the NMOS transistor NM3, the gate of the PMOS transistor PM1 is connected to the gate of the NMOS transistor NM1, the source of the NMOS transistor NM1 is connected to the ground voltage, the drain of the NMOS transistor NM1 is connected to the gate of the NMOS transistor NM3, the substrate of the NMOS transistor NM3 is connected to the source of the NMOS transistor NM3, the source of the NMOS transistor NM3 is connected to the reference voltage output by the reference voltage generating submodule 42, the drain of the NMOS transistor NM3 is connected to the output end of the switch selection unit, and the substrate of the PMOS transistor PM2 is connected to the PMOS transistor PM 2, the source of the PMOS transistor PM2 is connected to the bootstrap analog valid input signal output by the input signal bootstrap unit, the drain of the PMOS transistor PM2 is connected to the gate of the NMOS transistor NM4, the gate of the PMOS transistor PM2 is connected to the gate of the NMOS transistor NM2, the source of the NMOS transistor NM2 is connected to the ground voltage, the drain of the NMOS transistor NM2 is connected to the gate of the NMOS transistor NM4, the substrate of the NMOS transistor NM4 is connected to the source of the NMOS transistor NM4, the source of the NMOS transistor NM4 is connected to the analog valid input signal output by the digital-to-analog conversion unit 315 of the data preprocessing submodule 31, and the drain of the NMOS transistor NM4 is connected to the output end of the switch selection unit; the source of the NMOS transistor NM5 is connected to the ground voltage, the gate of the NMOS transistor NM5 is connected to the reset signal output by the reset control unit 4109, and the drain of the NMOS transistor NM5 is connected to the output end of the switch selection unit.

[0044] In the embodiment of the present application, the internal structures of the seven switch selection units are consistent, and they are only named "1st", "2nd", "4th", "5th", "6th" and "7th" respectively to distinguish their functions according to the fact that the NMOS transistors NM1 and NMOS transistors NM2 inside each switch selection unit are connected to different signals.

[0045] Specifically, the gate of the NMOS transistor NM1 of the first switch selection unit 4101 is connected to the first bit of the effective weight data, and the gate of the NMOS transistor NM2 of the first switch selection unit 4101 is connected to the inverted signal of the first bit of the effective weight data after passing through the inverter INV; the gate of the NMOS transistor NM1 of the second switch selection unit 4102 is connected to the second bit of the effective weight data, and the gate of the NMOS transistor NM2 of the second switch selection unit 4102 is connected to the inverted signal of the second bit of the effective weight data after passing through the inverter INV; the gate of the NMOS transistor NM1 of the third switch selection unit 4103 is connected to the third bit of the effective weight data, and the gate of the NMOS transistor NM2 of the third switch selection unit 4103 is connected to the inverted signal of the third bit of the effective weight data after passing through the inverter INV; the gate of the NMOS transistor NM1 of the fourth switch selection unit 4104 is connected to the fourth bit of the effective weight data, and the gate of the NMOS transistor NM2 of the fourth switch selection unit 4104 is connected to the fourth bit of the effective weight data. The gate of the NMOS transistor NM2 of the selection unit 4104 is connected to the inverted signal of the 4th bit of the effective weight data after passing through the inverter INV; the gate of the NMOS transistor NM1 of the 5th switch selection unit 4105 is connected to the 5th bit of the effective weight data, and the gate of the NMOS transistor NM2 of the 5th switch selection unit 4105 is connected to the inverted signal of the 5th bit of the effective weight data after passing through the inverter INV; the gate of the NMOS transistor NM1 of the 6th switch selection unit 4106 is connected to the 6th bit of the effective weight data, and the gate of the NMOS transistor NM2 of the 6th switch selection unit 4106 is connected to the inverted signal of the 6th bit of the effective weight data after passing through the inverter INV; the gate of the NMOS transistor NM1 of the 7th switch selection unit 4107 is connected to the 7th bit of the effective weight data, and the gate of the NMOS transistor NM2 of the 7th switch selection unit 4107 is connected to the inverted signal of the 7th bit of the effective weight data after passing through the inverter INV.

[0046] When the capacitive storage and computing integrated processing system selects the capacitive storage and computing integrated processing system to be in working mode according to the pre-configured control signal, the working principle of the switch selection unit is further introduced below by taking the first switch selection unit 4101 as an example.

[0047] Before the data buffer synchronization unit 314 completes data synchronization, the reset control unit 4109 outputs a high level to control the NMOS transistor NM5 of the first switch selection unit 4101 to be turned on. At this time, the first switch selection unit 4101 outputs a ground voltage, and the lower plate of the capacitor is connected to the ground voltage.

[0048] After the data buffer synchronization unit 314 completes data synchronization, the reset control unit outputs a low level to control the NMOS transistor NM5 of the first switch selection unit 4101 to be turned off, and the data buffer synchronization unit 314 outputs valid input data and valid weight data. The first bit of the effective weight data will control the NMOS transistors NM1, NM2 and PMOS transistors PM1, PM2 of the first switch selection unit 4101: when the first bit of the effective weight data is 0, NM1 is turned off and PM1 is turned on, the gate of NM3 is connected to the bootstrap reference voltage, the NM3 transistor is turned on, the output of the first switch selection unit 4101 is connected to the reference voltage, and the lower plate of the capacitor is connected to the reference voltage, while NM2 is turned on and PM2 is turned off, the gate of NM4 is connected to the ground voltage, and the NM4 transistor is turned off; when the first bit of the effective weight data is 1, NM1 is turned on and PM1 is turned off, the gate of NM3 is connected to the ground voltage, and the NM3 transistor is turned off, while NM2 is turned off and PM2 is turned on, the gate of NM4 is connected to the bootstrap analog effective input signal, the NM4 transistor is turned on, the output of the first switch selection unit 4101 is connected to the analog effective input signal, and the lower plate of the capacitor is connected to the analog effective input signal.

[0049] It should be noted that in the data calculation submodule 41, the working principles of the remaining 6 switch selection units are the same as that of the first switch selection unit 4101, and all of them select the current switch selection unit to output ground voltage, reference voltage or analog effective input signal according to the corresponding bits of the effective weight data.

[0050] Among them, before the data buffer submodule 314 completes data synchronization, the 7 switch selection units all output the ground voltage, and connect the lower plates of C01, C02, C03, C04, C05, C06, and C07 to the ground voltage; when the data buffer submodule 314 completes synchronization and outputs data, the 7 switch selection units connect their respective outputs to the reference voltage or the analog effective input signal according to the different bits of the effective weight data connected to them, and complete the connection of the lower plates of the capacitors connected to them to the reference voltage or the analog effective input voltage.

[0051] In the embodiment of the present application, the purpose of introducing the reference voltage is to support the INT8 data type. By introducing the reference voltage, two voltage ranges can be divided: ground voltage-reference voltage, as the case where the multiplication and addition result is a negative number; reference voltage-power supply voltage, as the case where the multiplication and addition result is a positive number.

[0052] In the embodiment of the present application, the analog-to-digital conversion module 5 includes a sampling and holding circuit, a CDAC array, a comparator and a successive approximation logic unit, supports a voltage signal with an input range between the ground voltage and the power supply voltage, and the analog-to-digital conversion resolution is greater than or equal to 8 bits.

[0053] In an embodiment of the present application, the data post-processing module 6 is used to complete post-processing of the valid digital output value output by the analog-to-digital conversion module: the data post-processing module 6 inverts the highest bit of the valid digital output value, and the remaining bits remain unchanged to obtain digital output data.

[0054] When the capacitive storage and computing integrated processing system selects the capacitive storage and computing integrated processing system to be in working mode according to a pre-configured control signal, the XOR unit 312 receives the highest bit of the input data and the highest bit of the weight data, the input conversion adjustment unit 311 outputs valid input data according to the received XOR unit output value and all 8-bit input data, and the weight conversion adjustment unit 313 outputs valid weight data according to the received XOR unit output value and all 8-bit weight data.

[0055] like Figure 4 As shown, this figure is a schematic diagram of the effective weight data output provided in an embodiment of the present application. The following is a detailed introduction to the four situations provided in an embodiment of the present application.

[0056] Case 1: When the output value of the XOR unit 312 is 0, and the highest bit of the input data is 0 and the highest bit of the weight data is 0, the input conversion adjustment unit 311 inverts the highest bit of the input data to obtain valid input data with a width of 8 bits, and outputs it to the data buffer synchronization unit. The weight conversion adjustment unit 313 truncates the highest bit of the weight data and does not adjust the lower 7 bits to obtain valid weight data with a width of 7 bits, and outputs it to the data buffer synchronization unit.

[0057] Case 2: When the output value of the XOR unit 312 is 0, and the highest bit of the input data is 1 and the highest bit of the weight data is 1, the input conversion and adjustment unit 311 converts the data type of the input data from the complement code to the original code to obtain valid input data with a width of 8 bits, which is output to the data buffer synchronization unit. The weight conversion and adjustment unit 313 converts the data type of the weight data from the complement code to the original code, truncates the highest bit, and obtains valid weight data with a width of 7 bits, which is output to the data buffer synchronization unit.

[0058] Case three: When the output value of the XOR unit 312 is 1, and the highest bit of the input data is 1 and the highest bit of the weight data is 0, the input conversion and adjustment unit 311 bit-wise inverts the input data and then subtracts 1 to obtain 8-bit valid input data, which is output to the data buffer synchronization unit. The weight conversion and adjustment unit 313 truncates the highest bit of the weight data to obtain 7-bit valid weight data, which is output to the data buffer synchronization unit.

[0059] Case 4: When the output value of the XOR unit 312 is 1, and the highest bit of the input data is 0 and the highest bit of the weight data is 1, the input conversion and adjustment unit 311 bitwise inverts the lower 7 bits of the input data to obtain valid input data with a width of 8 bits, and outputs it to the data buffer synchronization unit. The weight conversion and adjustment unit 313 converts the data type of the weight data from the complement code to the original code, truncates the highest bit, and obtains valid weight data with a width of 7 bits, and outputs it to the data buffer synchronization unit.

[0060] In this application, it should be noted that this method is used to support 8-bit signed integer data multiplication and accumulation calculations, that is, IN8 type data. By preprocessing the data, adjusting individual bits, and adapting the data calculation submodule, a set of INT8 type data multiplication and accumulation calculations are completed together. Different methods can be selected to output the effective weight data according to actual conditions.

[0061] It should be noted that the present invention does not specifically limit the output method of the effective weight data. The purpose of the present invention is to output the effective weight data based on the situation in this application.

[0062] Therefore, by using the system to process multiple groups of input data, different reference voltages can be obtained according to the analog input signals, so that the analog output voltage obtained in each group can be guaranteed to be more accurate, and the lower analog output voltage will not be ignored due to the high reference voltage value, resulting in a target analog output voltage with lower accuracy. It can be seen that the present application can improve the accuracy of the output data by combining the high energy efficiency of analog computing and the easy scalability of digital computing, and then introducing a reference voltage.

[0063] The present application also provides a method for processing a capacitor-type integrated storage and computing device. Figure 5 As shown, the figure is a flow chart of a capacitive storage and computing integrated processing method provided by an embodiment of the present application, which is applied to a processing device, and the method includes: S501. A processing device obtains first digital weight data, a first analog valid input signal, second digital weight data, a second analog valid input signal, a first reference voltage, and a second reference voltage.

[0064] The first digital weighted data, the first analog effective input signal, the second digital weighted data and the second analog effective input signal are all multiple data. The first reference voltage and the second reference voltage are generated by a reference voltage generating submodule. The reference voltage values ​​of different groups are not necessarily the same, because the reference voltage is obtained by taking the average value of the difference between the analog effective input signal and the ground voltage obtained by each data preprocessing submodule. The accuracy of each group of output data can be improved according to different reference voltages.

[0065] S502: The processing device obtains a first analog output voltage according to a first analog valid input signal and first digital valid weight data.

[0066] S503: The processing device sets a screening threshold, obtains a value obtained by multiplying the first reference voltage by the screening threshold, and screens out a first analog output voltage that is greater than or equal to the value obtained by multiplying the first reference voltage by the screening threshold.

[0067] S504: The processing device accumulates and averages the plurality of first analog output voltages obtained by screening to obtain a first target analog output voltage.

[0068] S505: The processing device obtains a second analog output voltage according to the second analog valid input signal and the second digital valid weight data.

[0069] S506: The processing device sets a screening threshold, obtains a value obtained by multiplying the second reference voltage by the screening threshold, and screens out a second analog output voltage that is greater than or equal to the value obtained by multiplying the second reference voltage by the screening threshold.

[0070] S507: The processing device then accumulates and averages the plurality of second analog output voltages obtained by screening to obtain a second target analog output voltage.

[0071] S508: The processing device processes the first target analog output voltage and the second target analog output voltage to obtain first digital output data and second digital output data.

[0072] S509: The processing device outputs first digital output data and second digital output data.

[0073] By processing multiple groups of input data using the above method, different reference voltages can be obtained according to the analog input signals, which ensures that the analog output voltage obtained in each group has higher accuracy, and does not ignore the lower analog output voltage due to the higher reference voltage value, thereby obtaining a target analog output voltage with lower accuracy. It can be seen that the present application combines the high energy efficiency of analog computing and the easy scalability of digital computing, and then introduces a reference voltage to improve the accuracy of the output data.

[0074] The present application also provides a computing device. Figure 6 As shown, this figure is a schematic diagram of a computing device provided in an embodiment of the present application, and the computing device 600 includes a bus 601, a processor 602, a communication interface 603 and a memory 604. The processor 602, the memory 604 and the communication interface 603 communicate with each other through the bus 601.

[0075] The bus 601 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0076] The processor 602 may be any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0077] The communication interface 603 is used for communicating with the outside.

[0078] The memory 604 may include a volatile memory, such as a random access memory (RAM). The memory 604 may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid state drive (SSD).

[0079] The memory 604 stores executable codes, and the processor 602 executes the executable codes to perform the aforementioned capacitive storage and computing integrated processing method.

[0080] The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be stored by the computing device or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid-state hard disk). The computer-readable storage medium includes instructions that instruct the computing device to execute the above-mentioned capacitive storage and computing integrated processing method.

[0081] The embodiment of the present application further provides a computer program product, which includes one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the process or function described in the embodiment of the present application is generated in whole or in part.

[0082] The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer or data center to another website, computer or data center via wired (e.g., coaxial cable, optical fiber) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0083] When the computer program product is executed by a computer, the computer executes any of the aforementioned capacitive storage and computing integrated processing methods. The computer program product may be a software installation package, and when any of the aforementioned capacitive storage and computing integrated processing methods is required, the computer program product may be downloaded and executed on a computer.

[0084] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0085] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application.

Claims

1. A capacitive storage and computing integrated processing system, characterized in that: The system comprises: an acquisition module, a data calculation module and an output module; The acquisition module includes a plurality of acquisition submodules for acquiring the first effective weight data, the first analog effective input signal, the second effective weight data, and the second analog effective input signal; A data calculation module, comprising a reference voltage generation submodule and a plurality of data calculation submodules, wherein the data calculation submodule comprises a plurality of calculation units and a plurality of switch selection units, the reference voltage generation submodule is used to generate a first reference voltage and a second reference voltage, the calculation unit is used to obtain a first analog output voltage according to the first analog valid input signal and the first valid weight data, the switch selection unit sets a screening threshold, obtains a value obtained by multiplying the first reference voltage and the screening threshold, screens out a first analog output voltage that is greater than or equal to the value obtained by multiplying the first reference voltage and the screening threshold, and accumulates and averages the plurality of first analog output voltages obtained by the screening to obtain a first target analog output voltage; The calculation unit is used to obtain a second analog output voltage according to the second analog valid input signal and the second valid weight data, the switch selection unit sets a screening threshold, obtains a value obtained by multiplying the second reference voltage and the screening threshold, screens out a second analog output voltage that is greater than or equal to the value obtained by multiplying the second reference voltage and the screening threshold, and accumulates and averages multiple second analog output voltages to obtain a second target analog output voltage; The output module is used to process the first target analog output voltage and the second target analog output voltage to obtain first output data and second output data, and output the first output data and the second output data.

2. The system according to claim 1, characterized in that The reference voltage generation submodule is specifically used to calculate the first reference voltage and the second reference voltage, and the calculation process is as follows: A first reference voltage is obtained by averaging the differences between a plurality of the first analog valid input signals and the ground voltage, and is outputted by the reference voltage generating submodule, wherein the plurality of the first analog valid input signals are obtained by a plurality of obtaining submodules; The second reference voltage is obtained by averaging the differences between multiple second analog valid input signals and the ground voltage, and is output by the reference voltage generation submodule. Multiple second analog valid input signals are obtained by multiple acquisition submodules.

3. The system according to claim 1, characterized in that The acquisition module includes an SRAM array, a data buffer module, and a data preprocessing module; The SRAM array is used to store multiple sets of digital input data and multiple sets of digital weight data; The data buffer module includes a plurality of data buffer submodules, which are used to buffer a plurality of groups of the digital input data and a plurality of groups of the digital weight data, and transmit the plurality of groups of the digital input data and the plurality of groups of the digital weight data to the data preprocessing module; The data preprocessing module includes multiple data preprocessing sub-modules, which are used to preprocess multiple groups of digital input data and multiple groups of digital weight data to obtain multiple groups of valid input data and multiple groups of valid weight data, and transmit the multiple groups of valid input data to the digital-to-analog converter to obtain multiple groups of analog valid input signals. The multiple groups of analog valid input signals include a first analog valid input signal and a second analog valid input signal. The first analog valid input signal contains multiple analog valid input signals, and the second analog valid input signal contains multiple analog valid input signals.

4. The system according to claim 1, characterized in that The output module includes an analog-to-digital conversion module and a data post-processing module; The analog-to-digital conversion module is used to convert the first target analog output voltage and the second target analog output voltage to obtain first valid output data and second valid output data; The data post-processing module is used to post-process the first valid output data and the second valid output data to obtain first output data and second output data, and output the first output data and the second output data.

5. The system according to claim 1, characterized in that The data calculation submodule is specifically used to multiply the first analog effective input signal and the first effective weight data to obtain a first analog output voltage; and multiply the second analog effective input signal and the second effective weight data to obtain a second analog output voltage.

6. A capacitive storage and computing integrated processing method, characterized in that: The method comprises: Acquire first weight data, a first analog valid input signal, second weight data, a second analog valid input signal, a first reference voltage, and a second reference voltage; Obtain a first analog output voltage according to the first analog valid input signal and the first valid weight data, set a screening threshold, obtain a value obtained by multiplying the first reference voltage and the screening threshold, screen out first analog output voltages that are greater than or equal to the value obtained by multiplying the first reference voltage and the screening threshold, and accumulate and average the multiple first analog output voltages obtained by screening to obtain a first target analog output voltage; Obtain a second analog output voltage according to the second analog valid input signal and the second valid weight data, set a screening threshold, obtain a value obtained by multiplying the second reference voltage and the screening threshold, screen out a second analog output voltage that is greater than or equal to the value obtained by multiplying the second reference voltage and the screening threshold, and accumulate and average the multiple second analog output voltages obtained by screening to obtain a second target analog output voltage; The first target analog output voltage and the second target analog output voltage are processed to obtain first output data and second output data, and the first output data and the second output data are output.

7. The method according to claim 6, characterized in that The method further comprises: The first reference voltage is obtained by averaging the differences between a plurality of the first analog valid input signals and the ground voltage; the second reference voltage is obtained by averaging the differences between a plurality of the second analog valid input signals and the ground voltage.

8. The method according to claim 6, characterized in that The method further comprises: The first analog effective input signal and the first effective weight data are multiplied to obtain a first analog output voltage.

9. A computing device, characterized in that including memory and processor; One or more computer programs are stored in the memory, and the one or more computer programs include instructions; when the instructions are executed by the processor, the computing device executes the method as claimed in any one of claims 6 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store a computer program, and the computer program is used to execute the method according to any one of claims 6 to 8.

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