Modulator for multi-level wireless charging system and application method

Abstract

The invention provides a modulator for a multi-level wireless charging system and an application method, belongs to the technical field of wireless electric energy transmission, and solves the problems that an existing method is large in output ripple and needs to add an additional circuit to maintain flying capacitance balance. The modulator comprises a finite-state machine, a proportional element, an integrator, a multiplier, a delay element and a microcontroller. The microcontroller is used for providing an external signal sign and an external signal k. The initial voltage delta FC-SDM of the inverter is input into the multi-level soft switching modulator, a signal i is obtained by combining the initial voltage delta FC-SDM with an external signal sign, and the finite-state machine is used for quantizing the input signal i; the integrator integrates the input delta and a feedback signal y of the finite-state machine to obtain an output e; the output e of the multiplier is multiplied by the signal sign to obtain the input i of the state machine; the delay link is used for controlling signal triggering time.

Description

Technical Field

[0001] The present invention relates to a modulator for a multi-level wireless charging system and an application method thereof, belonging to the technical field of wireless power transmission. Background Art

[0002] The primary drawback of wireless power transmission (WPT) compared to wired charging is its lower power consumption. One solution is to replace the traditional full-bridge inverter with a multilevel inverter, enabling it to withstand higher DC voltages. To reduce losses in multilevel power electronic converters, research is needed on soft-switching modulation methods for multilevel WPT systems. Soft-switching technology can improve device efficiency and enable higher-frequency power conversion components. Current methods suffer from large output ripple and the need for additional circuitry to maintain flying capacitor balance. Therefore, developing a new multilevel inverter modulation method that achieves soft switching operation and self-balancing flying capacitor voltage across the entire range is crucial for enhancing the application value of WPT technology. Summary of the Invention

[0003] In order to solve the above technical problems, the present invention further proposes a modulator for a multi-level wireless charging system and an application method.

[0004] The present invention adopts the following technical solution to solve the above problems: The present invention proposes a modulator for a multi-level wireless charging system, comprising:

[0005] Proportional links, integrators, multipliers, finite state machines, delay links, and microcontrollers;

[0006] The microcontroller is used to provide an external signal sign and an external signal k.

[0007] The initial inverter voltage δ FC-SDM Input multi-level soft switching modulator, proportional link and integrator will input δ FC-SDM Integrate with the finite state machine feedback signal y to obtain the output e;

[0008] The multiplier multiplies the signal e by the signal sign to obtain the input i of the state machine;

[0009] The finite state machine is used to quantize the input signal i in combination with the external signal k;

[0010] The delay link is used to control the signal trigger time.

[0011] Optionally, the wireless charging system used by the modulator is compensated as a series-series compensation network topology, including: a primary coil L1, a secondary coil L2, a primary compensation capacitor C1, a secondary compensation capacitor C2, and a flying capacitor C FC , filter capacitor C dc, load element Load, resistor R1, resistor R2, switch S1, switch S2, switch S3 and switch S4;

[0012] The primary coil L1, resistor R1 and primary compensation capacitor C1 are connected in series, and the flying capacitor C FC Connected in parallel with switch S2 and switch S3, and connected in series with switch S1 and switch S4;

[0013] The secondary side compensation capacitor C2 and the resistor R2 are connected in series;

[0014] Filter capacitor C dc Connect in parallel with the load element Load.

[0015] A method for applying a modulator for a multi-level wireless charging system, comprising:

[0016] Step 1: Set the initial output voltage δ FC-SDM The input multi-level modulator and the state machine feedback signal y are subtracted and then pass through the proportional link;

[0017] Step 2: Based on the integrator, the output signal of the proportional link is shaped and filtered to convert it into signal e;

[0018] Step 3: The microcontroller provides an external signal sign and an external signal k, and uses a multiplier to multiply the external signal sign and the signal e to obtain a signal i;

[0019] Step 4: Based on the finite state machine and the external signal k, quantize the signal i to obtain the digital output S1, S2, y, and use the signal y as the feedback quantity and the next input δ FC-SDM Combine;

[0020] Step 5: Use the output signals S1 and S2 of the finite state machine as the switch drive signals of the inverter, obtain three output types: full-step signal, half-step signal and hold signal, and realize soft switching operation of the transmitter inverter.

[0021] Optionally, the initial output voltage δ in step 1 FC-SDM The calculation formula is:

[0022]

[0023] In formula (1), N 1S is the number of half cycles of a full step, N 0.5S is the number of half cycles of a half step, N 0S The number of half cycles that the level is maintained.

[0024] Optionally, the external signal sign in step 3 is a direction signal of the inverter output current, where sign is a value of 1 and -1 corresponding to the direction of the inverter output current, and is inverted every half of the resonance period.

[0025] The external signal k is a flying capacitor voltage balance signal.

[0026] Optionally, the value of the digital output y in step 4 is one of 1, 0.5 and 0, wherein 1, 0.5 and 0 correspond to three output types: full-step signal, half-step signal and hold signal, respectively.

[0027] Optionally, the three output types of full-step signal, half-step signal, and hold signal obtained in step 5 specifically include:

[0028] If the finite state machine is in the "00" state with switches S1 and S2 both open, and the input signal i is less than 0.25, the state remains unchanged and the output type is a hold signal; during the path transfer process, when the signal 0.25≤i≤0.75 and k>0, the finite state machine transitions from the "00" state with switches S1 and S2 both open to the "01" state with switch S1 open and switch S2 closed, and the output type is a half-step signal; during the path transfer process, when the signal 0.25≤i≤0.75 and k<0, the finite state machine transitions from the "00" state with switches S1 and S2 both open to the "10" state with switch S1 closed and switch S2 open, and the output type is a half-step signal; during the path transfer process, when the signal i>0.75, the finite state machine transitions from the "00" state with switches S1 and S2 both open to the "11" state with switches S1 and S2 closed, and the output type is a full-step signal;

[0029] If the finite state machine is in the "01" state with switch S1 open and switch S2 closed, and the input signal |i| ≤ 0.25 and k > 0, the state remains unchanged and the output type is a hold signal; during the path transfer process, when the signal i < -0.25, the finite state machine is converted from the "01" state with switch S1 open and switch S2 closed to the "00" state with both switches S1 and S2 open, and the output type is a half-step signal; during the path transfer process, when the signal i > 0.25, the finite state machine is converted from the "01" state with switch S1 open and switch S2 closed to the "11" state with both switches S1 and S2 closed, and the output type is a half-step signal; during the path transfer process, when the signal |i| ≤ 0.25 and k < 0, the finite state machine is converted from the "01" state with switch S1 open and switch S2 closed to the "10" state with switch S1 closed and switch S2 open, and the output type is a hold signal;

[0030] If the finite state machine is in the "11" state with switches S1 and S2 both closed, and the input signal i>-0.25, the state remains unchanged and the output type is a hold signal. During the path transfer process, when the signal -0.75≤i≤-0.25 and k>0, the finite state machine switches from the "11" state with switches S1 and S2 both closed to the "01" state with switch S1 open and switch S2 closed, and the output type is a half-step signal. During the path transfer process, when the signal -0.75≤i≤-0.25 and k<0, the finite state machine switches from the "11" state with switches S1 and S2 both closed to the "10" state with switch S1 closed and switch S2 open, and the output type is a half-step signal. During the path transfer process, when the signal i<-0.75, the finite state machine switches from the "11" state with switches S1 and S2 both closed to the "00" state with switches S1 and S2 open, and the output type is a full-step signal.

[0031] If the finite state machine is in the "10" state with switch S1 closed and switch S2 open, and the input signal |i| ≤ 0.25 and k < 0, the state remains unchanged, and the output type is a hold signal. During the path transition, when the signal i > 0.25, the finite state machine transitions from the "10" state with switch S1 closed and switch S2 open to the "11" state with both switches S1 and S2 closed, and the output type is a half-step signal. During the path transition, when the signal i < -0.25, the finite state machine transitions from the "10" state with switch S1 closed and switch S2 open to the "00" state with both switches S1 and S2 open, and the output type is a half-step signal. During the path transition, when the signal |i| ≤ 0.25 and k > 0, the finite state machine transitions from the "10" state with switch S1 closed and switch S2 open to the "01" state with switch S1 open and switch S2 closed, and the signal type is a hold signal.

[0032] Optionally, during the signal step process, the signal step direction is consistent with the current conversion direction.

[0033] Optionally, the step of calculating the external signal k includes:

[0034] Step 3.1: Determine whether the states of switches S1 and S2 in the finite state machine are the same. If so, k = 1. If not, proceed to step 3.2.

[0035] Step 3.2: Determine whether switch S1 is closed. If so, calculate the Q value based on Q = Q-sign. If Q = 0, determine whether r is greater than 0.5. If so, calculate k = 1. If less than r, calculate k = -1. If Q ≠ 0, calculate the k value based on the current sign.

[0036] Step 3.3: If switch S1 is in the open state, calculate the Q value according to Q=Q+sign. If Q=0, determine whether r is greater than 0.5. If it is greater, k=1; if it is less, k=-1; if Q≠0, give the k value according to the sign at the current moment; where Q is the balance flag, the initial value is 0, the Q value is the difference between the number of charging cycles and the number of discharging cycles, and r is a random number uniformly distributed in the range of 0 to 1.

[0037] The beneficial effects of the present invention are:

[0038] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: the present invention realizes full-range zero voltage switching (ZVS) operation, the output voltage and current ripple of the multi-level inverter is small, and without the need for any auxiliary circuit, it can automatically achieve the balance of the flying capacitor voltage, and reduce the voltage fluctuation of the flying capacitor by optimizing the charging and discharging sequence of the flying capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic structural diagram of a modulator for a multi-level wireless charging system provided by the present invention;

[0040] Figure 2 A circuit diagram of a half-bridge three-level flying capacitor inverter wireless charging system using series-to-series compensation provided by the present invention;

[0041] Figure 3 A schematic diagram of an effective working state of a half-bridge three-level flying capacitor inverter provided by the present invention;

[0042] Figure 3 In the figure, (a) is a schematic diagram of the half-bridge three-level flying capacitor inverter in "11" working mode, (b) is a schematic diagram of the half-bridge three-level flying capacitor inverter in "01" working mode, (c) is a schematic diagram of the half-bridge three-level flying capacitor inverter in "00" working mode, and (d) is a schematic diagram of the half-bridge three-level flying capacitor inverter in "10" working mode;

[0043] Figure 4 The input δ provided by the present invention FCSDM =0.6 and δ FCSDM Schematic diagram of the change of inverter output voltage and current when =0.4;

[0044] Figure 4 In the example, (a) is the input δ FCSDM = 0.6, (b) is the schematic diagram of the change of inverter output voltage and current, FCSDM Schematic diagram of the change of inverter output voltage and current when =0.4;

[0045] Figure 5 A schematic diagram of the state path transition of the finite state machine provided by the present invention;

[0046] Figure 6 A flow chart of the calculation of the external signal k provided by the present invention;

[0047] Figure 7 The given input δ provided by the present invention FCSDM Schematic diagram of simulation results when = 0.7. DETAILED DESCRIPTION

[0048] Specific implementation method 1: Combination Figure 1 and Figure 2 This embodiment is described as follows. Figure 1 As shown, the structure of a modulator for a multi-level wireless charging system described in this embodiment includes:

[0049] Proportional links, integrators, multipliers, finite state machines, delay links, and microcontrollers;

[0050] The microcontroller is used to provide an external signal sign and an external signal k.

[0051] The initial inverter voltage δ FC-SDM Input multi-level soft switching modulator, proportional link and integrator will input δ FC-SDM Integrate with the finite state machine feedback signal y to obtain the output e;

[0052] The multiplier multiplies the signal e by the signal sign to obtain the input i of the state machine;

[0053] The finite state machine is used to quantize the input signal i in combination with the external signal k;

[0054] The delay link is used to control the signal trigger time.

[0055] like Figure 2 As shown in the figure, the wireless charging system used by the modulator is compensated as a series-series compensation network topology, including:

[0056] Primary coil L1, secondary coil L2, primary compensation capacitor C1, secondary compensation capacitor C2, flying capacitor C FC , filter capacitor C dc , load element Load, resistor R1, resistor R2, switch S1, switch S2, switch S3 and switch S4;

[0057] The primary coil L1, resistor R1 and primary compensation capacitor C1 are connected in series, and the flying capacitor C FC Connected in parallel with switch S2 and switch S3, and connected in series with switch S1 and switch S4;

[0058] The secondary side compensation capacitor C2 and the resistor R2 are connected in series;

[0059] Filter capacitor C dc Connect in parallel with the load element Load.

[0060] Specific implementation method 2: Combination Figure 3-6 This embodiment is described below. The application method of a modulator for a multi-level wireless charging system described in this embodiment includes the following steps:

[0061] S1: Set the initial output voltage δ FC-SDM The input multi-level modulator and the state machine feedback signal y are subtracted and then passed through a proportional link;

[0062] like Figure 4 As shown, Figure 4 is the input δ FC-SDM =0.6 and δ FC-SDM =0.4 The inverter output voltage and current. The inverter output voltage can be expressed as:

[0063]

[0064] In formula (1), N 1S is the number of half cycles of a full step, N 0.5S is the number of half cycles of a half step, N 0S The number of half cycles that the level is maintained.

[0065] S2: shaping and filtering the output signal of the proportional link based on the integrator to convert it into signal e;

[0066] S3: The microcontroller provides an external signal sign and an external signal k, and uses the multiplier to multiply the external signal sign and the signal e to obtain a signal i;

[0067] Both sign and k are external signals generated by the microcontroller. Sign is the direction signal of the inverter output current. It has two values, 1 and -1, and is inverted every half of the resonant cycle to meet the constraints of the FC-SDM modulation method. k is the flying capacitor voltage balance signal.

[0068] S4: Based on the finite state machine and the external signal k, the signal i is quantized to obtain digital outputs S1, S2 and y, and the signal y is used as feedback to be compared with the next input δ FC-SDM Combine;

[0069] like Figure 3 As shown in Figure 2, the four effective working modes of the flying capacitor inverter can be represented by the states of S1 and S2. "1" represents that the S1 or S2 switch is closed and the complementary switch is open, while "0" represents the opposite. Figure 3As shown in Figure 1, there are four states in total. To improve the power factor, FC-SDM modulation needs to follow a constraint: the step direction of the step signal must be consistent with the current conversion direction.

[0070] The value of the digital output y is one of 1, 0.5 and 0, where 1, 0.5 and 0 correspond to three output types: full-step signal, half-step signal and hold signal, respectively.

[0071] S5: Using the output signals S1 and S2 of the finite state machine as switch drive signals of the inverter, obtaining three output types of full-step signal, half-step signal and hold signal, and realizing soft switching operation of the transmitter inverter.

[0072] like Figure 5 As shown, if the finite state machine is in the "00" state where both switches S1 and S2 are open, and the input signal i is less than 0.25, the state remains unchanged, and the output type is a hold signal; during the path transfer process, when the signal 0.25≤i≤0.75 and k>0, the finite state machine is converted from the "00" state where both switches S1 and S2 are open to the "01" state where switch S1 is open and switch S2 is closed, and the output type is a half-step signal; during the path transfer process, when the signal 0.25≤i≤0.75 and k<0, the finite state machine is converted from the "00" state where both switches S1 and S2 are open to the "10" state where switch S1 is closed and switch S2 is open, and the output type is a half-step signal; during the path transfer process, when the signal i>0.75, the finite state machine is converted from the "00" state where both switches S1 and S2 are open to the "11" state where both switches S1 and S2 are closed, and the output type is a full-step signal;

[0073] If the finite state machine is in the "01" state with switch S1 open and switch S2 closed, and the input signal |i| ≤ 0.25 and k > 0, the state remains unchanged and the output type is a hold signal; during the path transfer process, when the signal i < -0.25, the finite state machine is converted from the "01" state with switch S1 open and switch S2 closed to the "00" state with both switches S1 and S2 open, and the output type is a half-step signal; during the path transfer process, when the signal i > 0.25, the finite state machine is converted from the "01" state with switch S1 open and switch S2 closed to the "11" state with both switches S1 and S2 closed, and the output type is a half-step signal; during the path transfer process, when the signal |i| ≤ 0.25 and k < 0, the finite state machine is converted from the "01" state with switch S1 open and switch S2 closed to the "10" state with switch S1 closed and switch S2 open, and the output type is a hold signal;

[0074] If the finite state machine is in the "11" state with switches S1 and S2 both closed, and the input signal i>-0.25, the state remains unchanged and the output type is a hold signal. During the path transfer process, when the signal -0.75≤i≤-0.25 and k>0, the finite state machine switches from the "11" state with switches S1 and S2 both closed to the "01" state with switch S1 open and switch S2 closed, and the output type is a half-step signal. During the path transfer process, when the signal -0.75≤i≤-0.25 and k<0, the finite state machine switches from the "11" state with switches S1 and S2 both closed to the "10" state with switch S1 closed and switch S2 open, and the output type is a half-step signal. During the path transfer process, when the signal i<-0.75, the finite state machine switches from the "11" state with switches S1 and S2 both closed to the "00" state with switches S1 and S2 open, and the output type is a full-step signal.

[0075] If the finite state machine is in the "10" state with switch S1 closed and switch S2 open, and the input signal |i| ≤ 0.25 and k < 0, the state remains unchanged, and the output type is a hold signal. During the path transition, when the signal i > 0.25, the finite state machine transitions from the "10" state with switch S1 closed and switch S2 open to the "11" state with both switches S1 and S2 closed, and the output type is a half-step signal. During the path transition, when the signal i < -0.25, the finite state machine transitions from the "10" state with switch S1 closed and switch S2 open to the "00" state with both switches S1 and S2 open, and the output type is a half-step signal. During the path transition, when the signal |i| ≤ 0.25 and k > 0, the finite state machine transitions from the "10" state with switch S1 closed and switch S2 open to the "01" state with switch S1 open and switch S2 closed, and the signal type is a hold signal.

[0076] The voltage balance condition of the half-bridge three-level flying capacitor inverter is:

[0077]

[0078] The present invention realizes full-range zero voltage switching (ZVS) operation, can automatically achieve flying capacitor voltage balance under the condition that the output voltage and current ripple of the multi-level inverter is small and no auxiliary circuit is required, and can reduce the voltage fluctuation of the flying capacitor by optimizing the charging and discharging sequence of the flying capacitor.

[0079] This embodiment proposes to use a random number method to achieve self-balancing of the flying capacitor. The specific method is: make the "01" and "10" states appear randomly with equal probability, which can effectively control the flying capacitor voltage to be stable at U dc / 2, however. Completely random selection of redundant paths may result in multiple consecutive charges or discharges, causing large fluctuations in the flying capacitor voltage. To address this issue, this embodiment designs a method for generating a balance signal k. Based on the positive or negative value of k, the state transition path of the finite state machine can be directly determined, as shown below:

[0080] S501: Determine whether the states of switches S1 and S2 in the finite state machine are the same. If so, k=1; if not, proceed to S502;

[0081] S502: Determine whether switch S1 is in a closed state. If so, calculate the Q value according to Q=Q-sign. If Q=0, determine whether r is greater than 0.5. If so, determine k=1; if less, determine k=-1. If Q≠0, determine the k value according to the current sign.

[0082] S503: If the switch S1 is in the open state, the Q value is calculated according to Q=Q+sign. If Q=0, it is determined whether r is greater than 0.5. If it is greater, k=1; if it is less, k=-1; if Q≠0, the k value is given according to the sign at the current moment; wherein Q is the balance flag bit, the initial value is 0, the Q value is the difference between the number of charging cycles and the number of discharging cycles, and r is a random number uniformly distributed in the range of 0 to 1.

[0083] Example

[0084] Combine Figure 7 To illustrate this embodiment, in order to verify the effect of the transcapacitor voltage self-balancing capability of the modulator for a multi-level wireless charging system described in the present invention, the following simulation experiment was designed in this embodiment:

[0085] In this example, a wireless charging system is built in simulation software to verify the effectiveness of the proposed flying capacitor multi-level soft switching modulation method. The mutual inductance M is set to 60.64μH, the load resistance is 40Ω, the bus voltage is 200V, and the flying capacitor initial voltage is 0V. Figure 7 Shows that given an input δ FCSDM = 0.7, including the balance signal k, switches S1 and S2, the inverter output voltage u and current i, and the flying capacitor voltage u c It can be seen that the output voltage has 4 full steps and 6 half steps in one cycle. The output calculated according to the formula is 0.7, which is consistent with the theory. The current fluctuation is small and the flying capacitor voltage is stable at around 100V, indicating that the balancing method of the flying capacitor self-balancing soft switching modulator designed in the present invention is effective.

[0086] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A modulator for a multi-level wireless charging system, characterized in that: The structure of a modulator for a multi-level wireless charging system includes: Proportional links, integrators, multipliers, finite state machines, delay links and microcontrollers; The microcontroller is used to provide an external signal sign and an external signal k. The initial inverter voltage δ FC-SDM Input multi-level soft switching modulator, the proportional link and integrator will input δ FC-SDM Integrate with the finite state machine feedback signal y to obtain the output e; The multiplier multiplies the signal e by the signal sign to obtain the input i of the state machine; The finite state machine is used to quantize the input signal i in combination with the external signal k; The delay link is used to control the signal trigger time.

2. The modulator for a multi-level wireless charging system according to claim 1, characterized in that: The wireless charging system in which the modulator is applied is compensated as a series-to-series compensation network topology, including: Primary coil L1, secondary coil L2, primary compensation capacitor C1, secondary compensation capacitor C2, flying capacitor C FC 、Filter capacitor C dc , load element Load, resistor R1, resistor R2, switch S1, switch S2, switch S3 and switch S4; The primary coil L1, the resistor R1 and the primary compensation capacitor C1 are connected in series. FC Connected in parallel with switch S2 and switch S3, and connected in series with switch S1 and switch S4; The secondary side compensation capacitor C2 and the resistor R2 are connected in series; Filter capacitor C dc Connected in parallel with the load element Load.

3. An application method of a modulator for a multi-level wireless charging system, applied to a modulator for a multi-level wireless charging system according to any one of claims 1 to 2, characterized in that: The steps of the application method of the modulator for the multi-level wireless charging system include: Step 1: Set the initial output voltage δ FC-SDM The input multi-level modulator and the state machine feedback signal y are subtracted and then passed through a proportional link; Step 2: shaping and filtering the output signal of the proportional link based on the integrator to convert it into a signal e; Step 3: The microcontroller provides an external signal sign and an external signal k, and uses the multiplier to multiply the external signal sign and the signal e to obtain a signal i; Step 4: Based on the finite state machine and the external signal k, the signal i is quantized to obtain digital outputs S1, S2 and y, and the signal y is used as feedback to be compared with the next input delta FC-SDM Combine; Step 5: Use the output signals S1 and S2 of the finite state machine as switch drive signals of the inverter, obtain three output types of full-step signal, half-step signal and hold signal, and realize soft switching operation of the transmitter inverter.

4. The application method of the modulator for a multi-level wireless charging system according to claim 3, characterized in that: Initial output voltage δ in step 1 FC-SDM The calculation formula is: In formula (1), N 1S is the number of half cycles of a full step, N 0.5S is the number of half-cycles of a half-step, N 0S The number of half cycles that the level is maintained.

5. The application method of the modulator for a multi-level wireless charging system according to claim 3, characterized in that: In step 3, the external signal sign is the direction signal of the inverter output current. sign is the two values ​​of 1 and -1 corresponding to the direction of the inverter output current, and is reversed every half of the resonance period. The external signal k is a flying capacitor voltage balance signal.

6. The application method of the modulator for a multi-level wireless charging system according to claim 3, characterized in that: In step 4, the value of the digital output y is one of 1, 0.5 and 0, where 1, 0.5 and 0 correspond to the three output types of full step signal, half step signal and hold signal respectively.

7. The application method of the modulator for a multi-level wireless charging system according to claim 3, characterized in that: The three output types of full step signal, half step signal and hold signal obtained in step 5 specifically include: If the finite state machine is in the "00" state where both switch S1 and switch S2 are open, and the input signal i<0.25, the state remains unchanged, and the output type is a hold signal; during the path transfer process, when the signal 0.25≤i≤0.75 and k>0, the finite state machine is converted from the "00" state where both switch S1 and switch S2 are open to the "01" state where switch S1 is open and switch S2 is closed, and the output type is a half-step signal; during the path transfer process, when the signal 0.25≤i≤0.75 and k<0, the finite state machine is converted from the "00" state where both switch S1 and switch S2 are open to the "10" state where switch S1 is closed and switch S2 is open, and the output type is a half-step signal; during the path transfer process, when the signal i>0.75, the finite state machine is converted from the "00" state where both switch S1 and switch S2 are open to the "11" state where both switch S1 and switch S2 are closed, and the output type is a full-step signal; If the finite state machine is in the "01" state with switch S1 open and switch S2 closed, the input signal |i|≤0.25 and k>0, the state remains unchanged, and the output type is a hold signal; during the path transfer process, when the signal i<-0.25, the finite state machine is converted from the "01" state with switch S1 open and switch S2 closed to the "00" state with both switch S1 and switch S2 open, and the output type is a half-step signal; during the path transfer process, when the signal i>0.25, the finite state machine is converted from the "01" state with switch S1 open and switch S2 closed to the "11" state with both switch S1 and switch S2 closed, and the output type is a half-step signal; during the path transfer process, when the signal |i|≤0.25 and k<0, the finite state machine is converted from the "01" state with switch S1 open and switch S2 closed to the "10" state with switch S1 closed and switch S2 open, and the output type is a hold signal; If the finite state machine is in the "11" state where both switch S1 and switch S2 are closed, and the input signal i>-0.25, the state remains unchanged, and the output type is a hold signal; during the path transfer process, when the signal -0.75≤i≤-0.25 and k>0, the finite state machine is converted from the "11" state where both switch S1 and switch S2 are closed to the "01" state where switch S1 is open and switch S2 is closed, and the output type is a half-step signal; during the path transfer process, when the signal -0.75≤i≤-0.25 and k<0, the finite state machine is converted from the "11" state where both switch S1 and switch S2 are closed to the "10" state where switch S1 is closed and switch S2 is open, and the output type is a half-step signal; during the path transfer process, when the signal i<-0.75, the finite state machine is converted from the "11" state where both switch S1 and switch S2 are closed to the "00" state where both switch S1 and switch S2 are open, and the output type is a full-step signal; If the finite state machine is in the "10" state with switch S1 closed and switch S2 open, the input signal |i|≤0.25 and k<0, the state remains unchanged, and the output type is a hold signal; during the path transfer process, when the signal i>0.25, the finite state machine is converted from the "10" state with switch S1 closed and switch S2 open to the "11" state with both switch S1 and switch S2 closed, and the output type is a half-step signal; during the path transfer process, when the signal i<-0.25, the finite state machine is converted from the "10" state with switch S1 closed and switch S2 open to the "00" state with both switch S1 and switch S2 open, and the output type is a half-step signal; during the path transfer process, when the signal |i|≤0.25 and k>0, the finite state machine is converted from the "10" state with switch S1 closed and switch S2 open to the "01" state with switch S1 open and switch S2 closed, and the signal type is a hold signal.

8. The application method of the modulator for a multi-level wireless charging system according to claim 7, characterized in that: During the signal step process, the signal step direction is consistent with the current change direction.

9. The application method of the modulator for a multi-level wireless charging system according to claim 3, characterized in that: The calculation steps of the external signal k include: Step 3.1: Determine whether the states of switches S1 and S2 in the finite state machine are the same. If so, k=1. If not, proceed to step 3.

2. Step 3.2: Determine whether the switch S1 is in a closed state. If it is in a closed state, calculate the Q value according to Q=Q-sign. If Q=0, determine whether r is greater than 0.

5. If it is greater, k=1. If it is less than, k=-1. If Q≠0, give the k value according to the sign at the current moment. Step 3.3: If the switch S1 is in the open state, the Q value is calculated according to Q=Q+sign. If Q=0, determine whether r is greater than 0.

5. If it is greater, k=1. If it is less than, k=-1. If Q≠0, the k value is given according to the sign at the current moment; wherein Q is the balance flag, the initial value is 0, the Q value is the difference between the number of charging cycles and the number of discharging cycles, and r is a random number uniformly distributed in the range of 0 to 1.

Images