Reconfigurable computing array, reconfigurable controller architecture, chip and reconfigurable computing method

Abstract

The invention discloses a reconfigurable computing array, a reconfiguration controller architecture, a chip and a reconfiguration computing method. The reconfigurable computing array comprises a main control module, a state machine module, a computing decoder module, a memory access resource controller module, a reconfiguration controller module, the reconfigurable computing array, an input buffer area module and an output buffer area module. The state machine module controls the whole reconstruction calculation process through state switching; the reconfiguration controller module configures the connection mode of PE units in the reconfigurable computing array according to the decoding result of the computing decoder module, and various computing functions are achieved so as to complete different types of data computing tasks. According to the method, the multiple computing units in the reconfigurable computing array are dynamically configured, so that a hardware architecture can be adjusted in real time according to different algorithm requirements, the reconfigurable computing array is accurately configured to complete different computing tasks, special hardware does not need to be designed for each task, and the computing efficiency is improved. Therefore, the flexibility of chip configuration and the resource utilization rate are improved.

Description

Technical Field

[0001] The present invention relates to the field of computer architecture, and in particular to a reconfigurable computing array, a reconfigurable controller architecture, a chip and a reconfigurable computing method. Background Art

[0002] DSP algorithms are widely used in various fields, such as modulation and demodulation in communication systems, noise reduction in audio processing, and filtering in image processing. DSP chips play a vital role in these applications because they are programmable, allowing processing algorithms to be adjusted as needed and able to perform complex operations at extremely high speeds. Traditional DSP chips usually use fixed hardware architectures and preset computing units, lack computing flexibility, and cannot meet new algorithm requirements and performance optimization needs. Reprogramming and resource allocation are required when processing complex and diverse digital signal processing algorithms, resulting in low chip resource utilization and low design efficiency.

[0003] For example, the patent with publication number CN102799563B discloses a reconfigurable computing array and construction method, including a preset number of single cores and interconnection modules, wherein any single core includes a reconfigurable computing module, a reconfigurable storage module, a reconfigurable control logic module and a configuration module, the reconfigurable computing module, the reconfigurable storage module and the reconfigurable control logic module are constructed with reference to the hardware structure of the basic computing core set contained in a certain application set, the preset number of single cores can support all the basic computing cores contained in the application set, and the interconnection module interconnects the preset number of single cores with reference to the hardware implementation of each application in the application set based on the basic computing core set.

[0004] The above patents all have the problems raised by this background technology: they use fixed hardware architecture and preset computing units, lack computing flexibility, cannot meet new algorithm requirements and performance optimization needs, and need to be reprogrammed and resource configured when processing complex and diverse digital signal processing algorithms, resulting in low resource utilization and low design efficiency of the chip; to solve these problems, the present invention proposes a reconfigurable computing array, a reconfigurable controller architecture, a chip and a reconfigurable computing method. Summary of the invention

[0005] In view of the shortcomings of the prior art, the main purpose of the present invention is to provide a reconfigurable computing array, a reconfigurable controller architecture, a chip and a reconfigurable computing method, which can effectively solve the problems in the background technology. The specific technical solutions of the present invention are as follows:

[0006] A reconfigurable computing array, comprising:

[0007] Single-precision arrays implement multiple real and complex number operations based on the reconfigured interconnection between multiple PE computing units. The reconfigured interconnection methods in real and complex modes are exactly the same.

[0008] Double-precision array, which realizes multiple computing functions based on the reconstructed interconnection between multiple computing units;

[0009] The MUX selector configures the connection mode between different computing units according to a preset configuration mode, so that the reconfigurable computing array can adapt to various computing tasks by integrating common operators of different algorithms and combining a unified input and output buffer.

[0010] Specifically, the single-precision array and the double-precision array include:

[0011] The single-precision array includes a plurality of 1 / 2PE units and a multiplication-addition bypass, wherein the 1 / 2PE unit is composed of a multiplexer, a comparator and a complex multiplier, and the multiplication-addition bypass is composed of a complex multiplier, a multiplexer and a divider;

[0012] The double-precision array consists of a double-precision comparator unit, a double-precision adder unit, a double-precision multiply-add unit, and a double-precision divide unit.

[0013] A reconfiguration computing method, used to configure the reconfigurable computing array, comprising:

[0014] The single-precision array is reconstructed in PE to realize multiplication and accumulation, multiplication and addition, and multiplication and subtraction operations;

[0015] The single-precision array is reconstructed through inter-PE reconstruction to implement comparison tree operation, accumulation tree operation, multiplication-accumulation tree operation and mean accumulation tree operation;

[0016] The double-precision array is connected through the reconstructed interconnection between the double-precision comparator unit, the double-precision adder unit, the double-precision multiplication-addition unit and the double-precision division unit to realize double-precision addition operation, double-precision subtraction operation, double-precision multiplication operation, double-precision division operation, double-precision comparison operation, double-precision multiplication-accumulation operation and double-precision accumulation operation.

[0017] Specifically, the reconstructing method of reconstructing the single-precision array in the PE to realize the multiplication-accumulation-addition operation, the multiplication-addition operation and the multiplication-subtraction operation includes:

[0018] In each 1 / 2PE unit, a multiplication-accumulation operation is realized by interconnecting a complex multiplier and two multiplexers, the complex multiplier performs multiplication calculation on input data to obtain a first result, the first result is input into a first multiplexer for accumulation to obtain an accumulation result, and the accumulation result and the first result are input into a second multiplexer to obtain a multiplication-accumulation calculation result;

[0019] In each 1 / 2PE unit, multiplication and addition operations and multiplication and subtraction operations are realized by interconnecting a complex multiplier and a multiplexer. The complex multiplier multiplies input data to obtain a multiplication result, and the multiplication result and input data are input into the multiplexer for calculation to obtain a multiplication and addition or a multiplication and subtraction result.

[0020] Specifically, the reconstruction method of reconstructing the single-precision array between PEs to implement comparison tree operations, accumulation tree operations, multiplication-accumulation tree operations, and mean accumulation tree operations includes:

[0021] A plurality of comparators between each 1 / 2PE unit are interconnected to realize a comparison tree operation, wherein the comparator compares the input data to obtain a comparison result, and the comparison result is input to the next comparator for comparison to obtain a final comparison result;

[0022] Multiple multiplexers of each 1 / 2PE unit are interconnected with multiple multiplexers of the multiplication-addition bypass to realize the accumulation tree operation. Two 1 / 2PE units are accumulated and calculated by multiple multiplexers to obtain the accumulation result of the first 1 / 2PE unit and the accumulation result of the second 1 / 2PE unit. The accumulation result of the first 1 / 2PE unit and the accumulation result of the second 1 / 2PE unit are input into the multiplexer in the multiplication-addition bypass for calculation to obtain the final accumulation tree calculation result.

[0023] The multiple complex multipliers and multiple adders of each 1 / 2PE unit are interconnected with the multiple multiplexers of the multiplication-addition bypass to realize the multiplication-accumulation tree operation. The two 1 / 2PE units input the calculation results of the complex multipliers into the multiple multiplexers for accumulation calculation to obtain the multiplication-accumulation result of the first 1 / 2PE unit and the multiplication-accumulation result of the second 1 / 2PE unit. The multiplication-accumulation result of the first 1 / 2PE unit and the multiplication-accumulation result of the second 1 / 2PE unit are input into the multiplexer in the multiplication-addition bypass for calculation to obtain the final multiplication-accumulation tree calculation result.

[0024] The multiple adders of each 1 / 2PE unit are interconnected with the multiple adders and dividers of the multiplication-addition bypass to realize the mean accumulation tree operation. The two 1 / 2PE units are accumulated and calculated by multiple multiplexers to obtain the third 1 / 2PE unit accumulation result and the fourth 1 / 2PE unit accumulation result. The third 1 / 2PE unit accumulation result and the fourth 1 / 2PE unit accumulation result are input into the multiple adders in the multiplication-addition bypass for accumulation calculation, and the calculation result is input into the divider to obtain the final mean accumulation tree calculation result.

[0025] A reconstruction controller architecture is used to implement a reconstruction calculation method, including:

[0026] A main control module, a state machine module, a computing decoder module, a memory access resource controller module, a reconstruction controller module, a reconfigurable computing array, an input buffer module and an output buffer module;

[0027] The main control module sends a control signal to the state machine module and sends a main control instruction to the calculation decoder module;

[0028] The state machine module switches states according to the received control signal to control the entire reconstruction calculation process;

[0029] The computing decoder module decodes the received master control instruction to obtain a decoding result, and receives the configuration instruction of the memory access resource controller module;

[0030] The reconfiguration controller module configures the connection mode of the reconfigurable computing array according to the decoding result, and controls the time interval of data transmission by setting a counter;

[0031] The reconfigurable computing array is an array composed of multiple interconnected PE units. Based on the configuration of the reconstruction controller module, the connection mode of the PE units is reorganized to realize multiple computing functions to complete data calculations, and the calculation results are transmitted to the output buffer module;

[0032] The input buffer module is used to receive input data and transmit the input data to the reconfigurable computing array;

[0033] The output buffer module is used to receive the calculation results of the reconfigurable computing array and output the calculation results.

[0034] Specifically, the state machine module switches states according to the received control signal, and controls the entire reconstruction calculation process including:

[0035] The state machine enters the IDLE state after the chip is started, waiting for the master control signal;

[0036] After receiving the start signal sent by the main control module, the state machine enters the DECODE state and controls the calculation decoder module to perform decoding;

[0037] After the decoding of the computing decoder module is completed, the state machine enters the RECONFIG state to control the reconstruction controller module to configure the reconfigurable computing array;

[0038] After the configuration process of the reconfiguration controller module is completed, the fixed calculation delay of the reconfigurable computing array is transmitted back to the main control module, the state machine enters the COMPUTE state, and the reconfigurable computing array starts to calculate the input data;

[0039] After receiving the end signal sent by the main control module, the state machine returns to the DECODE state;

[0040] After receiving the reset signal sent by the main control module, the state machine returns to the IDLE state.

[0041] Specifically, the calculation decoder module decodes the received main control instruction to obtain a decoding result, and receives the configuration instruction of the memory access resource controller module, including:

[0042] The calculation decoder module decodes the received master control instructions to determine the type of operation to be performed and the corresponding reconstruction interconnection method;

[0043] Receive and decode the configuration instructions of the memory resource controller to determine the data memory access strategy.

[0044] Specifically, the reconfiguration controller module configures the connection mode of the reconfigurable computing array according to the decoding result, and controls the time interval of data transmission by setting a counter, including:

[0045] The reconfiguration controller module controls the control end of the MUX selector in the reconfigurable computing array according to the operation type and the connection mode of the corresponding reconfigurable computing array to configure the reconfigurable computing array;

[0046] By setting a counter to control the time interval for data transmission, the calculation delays of different operation types can be transmitted to each other after the correct number of beats.

[0047] A chip having a module for reconstructing a controller architecture arranged inside the chip.

[0048] Compared with the prior art, the present invention has the following beneficial effects:

[0049] The present invention realizes multiplication-accumulation operation, multiplication-addition operation, multiplication-subtraction operation, comparison tree operation, accumulation tree operation, multiplication-accumulation tree operation and mean accumulation tree operation through the reconstruction interconnection between multiple PE computing units of a single-precision array. It adopts two 1 / 2PE units and a multiplication-addition bypass interconnection mode, and can flexibly support multiple operation modes, and can support independent execution of each 1 / 2PE unit and communication between 1 / 2PEs. It realizes addition operation, subtraction operation, multiplication operation, division operation, comparison operation, multiplication-accumulation operation and accumulation operation through the reconstruction interconnection between multiple computing units of a double-precision array. It enables the hardware architecture to be adjusted in real time according to different algorithm requirements by dynamically configuring multiple computing units, so that the computing array can adapt to different digital signal processing tasks without designing dedicated hardware for each task, thereby improving the flexibility of DSP chip configuration, optimizing computing performance and improving resource utilization. The present invention controls the reconfigurable computing array by reconstructing the controller architecture, and completes the efficient mapping and deployment of the signal processing algorithm in a data flow driven manner. At the same time, the design complexity of the data and control paths is reduced, which can effectively reduce the difficulty of physical implementation, thereby realizing efficient on-chip reconfiguration in multi-dimensional space dimensions, time dimensions, and resource dimensions, and accurately configuring the reconfigurable computing array to complete different computing tasks. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A schematic diagram of the structure of a reconfigurable computing array of the present invention;

[0051] Figure 2 This is a schematic diagram of the structure of a 1 / 2PE unit in Example 1 of the present invention;

[0052] Figure 3 Schematic diagram of the structure of the multiplication-addition bypass in Embodiment 1 of the present invention;

[0053] Figure 4 A reconstructed interconnection graph for the multiplication-accumulation-addition operation in Embodiment 2 of the present invention;

[0054] Figure 5 A reconstructed interconnection diagram of the multiplication-addition / multiplication-subtraction operation in Embodiment 2 of the present invention;

[0055] Figure 6 A reconstructed interconnection graph of the comparison tree operation in Embodiment 2 of the present invention;

[0056] Figure 7 A reconstructed interconnection graph of the cumulative tree operation in Embodiment 2 of the present invention;

[0057] Figure 8 A reconstructed interconnection graph of the multiplication-accumulation tree operation in Embodiment 2 of the present invention;

[0058] Fig. 9A reconstructed interconnection graph of the mean accumulation tree operation in Embodiment 2 of the present invention;

[0059] Fig.10 A schematic diagram of a module of a reconstructed controller architecture of the present invention;

[0060] Fig.11 This is a schematic diagram of the state transition of the state machine in Example 3 of the present invention. DETAILED DESCRIPTION

[0061] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0062] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0063] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0064] Example 1

[0065] This embodiment provides a reconfigurable computing array, and the specific solution is as follows: Figure 1 As shown, the reconfigurable computing array comprises:

[0066] Single-precision arrays implement multiple real and complex number operations based on the reconfigured interconnection between multiple PE computing units. The reconfigured interconnection methods in real and complex modes are exactly the same.

[0067] Double-precision array, which realizes multiple computing functions based on the reconstructed interconnection between multiple computing units;

[0068] The MUX selector configures the connection mode between different computing units according to a preset configuration mode, so that the reconfigurable computing array can adapt to various computing tasks by integrating common operators of different algorithms and combining a unified input and output buffer.

[0069] In this embodiment, the single-precision array is composed of multiple PE computing units, including 2 1 / 2PE units and a bypass. The PE computing unit is composed of multiple basic operation units, such as adders, multipliers, etc. Each computing unit is connected through a programmable interconnect structure. According to actual computing needs, the connection method between the computing units can be dynamically changed to support multiple operations. For example, to achieve multiplication operations, the corresponding basic operation units can be connected together for parallel processing, and the input data can be calculated. It can be reconstructed according to different computing needs, supporting a wide range of application scenarios, with higher flexibility. Through parallel processing, multiple computing tasks to be processed can be executed simultaneously to achieve faster computing speed. Computing resources can be dynamically allocated between different computing tasks, avoiding resource waste under a fixed architecture.

[0070] The double-precision array of this embodiment is also composed of multiple computing units, including comparators, multipliers, dividers, etc., and uses double-precision floating-point operations to meet higher computing accuracy requirements. Similar to the single-precision array, the double-precision array also relies on a programmable interconnect structure to achieve dynamic connection between computing units. The double-precision array supports more complex calculations and can meet application scenarios that require high reliability. Generally, double-precision operations consume more energy, but through dynamic reconstruction, energy efficiency can be optimized and resources can be saved on specific tasks.

[0071] The MUX selector of this embodiment uses the multiplexing principle to select different input connections to outputs through control signals to realize flexible configuration of the connection mode between multiple computing units. According to the actual computing task requirements, the MUX selector configures the connection mode between the computing units according to the preset configuration mode, integrates the common operators of various algorithms in the DSP, quantifies a set of reconstruction modes, outputs the input buffer through a unified standard interface, reduces the complexity of external interconnection, and solves the problem of redundant wiring. Instead of the traditional method, one algorithm and one interconnection line are no longer connected to the computing resources. By quickly switching the connection mode, the computing array can quickly switch between different computing tasks, adapt to diverse needs, and dynamically adjust resource usage according to the current task, which can improve computing efficiency and system response speed.

[0072] The present invention realizes multiplication-accumulation operation, multiplication-addition operation, multiplication-subtraction operation, comparison tree operation, accumulation tree operation, multiplication-accumulation tree operation and mean accumulation tree operation through the reconstruction interconnection between multiple PE computing units of a single-precision array. It adopts two 1 / 2PE units and a multiplication-addition bypass interconnection mode, and can flexibly support multiple operation modes, and can support independent execution of each 1 / 2PE unit and communication between 1 / 2PEs. It realizes addition operation, subtraction operation, multiplication operation, division operation, comparison operation, multiplication-accumulation operation and accumulation operation through the reconstruction interconnection between multiple computing units of a double-precision array. It enables the hardware architecture to be adjusted in real time according to different algorithm requirements by dynamically configuring multiple computing units, so that the computing array can adapt to different digital signal processing tasks without designing dedicated hardware for each task, thereby improving the flexibility of DSP chip configuration, optimizing computing performance and improving resource utilization. The present invention controls the reconfigurable computing array by reconstructing the controller architecture, and completes the efficient mapping and deployment of the signal processing algorithm in a data flow driven manner. At the same time, the design complexity of the data and control paths is reduced, which can effectively reduce the difficulty of physical implementation, thereby realizing efficient on-chip reconfiguration in multi-dimensional space dimensions, time dimensions, and resource dimensions, and accurately configuring the reconfigurable computing array to complete different computing tasks.

[0073] Furthermore, the single-precision array and the double-precision array include:

[0074] The single-precision array includes a plurality of 1 / 2PE units and a multiplication-addition bypass, wherein the 1 / 2PE unit is composed of a multiplexer, a comparator and a complex multiplier, and the multiplication-addition bypass is composed of a complex multiplier, a multiplexer and a divider;

[0075] The double-precision array consists of a double-precision comparator unit, a double-precision adder unit, a double-precision multiply-add unit, and a double-precision divide unit.

[0076] The single-precision array in this embodiment includes two 1 / 2PE units and a multiply-add bypass, such as Figure 2 Each 1 / 2PE unit consists of 16 adders, 8 comparators and 8 complex multipliers. The adders are used to perform addition operations, the comparators are used to compare different input values ​​for conditional judgment, and the complex multipliers are used to perform multiplication operations. Setting multiple adders and complex multipliers in a 1 / 2PE unit can process multiple operations at the same time, which can improve the calculation speed. By connecting different operation units, it can meet various operation requirements and complex logical operations. Figure 3The multiply-add bypass consists of 4 complex multipliers, 4 complex adders and 1 divider. The multiply-add bypass provides efficient multiply-add operations. Through the bypass structure, these operations can be performed in parallel, thereby reducing delays and improving system flexibility. The double-precision array consists of a double-precision comparator unit, a double-precision adder unit, a double-precision multiply-add unit and a double-precision divider unit, which can meet double-precision calculations.

[0077] Example 2

[0078] A reconfiguration computing method, used to configure the reconfigurable computing array, comprising:

[0079] The single-precision array is reconstructed in PE to realize multiplication and accumulation, multiplication and addition, and multiplication and subtraction operations;

[0080] The single-precision array is reconstructed through inter-PE reconstruction to implement comparison tree operation, accumulation tree operation, multiplication-accumulation tree operation and mean accumulation tree operation;

[0081] The double-precision array is connected through the reconstructed interconnection between the double-precision comparator unit, the double-precision adder unit, the double-precision multiplication-addition unit and the double-precision division unit to realize double-precision addition operation, double-precision subtraction operation, double-precision multiplication operation, double-precision division operation, double-precision comparison operation, double-precision multiplication-accumulation operation and double-precision accumulation operation.

[0082] The single-precision array in this embodiment implements multiplication-accumulation-addition operations, multiplication-addition operations, and multiplication-subtraction operations through a reconstruction method within the PE. By dynamically reconfiguring the multiplexers and complex multipliers within 1 / 2PE and connecting them into a summation network or a multiplication network, it can adapt to the needs of specific operations and implement multiplication-accumulation-addition operations, multiplication-addition operations, and multiplication-subtraction operations. Through different connection modes, the input and output paths are adjusted according to different operation requirements, and the flow of data is adjusted. It has high flexibility and can quickly adapt to different mathematical operations, reduce delays caused by hardware changes, and allow multiple operations to be performed alternately on the same hardware platform. There is no need to design separate hardware for each operation, thereby reducing waste of hardware resources.

[0083] The single-precision array in this embodiment realizes comparison tree operation, accumulation tree operation, multiplication-accumulation tree operation and mean accumulation tree operation through the reconstruction method of reconstruction between PEs. Between multiple PEs, by reconstructing the connection of adjacent PEs, a more complex operation structure, such as a tree structure, is formed to realize comparison tree operation, accumulation tree operation, multiplication-accumulation tree operation and mean accumulation tree operation. For example, by connecting the multiplexers between different PEs, an accumulation tree can be formed. By processing multiple inputs in parallel, multiple operations can be performed simultaneously to improve the overall efficiency, especially when large-scale data processing is performed, the calculation efficiency can be significantly improved, and the complex calculation functions can be modularized to facilitate maintenance and upgrading, thereby improving flexibility. By designing a reasonable single-precision array, using two 1 / 2PE units and multiplication-addition bypass, combined with a flexible internal and external reconstruction mechanism, it is possible to effectively support diversified calculation requirements, which not only improves the calculation efficiency, but also greatly enhances the flexibility and reconfigurability of the system.

[0084] In this embodiment, the double-precision array includes a double-precision comparator unit, a double-precision adder unit, a double-precision multiplication-addition unit, and a double-precision division unit. Double-precision comparison operations, addition operations, multiplication-addition operations, and division operations are realized through multiple units. The structure of the double-precision array allows these units to be dynamically interconnected. According to the type of operation currently required, the connection mode between the calculation units is configured to adapt to different operation requirements. For example, when performing multiplication-accumulation operations, the multiplication-addition unit and the adder unit can be connected; and when performing comparison operations, the input is connected to the comparator unit. By reconstructing the interconnection design, different operations can be completed on the same hardware to adapt to different computing requirements and improve flexibility. Different operations share the same hardware resources, reducing redundancy and hardware costs, and improving resource utilization. The double-precision unit can accurately process floating-point calculations to meet high-precision requirements.

[0085] Furthermore, the reconstructing method of reconstructing the single-precision array within the PE to realize the multiplication-accumulation-addition operation, the multiplication-addition operation and the multiplication-subtraction operation includes:

[0086] In each 1 / 2PE unit, a multiplication-accumulation operation is realized by interconnecting a complex multiplier and two multiplexers, the complex multiplier performs multiplication calculation on input data to obtain a first result, the first result is input into a first multiplexer for accumulation to obtain an accumulation result, and the accumulation result and the first result are input into a second multiplexer to obtain a multiplication-accumulation calculation result;

[0087] In each 1 / 2PE unit, multiplication and addition operations and multiplication and subtraction operations are realized by interconnecting a complex multiplier and a multiplexer. The complex multiplier multiplies input data to obtain a multiplication result, and the multiplication result and input data are input into the multiplexer for calculation to obtain a multiplication and addition or a multiplication and subtraction result.

[0088] In this embodiment, if Figure 4 In the 1 / 2PE unit, a multiplication-accumulation operation is realized by interconnecting a complex multiplier and two multiplexers. The complex multiplier performs multiplication calculation on the input data to obtain a first result, the first result is input into the first multiplexer for accumulation to obtain an accumulation result, and the accumulation result and the first result are input into the second multiplexer to obtain a multiplication-accumulation calculation result.

[0089] Specifically, the complex multiplier receives two complex input data A and B, A = (a1, a2) and B = (b1, b2), and performs a multiplication operation to obtain a first result, then the first result = A × B = (a1b1-a2b2, a1b2+a2b1), the first result is input into the first multiplexer for accumulation operation, the first result is added to the first result to obtain an accumulation result, the accumulation result = the first result + the first result, the accumulation result and the first result are input into the second multiplexer together to calculate the multiplication and accumulation result, the multiplication and accumulation result = the accumulation result + the first result. For example, input data A = 1 + 2i, B = 3 + 4i, C = 5 + 6i, A and B are input into the complex multiplier to calculate the first result of -5 + 10i, the first result is input into the first multiplexer to calculate the accumulation result of -10 + 20i, the first result and the accumulation result are input into the second multiplexer to calculate the multiplication and accumulation result of -15 + 30i. By using a combination of complex multipliers and complex adders, multiplication and accumulation calculations can be completed quickly, improving computing efficiency. Compared with the traditional multiplication and addition step-by-step execution, by fusing the two operations, the hardware implementation can save area and power consumption.

[0090] In this embodiment, if Figure 5 , inside the 1 / 2PE unit, multiplication and addition and multiplication and subtraction operations are realized by interconnecting a complex multiplier and a multiplexer. The complex multiplier multiplies the input data to obtain the multiplication result, and the multiplication result and the input data are input into the multiplexer for calculation to obtain the multiplication and addition or multiplication and subtraction result.

[0091] Specifically, the complex multiplier receives two complex input data C and D, C = (c1, c2) and D = (d1, d2), and performs multiplication operation to obtain the multiplication result, then the multiplication result = C × D = (c1d1-c2d2, c1d2+c2d1), the multiplication result and the input data E are input to the multiplexer for operation, and the multiplication and addition or multiplication and subtraction result is obtained. For example, the input data C = 1 + 2i, D = 3 + 4i, E = 5 + 6i, C and D are input to the complex multiplier to calculate the multiplication result of -5 + 10i, and the multiplication result and E are input to the multiplexer to calculate the multiplication and addition result of 16i. By using a combination of complex multipliers and multiplexers, multiplication and addition and multiplication and subtraction calculations can be completed quickly, and the calculation efficiency can be improved. Compared with the traditional multiplication and addition step-by-step execution, by fusing the two operations, the area and power consumption can be saved in hardware implementation.

[0092] Furthermore, the reconstruction of the single-precision array through inter-PE reconstruction to implement comparison tree operation, accumulation tree operation, multiplication-accumulation tree operation and mean accumulation tree operation includes:

[0093] A plurality of comparators between each 1 / 2PE unit are interconnected to realize a comparison tree operation, wherein the comparator compares the input data to obtain a comparison result, and the comparison result is input to the next comparator for comparison to obtain a final comparison result;

[0094] Multiple multiplexers of each 1 / 2PE unit are interconnected with multiple multiplexers of the multiplication-addition bypass to realize the accumulation tree operation. Two 1 / 2PE units are accumulated and calculated by multiple multiplexers to obtain the accumulation result of the first 1 / 2PE unit and the accumulation result of the second 1 / 2PE unit. The accumulation result of the first 1 / 2PE unit and the accumulation result of the second 1 / 2PE unit are input into the multiplexer in the multiplication-addition bypass for calculation to obtain the final accumulation tree calculation result.

[0095] The multiple complex multipliers and multiple adders of each 1 / 2PE unit are interconnected with the multiple multiplexers of the multiplication-addition bypass to realize the multiplication-accumulation tree operation. The two 1 / 2PE units input the calculation results of the complex multipliers into the multiple multiplexers for accumulation calculation to obtain the multiplication-accumulation result of the first 1 / 2PE unit and the multiplication-accumulation result of the second 1 / 2PE unit. The multiplication-accumulation result of the first 1 / 2PE unit and the multiplication-accumulation result of the second 1 / 2PE unit are input into the multiplexer in the multiplication-addition bypass for calculation to obtain the final multiplication-accumulation tree calculation result.

[0096] The multiple adders of each 1 / 2PE unit are interconnected with the multiple adders and dividers of the multiplication-addition bypass to realize the mean accumulation tree operation. The two 1 / 2PE units are accumulated and calculated by multiple multiplexers to obtain the third 1 / 2PE unit accumulation result and the fourth 1 / 2PE unit accumulation result. The third 1 / 2PE unit accumulation result and the fourth 1 / 2PE unit accumulation result are input into the multiple adders in the multiplication-addition bypass for accumulation calculation, and the calculation result is input into the divider to obtain the final mean accumulation tree calculation result.

[0097] In this embodiment, if Figure 6 , multiple comparators between two 1 / 2PE units are interconnected to implement comparison tree operation, the comparator compares the input data to obtain a comparison result, and the comparison result is input into the next comparator for comparison to obtain a final comparison result.

[0098] Specifically, multiple data to be compared are provided as input to the comparator of the first level. Each comparator receives two input data, compares them, and outputs the comparison result. The comparator outputs a larger value or a smaller value. For example, when the comparator receives x1 and x2 and needs to find the maximum value, when x1>x2, it outputs x1. The comparison result of the comparator of the previous layer is input to the comparator of the next layer for further comparison, thus forming a tree structure. The comparator of each layer processes the comparison result of the previous layer. The two 1 / 2PE units respectively calculate the comparison result of the first 1 / 2PE unit and the comparison result of the second 1 / 2PE unit. The two 1 / 2PE units are connected, and the comparison result of the first 1 / 2PE unit and the comparison result of the second 1 / 2PE unit are input into the comparator for comparison to obtain the final comparison result. The comparison tree structure allows multiple comparisons to be performed simultaneously, which significantly improves the processing speed. By adjusting the structure or depth of the comparison tree, it can flexibly cope with different quantities and types of data.

[0099] In this embodiment, if Figure 7 , interconnect multiple multiplexers of the two 1 / 2PE units with multiple multiplexers of the multiplication-addition bypass to realize the accumulation tree operation, the two 1 / 2PE units accumulate and calculate through multiple multiplexers to obtain the accumulation result of the first 1 / 2PE unit and the accumulation result of the second 1 / 2PE unit, input the accumulation result of the first 1 / 2PE unit and the accumulation result of the second 1 / 2PE unit into the multiplexer in the multiplication-addition bypass for calculation, and obtain the final accumulation tree calculation result.

[0100] Specifically, for example, there are multiple input data Y=[y1, y2, y3, y4, y5, y6, y7, y8], and two 1 / 2PE units accumulate the input data respectively. The first 1 / 2PE unit accumulates y1, y2, y3, and y4, and the second 1 / 2PE unit accumulates y5, y6, y7, and y8. The input data is input into the multiplexer of the first level for calculation, and the calculation result of the multiplexer of the previous level is input into the multiplexer of the next level for further calculation, thus forming an accumulation tree structure. Accumulation calculation is performed in each 1 / 2PE unit to obtain the accumulation result of the first 1 / 2PE unit and the accumulation result of the second 1 / 2PE unit, and the two 1 / 2PE units are respectively connected to the multiplexer of the multiplication-addition bypass, and the accumulation result of the first 1 / 2PE unit and the accumulation result of the second 1 / 2PE unit are input into the multiplexer of the multiplication-addition bypass for calculation to obtain the final accumulation tree calculation result. Different multiplexers can process multiple inputs at the same time, greatly improving the overall computing speed. Through the hierarchical structure, partial results can be calculated at each layer, reducing the delay from input to final output.

[0101] In this embodiment, if Figure 8, interconnect multiple complex multipliers and multiple adders of the two 1 / 2PE units with multiple multiplexers of the multiplication-addition bypass to realize multiplication-accumulation tree operation, the two 1 / 2PE units input the calculation results of the complex multipliers into multiple multiplexers for accumulation calculation to obtain the multiplication-accumulation result of the first 1 / 2PE unit and the multiplication-accumulation result of the second 1 / 2PE unit, input the multiplication-accumulation result of the first 1 / 2PE unit and the multiplication-accumulation result of the second 1 / 2PE unit into the multiplexer in the multiplication-addition bypass for calculation, and obtain the final multiplication-accumulation tree calculation result.

[0102] Specifically, for example, there are multiple input data Z = [z1, z2, z3, z4, z5, z6, z7, z8], and two 1 / 2PE units input the input data into the multiplexer for calculation in pairs. The first 1 / 2PE unit multiplies z1, z2, z3, and z4, and the second 1 / 2PE unit multiplies z5, z6, z7, and z8, and the calculation results of each two multiplexers are input into the multiplexer for calculation, and the calculation result of the previous layer of multiplexers is input into the next layer of multiplexers for calculation until all the calculation results of the multiplexers are added up, and the multiplication and accumulation results of the first 1 / 2PE unit and the multiplication and accumulation results of the second 1 / 2PE unit are obtained by cumulative calculation, and the two 1 / 2PE units are respectively connected to the multiplexers of the multiplication and addition bypass, and the multiplication and accumulation results of the first 1 / 2PE unit and the second 1 / 2PE unit are input into the multiplexers of the multiplication and addition bypass for calculation to obtain the final multiplication and accumulation tree calculation result. Through the parallel operation of multiple complex multipliers and adders, the computing efficiency can be significantly improved, large-scale data can be processed quickly, and it has high efficiency, flexibility and excellent resource utilization.

[0103] In this embodiment, if Fig. 9 , interconnect multiple adders of two 1 / 2PE units with multiple adders and dividers of multiplication-addition bypass to realize mean accumulation tree operation, and the two 1 / 2PE units accumulate and calculate the third 1 / 2PE unit accumulation result and the fourth 1 / 2PE unit accumulation result through multiple adders, input the third 1 / 2PE unit accumulation result and the fourth 1 / 2PE unit accumulation result into the multiple adders in the multiplication-addition bypass for accumulation calculation, and input the calculation result into the divider to obtain the final mean accumulation tree calculation result.

[0104] Specifically, the mean accumulation tree operation is based on the accumulation tree operation. The accumulation tree calculation result is input into the divider in the multiplication-addition bypass to be averaged to obtain the final mean accumulation tree calculation result. By using multiple adders and multiplication-addition bypasses, parallel calculation can be achieved, thereby accelerating the calculation efficiency and being able to quickly calculate large-scale data sets. Connecting multiple adders and dividers can save hardware resources and improve calculation flexibility.

[0105] Example 3

[0106] This embodiment provides a reconstruction controller architecture for implementing a reconstruction calculation method of embodiment 2, such as Fig.10 , the reconstructed controller architecture comprises:

[0107] A main control module, a state machine module, a computing decoder module, a memory access resource controller module, a reconstruction controller module, a reconfigurable computing array, an input buffer module and an output buffer module;

[0108] The main control module sends a control signal to the state machine module and sends a main control instruction to the calculation decoder module;

[0109] The state machine module switches states according to the received control signal to control the entire reconstruction calculation process;

[0110] The computing decoder module decodes the received master control instruction to obtain a decoding result, and receives the configuration instruction of the memory access resource controller module;

[0111] The reconfiguration controller module configures the connection mode of the reconfigurable computing array according to the decoding result, and controls the time interval of data transmission by setting a counter;

[0112] The reconfigurable computing array is an array composed of multiple interconnected PE units. Based on the configuration of the reconstruction controller module, the connection mode of the PE units is reorganized to realize multiple computing functions to complete data calculations, and the calculation results are transmitted to the output buffer module;

[0113] The input buffer module is used to receive input data and transmit the input data to the reconfigurable computing array;

[0114] The output buffer module is used to receive the calculation results of the reconfigurable computing array and output the calculation results.

[0115] A reconstruction controller architecture of this embodiment includes a main control module, a state machine module, a calculation decoder module, a memory access resource controller module, a reconstruction controller module, a reconfigurable calculation array, an input buffer module and an output buffer module. The main control module generates control signals and instructions by receiving user input or preset tasks, and is responsible for sending control signals and main control instructions to coordinate the functions of other modules, sending control signals to the state machine module to start and manage the calculation process, and sending main control instructions to the calculation decoder module to indicate the required calculation tasks. By centrally managing the calculation process, the controllability and consistency of the system are improved, and the control signals and instructions can be quickly adjusted according to different calculation requirements; the state machine module switches the state according to the received control signal to control the entire reconstruction calculation process, and the state machine module switches between different states, such as the initial state, the calculation state and the transmission state. Through the state transfer logic, the control signal guides other modules to complete specific tasks, and the state machine can respond quickly according to the signal changes and dynamically control the calculation process.

[0116] Among them, the computing decoder module is responsible for decoding the master control instructions to obtain the actual computing instructions, and receiving the configuration instructions of the memory access resource controller module to configure computing resources. By decoding the master control instructions sent by the master control module, it generates instructions that can be understood and executed by other modules to improve computing efficiency. At the same time, it receives configuration instructions from the memory access resource controller, and reasonably allocates and manages computing resources according to the configuration instructions to improve resource utilization efficiency. The memory access resource controller module is responsible for managing data access, receiving data requests, and reading data from the input buffer or output buffer. It can quickly manage data access and reduce computing delays.

[0117] The reconstruction controller module of this embodiment configures the connection mode of the reconfigurable computing array according to the decoding result, selects the corresponding connection mode to configure the computing array according to the computing requirements, controls the time interval of data transmission by setting a counter to ensure the validity of the data, and quickly reconstructs the connection mode according to different computing tasks to adapt to various operations. By controlling the data transmission frequency, the ability to process data is improved. The reconfigurable computing array is composed of multiple interconnected PE units to perform actual computing tasks. According to the configuration of the reconstruction controller, the connection mode between PE units is dynamically adjusted to adapt to different computing algorithms, accept input data, perform calculations and send the results to the output buffer. It can realize various computing functions through different reconstruction methods, and the parallel processing of multiple PE units can significantly improve the computing speed. The input buffer module is used to receive input data and transmit the input data to the reconfigurable computing array; the output buffer module is used to receive the calculation results of the reconfigurable computing array and output the calculation results. The reconstruction controller architecture realizes efficient and flexible data computing functions through the collaborative work of various modules. Each module plays an important role in computing, data flow management and control, and the overall computing efficiency and performance of the system are improved through reasonable design.

[0118] Further, such as Fig.11 The state machine module switches states according to the received control signal, and controls the entire reconstruction calculation process including:

[0119] The state machine enters the IDLE state after the chip is started, waiting for the master control signal;

[0120] After receiving the start signal sent by the main control module, the state machine enters the DECODE state and controls the calculation decoder module to perform decoding;

[0121] After the decoding of the computing decoder module is completed, the state machine enters the RECONFIG state to control the reconstruction controller module to configure the reconfigurable computing array;

[0122] After the configuration process of the reconfiguration controller module is completed, the fixed calculation delay of the reconfigurable computing array is transmitted back to the main control module, the state machine enters the COMPUTE state, and the reconfigurable computing array starts to calculate the input data;

[0123] After receiving the end signal sent by the main control module, the state machine returns to the DECODE state;

[0124] After receiving the reset signal sent by the main control module, the state machine returns to the IDLE state.

[0125] like Fig.11The state machine controls the entire reconstruction calculation process by switching states. After the chip is started, it enters the IDLE state and waits for the main control module to send a signal. At this time, the system is in a standby mode and does not perform any calculations. By maintaining the IDLE state, the reconfigurable computing array and other modules are not used to reduce resource consumption; when the state machine receives the start signal sent by the main control module, it enters the DECODE state. In this state, the state machine instructs the computing decoder module to perform the decoding process, generates the corresponding computing configuration according to the received instructions, and switches the system from the low-power state to the ready state to ensure timely response to the main control signal; after the decoding of the computing decoder module is completed, the state machine enters the RECONFIG state. In this state, the state machine controls the reconstruction controller module to configure the reconfigurable computing array to achieve specific computing functions, and flexibly modify the structure of the computing array according to the decoding results to support variable computing needs; the configuration of the reconstruction controller module After the configuration process is completed, the fixed computing delay of the reconfigurable computing array is transmitted back to the main control module, and the state machine enters the COMPUTE state. In this state, the reconfigurable computing array starts to perform the calculation of the input data and perform actual numerical processing, giving full play to the high efficiency of the computing array and quickly processing the input data; after the state machine receives the end signal sent by the main control module, it returns to the DECODE state. This state allows the system to prepare to accept new computing instructions and decode again. By quickly switching back to the decoding state, it can adapt to multiple continuous computing tasks and maintain the efficiency and flexibility of the system calculation; after the state machine receives the reset signal sent by the main control module, it returns to the IDLE state, and the system enters the standby state again, waiting for the next round of tasks. By returning to the initial state, the data residue of the current state is eliminated to ensure that each calculation is independent and stable. When the calculation is no longer needed, it enters the low power consumption state in time to avoid unnecessary waste of resources or accidental operations.

[0126] By controlling the entire reconfigurable computing process through the state machine, clear task management and efficient resource utilization can be achieved. Each step and its state transition helps to improve system performance and flexibility, enabling the reconfigurable computing array to adapt to a variety of application requirements and maintain efficient computing capabilities, which helps to improve the response speed, stability and reusability of the entire system.

[0127] Furthermore, the calculation decoder module decodes the received master control instruction to obtain a decoding result, and receives the configuration instruction of the memory access resource controller module, including:

[0128] The calculation decoder module decodes the received master control instructions to determine the type of operation to be performed and the corresponding reconstruction interconnection method;

[0129] Receive and decode the configuration instructions of the memory resource controller to determine the data memory access strategy.

[0130] In this embodiment, the computing decoder module receives the main control instruction from the main control module, decodes the main control instruction, identifies the operation type represented by the instruction (such as addition, multiplication, comparison, etc.), and according to the identified operation type, the decoder provides the corresponding reconstruction interconnection mode to the reconstruction controller module to configure the connection mode of the reconfigurable computing array; by translating complex main control instructions into clear execution operations, the control logic of the entire computing process is simplified, and the readability and maintainability of the system are improved; the computing decoding module also receives configuration instructions from the memory access controller, which are responsible for managing the rules of data access, decodes the configuration instructions, obtains specific data storage strategies, including access modes, cache strategies, data prefetching, etc., generates control signals, and feeds back to the memory access resource controller to achieve efficient data access, improves the utilization level of storage resources through the data access strategy, reduces the delay that may be caused during data access by quickly analyzing and processing the configuration instructions, and improves the data access efficiency.

[0131] Furthermore, the reconfiguration controller module configures the connection mode of the reconfigurable computing array according to the decoding result, and controls the time interval of data transmission by setting a counter, including:

[0132] The reconfiguration controller module controls the control end of the MUX selector in the reconfigurable computing array according to the operation type and the connection mode of the corresponding reconfigurable computing array to configure the reconfigurable computing array;

[0133] By setting a counter to control the time interval for data transmission, the calculation delays of different operation types can be transmitted to each other after the correct number of beats.

[0134] In this embodiment, the reconstruction controller module determines the connection mode of the corresponding reconfigurable computing array according to the operation type transmitted by the computing decoder, controls the control end of the MUX selector in the reconfigurable computing array, establishes an appropriate signal path between PE units, and realizes the configuration of the reconfigurable computing array. The configuration of the MUX selector enables the same hardware to be reconstructed according to different operation types, which can maximize the use of hardware resources and reduce unnecessary energy consumption or operation redundancy. By setting a counter to control and adjust the time interval between data transmission, data conflicts can be prevented and data can be ensured to be transmitted within the correct time window. Each operation type may correspond to different calculation delays. The reconstruction controller appropriately adjusts the value of the counter according to the delay information, so that the operation module accepts the result of the previous calculation at an appropriate time. Through effective time control, the risk of errors in data transmission is reduced, ensuring the accuracy of the calculation.

[0135] A chip, wherein a module for reconstructing a controller architecture as claimed in claims 6 to 9 is arranged inside the chip.

[0136] Specifically, the resources inside the chip are divided in a modular way, and each module can work independently. This structure makes the communication and control between the modules more flexible and simple. By setting up the modules of the reconfigurable controller architecture, the control of the reconfigurable computing array can be achieved. The limited hardware resources can be effectively utilized by dynamic reconstruction. The configuration is optimized according to different computing needs, so that the chip can respond quickly to different computing tasks, reduce the fixedness in hardware design, and increase the flexibility of the chip. When the device is in standby mode, most of the resources can be turned off, and only basic monitoring functions are running, thereby maximizing power saving. By setting up modules of the reconfigurable controller architecture inside the chip, the flexibility, performance and energy efficiency of the chip can be significantly improved. This design method can not only adapt to a variety of application scenarios, but also bring higher resource utilization and longer product life cycle, meeting a variety of computing needs while optimizing the user experience.

[0137] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A reconfigurable computing array, characterized in that: include: Single-precision arrays implement multiple real and complex number operations based on the reconfigured interconnection between multiple PE computing units. The reconfigured interconnection methods in real and complex modes are exactly the same. Double-precision array, which realizes multiple computing functions based on the reconstructed interconnection between multiple computing units; The MUX selector configures the connection mode between different computing units according to a preset configuration mode, so that the reconfigurable computing array can adapt to various computing tasks by integrating common operators of different algorithms and combining a unified input and output buffer.

2. A reconfigurable computing array according to claim 1, characterized in that: The single precision array and the double precision array include: The single-precision array includes a plurality of 1 / 2PE units and a multiplication-addition bypass, wherein the 1 / 2PE unit is composed of a multiplexer, a comparator and a complex multiplier, and the multiplication-addition bypass is composed of a complex multiplier, a multiplexer and a divider; The double-precision array consists of a double-precision comparator unit, a double-precision adder unit, a double-precision multiply-add unit, and a double-precision divide unit.

3. A reconfiguration computing method for configuring a reconfigurable computing array as claimed in claims 1 to 2, characterized in that: include: The single-precision array is reconstructed in PE to realize multiplication and accumulation, multiplication and addition, and multiplication and subtraction operations; The single-precision array is reconstructed through inter-PE reconstruction to implement comparison tree operation, accumulation tree operation, multiplication-accumulation tree operation and mean accumulation tree operation; The double-precision array is connected through the reconstructed interconnection between the double-precision comparator unit, the double-precision adder unit, the double-precision multiplication-addition unit and the double-precision division unit to realize double-precision addition operation, double-precision subtraction operation, double-precision multiplication operation, double-precision division operation, double-precision comparison operation, double-precision multiplication-accumulation operation and double-precision accumulation operation.

4. A reconstruction calculation method according to claim 3, characterized in that: The method of reconstructing the single-precision array in the PE to realize multiplication-accumulation-addition operation, multiplication-addition operation and multiplication-subtraction operation includes: In each 1 / 2PE unit, a multiplication-accumulation operation is realized by interconnecting a complex multiplier and two multiplexers, the complex multiplier performs multiplication calculation on input data to obtain a first result, the first result is input into a first multiplexer for accumulation to obtain an accumulation result, and the accumulation result and the first result are input into a second multiplexer to obtain a multiplication-accumulation calculation result; In each 1 / 2PE unit, multiplication and addition operations and multiplication and subtraction operations are realized by interconnecting a complex multiplier and a multiplexer. The complex multiplier multiplies input data to obtain a multiplication result, and the multiplication result and input data are input into the multiplexer for calculation to obtain a multiplication and addition or a multiplication and subtraction result.

5. A reconstruction calculation method according to claim 3, characterized in that: The method of reconstructing the single-precision array between PEs to realize comparison tree operation, accumulation tree operation, multiplication-accumulation tree operation and mean accumulation tree operation includes: A plurality of comparators between each 1 / 2PE unit are interconnected to realize a comparison tree operation, wherein the comparator compares the input data to obtain a comparison result, and the comparison result is input to the next comparator for comparison to obtain a final comparison result; Multiple multiplexers of each 1 / 2PE unit are interconnected with multiple multiplexers of the multiplication-addition bypass to realize the accumulation tree operation. Two 1 / 2PE units are accumulated and calculated by multiple multiplexers to obtain the accumulation result of the first 1 / 2PE unit and the accumulation result of the second 1 / 2PE unit. The accumulation result of the first 1 / 2PE unit and the accumulation result of the second 1 / 2PE unit are input into the multiplexer in the multiplication-addition bypass for calculation to obtain the final accumulation tree calculation result. The multiple complex multipliers and multiple adders of each 1 / 2PE unit are interconnected with the multiple multiplexers of the multiplication-addition bypass to realize the multiplication-accumulation tree operation. The two 1 / 2PE units input the calculation results of the complex multipliers into the multiple multiplexers for accumulation calculation to obtain the multiplication-accumulation result of the first 1 / 2PE unit and the multiplication-accumulation result of the second 1 / 2PE unit. The multiplication-accumulation result of the first 1 / 2PE unit and the multiplication-accumulation result of the second 1 / 2PE unit are input into the multiplexer in the multiplication-addition bypass for calculation to obtain the final multiplication-accumulation tree calculation result. The multiple adders of each 1 / 2PE unit are interconnected with the multiple adders and dividers of the multiplication-addition bypass to realize the mean accumulation tree operation. The two 1 / 2PE units are accumulated and calculated by multiple multiplexers to obtain the third 1 / 2PE unit accumulation result and the fourth 1 / 2PE unit accumulation result. The third 1 / 2PE unit accumulation result and the fourth 1 / 2PE unit accumulation result are input into the multiple adders in the multiplication-addition bypass for accumulation calculation, and the calculation result is input into the divider to obtain the final mean accumulation tree calculation result.

6. A reconstruction controller architecture, used to implement a reconstruction calculation method as claimed in any one of claims 3 to 5, characterized in that: include: A main control module, a state machine module, a computing decoder module, a memory access resource controller module, a reconstruction controller module, a reconfigurable computing array, an input buffer module and an output buffer module; The main control module sends a control signal to the state machine module and sends a main control instruction to the calculation decoder module; The state machine module switches states according to the received control signal to control the entire reconstruction calculation process; The computing decoder module decodes the received master control instruction to obtain a decoding result, and receives the configuration instruction of the memory access resource controller module; The reconfiguration controller module configures the connection mode of the reconfigurable computing array according to the decoding result, and controls the time interval of data transmission by setting a counter; The reconfigurable computing array is an array composed of multiple interconnected PE units. Based on the configuration of the reconstruction controller module, the connection mode of the PE units is reorganized to realize multiple computing functions to complete data calculations, and the calculation results are transmitted to the output buffer module; The input buffer module is used to receive input data and transmit the input data to the reconfigurable computing array; The output buffer module is used to receive the calculation results of the reconfigurable computing array and output the calculation results.

7. A reconfigurable controller architecture according to claim 6, characterized in that: The state machine module switches states according to the received control signal, and controls the entire reconstruction calculation process including: The state machine enters the IDLE state after the chip is started, waiting for the master control signal; After receiving the start signal sent by the main control module, the state machine enters the DECODE state and controls the calculation decoder module to perform decoding; After the decoding of the computing decoder module is completed, the state machine enters the RECONFIG state to control the reconstruction controller module to configure the reconfigurable computing array; After the configuration process of the reconfiguration controller module is completed, the fixed calculation delay of the reconfigurable computing array is transmitted back to the main control module, the state machine enters the COMPUTE state, and the reconfigurable computing array starts to calculate the input data; After receiving the end signal sent by the main control module, the state machine returns to the DECODE state; After receiving the reset signal sent by the main control module, the state machine returns to the IDLE state.

8. The reconfigurable computing array and the reconfiguration controller architecture thereof according to claim 6, characterized in that: The calculation decoder module decodes the received main control instruction to obtain a decoding result, and receives the configuration instruction of the memory access resource controller module, including: The calculation decoder module decodes the received master control instructions to determine the type of operation to be performed and the corresponding reconstruction interconnection method; Receive and decode the configuration instructions of the memory resource controller to determine the data memory access strategy.

9. The reconfigurable computing array and the reconfiguration controller architecture thereof according to claim 1, characterized in that: The reconfiguration controller module configures the connection mode of the reconfigurable computing array according to the decoding result, and controls the time interval of data transmission by setting a counter, including: The reconfiguration controller module controls the control end of the MUX selector in the reconfigurable computing array according to the operation type and the connection mode of the corresponding reconfigurable computing array to configure the reconfigurable computing array; By setting a counter to control the time interval for data transmission, the calculation delays of different operation types can be transmitted to each other after the correct number of beats.

10. A chip, characterized in that The chip is internally provided with a module for reconstructing the controller architecture as claimed in claims 6 to 9.

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