Neutral-point potential balance control system and method for three-level Buck direct-current converter

Abstract

The invention provides a neutral-point potential balance control system and method for a three-level Buck direct-current converter, and belongs to the technical field of switching power supplies. The power part comprises an input voltage source, an upper voltage-dividing capacitor, a lower voltage-dividing capacitor, a first switching tube, a second switching tube, a first diode, a second diode, an output filter inductor, an output filter capacitor and an output load resistor, the upper voltage-dividing capacitor and the lower voltage-dividing capacitor are connected in series and then connected with the input voltage source in parallel, and the first diode is connected with the second diode; the cathode of the first diode is connected with the first switch tube and then connected to the anode of the voltage source, the anode of the second diode is connected with the second switch tube and then connected to the cathode of the voltage source, the midpoint of the two capacitors is connected with the midpoint of the two diodes, voltages at two ends of the lower voltage-dividing capacitor are midpoint potentials, and midpoint potential balance control is carried out by adjusting edges of switch tube driving signals. The efficiency, the power density and the reliability of the converter are improved.

Description

Technical Field

[0001] The present application relates to the technical field of switching power supplies, and in particular to a midpoint potential balance control system and method for a three-level Buck DC converter. Background Art

[0002] The three-level Buck DC converter reduces the voltage stress of power devices and the high-frequency AC component of the voltage across the filter inductor by introducing an additional mid-point potential, which is conducive to achieving high efficiency and high power density of the converter. Therefore, it is widely used in high input voltage scenarios.

[0003] A key difficulty in the application of three-level Buck DC converters is that the incomplete symmetry of the circuit parameters leads to an unbalanced midpoint potential, which increases the voltage stress of the power devices and the current pulsation of the filter inductor. In severe cases, it leads to overvoltage failure of the devices and damage to the converter.

[0004] The midpoint potential balance control methods for three-level Buck DC converters can be divided into two categories: analog control and digital control. The implementation circuit of analog control is more complex and is limited by the functions of analog devices. Taking the UCx84x series PWM controller as an example, it can only generate a driving signal with a fixed leading edge and modulated trailing edge. This scheme has certain restrictions when implementing midpoint potential balance control and requires the introduction of additional auxiliary control schemes. The digital control scheme has the advantages of flexible algorithm, simple implementation, and lower cost. It does not rely on specific hardware and circuit design, and can implement complex control methods. Therefore, it is necessary to study the digital control strategy for achieving midpoint potential balance. Summary of the invention

[0005] In view of this, an embodiment of the present application provides a three-level Buck DC converter midpoint potential balance control system and method, which samples the error between the input voltage and the midpoint potential, adopts an edge modulation control strategy, delays or advances the edge of the switch tube drive signal according to the midpoint potential error, and realizes midpoint potential balance control, reduces the voltage stress of power devices and the size of passive filter devices in the three-level Buck circuit, and realizes high efficiency, high power density and high reliability of the converter.

[0006] In a first aspect, an embodiment of the present application provides a three-level Buck DC converter midpoint potential balance control system, the system comprising a power part and a control part, the power part comprising an input voltage source V in , upper voltage divider capacitor C in1 , lower voltage divider capacitor C in2 , a first switch tube Q1, a second switch tube Q2, a first diode D1, a second diode D2 and an output load resistor R out , output load resistance R outThe voltage across the two ends is the output voltage V o , upper voltage divider capacitor C in1 And the lower voltage divider capacitor C in2 After being connected in series, they are connected in parallel to the input voltage source V in The first diode D1 and the second diode D2 are connected in series, the anode of the first diode D1 is connected to the cathode of the second diode D2, and the cathode of the first diode D1 is connected to the first switch tube Q1 and then to the voltage source V in The positive electrode of the second diode D2 is connected to the second switch tube Q2 and then to the voltage source V in The negative pole of the upper voltage divider capacitor C in1 And the lower voltage divider capacitor C in2 The midpoint N is connected to the midpoint of the first diode D1 and the second diode D2, and the lower voltage divider capacitor C in2 The voltage between the two ends is the midpoint potential V n The control part is connected to the first switch tube Q1 and the second switch tube Q2 respectively, and the edge of the driving signal of the first switch tube Q1 and / or the second switch tube Q2 is adjusted by the control part to adjust the midpoint potential V n balance control.

[0007] According to a specific implementation of the embodiment of the present application, the power part also includes an output filter inductor L and an output filter capacitor C out , one end of the output filter inductor L is connected to the cathode of the first diode D1, and the other end of the output filter inductor L is connected to the output load resistor R out One end of the output filter capacitor C out Connect in parallel to the output load resistor R out both ends of .

[0008] According to a specific implementation of the embodiment of the present application, the control part includes an output voltage stabilization control part, a midpoint potential balance control part, an output voltage PI controller, a midpoint potential PI controller, a first superposition module and a second superposition module, and an output filter capacitor C out and the output load resistor R out The voltage at both ends is the output voltage. The output voltage stabilization control part is used to convert the output voltage sampling value v os and the output voltage reference value v ref After comparison, the output voltage error signal v is obtained oerr , the output voltage PI controller is used based on the output voltage error signal v oerr Generates output voltage regulation signal v oerr_out The midpoint potential balance control part is used to convert the input voltage sampling value v ins and midpoint potential sampling value v ns After comparison, the midpoint potential error signal v is obtained nerrThe midpoint potential PI controller is used based on the midpoint potential error signal v nerr Generate midpoint potential adjustment signal v nerr_out The first superposition module is used to adjust the output voltage signal v oerr_out and midpoint potential adjustment signal v nerr_out The first comparison value v that reflects both the midpoint potential error and the output voltage error is obtained by superposition. compare1 The second superposition module is used to adjust the output voltage signal v oerr_out and midpoint potential adjustment signal v nerr_out The second comparison value v is obtained by superposition, which reflects both the midpoint potential error and the output voltage error. compare2 , the first comparison value v compare1 Used to modulate the edge of the first drive signal D1, the second comparison value v compare2 It is used to modulate the edge of the second drive signal D2. The first drive signal D1 is output as the duty cycle of the first switch tube Q1, and the second drive signal D2 is output as the duty cycle of the second switch tube Q2.

[0009] In a second aspect, an embodiment of the present application further provides a method for controlling a midpoint potential balance of a three-level Buck DC converter, using the three-level Buck DC converter midpoint potential balance control system as described in any embodiment of the first aspect, the method comprising:

[0010] Set the voltage divider capacitor C in2 The voltage between the two ends is the midpoint potential V n The control part adjusts the edge of the driving signal of the first switch tube Q1 and / or the second switch tube Q2 to adjust the midpoint potential V n balance control.

[0011] According to a specific implementation of the embodiment of the present application, the driving signal is a PWM signal.

[0012] According to a specific implementation of the embodiment of the present application, the edge of the driving signal is adjusted by leading edge modulation of a PWM signal.

[0013] According to a specific implementation of the embodiment of the present application, the leading edge modulation includes:

[0014] When the voltage divider capacitor C in1 The voltage across the capacitor is lower than the lower voltage divider capacitor C in2 When the voltage at both ends is high, the leading edge of the driving signal of the second switch tube Q2 is advanced; when the upper voltage dividing capacitor C in1 The voltage across the capacitor is higher than the lower voltage divider capacitor C in2 When the voltage across both ends is , the leading edge of the driving signal of the second switch tube Q2 is delayed.

[0015] According to a specific implementation of the embodiment of the present application, the edge of the driving signal is adjusted by double-edge modulation of a PWM signal.

[0016] According to a specific implementation of the embodiment of the present application, the dual-edge modulation includes:

[0017] When the voltage divider capacitor C in1 The voltage across the capacitor is lower than the lower voltage divider capacitor C in2 When the voltage at both ends is , the leading edge of the driving signal of the first switch tube Q1 and the trailing edge of the driving signal of the second switch tube Q2 are delayed, and the trailing edge of the driving signal of the first switch tube Q1 and the leading edge of the driving signal of the second switch tube Q2 are advanced, and at this time, the amount of delay and advance is equal;

[0018] When the voltage divider capacitor C in1 The voltage across the capacitor is higher than the lower voltage divider capacitor C in2 When the voltage at both ends is , the trailing edge of the driving signal of the first switch tube Q1 and the leading edge of the driving signal of the second switch tube Q2 are delayed, and the leading edge of the driving signal of the first switch tube Q1 and the trailing edge of the driving signal of the second switch tube Q2 are advanced. At this time, the delay and advance amounts are equal.

[0019] According to a specific implementation of the embodiment of the present application, the control part adjusts the edge of the driving signal of the first switch tube Q1 and / or the second switch tube Q2 to the midpoint potential V n Balance control, including:

[0020] The output voltage stabilization control part converts the output voltage sampling value v os and the output voltage reference value v ref After comparison, the output voltage error signal v is obtained oerr , output voltage error signal v oerr The output voltage PI controller generates the output voltage regulation signal v oerr_out ;

[0021] The midpoint potential balance control part inputs the voltage sampling value v ins and midpoint potential sampling value v ns After comparison, the midpoint potential error signal v is obtained nerr , midpoint potential error signal v nerr The midpoint potential PI controller generates the midpoint potential adjustment signal v nerr_out ;

[0022] The output voltage regulation signal v in the output voltage closed-loop feedback calculation result oerr_out and the midpoint potential closed-loop feedback calculation result of the midpoint potential adjustment signal v nerr_out The first comparison value v that reflects both the midpoint potential error and the output voltage error is obtained by superposition. compare1and the second comparison value v compare2 , the first comparison value v compare1 Used to modulate the edge of the first drive signal D1, the second comparison value v compare2 It is used to modulate the edge of the second drive signal D2. The first drive signal D1 is used as the duty cycle output of the first switch tube Q1, and the second drive signal D2 is used as the duty cycle output of the second switch tube Q2, so as to achieve the midpoint potential balance and output voltage stabilization of the three-level Buck DC converter.

[0023] Beneficial effects:

[0024] The three-level Buck DC converter midpoint potential balance control system and method in the embodiment of the present application realizes the drive signal adjustment of the three-level Buck DC converter through the edge modulation digital control circuit, and then controls the midpoint potential balance and output voltage stabilization, so that the midpoint potential is half of the input voltage, reduces the switch tube voltage stress and filter inductor current pulsation component of the three-level Buck DC converter, and improves the efficiency, power density and reliability of the converter. The control method proposed by the present invention is easy to implement, has high reliability, and can save design costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 A structural diagram of the power part of a three-level Buck DC converter midpoint potential balance control system provided by the present invention;

[0027] Figure 2 The key waveform for achieving midpoint potential balance by aligning the leading edge and modulating the trailing edge;

[0028] Figure 3 The key waveform for achieving midpoint potential balance by aligning the trailing edge and modulating the leading edge;

[0029] Figure 4 For center alignment, double-edge modulation is the key waveform to achieve midpoint potential balance;

[0030] Figure 5 This is a structural diagram of the control part of a midpoint potential balance control system of a three-level Buck DC converter proposed in the present invention;

[0031] Figure 6 is a circuit block diagram provided by Embodiment 1 of the present invention;

[0032] Figure 7 It is an equivalent diagram of the process of generating PWM waveform by the internal timer of the MCU in the first embodiment of the present invention;

[0033] Figure 8 is a circuit block diagram provided by Embodiment 2 of the present invention;

[0034] Fig. 9 It is an equivalent diagram of the process of generating PWM waveform by the internal timer of the MCU in the second embodiment of the present invention. DETAILED DESCRIPTION

[0035] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0036] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0037] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0038] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0039] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0040] In the first aspect, the present application embodiment provides a three-level Buck DC converter midpoint potential balance control system, as shown below: Figure 1 and Figure 5 Describe in detail.

[0041] In one embodiment, referring to Figure 1 The three-level Buck DC converter midpoint potential balance control system includes a power part and a control part. The power part includes an input voltage source V in , upper voltage divider capacitor C in1 , lower voltage divider capacitor C in2 , a first switch tube Q1, a second switch tube Q2, a first diode D1, a second diode D2 and an output load resistor R out , output load resistance R out The voltage across the two ends is the output voltage V o , upper voltage divider capacitor C in1 And the lower voltage divider capacitor C in2 After being connected in series, they are connected in parallel to the input voltage source V in The first diode D1 and the second diode D2 are connected in series, the anode of the first diode D1 is connected to the cathode of the second diode D2, and the cathode of the first diode D1 is connected to the first switch tube Q1 and then to the voltage source V in The positive electrode of the second diode D2 is connected to the second switch tube Q2 and then to the voltage source V in The negative pole of the upper voltage divider capacitor C in1 And the lower voltage divider capacitor C in2 The midpoint N is connected to the midpoint of the first diode D1 and the second diode D2, and the lower voltage divider capacitor C in2 The voltage between the two ends is the midpoint potential V n The control part is connected to the first switch tube Q1 and the second switch tube Q2 respectively, and the edge of the driving signal of the first switch tube Q1 and / or the second switch tube Q2 is adjusted by the control part to adjust the midpoint potential V n balance control.

[0042] Specifically, the drain of the first switch tube Q1 is connected to the input voltage source V in The positive electrode and the upper voltage divider capacitor C in1 The source of the first switch tube Q1 is connected to the cathode of the first diode D1, and the source of the second switch tube Q2 is connected to the input voltage source V in The negative electrode and the lower voltage divider capacitor C in2The drain of the second switch tube Q2 is connected to the anode of the second diode D2, and the base of the first switch tube Q1 and the base of the second switch tube Q2 are respectively connected to the control part.

[0043] Furthermore, the power part also includes an output filter inductor L and an output filter capacitor C out , one end of the output filter inductor L is connected to the cathode of the first diode D1, and the other end of the output filter inductor L is connected to the output load resistor R out One end of the output filter capacitor C out Connect in parallel to the output load resistor R out both ends of .

[0044] Further, see Figure 5 The control part includes an output voltage stabilization control part, a midpoint potential balance control part, an output voltage PI controller, a midpoint potential PI controller, a first superposition module and a second superposition module, and an output filter capacitor C out and the output load resistor R out The voltage at both ends is the output voltage. The output voltage stabilization control part is used to convert the output voltage sampling value v os and the output voltage reference value v ref After comparison, the output voltage error signal v is obtained oerr , the output voltage PI controller is used based on the output voltage error signal v oerr Generates output voltage regulation signal v oerr_out The midpoint potential balance control part is used to convert the input voltage sampling value v ins and midpoint potential sampling value v ns After comparison, the midpoint potential error signal v is obtained nerr The midpoint potential PI controller is used based on the midpoint potential error signal v nerr Generate midpoint potential adjustment signal v nerr_out The first superposition module is used to adjust the output voltage signal v oerr_out and midpoint potential adjustment signal v nerr_out The first comparison value v that reflects both the midpoint potential error and the output voltage error is obtained by superposition. compare1 The second superposition module is used to adjust the output voltage signal v oerr_out and midpoint potential adjustment signal v nerr_out The second comparison value v is obtained by superposition, which reflects both the midpoint potential error and the output voltage error. compare2 , the first comparison value v compare1 Used to modulate the edge of the first drive signal D1, the second comparison value v compare2It is used to modulate the edge of the second drive signal D2. The first drive signal D1 is output as the duty cycle of the first switch tube Q1, and the second drive signal D2 is output as the duty cycle of the second switch tube Q2.

[0045] In a second aspect, an embodiment of the present application further provides a method for controlling a midpoint potential balance of a three-level Buck DC converter, using the three-level Buck DC converter midpoint potential balance control system as described in any embodiment of the first aspect, the method comprising:

[0046] Set the voltage divider capacitor C in2 The voltage between the two ends is the midpoint potential V n The control part adjusts the edge of the driving signal of the first switch tube Q1 and / or the second switch tube Q2 to adjust the midpoint potential V n balance control.

[0047] In specific implementation, the upper voltage dividing capacitor C in1 And the lower voltage divider capacitor C in2 The connection point is the midpoint N, the lower voltage divider capacitor C in2 The voltage between the two ends is the midpoint potential V n , midpoint potential balance means controlling the midpoint potential V n is the input voltage V in half of the output filter capacitor C out and the output load resistor R out The voltage across the two ends is the output voltage V o .

[0048] When the duty cycle of the driving signal of the first switch tube Q1 and the second switch tube Q2 is the same but the phase difference is 180°, and the upper voltage divider capacitor C in1 And the lower voltage divider capacitor C in2 When the input voltage is evenly divided, the voltage stress on the switch tube is reduced to V in / 2, which can maximize the advantages of the three-level Buck DC converter. However, since the parasitic parameters of the power circuit and the control circuit cannot be completely symmetrical, there is generally a voltage difference between the upper and lower voltage-dividing capacitors, that is, the midpoint potential is unbalanced. At this time, the midpoint potential balance control can be performed by adjusting the edge of the drive signal of the first switch tube Q1 and the second switch tube Q2. The leading edge and trailing edge of the drive signal can be adjusted at the same time, or the leading edge or trailing edge of the drive signal can be adjusted separately.

[0049] Furthermore, the driving signal is a PWM signal, and the edge of the driving signal is regulated by leading edge modulation of the PWM signal.

[0050] In specific implementation, the general generation methods of digital PWM signals include edge alignment and center alignment, wherein edge alignment is further divided into leading edge alignment and trailing edge alignment. The principles of implementing midpoint potential balance control by the above three methods are analyzed in turn below. It should be noted that the analysis method is also applicable to the two adjustment strategies of only adjusting the edge of the drive signal of the first switch tube Q1 or the second switch tube Q2 or adjusting the edge of the drive signal of the first switch tube Q1 and the second switch tube Q2 at the same time.

[0051] Specifically, under the leading edge alignment scheme, the leading edge of the PWM signal is aligned and the trailing edge is modulated. in1 The voltage across the capacitor is lower than the lower voltage divider capacitor C in2 When the voltage across both ends is high, the trailing edge of the driving signal of the second switch tube Q2 is delayed; when the upper voltage dividing capacitor C in1 The voltage across the capacitor is higher than the lower voltage divider capacitor C in2 When the voltage across both ends is high, the trailing edge of the driving signal of the second switch tube Q2 is advanced, and the waveform of the key signal is Figure 2 Given in.

[0052] Figure 2 Where D1 and D2 are the driving signals of the first switch tube Q1 and the second switch tube Q2 respectively. L is the inductor current. Before regulation, the conduction time of the first switch tube Q1 and the second switch tube Q2 is equal, and the amount of charge released by the upper and lower voltage divider capacitors in one cycle is equal. Assume that V n >V in / 2, at this time, the trailing edge of D2 is delayed, so that the conduction time of the second switch tube Q2 is t on Add Δt on the basis of , and Δt is much smaller than t on Since the midpoint potential balance is the result of closed-loop control, although there is a difference between the voltages at both ends of the upper and lower voltage divider capacitors, their values ​​are both within V in / 2, and to simplify the calculation process, the voltage across the upper and lower voltage divider capacitors is assumed to be V in / 2. It is calculated that in the current cycle, due to the increase in the conduction time of Q2, the lower voltage divider capacitor C in2 The additional charge released is Figure 2 The shaded area from t1 to t1' has a value of

[0053]

[0054] In formula 1, I v is the valley value of the inductor current.

[0055] Although the conduction time of the first switch tube Q1 remains unchanged, the demagnetization time of the filter inductor L is reduced, which makes the inductor current when the first switch tube Q1 is turned on larger. in1 The additional amount of charge released is Figure 2 The shaded area from t2 to t3 has a value of

[0056]

[0057] The difference in the amount of charge released by the upper and lower voltage divider capacitors in one cycle is

[0058]

[0059] like Then ΔQ>0, the voltage divider capacitor C in2 The voltage divider capacitor C in1 Multiple discharge, C in2 Voltage across the terminals V n Decrease, and the midpoint potential is balanced. Then ΔQ≤0, the voltage divider capacitor C in2 The voltage divider capacitor C in1 Less discharge, C in2 Voltage across the terminals V n The above analysis shows that the control scheme of generating PWM signal by leading edge alignment and trailing edge modulation is affected by I v 、V o ,t on and L, the opposite result will occur as the load changes.

[0060] Further, the leading edge modulation includes:

[0061] When the voltage divider capacitor C in1 The voltage across the capacitor is lower than the lower voltage divider capacitor C in2 When the voltage at both ends is high, the leading edge of the driving signal of the second switch tube Q2 is advanced; when the upper voltage divider capacitor C in1 The voltage across the capacitor is higher than the lower voltage divider capacitor C in2 When the voltage across both ends is , the leading edge of the driving signal of the second switch tube Q2 is delayed.

[0062] In specific implementation, under the trailing edge alignment scheme, the trailing edge of the PWM signal is aligned and the leading edge is modulated. in1 The voltage across the capacitor is lower than the lower voltage divider capacitor C in2 When the voltage at both ends is high, the leading edge of the driving signal of the second switch tube Q2 is advanced; when the upper voltage divider capacitor C in1 The voltage across the capacitor is higher than the lower voltage divider capacitor C in2 When the voltage across both ends is high, the leading edge of the driving signal of the second switch tube Q2 is delayed, and the waveform of the key signal is Figure 3 Given in, assuming V n >V in / 2, at this time, the leading edge of D2 is advanced, so that the conduction time of the second switch tube Q2 is t onAdd Δt on the basis of , and Δt is much smaller than t on To simplify the calculation process, it is assumed that the voltage across the upper and lower voltage divider capacitors is V in / 2. Before calculating the duty cycle, the voltage divider capacitor C in2 The amount of charge released in one cycle is

[0063]

[0064] After adjusting the duty cycle, the lower voltage divider capacitor C in2 The amount of charge released in the current cycle is

[0065]

[0066] As the conduction time of the second switch tube Q2 increases, the voltage divider capacitor C in2 The additional charge released is Figure 3 The shaded area from t0' to t1 has a value of

[0067] ΔQ1=Q2-Q1 (Equation 6)

[0068] Although the turn-on time of the first switch tube Q1 remains unchanged, the demagnetization time of the filter inductor L is reduced, which makes the inductor current larger when the switch tube Q1 is turned on. in1 The additional amount of charge released is Figure 3 The shaded area from t2 to t3 has a value of

[0069]

[0070] The difference in the amount of charge released by the upper and lower voltage divider capacitors in one cycle is

[0071]

[0072] Since ΔQ>0, the voltage divider capacitor C in2 The voltage divider capacitor C in1 Multiple discharge, C in2 Voltage across the terminals V n Decrease to achieve midpoint potential balance.

[0073] Furthermore, the edge of the driving signal is regulated by dual-edge modulation of a PWM signal, and the dual-edge modulation includes:

[0074] When the voltage divider capacitor C in1 The voltage across the capacitor is lower than the lower voltage divider capacitor C in2When the voltage at both ends is , the leading edge of the driving signal of the first switch tube Q1 and the trailing edge of the driving signal of the second switch tube Q2 are delayed, and the trailing edge of the driving signal of the first switch tube Q1 and the leading edge of the driving signal of the second switch tube Q2 are advanced, and at this time, the amount of delay and advance is equal;

[0075] When the voltage divider capacitor C in1 The voltage across the capacitor is higher than the lower voltage divider capacitor C in2 When the voltage at both ends is , the trailing edge of the driving signal of the first switch tube Q1 and the leading edge of the driving signal of the second switch tube Q2 are delayed, and the leading edge of the driving signal of the first switch tube Q1 and the trailing edge of the driving signal of the second switch tube Q2 are advanced. At this time, the delay and advance amounts are equal.

[0076] In specific implementation, under the center alignment scheme, the pulse center of the PWM signal is aligned, and the leading and trailing edges are modulated at the same time. in1 The voltage across the capacitor is lower than the lower voltage divider capacitor C in2 When the voltage at both ends is 1, the leading edge of the driving signal of the first switch tube Q1 and the trailing edge of the driving signal of the second switch tube Q2 are delayed, and the trailing edge of the driving signal of the first switch tube Q1 and the leading edge of the driving signal of the second switch tube Q2 are advanced, and the delay and advance amounts are equal; when the upper voltage dividing capacitor C in1 The voltage across the capacitor is higher than the lower voltage divider capacitor C in2 When the voltage at both ends is , the trailing edge of the driving signal of the first switch tube Q1 and the leading edge of the driving signal of the second switch tube Q2 are delayed, and the leading edge of the driving signal of the first switch tube Q1 and the trailing edge of the driving signal of the second switch tube Q2 are advanced, and the delay and advance amounts are equal.

[0077] The waveform of the key signal is Figure 4 Given in, assuming V n >V in / 2, the digital PWM controller updates the driving waveform from time t0, which is manifested as the leading edge of D1 is delayed by Δt, and the trailing edge is advanced by Δt; the leading edge of D2 is advanced by Δt, and the trailing edge is delayed by Δt, and Δt is much smaller than t on To simplify the calculation process, it is assumed that the voltage across the upper and lower voltage divider capacitors is V in / 2. In the period [t1, t1'], the lower voltage divider capacitor C in2 The additional amount of charge released is Figure 4 The shaded area from t1 to t1' has a value of

[0078]

[0079] During the period [t2, t2'], the upper voltage divider capacitor C in1 The less amount of charge released, Figure 4 The shaded area from t2 to t2' has a value of

[0080]

[0081] During the period [t3', t3], the upper voltage divider capacitor C in1 The less amount of charge released, Figure 4 The shaded area from t3' to t3 has a value of

[0082]

[0083] In the time period [t0', t0+T], the lower voltage divider capacitor C in2 The additional amount of charge released is Figure 4 The shaded area from t0' to t0+T has a value

[0084]

[0085] Combining equations 9 to 12, the voltage divider capacitor C in2 As the amount of charge released increases, the upper voltage divider capacitor C in1 The amount of charge released decreases, and the difference in the amount of charge released by the upper and lower voltage divider capacitors is

[0086]

[0087] Since ΔQ>0, the voltage divider capacitor C in2 The voltage divider capacitor C in1 Multiple discharge, C in2 Voltage across the terminals V n Decrease to achieve midpoint potential balance.

[0088] Combined with the above analysis, the dual-edge modulation or leading-edge modulation digital control strategy of the present invention can realize the midpoint potential balance control of the three-level Buck DC converter. It should be noted that the action mechanism of the above control strategy is explained with the three-level Buck DC converter in continuous conduction mode and the driving duty cycle of the switch tube is less than 50%. When the three-level Buck DC converter is in continuous conduction mode and the duty cycle is greater than 50%, the above analysis conclusion is also valid.

[0089] In one embodiment, the control part adjusts the edge of the driving signal of the first switch tube Q1 and / or the second switch tube Q2 to the midpoint potential V n Balance control, including:

[0090] The output voltage stabilization control part converts the output voltage sampling value v os and the output voltage reference value v ref After comparison, the output voltage error signal v is obtained oerr , output voltage error signal v oerr The output voltage PI controller generates the output voltage regulation signal voerr_out ;

[0091] The midpoint potential balance control part inputs the voltage sampling value v ins and midpoint potential sampling value v ns After comparison, the midpoint potential error signal v is obtained nerr , midpoint potential error signal v nerr The midpoint potential PI controller generates the midpoint potential adjustment signal v nerr_out ;

[0092] The output voltage regulation signal v in the output voltage closed-loop feedback calculation result oerr_out and the midpoint potential closed-loop feedback calculation result of the midpoint potential adjustment signal v nerr_out The first comparison value v that reflects both the midpoint potential error and the output voltage error is obtained by superposition. compare1 and the second comparison value v compare2 , the first comparison value v compare1 Used to modulate the edge of the first drive signal D1, the second comparison value v compare2 It is used to modulate the edge of the second drive signal D2. The first drive signal D1 is used as the duty cycle output of the first switch tube Q1, and the second drive signal D2 is used as the duty cycle output of the second switch tube Q2, so as to achieve the midpoint potential balance and output voltage stabilization of the three-level Buck DC converter.

[0093] In specific implementation, the control part adds midpoint potential balance control on the basis of traditional output voltage stabilization control, and uses double-edge modulation or leading-edge modulation scheme to adjust the midpoint potential. The control process of the loop is as follows: Figure 5 As shown. The output voltage stabilization control part converts the output voltage sampling value v os and the output voltage reference value v ref After comparison, the output voltage error signal v is obtained oerr , output voltage error signal v oerr The output voltage PI controller generates the output voltage regulation signal v oerr_out The midpoint potential balance control part inputs the voltage sampling value v ins and midpoint potential sampling value v ns After comparison, the midpoint potential error signal v is obtained nerr , midpoint potential error signal v nerr The midpoint potential PI controller generates the midpoint potential adjustment signal v nerr out The calculation results of the output voltage closed-loop feedback and the midpoint potential closed-loop feedback are superimposed to obtain a comparison value v that reflects both the midpoint potential error and the output voltage error. compare1 and v compare2, used to modulate the edges of the drive signals D1 and D2. The drive signals D1 and D2 are used as duty cycle outputs of the first switch tube Q1 and the second switch tube Q2, thereby achieving midpoint potential balance and output voltage stabilization of the three-level Buck DC converter.

[0094] The following is a detailed description of the three-level Buck DC converter midpoint potential balance control method of the present application with reference to a specific embodiment.

[0095] Embodiment 1

[0096] Figure 6 The structure diagram of the midpoint potential balance control system of the three-level Buck DC converter provided in this embodiment includes a power part, a sampling part and a digital control part.

[0097] The power part includes: an input voltage source V in , upper voltage divider capacitor C in1 , lower voltage divider capacitor C in2 , first switch tube Q1, second switch tube Q2, first diode D1, second diode D2, output filter inductor L, output filter capacitor C out and the output load resistor R out The upper voltage divider capacitor C in1 And the lower voltage divider capacitor C in2 The connection point is the midpoint N, the lower voltage divider capacitor C in2 The voltage across the terminals is V n In this embodiment, the control target of the midpoint potential balance is to control the midpoint voltage V n is the input voltage V in The output filter capacitor C out and the output load resistor R out The voltage across the two ends is the output voltage V o .

[0098] The sampling part includes the output voltage V o Sampling, inductor current i L Sampling, input voltage V in Sampling and midpoint potential V n Sampling. Output voltage V o The sampling factor is H vo ; Inductor current i L The sampling factor is H IL ; Input voltage V in The sampling factor is H vin ; Midpoint potential V n The sampling factor is H vn It should be noted that in order to ensure the input voltage sampling value v ins and midpoint potential sampling value v nsAt the same order of magnitude, the input voltage V in and midpoint potential V n The sampling circuit should meet the input voltage sampling coefficient H vin is the midpoint potential sampling coefficient H vn half of its value.

[0099] The control part adopts a center-aligned, dual-edge modulation scheme, including output voltage closed-loop feedback control and midpoint potential closed-loop feedback control. The output voltage closed-loop feedback calculation obtains the output voltage regulation signal v oerr_out , v oerr_out By comparing the voltage values ​​of the two symmetrical triangular carriers staggered 180°, the driving signals D1 and D2 with the same duty cycle but a phase difference of 180° are obtained. The midpoint potential closed-loop feedback calculation obtains the midpoint potential adjustment signal v nerr_out , output voltage regulation signal v oerr_out With the midpoint potential adjustment signal v nerr_out Superposition to get the comparison value v compare1 and comparison value v compare2 , v compare1 and v compare2 The voltage values ​​of the two carriers staggered 180° are compared to obtain driving signals D1 and D2 that simultaneously reflect the midpoint potential error and the output voltage error. Based on the control part, the driving signal of the switch tube of the three-level Buck DC converter can be adjusted to achieve midpoint potential balance and output voltage stabilization of the converter.

[0100] The output voltage closed-loop feedback part in the control part is used to realize the voltage regulation control of the output voltage and introduce the damping control of the inductor current. The feedback loop samples the output voltage V o and the inductor current i L As the input signal, the output voltage regulation signal v is generated after loop regulation oerr_out1 The midpoint potential closed-loop feedback part in the control part is used to realize midpoint potential balance control. The feedback loop samples the input voltage V in and midpoint potential V n As the input signal, the midpoint potential adjustment signal v is generated after loop adjustment nerr_out . The following steps are included:

[0101] Step 1: Calculate the output voltage sampling value v at the current moment os (k) and the output voltage reference v ref The difference between the output voltage and the error signal v oerr (k), which is expressed as follows:

[0102] v oerr (k) = v ref -v os(k) (Equation 14)

[0103] Step 2: Output voltage error signal v oerr (k) Perform loop calculation through PI control to generate output voltage regulation signal v oerr_out (k), v oerr_out (k) The expression is as follows:

[0104]

[0105] In formula 15, Δv oerr_out (k) represents the compensation value of the output voltage PI control algorithm for the output voltage regulation signal at the current moment, v oerr (k) represents the value of the output voltage error signal at the current moment, v oerr (k-1) represents the value of the output voltage error signal at the previous moment, v oerr_out (k) represents the value of the output voltage regulation signal at the current moment, v oerr_out (k-1) represents the value of the output voltage regulation signal at the previous moment. K p_vo and K i_vo It represents the proportional coefficient and integral coefficient obtained by discretizing the output voltage PI controller.

[0106] Step 3: Introduce the damping control of the inductor current to obtain the final calculation result of the output voltage closed-loop feedback v oerr_out1 (k), whose value is:

[0107] v oerr_out1 (k) = v oerr_out (k)-k L ·i Ls (k) (Equation 16)

[0108] In formula 16, k L is the inductor current damping coefficient, i Ls (k) represents the inductor current sampling value at the current moment.

[0109] Step 4: Calculate the current input voltage sampling value v ins (k) and midpoint potential sampling value v ns (k), i.e. the midpoint potential error signal v nerr (k), which is expressed as follows:

[0110] v nerr (k) = v ns (k)-v ins (k) (Equation 17)

[0111] Step 5: Midpoint potential error signal v nerr(k) Perform loop calculation through PI control to generate the midpoint potential adjustment signal v nerr_out (k), v nerr_out (k) The expression is as follows:

[0112]

[0113] In formula 18, Δv nerr_out (k) represents the compensation value of the midpoint potential PI control algorithm to the midpoint potential regulation signal at the current moment, v nerr (k) represents the value of the midpoint potential error signal at the current moment, v nerr (k-1) represents the value of the midpoint potential error signal at the previous moment, v nerr_out (k) represents the value of the midpoint potential adjustment signal at the current moment, v nerr_out (k-1) represents the value of the midpoint potential adjustment signal at the previous moment. p_vn and K i_vn It represents the proportional coefficient and integral coefficient obtained by discretizing the midpoint potential PI controller.

[0114] Step 6: Calculation result of output voltage closed loop feedback v oerr_out1 (k) The calculation result of the midpoint potential closed loop feedback v nerr_out (k) Subtract to get the comparison value v compare1 (k), the calculation result of the output voltage closed-loop feedback v oerr_out1 (k) The calculation result of the midpoint potential closed loop feedback v nerr_out (k) Sum to get the comparison value v compare2 (k), which is expressed as follows:

[0115]

[0116] In formula 19, k1 is the proportional coefficient of the output voltage adjustment signal superimposed on the comparison value, and k2 is the proportional coefficient of the midpoint potential adjustment signal superimposed on the comparison value. If the natural voltage equalization characteristic of the converter is poor, the proportional coefficient of the midpoint potential adjustment signal is appropriately increased to ensure the control circuit's ability to adjust the midpoint potential imbalance.

[0117] Step 7: The first embodiment of the present invention uses different channels of the same timer to generate two PWM signals. The timer adopts the center-aligned counting mode, and the channel working mode selects the output comparison mode. For the channel generating the driving signal D1, the comparison value v is taken. compare1 With the current count value v cnt1 For comparison, the channel can be configured as PWM mode 1. In the up counting mode, if the count value v cnt1 Less than comparison value v compare1The channel outputs a high level, otherwise it outputs a low level. In the down counting mode, if the count value v cnt1 Higher than comparison value v compare1 For the channel that generates the drive signal D2, make the upper limit value of the counter equal to v compare2 Subtract and get the final comparison value v compare3 , and the current count value v cnt1 For comparison, the channel can be configured as PWM mode 2. In the up counting mode, if the count value v cnt1 Greater than the final comparison value v compare3 The channel outputs a high level, otherwise it outputs a low level. In the down counting mode, if the count value v cnt1 Less than the final comparison value v compare3 The channel outputs a low level, otherwise it outputs a high level. This process is equivalent to Figure 7 , that is, v compare1 and v compare2 The symmetrical triangular carrier v is staggered 180° cnt1 and v cnt2 The drive signals D1 and D2 that reflect both the midpoint potential error and the output voltage error are exchanged and obtained as the duty cycle outputs of the switch tubes Q1 and Q2 to adjust the charge and discharge amount of the upper and lower voltage-dividing capacitors, thereby achieving the midpoint potential balance and output voltage stabilization of the three-level Buck DC converter.

[0118] Example 2:

[0119] Figure 8 The structural diagram of the midpoint potential balance control system of the three-level Buck DC converter provided in this embodiment includes a power part, a sampling part and a digital control part. The power part and the sampling part are consistent with the first embodiment of the present invention. In the second embodiment of the present invention, the control part adopts the trailing edge alignment and the leading edge modulation scheme to realize the midpoint potential balance control. The digital control part of the second embodiment of the present invention includes the following steps:

[0120] Steps 1 to 5 are consistent with the digital control part of the first embodiment of the present invention, and will not be described in detail here. Please refer to steps 1 to 5 of the first embodiment;

[0121] Step 6: In the second embodiment of the present invention, the calculation result v of the output voltage closed-loop feedback is taken according to a certain ratio oerr_out1 (k) Get the comparison value v compare1 (k), the calculation result of the output voltage closed-loop feedback v oerr_out1 (k) The calculation result of the midpoint potential closed loop feedback v nerr_out (k) Sum the comparison value v according to a certain ratio compare2 (k), which is expressed as follows:

[0122]

[0123] Step 7: In the second embodiment of the present invention, the control part needs to use two timers, and the two timers can be configured in the down counting mode. The clock frequency and the upper limit of the count are consistent. When the count value v of the main timer Tim1 cnt1 When it drops to half of the upper limit of the count, the counter of slave timer Tim2 is reset, so that the phase difference between the trailing edges of drive signals D1 and D2 is fixed at 180°. The channel working mode selects the output comparison mode, which is configured as PWM mode 1. This process is equivalent to: Fig. 9 The driving signals D1 and D2 can simultaneously reflect the midpoint potential and the error of the output voltage relative to the reference value. By adjusting the driving signal, the charge and discharge amount of the upper and lower voltage divider capacitors can be changed, thereby achieving the midpoint potential balance and output voltage stabilization of the three-level Buck DC converter.

[0124] Through the above example analysis, it can be seen that the dual-edge modulation or leading-edge modulation digital control scheme involved in the present invention can realize the midpoint potential balance control of the three-level Buck DC converter, and has high control freedom, low design cost, strong scalability and portability, and can ensure output voltage stability while achieving midpoint potential balance, thereby achieving high efficiency, high power density and high reliability of the converter.

[0125] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A three-level Buck DC converter midpoint potential balance control system, characterized in that: The system includes a power part and a control part. The power part includes an input voltage source V in , upper voltage divider capacitor C in1 , lower voltage divider capacitor C in2 , a first switch tube Q1, a second switch tube Q2, a first diode D1, a second diode D2 and an output load resistor R out , output load resistance R out The voltage across the two ends is the output voltage V0, and the upper voltage divider capacitor C in1 And the lower voltage divider capacitor C in2 After being connected in series, they are connected in parallel to the input voltage source V in The first diode D1 and the second diode D2 are connected in series, the anode of the first diode D1 is connected to the cathode of the second diode D2, and the cathode of the first diode D1 is connected to the first switch tube Q1 and then to the voltage source V in The positive electrode of the second diode D2 is connected to the second switch tube Q2 and then to the voltage source V in The negative pole of the upper voltage divider capacitor C in1 And the lower voltage divider capacitor C in2 The midpoint N is connected to the midpoint of the first diode D1 and the second diode D2, and the lower voltage divider capacitor C in2 The voltage between the two ends is the midpoint potential V n The control part is connected to the first switch tube Q1 and the second switch tube Q2 respectively, and the edge of the driving signal of the first switch tube Q1 and / or the second switch tube Q2 is adjusted by the control part to adjust the midpoint potential V n balance control.

2. The three-level Buck DC converter midpoint potential balance control system according to claim 1, characterized in that: The power part also includes an output filter inductor L and an output filter capacitor C out , one end of the output filter inductor L is connected to the cathode of the first diode D1, and the other end of the output filter inductor L is connected to the output load resistor R out One end of the output filter capacitor C out Connect in parallel to the output load resistor R out both ends of .

3. The three-level Buck DC converter midpoint potential balance control system according to claim 1, characterized in that: The control part includes an output voltage stabilization control part, a midpoint potential balance control part, an output voltage PI controller, a midpoint potential PI controller, a first superposition module and a second superposition module, an output filter capacitor C out and the output load resistor R out The voltage at both ends is the output voltage. The output voltage stabilization control part is used to convert the output voltage sampling value v os and the output voltage reference value v ref After comparison, the output voltage error signal v is obtained oerr , the output voltage PI controller is used based on the output voltage error signal v oerr Generates output voltage regulation signal v oerr_out The midpoint potential balance control part is used to convert the input voltage sampling value v ins and midpoint potential sampling value v ns After comparison, the midpoint potential error signal v is obtained nerr The midpoint potential PI controller is used based on the midpoint potential error signal v nerr Generate midpoint potential adjustment signal v nerr_out The first superposition module is used to adjust the output voltage signal v oerr_out and midpoint potential adjustment signal v nerr_out The first comparison value v that reflects both the midpoint potential error and the output voltage error is obtained by superposition. compare1 The second superposition module is used to adjust the output voltage signal v oerr_out and midpoint potential adjustment signal v nerr_out The second comparison value v is obtained by superposition, which reflects both the midpoint potential error and the output voltage error. compare2 , the first comparison value v compare1 Used to modulate the edge of the first drive signal D1, the second comparison value v compare2 It is used to modulate the edge of the second drive signal D2. The first drive signal D1 is output as the duty cycle of the first switch tube Q1, and the second drive signal D2 is output as the duty cycle of the second switch tube Q2.

4. A method for controlling the midpoint potential balance of a three-level Buck DC converter, using the midpoint potential balance control system of a three-level Buck DC converter according to any one of claims 1 to 3, characterized in that: The method comprises: Set the voltage divider capacitor C in2 The voltage between the two ends is the midpoint potential V n The control part adjusts the edge of the driving signal of the first switch tube Q1 and / or the second switch tube Q2 to adjust the midpoint potential V n balance control.

5. The method for controlling the midpoint potential balance of a three-level Buck DC converter according to claim 4, characterized in that: The driving signal is a PWM signal.

6. The method for controlling the midpoint potential balance of a three-level Buck DC converter according to claim 5, characterized in that: The edge of the driving signal is regulated by leading edge modulation of a PWM signal.

7. The method for controlling the midpoint potential balance of a three-level Buck DC converter according to claim 6, characterized in that: The leading edge modulation comprises: When the voltage divider capacitor C in1 The voltage across the capacitor is lower than the lower voltage divider capacitor C in2 When the voltage at both ends is high, the leading edge of the driving signal of the second switch tube Q2 is advanced; when the upper voltage dividing capacitor C in1 The voltage across the capacitor is higher than the lower voltage divider capacitor C in2 When the voltage across both ends is , the leading edge of the driving signal of the second switch tube Q2 is delayed.

8. The method for controlling the midpoint potential balance of a three-level Buck DC converter according to claim 5, characterized in that: The edge of the driving signal is adjusted by double-edge modulation of the PWM signal.

9. The method for controlling the midpoint potential balance of a three-level Buck DC converter according to claim 8, characterized in that: The double-edge modulation comprises: When the voltage divider capacitor C in1 The voltage across the capacitor is lower than the lower voltage divider capacitor C in2 When the voltage at both ends is , the leading edge of the driving signal of the first switch tube Q1 and the trailing edge of the driving signal of the second switch tube Q2 are delayed, and the trailing edge of the driving signal of the first switch tube Q1 and the leading edge of the driving signal of the second switch tube Q2 are advanced, and at this time, the amount of delay and advance is equal; When the voltage divider capacitor C in1 The voltage across the capacitor is higher than the lower voltage divider capacitor C in2 When the voltage at both ends is , the trailing edge of the driving signal of the first switch tube Q1 and the leading edge of the driving signal of the second switch tube Q2 are delayed, and the leading edge of the driving signal of the first switch tube Q1 and the trailing edge of the driving signal of the second switch tube Q2 are advanced. At this time, the delay and advance amounts are equal.

10. The method for controlling the midpoint potential balance of a three-level Buck DC converter according to claim 4, characterized in that: The control part adjusts the edge of the driving signal of the first switch tube Q1 and / or the second switch tube Q2 to the midpoint potential V n Balance control, including: The output voltage stabilization control part converts the output voltage sampling value v os and the output voltage reference value v ref After comparison, the output voltage error signal v is obtained oerr , output voltage error signal v oerr The output voltage PI controller generates the output voltage regulation signal v oerr_out ; The midpoint potential balance control part inputs the voltage sampling value v ins and midpoint potential sampling value v ns After comparison, the midpoint potential error signal v is obtained nerr , midpoint potential error signal v nerr The midpoint potential PI controller generates the midpoint potential adjustment signal v nerr_out ; The output voltage regulation signal v in the output voltage closed-loop feedback calculation result oerr_out and the midpoint potential closed-loop feedback calculation result of the midpoint potential adjustment signal v nerr_out The first comparison value v that reflects both the midpoint potential error and the output voltage error is obtained by superposition. compare1 and the second comparison value v compare2 , the first comparison value v compare1 Used to modulate the edge of the first drive signal D1, the second comparison value v compare2 It is used to modulate the edge of the second drive signal D2. The first drive signal D1 is used as the duty cycle output of the first switch tube Q1, and the second drive signal D2 is used as the duty cycle output of the second switch tube Q2, so as to achieve the midpoint potential balance and output voltage stabilization of the three-level Buck DC converter.

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