Reading circuit with low noise and high dynamic range in small pixel and infrared focal plane array

Abstract

The invention provides a low-noise and high-dynamic-range reading circuit in a small pixel and an infrared focal plane array. The reading circuit comprises a CTIA circuit, a CDS circuit, a column-level transmission circuit and a time sequence control circuit. The CTIA circuit comprises a photoelectric detector D1, a single-ended cascode amplifier AMP, a reset switch RST, a layout extraction parasitic capacitor C0, a first-gear capacitor C1 and a selective switch GS0, a second-gear capacitor C2 and a selective switch GS1, a third-gear large capacitor C3 and a selective switch GS2 / GS2, and an AMP bandwidth limiting capacitor C4. The CTIA circuit is configured to select the integrating capacitor combination of the corresponding output channel according to the size of the light current; the time sequence control circuit is used for generating time sequence control signals needed by circuit work and comprises an output channel selection switch. According to the invention, different integrating capacitors can be switched for integration according to light intensity, and fA-level injection current can be processed; the output result has ultrahigh linearity; and meanwhile, CTIA and CDS structures are realized in the pixels, the CTIA noise is lower, and the dynamic range is higher.

Description

Technical Field

[0001] The invention relates to the technical field of infrared focal plane arrays, and in particular to a readout circuit with low noise and high dynamic range in a small pixel and an infrared focal plane array. Background Art

[0002] Infrared focal plane array (FPA) is widely used in many fields such as security monitoring, medical diagnosis and industrial detection. Infrared focal plane array consists of infrared sensor array and readout circuit. The detector is mainly used to convert optical signal to electrical signal; the readout circuit further processes the converted electrical signal, including integration, sampling, holding, amplification and selective readout, which plays a vital role in the working performance of the entire infrared focal plane array.

[0003] With the continuous development of image sensor technology, the reduction of pixel size has improved the spatial resolution of the focal plane array, improved image quality and system recognition capabilities, and helped to reduce the size and weight of components. However, the reduction of pixel size requires the pixel unit of the readout circuit to be reduced accordingly, requiring a low-noise, high-dynamic range readout circuit.

[0004] In the related art, on the one hand, when a simple direct injection (DI) structure is used in a small pixel to control the pixel area, although it can adapt well to the size limitation, the processing effect of weak current is not ideal, resulting in a decrease in the signal-to-noise ratio. On the other hand, although the capacitive transconductance integrator amplifier (CTIA) readout circuit can provide better noise suppression and high gain characteristics, it is difficult to be applied to the small pixel design due to the large occupied area required by its own amplifier, or even if it is used, it will affect the overall performance due to problems such as large noise and insufficient dynamic range. In addition, the correlated double sampling (CDS) circuit is a noise suppression method widely used in the readout circuit. The reset noise of the circuit can be effectively eliminated by sampling and subtracting the reset voltage and the final voltage of the integration. However, due to the need for multiple sampling and holding operations, the design area of ​​the CDS circuit is usually large; in order to reduce the design area, a column-level CDS solution is usually adopted, but the column-level CDS design timing is complex and it is difficult to implement multiple data readout modes. The CDS in the pixel is strictly limited by the overall area, making it difficult to achieve high-performance noise suppression.

[0005] In the design process of focal plane circuits, existing structures are always unable to take into account small pixels, low noise and high dynamic range, which limits the image quality in certain key application scenarios. Summary of the invention

[0006] The present invention provides a readout circuit with low noise and high dynamic range in a small pixel and an infrared focal plane array, which solves the problem of how to achieve both low noise and high dynamic range in an infrared image sensor under the condition of small pixel in the related art.

[0007] In order to achieve the above objectives, this application adopts the following technical solutions:

[0008] In a first aspect, a low-noise and high-dynamic-range readout circuit in a small pixel is provided, and for the pixel and column-level transmission circuit in the readout circuit array, the circuit includes: a CTIA circuit, a CDS circuit, a column-level transmission circuit, and a timing control circuit;

[0009] The CTIA circuit includes: a photodetector D1, a single-ended common-source common-gate amplifier AMP, a reset switch RST, a layout extraction parasitic capacitor C0, a first-level capacitor C1 and a selection switch GS0, a second-level capacitor C2 and a selection switch GS1, a third-level large capacitor C3 and a selection switch GS2 / GS2_, and an AMP bandwidth limiting capacitor C4;

[0010] The photodetector D1 has a P-pole connected to the substrate voltage SUBPV and an N-pole connected to the input stage of the single-ended cascode amplifier AMP; the input stage of the single-ended cascode amplifier AMP is also connected to one end of the reset switch RST, the upper plate of the layout extraction parasitic capacitor C0, one end of the selection switch GS0, one end of the selection switch GS1, and one end of the selection switch GS2; the other end of the selection switch GS0 is connected to the upper plate of the first-gear capacitor C1; the other end of the selection switch GS1 is connected to the upper plate of the second-gear capacitor C2; the other end of the selection switch GS2 is connected to the upper plate of the third-gear capacitor C3; the output stage of the single-ended cascode amplifier AMP is connected to the other end of the reset switch RST, the lower plate of the layout extraction parasitic capacitor C0, the lower plate of the first-gear capacitor C1, the lower plate of the second-gear capacitor C2, the lower plate of the third-gear capacitor C3, and the lower plate of the bandwidth limiting capacitor C4, and is connected to the CDS circuit as the output port of the CTIA circuit;

[0011] The CTIA circuit is configured to select an integrating capacitor combination corresponding to an output channel according to the magnitude of the photocurrent;

[0012] The timing control circuit is used to generate a timing control signal required for circuit operation, and includes an output channel selection switch.

[0013] In a first possible implementation manner of the first aspect, the CDS circuit includes: a PMOS clamp capacitor Q4, a clamp switch Clamp, a source follower, a sampling switch SH, and an NMOS sampling capacitor Q7;

[0014] The gate of the PMOS clamp capacitor Q4 is connected to the output stage of the CTIA circuit, and its source, drain and substrate are connected to one end of the clamp switch Clamp and input to the input stage of the source follower; the source follower is composed of a MOS transistor Q5 and a MOS transistor Q6, the output stage of the source follower is connected to one end of the sampling switch SH, and the other end of the sampling switch is connected to the gate of the NMOS sampling capacitor Q7 and connected to the column-level transmission circuit as the output port of the CDS circuit.

[0015] In a second possible implementation of the first aspect, the column-level transmission circuit includes: an NMOS input tube Q8 and a column-level selection switch tube Q9;

[0016] The column-level selection switch tube Q9 is used as a row selection control switch and is controlled by a digitally generated RS signal.

[0017] In a third possible implementation of the first aspect, the reset switch RST is controlled by an external input signal RST; the selection switches GS0, GS1, GS2\GS2_ are controlled by the column-level gain control signals GS0, GS1 and a pair of opposite signals GS2\GS2_ generated by the digital part. Take control.

[0018] In a fourth possible implementation manner of the first aspect, selecting the integration capacitor combination corresponding to the output channel according to the size of the photocurrent specifically includes:

[0019] If the photocurrent is estimated to be between 0 and 1 pA, the output channel of the integrating capacitor C0 is selected, and GS0, GS1, and GS2 are at a low level;

[0020] The photocurrent is estimated to be 1-60pA, and the output channel of the integral capacitor C0+C1 is selected, and the corresponding signal GS0 is high level, and GS1 and GS2 are low level;

[0021] The photocurrent is estimated to be 60-200 pA, and the output channel of the integral capacitor C0+C1+C2 is selected, corresponding to the signals GS0 and GS1 being high level and GS2 being low level;

[0022] The photocurrent is estimated to be more than 200 pA, and the output channel of the integrating capacitor C0+C1+C2+C3 is selected, and the corresponding signals GS0, GS1, and GS2 are all high level.

[0023] Based on the fourth possible implementation of the first aspect, in a fifth possible implementation of the first aspect, switches GS0 and GS1 are selected to control the low-level integral capacitor, and switch GS2 is selected to control the high-level integral capacitor;

[0024] When a low-level integrating capacitor is selected, the three-level large capacitor C3 is connected in parallel with the AMP bandwidth limiting capacitor C4 as the load capacitor of the single-ended common-source common-gate amplifier AMP to limit the bandwidth and thus suppress the single-ended operational amplifier noise; when a high-level integrating capacitor is selected, the three-level large capacitor C3 is used as the integrating capacitor, and only the AMP bandwidth limiting capacitor C4 is used as the load capacitor to suppress noise.

[0025] Based on the first possible implementation of the first aspect, in a sixth possible implementation of the first aspect, during the reset phase of the CTIA circuit, the PMOS capacitor is controlled by a Clamp signal to store charge, thereby achieving voltage clamping. After clamping, the source follower increases the clamp voltage by a PMOS tube threshold voltage and transmits it to the NMOS sampling capacitor.

[0026] Based on the second possible implementation manner of the first aspect, in a sixth possible implementation manner of the first aspect, the column-level transmission circuit supports two working modes: integration before readout and integration while readout.

[0027] Based on any possible implementation of the first aspect, in a seventh possible implementation of the first aspect, the readout circuit also includes an output stage, and the output stage is implemented by a two-stage operational amplifier, the first stage is a folded common-source common-gate amplifier, and the second stage is a Hogvorst output stage, forming a class AB output operational amplifier structure.

[0028] In a second aspect, a small pixel infrared focal plane array is provided, comprising a low noise and high dynamic range readout circuit within the small pixel as described in the first aspect.

[0029] The circuit structure of this application can be simultaneously implemented in a small pixel of 15μm×15μm by improving the CTIA and CDS circuits. Different integral capacitors can be switched for integration according to the light intensity, and the lowest injection current can be processed at the fA level. The CTIA op amp uses a high-gain single-ended op amp, and the output result has ultra-high linearity. Within the voltage output range, the linearity can reach 99.94%. At the same time, the CTIA and CDS structures are implemented in the pixel, which has lower noise and higher dynamic range than the CTIA of the same size. The separation of the clamping capacitor and the sampling capacitor can take into account both ITR and IWR working modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of the overall circuit architecture of a low-noise and high dynamic range readout circuit in a small pixel provided in an embodiment of the present application;

[0031] Figure 2 A schematic diagram of a circuit architecture for implementing a CTIA and CDS structure in a small pixel provided in an embodiment of the present application;

[0032] Figure 3 A schematic diagram of circuit operation timing requirements provided in an embodiment of the present application;

[0033] Figure 4 A small pixel circuit operation flow chart provided in an embodiment of the present application;

[0034] Figure 5 An equivalent circuit diagram of a CTIA reset in a small capacitance position and a large capacitance position provided in an embodiment of the present application;

[0035] Figure 6 Another integral equivalent circuit diagram of a CTIA in a small capacitance position and a large capacitance position provided in an embodiment of the present application;

[0036] Figure 7 A functional simulation diagram of a CTIA provided in an embodiment of the present application;

[0037] Figure 8 An internal timing diagram of a pixel provided in an embodiment of the present application;

[0038] Fig. 9 A clamping function simulation diagram provided in an embodiment of the present application;

[0039] Fig.10 A capacitance variation curve diagram of a PMOS capacitor, an NMOS capacitor and a MIM capacitor provided in an embodiment of the present application;

[0040] Fig.11 A loop gain and phase gain diagram of an output stage operational amplifier provided in an embodiment of the present application;

[0041] Fig.12 A linearity simulation and fitting curve diagram provided in an embodiment of the present application; DETAILED DESCRIPTION

[0042] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined purpose, the technical solutions in the embodiments of the present application are clearly described. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0043] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0044] The description of the method flow in the specification of the present application and the steps of the flowchart in the drawings of the present specification do not have to be strictly executed according to the step numbers, and the method steps can be executed in a different order. Moreover, some steps can be omitted, multiple steps can be combined into one step, and / or one step can be decomposed into multiple steps.

[0045] The following is a detailed description of the small pixel low noise and high dynamic range readout circuit and infrared focal plane array provided by the embodiments of the present application in conjunction with the accompanying drawings and preferred embodiments.

[0046] First, the application scenario of the low noise and high dynamic range readout circuit in a small pixel of the embodiment of the present application is described in detail.

[0047] For infrared focal plane detectors, additional electronic noise (such as thermal noise and shot noise from the readout circuit itself) can easily mask the signal. In order to ensure image quality, the lower the noise level of the readout circuit, the clearer the image with a high signal-to-noise ratio can be provided.

[0048] The current of the signal is greatly affected by the intensity of the light source. For different background intensities, the sudden change of the photocurrent may damage the circuit function and make imaging impossible. Therefore, a high dynamic range current processing capability is required.

[0049] As the pixel size decreases, the number of photons received by each pixel decreases, so the resulting photocurrent signal becomes weaker. In this case, any additional electronic noise will be relatively more significant and easily mask the weak signal. At the same time, a readout circuit with a high dynamic range can accurately measure these current changes over a wide range. This is critical to providing clear, high signal-to-noise ratio images while maintaining image details and correctly reflecting the brightness contrast of the real world.

[0050] With regard to the technical difficulties of high noise and low dynamic range in small pixels, the existing solutions known to the inventors are often difficult to simultaneously meet the requirements of small pixel size, low noise level and high dynamic range. Therefore, the present application provides a technical solution for realizing a structure combining CTIA and CDS in a small pixel (15μm×15μm), which effectively solves the technical difficulties of high noise and low dynamic range in small pixels, and realizes the technical effect of infrared image sensors with both low noise and high dynamic range under small pixel conditions.

[0051] See also Figure 1 , the embodiment of the present application provides a readout circuit with low noise and high dynamic range in a small pixel, such as Figure 1 As shown, the readout circuit of the embodiment of the present application, for the pixel and column-level transmission circuit in the readout circuit array, includes:

[0052] CTIA circuit, CDS circuit, column-level transmission circuit, and timing control circuit;

[0053] The CTIA circuit includes: photodetector D1, single-ended common-source common-gate amplifier AMP, reset switch RST, layout extraction parasitic capacitor C0, first-level capacitor C1 and selection switch GS0, second-level capacitor C2 and selection switch GS1, third-level large capacitor C3 and selection switch GS2 / GS2_, and AMP bandwidth limiting capacitor C4.

[0054] The photodetector D1 is used to convert the incident light signal into an electrical signal, and its P pole is connected to the substrate voltage SUBPV, and its N pole is connected to the input stage of the single-ended cascode amplifier AMP. The input stage of the single-ended cascode amplifier AMP is also connected to one end of the reset switch RST, the upper plate of the layout extraction parasitic capacitor C0, one end of the selection switch GS0, one end of the selection switch GS1, and one end of the selection switch GS2; the other end of the selection switch GS0 is connected to the upper plate of the first-stage capacitor C1; the other end of the selection switch GS1 is connected to the upper plate of the second-stage capacitor C2; the other end of the selection switch GS2 is connected to the upper plate of the third-stage capacitor C3; the output stage of the single-ended cascode amplifier AMP is connected to the other end of the reset switch RST, the lower plate of the layout extraction parasitic capacitor C0, the lower plate of the first-stage capacitor C1, the lower plate of the second-stage capacitor C2, the lower plate of the third-stage capacitor C3, and the lower plate of the bandwidth limiting capacitor C4, and is connected to the CDS circuit as the output port of the CTIA circuit.

[0055] The reset switch RST is controlled by the external input signal RST. The selection switches GS0, GS1, GS2\GS2_are controlled by the column-level gain control signals GS0, GS1 and a pair of opposite signals GS2\ During operation, the CTIA circuit is configured to select an integral capacitor combination of the corresponding output channel according to the size of the photocurrent, that is, different capacitor combinations are configured as needed to perform gear control.

[0056] The CDS circuit includes: a PMOS clamp capacitor Q4, a clamp switch Clamp, a source follower, a sampling switch SH and an NMOS sampling capacitor Q7.

[0057] Among them, the gate of the PMOS clamp capacitor Q4 is connected to the output stage of the CTIA circuit, and its source, drain and substrate are connected to one end of the clamp switch Clamp and input to the input stage of the source follower; the source follower is composed of MOS transistors Q5 and Q6, and the output stage of the source follower is connected to one end of the sampling switch SH, and the other end of the sampling switch is connected to the gate of the NMOS sampling capacitor Q7 and connected to the column-level transmission circuit as the output port of the CDS circuit.

[0058] The clamp switch Clamp is controlled by the digitally generated Clamp signal; the NMOS sampling capacitor Q7 is controlled by a pair of opposite signals SH generated by the digital circuit. Take control.

[0059] The column-level transmission circuit includes: NMOS input tube Q8 and column-level selection switch tube Q9, which are the connection parts of the column-level operational amplifier. The column-level selection switch tube Q9 is used as a row selection control switch and is controlled by the digitally generated RS signal. The output stage of the CDS circuit is connected to the gate of the NMOS tube Q8, and the drain of the NMOS tube Q8 and the source of the column-level selection switch tube Q9 are connected to the subsequent circuit as the column-level transmission circuit output.

[0060] The timing control circuit is used to generate the timing control signals required for the circuit operation, including integration, reset, sampling, clamping, row selection, column selection and output channel selection switch, etc. The circuit supports the integration before reading (ITR) and integration while reading (IWR) modes. The circuit power consumption control, window control, output channel selection, row gain selection, etc. are written in sequence by the serial port module through the single pin SERDAT.

[0061] See also Figure 2 , the overall digital timing is as follows Figure 2 As shown, the rising edge of MC (main clock signal) is aligned with the clock edge of INT (integral control signal), the high level of INT is the integration time, and the low level is the reset time.

[0062] In the specific implementation process, the workflow of the CTIA circuit is as follows Figure 3-4 As shown:

[0063] The first step is that the photodetector D1 generates photocurrent through the photoelectric effect in the application scenario, and the appropriate integral capacitor gear is selected according to the estimated photocurrent of the application scenario. If the photocurrent is estimated to be 0-1pA, the output channel of the integral capacitor C0 is selected, and GS0, GS1, and GS2 are low levels; if the photocurrent is estimated to be 1-60pA, the output channel of the integral capacitor C0+C1 is selected, and the corresponding signal GS0 is high, and GS1 and GS2 are low levels; if the photocurrent is estimated to be 60-200pA, the output channel of the integral capacitor C0+C1+C2 is selected, and the corresponding signals GS0 and GS1 are high, and GS2 is low.

[0064] When the photocurrent is estimated to exceed 200pA, the output channel of the integral capacitor C0+C1+C2+C3 is selected, and the corresponding signals GS0, GS1, and GS2 are all high level. When the low-level integral capacitor is selected, the three-level large capacitor C3 is connected in parallel with the AMP bandwidth limiting capacitor C4 as the load capacitor of the single-ended common source and common gate amplifier AMP to limit the bandwidth and thus suppress the single-ended op amp noise; when the high-level integral capacitor is selected, the three-level large capacitor C3 is used as the integral capacitor, and only the AMP bandwidth limiting capacitor C4 is used as the load capacitor to suppress noise. The remaining control signals are as follows: Figure 8 shown.

[0065] The second step is to carry out the integration process. Before the current integration begins, the level of the integration capacitor is reset. At this time, the RST signal is high level. The equivalent circuit diagram of the CTIA circuit is as follows: Figure 5 As shown, the reset level is determined by the feedback of the cascode amplifier itself. When the cascode amplifier device is selected, the integral reference voltage is determined by the amplifier bias current and has nothing to do with the integral current. The specific functional simulation is as follows Figure 7 shown.

[0066] Furthermore, the CTIA circuit enters the integration mode, at which time the RST signal changes from high level to low level. The equivalent circuit diagram is as follows: Figure 6 As shown, it performs the integrator function, integrating the input current to output the voltage. Figure 7 Voltage rising stage. Compared with the traditional CTIA op amp, this single-ended op amp CTIA circuit has a simple structure and occupies a small area, and realizes the structure of small pixel CTIA and CDS. The CTIA op amp uses a high-gain single-ended op amp, and the output result has ultra-high linearity. Within the voltage output range, the linearity can reach 99.94%.

[0067] For the CDS circuit, in the CTIA reset phase, the Clamp signal is high level, and the charge of the PMOS capacitor can be expressed as:

[0068] Q1=C Q4 *(0-V rst )

[0069] Among them, C Q4 is the capacitance of the PMOS capacitor, V rst Reset level for the CTIA circuit.

[0070] Furthermore, 2μs after the RST signal changes from high level to low level, the Clamp changes from high level to low level. At this time, the charge of the PMOS capacitor is:

[0071] Q2=C Q4 *(V clamp -V int -V rst )

[0072] Among them, V clamp is the source-drain voltage of clamp capacitor Q4, V int is the net integrated voltage. In the whole process, the charge of the PMOS capacitor is conserved, Q1 = Q2, and V clamp =V int , the clamping function simulation is as follows Fig. 9 shown.

[0073] After voltage clamping, the source follower raises the clamp voltage by a PMOS threshold voltage, corresponding to a high level SH signal, and transmits the voltage to the NMOS sampling capacitor. The source follower acts as a voltage buffer and raises the clamp voltage by a threshold voltage to facilitate subsequent signal transmission at the column level.

[0074] The selection of PMOS capacitor Q4 and NMOS capacitor Q7 in this application is done through special configuration. Fig.10 This is the capacitance change curve of PMOS capacitor, NMOS capacitor and MIM capacitor under the process used. In the small pixel design, MIM capacitor is mainly used to design the integration capacitor with high precision requirements. The clamping capacitor can be selected from NMOS capacitor and PMOS capacitor. The grounding of NMOS capacitor substrate will cause corresponding charge leakage, so the clamping capacitor selects PMOS capacitor. The sampling capacitor is also limited by the small pixel area, so MOS capacitor is selected. Under the corresponding transmission voltage, the NMOS capacitor value is more stable, and the same size has a larger corresponding capacitance value, so the sampling capacitor selects NMOS capacitor.

[0075] The CDS circuit implementation scheme of this application realizes the capacitor design requirements of each part, and can stack MIM capacitors and MOS capacitors to improve space utilization. The introduction of CDS reduces the noise interference caused by transient switching and reset of switches. In addition, the introduction of CTIA realizes the low-noise design of weak current integration. Compared with the traditional CTIA circuit, the dynamic range has been greatly improved.

[0076] The column-level transmission circuit is part of the column-level transmission amplifier. When the RS level is high, the column level is turned on and the sampling capacitor voltage is transmitted to the column-level bus for final output.

[0077] In some possible implementations, the readout circuit further includes an output stage, which is implemented by a two-stage operational amplifier, the first stage being a folded cascode amplifier, and the second stage being a Hogvorst output stage, which constitutes a class AB output operational amplifier. The fastest analog data transmission can be 20MHz, and the loop gain and phase curves of the output stage are as follows: Figure 11-12 shown.

[0078] Based on the above technical solution, the circuit structure of this application can be simultaneously implemented in a small pixel of 15μm×15μm by improving the CTIA and CDS circuits. Different integral capacitors can be switched for integration according to the light intensity, and the lowest injection current can be processed at the fA level. The CTIA op amp uses a high-gain single-ended op amp, and the output result has ultra-high linearity. Within the voltage output range, the linearity can reach 99.94%. At the same time, the CTIA and CDS structures are implemented in the pixel, which has lower noise and higher dynamic range than the CTIA of the same size. The separation of the clamping capacitor and the sampling capacitor can take into account both ITR and IWR working modes.

[0079] Specifically, the present application controls the integration capacitors C0, C1, C2, and C3 of different sizes by selecting switches GS0, GS1, and GS2, and can automatically adjust the integration capacitor according to the expected photocurrent size, thereby achieving a high dynamic range. This variable gain structure allows the system to adapt to different lighting conditions. Use a large capacitor C3 and an AMP bandwidth limiting capacitor C4 as a load capacitor when selecting a low-range integration capacitor to limit the bandwidth and suppress the noise of the single-ended op amp, thereby maintaining a low noise level when processing weak signals. The reset switch RST is used to reset the integration capacitor before each integration, and the PMOS clamping capacitor Q4 and the clamping switch Clamp in the CDS circuit are used to eliminate reset noise, thereby reducing the nonlinear and fixed pattern noise caused by reset. The single-ended common source and common gate amplifier AMP simplifies the design of CTIA, reduces the occupied area, is suitable for applications with small pixel sizes, and still maintains good linearity. The selection of PMOS capacitor Q4 and NMOS capacitor Q7 is based on their characteristics under specific processes, ensuring the accuracy of clamping and sampling and the effective use of space. The column-level transmission circuit design takes space efficiency into consideration while providing sufficient drive capability to support high-speed data transmission. The two-stage op amp design of the output stage ensures stable voltage following characteristics and high output slew rate.

[0080] The embodiment of the present application also provides a small pixel infrared focal plane array, including the above-mentioned small pixel low noise and high dynamic range readout circuit. The beneficial effects of the readout circuit are the same as those of the above-mentioned readout circuit, which will not be described in detail here.

[0081] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0082] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A low noise and high dynamic range readout circuit in a small pixel, characterized in that: The pixel and column-level transmission circuit in the readout circuit array includes: a CTIA circuit, a CDS circuit, a column-level transmission circuit and a timing control circuit; The CTIA circuit includes: a photodetector D1, a single-ended common-source common-gate amplifier AMP, a reset switch RST, a layout extraction parasitic capacitor C0, a first-level capacitor C1 and a selection switch GS0, a second-level capacitor C2 and a selection switch GS1, a third-level large capacitor C3 and a selection switch GS2 / GS2_, and an AMP bandwidth limiting capacitor C4; The photodetector D1 has a P-pole connected to the substrate voltage SUBPV and an N-pole connected to the input stage of the single-ended cascode amplifier AMP; the input stage of the single-ended cascode amplifier AMP is also connected to one end of the reset switch RST, the upper plate of the layout extraction parasitic capacitor C0, one end of the selection switch GS0, one end of the selection switch GS1, and one end of the selection switch GS2; the other end of the selection switch GS0 is connected to the upper plate of the first-gear capacitor C1; the other end of the selection switch GS1 is connected to the upper plate of the second-gear capacitor C2; the other end of the selection switch GS2 is connected to the upper plate of the third-gear capacitor C3; the output stage of the single-ended cascode amplifier AMP is connected to the other end of the reset switch RST, the lower plate of the layout extraction parasitic capacitor C0, the lower plate of the first-gear capacitor C1, the lower plate of the second-gear capacitor C2, the lower plate of the third-gear capacitor C3, and the lower plate of the bandwidth limiting capacitor C4, and is connected to the CDS circuit as the output port of the CTIA circuit; The CTIA circuit is configured to select an integrating capacitor combination corresponding to an output channel according to the magnitude of the photocurrent; The timing control circuit is used to generate a timing control signal required for circuit operation, and includes an output channel selection switch.

2. The small pixel low noise and high dynamic range readout circuit according to claim 1, characterized in that: The CDS circuit includes: a PMOS clamp capacitor Q4, a clamp switch Clamp, a source follower, a sampling switch SH and an NMOS sampling capacitor Q7; The gate of the PMOS clamp capacitor Q4 is connected to the output stage of the CTIA circuit, and its source, drain and substrate are connected to one end of the clamp switch Clamp and input to the input stage of the source follower; the source follower is composed of a MOS transistor Q5 and a MOS transistor Q6, the output stage of the source follower is connected to one end of the sampling switch SH, and the other end of the sampling switch is connected to the gate of the NMOS sampling capacitor Q7 and connected to the column-level transmission circuit as the output port of the CDS circuit.

3. The low noise and high dynamic range readout circuit in a small pixel according to claim 1, characterized in that: The column-level transmission circuit includes: an NMOS input tube Q8 and a column-level selection switch tube Q9; The column-level selection switch tube Q9 is used as a row selection control switch and is controlled by a digitally generated RS signal.

4. The small pixel low noise and high dynamic range readout circuit according to claim 1, characterized in that: The reset switch RST is controlled by the external input signal RST; the selection switches GS0, GS1, GS2\GS2_ are controlled by the column-level gain control signals GS0, GS1 and a pair of opposite signals generated by the digital part. Take control.

5. The small pixel low noise and high dynamic range readout circuit according to claim 1, characterized in that: The step of selecting the integration capacitor combination corresponding to the output channel according to the size of the photocurrent specifically includes: If the photocurrent is estimated to be between 0 and 1 pA, the output channel of the integrating capacitor C0 is selected, and GS0, GS1, and GS2 are at a low level; The photocurrent is estimated to be 1-60pA, and the output channel of the integral capacitor C0+C1 is selected, and the corresponding signal GS0 is high level, and GS1 and GS2 are low level; The photocurrent is estimated to be 60-200 pA, and the output channel of the integral capacitor C0+C1+C2 is selected, corresponding to the signals GS0 and GS1 being high level and GS2 being low level; The photocurrent is estimated to be more than 200 pA, and the output channel of the integrating capacitor C0+C1+C2+C3 is selected, and the corresponding signals GS0, GS1, and GS2 are all high level.

6. The small pixel low noise and high dynamic range readout circuit according to claim 5, characterized in that: Select switches GS0 and GS1 to control the low-level integrating capacitor, and select switch GS2 to control the high-level integrating capacitor; When a low-level integrating capacitor is selected, the three-level large capacitor C3 is connected in parallel with the AMP bandwidth limiting capacitor C4 as the load capacitor of the single-ended common-source common-gate amplifier AMP to limit the bandwidth and thus suppress the single-ended operational amplifier noise; when a high-level integrating capacitor is selected, the three-level large capacitor C3 is used as the integrating capacitor, and only the AMP bandwidth limiting capacitor C4 is used as the load capacitor to suppress noise.

7. The small pixel low noise and high dynamic range readout circuit according to claim 2, characterized in that: In the reset phase of the CTIA circuit, the PMOS capacitor is controlled by the Clamp signal to store charge, thereby realizing voltage clamping. After clamping, the source follower increases the clamp voltage by a PMOS tube threshold voltage and transmits it to the NMOS sampling capacitor.

8. The small pixel low noise and high dynamic range readout circuit according to claim 3, characterized in that: The column-level transmission circuit supports two working modes: integration before reading out and integration while reading out.

9. The small pixel low noise and high dynamic range readout circuit according to any one of claims 1 to 7, characterized in that: The readout circuit also includes an output stage, which is implemented by a two-stage operational amplifier, wherein the first stage is a folded common-source common-gate amplifier and the second stage is a Hogvorst output stage, forming a class AB output operational amplifier structure.

10. A small pixel infrared focal plane array, characterized in that: It comprises a low noise and high dynamic range readout circuit in a small pixel as described in any one of claims 1 to 8.

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