Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate; the word line structures are located on the substrate and arranged at intervals in the first direction, and each word line structure comprises a plurality of gate structures which are sequentially arranged at intervals in the third direction; the plurality of active column structures are arranged on the outer wall of each gate structure; at least one end of the active column structure along the second direction is provided with a groove with an opening facing the second direction; part of the active column structure surrounding the gate structure forms a channel structure, and part of the active column structure which is located at two sides of the channel structure along the second direction and is adjacent to the groove forms a source and a drain; the isolation structure is located on the inner wall, adjacent to the gate structure, in the groove; the first direction and the second direction intersect and are located in the plane where the substrate is located; the third direction intersects with the plane where the substrate is located.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor structure and a method for forming the same. Background Art

[0002] At present, in order to achieve the miniaturization of semiconductor structure size, a channel-all-around (CAA) structure is usually used as the channel structure of an indium gallium zinc oxide (IGZO) transistor. However, in the CAA structure based on IGZO devices, the distance between the gate structure and the source and drain is relatively close, which makes it easy for gate-induced drain leakage (GIDL) to occur between the gate structure and the source and drain. Summary of the invention

[0003] In view of this, an embodiment of the present disclosure provides a semiconductor structure and a method for forming the same.

[0004] In a first aspect, an embodiment of the present disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0005] substrate;

[0006] word line structures arranged at intervals along a first direction on the substrate, each of the word line structures comprising a plurality of gate structures sequentially arranged at intervals along a third direction;

[0007] A plurality of active column structures are arranged on the outer wall of each gate structure; at least one end of the active column structure along the second direction has a groove opening toward the second direction; a portion of the active column structure surrounding the gate structure constitutes a channel structure, and a portion of the active column structure located on both sides of the channel structure along the second direction and adjacent to the groove constitutes a source and a drain;

[0008] an isolation structure, located in the trench adjacent to an inner wall of the gate structure;

[0009] The first direction intersects with the second direction and is located in the plane where the substrate is located; the third direction intersects with the plane where the substrate is located.

[0010] In some embodiments, the trench includes a first trench and a second trench respectively located at two ends of the active pillar structure along the second direction;

[0011] The isolation structure comprises: a first isolation structure and a second isolation structure;

[0012] The first isolation structure is located in the first trench adjacent to an inner wall of the gate structure, and the second isolation structure is located in the second trench adjacent to an inner wall of the gate structure.

[0013] In some embodiments, the sidewalls of the word line structure along the cross-section of the third direction are sawtooth-shaped, and the word line structure includes gate structures and recessed portions alternately arranged in sequence along the third direction, the size of the gate structure along the second direction is larger than the size of the recessed portion along the second direction, and the size of the gate structure along the first direction is larger than the size of the recessed portion along the first direction.

[0014] In some embodiments, the source and drain include a first source and drain and a second source and drain located at two ends of the active pillar structure along the second direction;

[0015] The portion of the active pillar structure adjacent to the first trench constitutes the first source and drain, and the portion of the active pillar structure adjacent to the second trench constitutes the second source and drain.

[0016] In some embodiments, further comprising: a bit line and a capacitor structure;

[0017] The bit line is connected to the first source and drain, and is embedded in the first trench and connected to the first isolation structure;

[0018] The capacitor structure is connected to the second source and drain, and is embedded in the second trench and connected to the second isolation structure.

[0019] In some embodiments, further comprising: a spacer layer;

[0020] The spacer layer is located between the plurality of bit lines arranged along the third direction, between the plurality of capacitor structures arranged along the third direction, and between the plurality of active pillar structures arranged along the third direction.

[0021] In some embodiments, the bit lines extend along the first direction, and a row of the bit lines arranged along the first direction are connected to each other;

[0022] A plurality of bit lines arranged along the third direction form a step structure.

[0023] In a second aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, the method comprising:

[0024] A substrate is provided, on which a stacking structure is formed; the projection of the stacking structure on the substrate is a comb-tooth shape; the stacking structure includes a first area and a second area arranged along a second direction; the second area includes a plurality of sub-areas arranged at intervals along the first direction;

[0025] forming a word line structure extending along a third direction and penetrating the sub-region, each of the word line structures comprising a plurality of gate structures sequentially spaced apart along the third direction;

[0026] A plurality of active pillar structures are formed around the gate structure and are arranged at intervals; at least one end of the active pillar structure along the second direction has a groove opening toward the second direction; a portion of the active pillar structure surrounding the gate structure constitutes a channel structure, and a portion of the active pillar structure located on both sides of the channel structure along the second direction and adjacent to the groove constitutes a source and a drain;

[0027] forming an isolation structure in the trench adjacent to an inner wall of the gate structure;

[0028] The first direction intersects with the second direction and is parallel to the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.

[0029] In some embodiments, the stacked structure includes a spacer layer, a first sacrificial layer, a second sacrificial layer, and the first sacrificial layer that are cyclically and alternately arranged along the third direction; and forming a word line structure extending through the sub-region along the third direction includes:

[0030] Etching the sub-region to form a third groove extending along the third direction; the third groove exposes the bottommost spacer layer;

[0031] forming a first initial active pillar structure on a portion of the inner wall of the third trench; the first initial active pillar structure is partially or completely embedded in the first sacrificial layer;

[0032] The word line structure is formed in the third trench having the first preliminary active pillar structure.

[0033] In some embodiments, forming a plurality of active pillar structures surrounding the gate structure and arranged at intervals includes:

[0034] removing a portion of the first initial active pillar structure extending in the first direction into between the second sacrificial layer and the spacer layer to form the active pillar structure;

[0035] Wherein, the remaining portion of the first initial active pillar structure embedded between the second sacrificial layer and the spacer layer constitutes the source and drain;

[0036] The remaining portion of the first initial active pillar structure extending into between the second sacrificial layer and the spacer layer and the region between the first initial active pillar structure located on the sidewall of the second sacrificial layer form the trench.

[0037] In some embodiments, the trench includes a first trench and a second trench respectively located at two ends of the active pillar structure along the second direction; the isolation structure includes a first isolation structure located in the first trench adjacent to an inner wall of the gate structure, and a second isolation structure located in the second trench adjacent to an inner wall of the gate structure; forming an isolation structure in the trench adjacent to an inner wall of the gate structure includes:

[0038] removing the second sacrificial layer between the channel structures to form the first trench and the second trench;

[0039] The first isolation structure and the second isolation structure are formed adjacent to inner walls of the gate structure in the first trench and the second trench, respectively.

[0040] In some embodiments, the source and drain include a first source and drain and a second source and drain located at two ends of the active pillar structure along the second direction, and a portion of the active pillar structure adjacent to the first trench constitutes the first source and drain; the method further includes:

[0041] While forming the first trench and the second trench, removing the second sacrificial layer in the stacked structure to form a fourth trench and a fifth trench; the fourth trench wraps around the first trench; the fifth trench wraps around the second trench;

[0042] After or at the same time as the first isolation structure and the second isolation structure are formed, the first sacrificial layer on one side of the first region and the second region along the first direction close to the first region is removed to form a sixth trench; the sixth trench wraps the fourth trench;

[0043] A bit line connected to the first source and drain is formed in the sixth trench.

[0044] In some embodiments, a portion of the active pillar structure adjacent to the second trench constitutes the second source and drain; and the method further comprises:

[0045] Removing the remaining first sacrificial layer in the stacked structure to form a seventh groove; the seventh groove wraps the fifth groove;

[0046] A capacitor structure connected to the second source and drain is formed in the seventh trench.

[0047] In some embodiments, forming a first initial active pillar structure on a portion of the inner wall of the third trench includes:

[0048] forming a second initial active pillar structure on the inner wall and bottom of the third trench;

[0049] The second initial active pillar structure at the bottom of the third trench and the sidewall of the spacer layer is removed to form the first initial active pillar structure.

[0050] In some embodiments, etching the sub-region to form a third trench extending along the third direction includes:

[0051] Etching the sub-region until the bottommost spacer layer is exposed to form an eighth groove extending along the third direction;

[0052] Through the eighth groove, part of the first sacrificial layer and part of the second sacrificial layer are removed by side etching to form the third groove; the third groove wraps the eighth groove and is zigzag-shaped; the size of the third groove located between the first sacrificial layers is larger than the size of the third groove located between the second sacrificial layers.

[0053] An embodiment of the present disclosure provides a semiconductor structure, which includes: a substrate; a word line structure arranged at intervals along a first direction on the substrate, each word line structure including a plurality of gate structures arranged in sequence at intervals along a third direction; a plurality of active pillar structures, which are arranged on the outer wall of each gate structure; at least one end of the active pillar structure along a second direction has a groove opening toward the second direction; part of the active pillar structure surrounding the gate structure constitutes a channel structure, and part of the active pillar structure located on both sides of the channel structure along the second direction and adjacent to the groove constitutes a source and a drain; an isolation structure, which is located on the inner wall of the trench adjacent to the gate structure. Since at least one end of the active pillar structure along the second direction has a groove opening toward the second direction, and part of the active pillar structure adjacent to the groove constitutes the source and drain, this can not only increase the distance between the gate structure and the drain and reduce the generation of GIDL, but also increase the contact area between the capacitor structure and the source and drain, as well as the contact area between the bit line and the source and drain, thereby reducing the contact resistance and improving the response speed of the semiconductor structure. In addition, since the inner wall adjacent to the gate structure in the groove has an isolation structure, not only can the GIDL be further reduced, but also the parasitic capacitance between the gate structure and the capacitor structure, and between the gate structure and the bit line can be reduced, thereby reducing the power consumption of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0055] Figures 1 to 3 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0056] Figure 4A schematic diagram of a process for forming a semiconductor structure provided by an embodiment of the present disclosure;

[0057] Figures 5 to 20 A schematic diagram of a structure during the formation of a semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0059] In the following description, a large number of details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0060] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0061] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0062] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0063] At present, six times the square of the characteristic size (6F 2 ) and buried word lines to manufacture small-sized dynamic random access memory (DRAM). However, further miniaturization of such small-sized DRAM will cause great damage to its electrical performance, making it very difficult to miniaturize DRAM. In order to achieve the miniaturization of semiconductor structure size, CAA structure is usually used as the channel structure of IGZO transistor. However, in the CAA structure based on IGZO device, the distance between the gate structure and the source and drain is relatively close, which makes it easy to generate GIDL between the gate structure and the source and drain.

[0064] Based on this, an embodiment of the present disclosure provides a semiconductor structure, which includes: a substrate; a word line structure arranged at intervals along a first direction on the substrate, each word line structure including a plurality of gate structures arranged in sequence at intervals along a third direction; a plurality of active pillar structures, arranged on the outer wall of each gate structure; at least one end of the active pillar structure along the second direction has a groove opening toward the second direction; part of the active pillar structure surrounding the gate structure constitutes a channel structure, and part of the active pillar structure located on both sides of the channel structure along the second direction and adjacent to the groove constitutes a source and a drain; an isolation structure, located on the inner wall of the trench adjacent to the gate structure. Since at least one end of the active pillar structure along the second direction has a groove opening toward the second direction, and part of the active pillar structure adjacent to the groove constitutes the source and drain, this can not only increase the distance between the gate structure and the drain and reduce the generation of GIDL, but also increase the contact area between the capacitor structure and the source and drain, as well as the contact area between the bit line and the source and drain, thereby reducing the contact resistance and improving the response speed of the semiconductor structure. In addition, since the inner wall adjacent to the gate structure in the groove has an isolation structure, not only can the GIDL be further reduced, but also the parasitic capacitance between the gate structure and the capacitor structure, and between the gate structure and the bit line can be reduced, thereby reducing the power consumption of the semiconductor structure.

[0065] The semiconductor structure and the method for forming the same in the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0066] Before introducing the embodiments of the present disclosure, the three directions that may be used in the following embodiments to describe the three-dimensional structure are defined. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis and Z-axis directions. The substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top surface and the bottom surface, the direction intersecting (e.g., perpendicular) with the top surface and the bottom surface of the substrate is defined as the third direction. In the directions of the top surface and the bottom surface of the substrate (i.e., the plane where the base is located), two directions intersecting (e.g., perpendicular to each other) are defined. For example, the direction in which the word line structure is arranged may be defined as the first direction, and the plane direction of the substrate may be determined based on the first direction and the second direction. In the embodiments of the present disclosure, the first direction, the second direction and the third direction may be perpendicular to each other. In other embodiments, the first direction, the second direction and the third direction may not be perpendicular. In the embodiments of the present disclosure, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.

[0067] Figures 1 to 3 A schematic diagram of the structure of a semiconductor structure 100 provided in an embodiment of the present disclosure is shown in FIG. Figures 1 to 3 As shown, the semiconductor structure 100 includes: a substrate 110; word line structures 120 arranged at intervals along the X-axis direction on the substrate 110, each word line structure 120 includes a plurality of gate structures 130 arranged in sequence at intervals along the Z-axis direction; a plurality of active pillar structures 140, arranged on the outer wall of each gate structure 130; at least one end of the active pillar structure 140 along the Y-axis direction has a groove 170 opening toward the Y-axis direction; part of the active pillar structure 140 surrounding the gate structure 130 constitutes a channel structure 150, and part of the active pillar structure 140 located on both sides of the channel structure 150 along the Y-axis direction and adjacent to the groove constitutes a source and a drain (i.e., 181 and 182 in the figure); an isolation structure 160; and an inner wall located in the groove adjacent to the gate structure 130.

[0068] It should be noted that Figure 2 The embodiments of the present disclosure provide Figure 1 A top view of the semiconductor structure 100 and a cross-sectional view along line a-a' are shown in FIG. Figure 3 is a schematic diagram of the structure of a memory cell in the semiconductor structure 100. In addition, Figure 1 The substrate 110 and the gate structure 130 are not shown. For the positions of the substrate 110 and the gate structure 130, please refer to Figure 2 To understand.

[0069] In the disclosed embodiment, the substrate 110 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate, etc.; the substrate 110 may also include other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. In other embodiments, the substrate 110 may also be an ion-doped substrate, such as a P-type doped substrate or an N-type doped substrate.

[0070] Please continue to refer to Figures 1 to 3 The word line structure 120 extends along the Z-axis direction. In this way, on the one hand, the distance between a column of storage cells arranged along the Z-axis direction can be reduced, thereby effectively reducing signal delay and improving signal transmission speed; on the other hand, the integration of the stacked structure of the semiconductor structure 100 can be improved, and the storage density of the semiconductor structure 100 can be improved, so that the space in the semiconductor structure can be effectively utilized to achieve miniaturization of the semiconductor structure.

[0071] For further information, please refer to Figures 1 to 3 The word line structure 120 may have at least one gate structure 130 (i.e., a protruding portion on the word line structure 120) and at least one recessed portion, and the gate structure 130 and the recessed portion are alternately arranged in sequence along the Z-axis direction. The size of the gate structure 130 along the Y-axis direction is greater than the size of the recessed portion along the Y-axis direction, and the size of the gate structure 130 along the X-axis direction is greater than the size of the recessed portion along the X-axis direction. In this way, the contact area between the gate structure 130 and the channel structure (i.e., the active pillar structure 140) can be increased, and the control capability of the gate structure 130 can be improved.

[0072] In the embodiment of the present disclosure, the gate structure 130 may be axisymmetric along the Z axis (see Figure 2 ), or is mirror-symmetrical along the XZ plane, so that the gate structure 130 can uniformly control the channel structure, thus making the signal transmission more stable and uniform.

[0073] In this disclosure, please continue to refer to Figures 1 to 3 Each word line structure 120 includes a plurality of gate structures 130 arranged in sequence along the Z-axis direction, and the gate structure 130 includes a gate insulating layer 131 and a gate conductive layer. The material of the word line structure 120 may be any one of cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), platinum (Pt) and palladium (Pd). The gate insulating layer 131 may be composed of a high dielectric constant (HK) material or other suitable materials such as silicon oxide. The high dielectric constant material may include, for example, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO2), zirconium oxide (ZrO2) and aluminum oxide (Al2O3).

[0074] In this disclosure, please continue to refer to Figures 1 to 3 The multiple active pillar structures 140 are arranged on the outer wall of each gate structure 130, which means that each active pillar structure 140 is arranged around the outer side of the corresponding gate structure 130, or in other words, each word line structure 120 penetrates the multiple active pillar structures 140 arranged along the Z-axis direction.

[0075] In the embodiment of the present disclosure, both ends of the active pillar structure 140 along the Y-axis direction have grooves with openings facing the Y-axis direction (see Figures 1 to 3 ), that is, there are two grooves, or, any end of the active pillar structure 140 along the Y-axis direction has a groove opening toward the Y-axis direction, that is, there is one groove. Here, the number of grooves on the active pillar structure 140 can be set according to actual needs.

[0076] It should be noted that the transistor of the semiconductor structure 100 is an oxide thin film transistor. It can be understood that the material of the active column structure 140 (i.e., the channel structure 150) may include an oxide semiconductor, such as indium gallium zinc oxide; due to the inherent characteristics of oxide semiconductors (low electron mobility), when the material of the active column structure 140 is an oxide semiconductor, the leakage current of the transistor located on the surface of the active column structure 140 can be reduced, thereby reducing the speed of charge loss on the capacitor structure 190, thereby extending the data retention time of the semiconductor structure 100 and reducing the power consumption of the semiconductor structure. In other embodiments, the transistor of the semiconductor structure 100 may also be an ordinary silicon-based transistor or other types of transistors.

[0077] In the disclosed embodiment, since at least one end of the active pillar structure along the Y-axis direction has a groove opening toward the Y-axis direction, and part of the active pillar structure adjacent to the groove constitutes the source and drain, this can not only increase the distance between the gate structure and the drain and reduce the generation of GIDL, but also increase the contact area between the capacitor structure and the source and drain, as well as the contact area between the bit line and the source and drain, thereby reducing the contact resistance and improving the response speed of the semiconductor structure. In addition, since the inner wall adjacent to the gate structure in the groove has an isolation structure, not only can the GIDL be further reduced, but also the parasitic capacitance between the gate structure and the capacitor structure, and between the gate structure and the bit line can be reduced, thereby reducing the power consumption of the semiconductor structure.

[0078] In some embodiments, please refer to Figures 1 to 3The groove 170 includes a first groove 171 and a second groove 172 respectively located at both ends of the active pillar structure 140 along the Y-axis direction; the isolation structure 160 includes: a first isolation structure 161 and a second isolation structure 162; the first isolation structure 161 is located in the first groove 171 adjacent to the inner wall of the gate structure 130, and the second isolation structure 162 is located in the second groove 172 adjacent to the inner wall of the gate structure 130.

[0079] In the disclosed embodiment, the first isolation structure 161 and the second isolation structure 162 may be any insulating material, such as silicon oxide or silicon oxynitride. The first isolation structure 161 and the second isolation structure 162 may also be air gaps. Since the dielectric constant of air is relatively small, the first isolation structure 161 and the second isolation structure 162 are set as air gaps to reduce the parasitic capacitance of the structure in contact with the channel structure 150 (e.g., the bit line 200 and the capacitor structure 190), thereby improving the read and write performance of the semiconductor structure.

[0080] Here, the materials of the first isolation structure 161 and the second isolation structure 162 can be the same or different. For example, the materials of the first isolation structure 161 and the second isolation structure 162 are both silicon oxide; for another example, the material of the first isolation structure 161 is silicon oxynitride, and the second isolation structure 162 is an air gap. The thickness of the first isolation structure 161 and the second isolation structure 162 is greater than the thickness of the gate insulation layer 131.

[0081] In the embodiment of the present disclosure, since the first isolation structure 161 is located in the first trench 171 adjacent to the inner wall of the gate structure 130, and the second isolation structure 162 is located in the second trench 172 adjacent to the inner wall of the gate structure 130, not only can the GIDL be further reduced, but also the parasitic capacitance between the gate structure and the capacitor structure, as well as the gate structure and the bit line can be reduced, thereby reducing the power consumption of the semiconductor structure.

[0082] In some embodiments, please refer to Figure 2 The sidewall of the word line structure 120 along the Z-axis direction is sawtooth-shaped. That is, the sidewall of the gate structure 130 along the Z-axis direction is sawtooth-shaped, so that the contact area between the gate structure 130 and the channel structure (that is, the active pillar structure 140) can be increased, and the control capability of the gate structure 130 can be improved.

[0083] In some embodiments, please refer to Figures 1 to 3 The source and drain include a first source and drain 181 and a second source and drain 182 located at both ends of the active column structure 140 along the Y-axis direction; wherein, the portion of the active column structure 140 adjacent to the first trench 171 constitutes the first source and drain 181, and the portion of the active column structure 140 adjacent to the second trench 172 constitutes the second source and drain 182.

[0084] In the embodiment of the present disclosure, the first source drain 181 and the second source drain 182 can be doped with atoms, ions or plasma of group III elements such as boron, gallium, indium, etc.; they can also be doped with atoms, ions or plasma of group V elements such as phosphorus, antimony, arsenic, etc.; the embodiment of the present disclosure is not limited to this.

[0085] In the embodiment of the present disclosure, since at least one end of the active pillar structure along the Y-axis direction has a first groove 171 and a second groove 172 opening toward the Y-axis direction, and a portion of the active pillar structure 140 adjacent to the first groove 171 constitutes a first source and drain 181, and a portion of the active pillar structure 140 adjacent to the second groove 172 constitutes a second source and drain 182; in this way, not only the distance between the gate structure and the drain can be increased, reducing the generation of GIDL; the contact area between the capacitor structure and the second source and drain 182, as well as the contact area between the bit line and the first source and drain 181 are increased, thereby reducing the contact resistance and further improving the response speed of the semiconductor structure.

[0086] In some embodiments, please refer to Figures 1 to 3 The semiconductor structure 100 also includes: a bit line 200 and a capacitor structure 190; the bit line 200 is connected to the first source and drain 181, and is embedded in the first trench 171 and connected to the first isolation structure 161; the capacitor structure 190 is connected to the second source and drain 182, and is embedded in the second trench 172 and connected to the second isolation structure 162.

[0087] In this disclosure, please continue to refer to Figure 2 The capacitor structure 190 includes a first electrode layer 191, a dielectric layer 192, and a second electrode layer 193; wherein the materials of the first electrode layer 191 and the second electrode layer 193 may include metal nitrides or metal silicides, such as titanium nitride. The material of the dielectric layer 192 may include a high-K dielectric material, such as lanthanum oxide (La2O3), aluminum oxide, hafnium oxide, hafnium oxynitride (HfON), hafnium silicate (HfSiO x ) or zirconium oxide or any combination thereof. In other embodiments, the material of the first electrode layer 191 and the second electrode layer 193 may also be polysilicon.

[0088] In the embodiment of the present disclosure, the capacitor structure 190 is horizontal and arranged in an array along the X-axis direction and the Z-axis direction. The horizontal capacitor structure 190 can reduce the possibility of tipping over or breaking. A stacked structure formed by stacking multiple capacitor structures 190 in the Z-axis direction can form a three-dimensional semiconductor structure, thereby improving the integration of the semiconductor structure 100 and achieving miniaturization.

[0089] In the embodiment of the present disclosure, the material of the bit line 200 includes: tungsten, cobalt, copper (Cu), aluminum (Al), titanium nitride (TiN), polysilicon or any combination thereof.

[0090] In some embodiments, please refer to Figures 1 to 3 The bit lines 200 extend along the X-axis direction, and a row of bit lines 200 arranged along the X-axis direction are connected to each other; a plurality of bit lines 200 arranged along the Z-axis direction form a step structure.

[0091] In some embodiments, please refer to Figures 1 to 3 The semiconductor structure 100 further includes: a spacer layer 210; the spacer layer 210 is located between a plurality of bit lines 200 arranged along the Z-axis direction, between a plurality of capacitor structures 190 arranged along the Z-axis direction, and between a plurality of active pillar structures 140 arranged along the Z-axis direction.

[0092] In the embodiment of the present disclosure, the material of the spacer layer 210 can be silicon nitride or silicon carbonitride; on the one hand, the spacer layer 210 can be used to support the formed capacitor structure to reduce the collapse of the capacitor structure and improve the stability of the formed semiconductor structure; on the other hand, the spacer layer 210 can also isolate adjacent capacitor structures, as well as the capacitor structure and the bit line structure, to reduce the generation of leakage current.

[0093] Please continue to refer to Figure 2 , the spacer layer 210 is also located between the substrate 110 and the memory cell.

[0094] In this disclosure, please continue to refer to Figure 2 The semiconductor structure 100 further includes a second insulating structure 111, which is located between the substrate 110 and the spacer layer 210. The material of the second insulating structure 111 can be any insulating material, such as silicon oxide. The second insulating structure 111 and the spacer layer 210 are used together to isolate the memory cell from the substrate 110 to reduce leakage of the memory cell and improve the performance of the semiconductor structure.

[0095] In this disclosure, please continue to refer to Figure 2 The semiconductor structure 100 further includes a first insulating structure 220, which is located between adjacent memory cells along the X-axis direction to prevent leakage of the memory cells. In addition, a Low K (low dielectric constant) material can be used as the material of the first insulating structure 220, so that the parasitic capacitance of the semiconductor structure can be reduced, thereby reducing the capacitance and resistance delay and improving the response time of the semiconductor structure.

[0096] In addition, the present disclosure also provides a method for forming a semiconductor structure. Figure 4 A schematic diagram of a process for forming a semiconductor structure provided by an embodiment of the present disclosure, Figures 5 to 20 A schematic diagram of a structure in a semiconductor structure formation process provided by an embodiment of the present disclosure, wherein: Figures 5 to 7 For three-dimensional view; Figures 8 to 20 It is a top view of the semiconductor structure forming process, and a cross-sectional view along a-a' and bb'. Figure 4 As shown, the method for forming a semiconductor structure includes steps: step S101 to step S104.

[0097] First, refer to Figures 4 to 7 , perform step S101, provide a substrate 110, and form a stacking structure 300 on the substrate 110; the projection of the stacking structure 300 on the substrate 110 is a comb-tooth shape; the stacking structure 300 includes a first area A and a second area B arranged along the Y-axis direction; the second area B includes a plurality of sub-areas b arranged at intervals along the X-axis direction.

[0098] In some embodiments, the stack structure 300 can be formed by the following steps S1011 and S1012:

[0099] Step S1011, forming a cyclic and alternate stacking of an initial spacer layer 210a, an initial first sacrificial layer 211a, an initial second sacrificial layer 212a and an initial first sacrificial layer 211a on the surface of the substrate 110, so as to form Figure 5 An initial stacking structure 300a is shown.

[0100] Here, please continue to refer to Figure 5 Before forming the initial stacking structure 300 a , the method for forming the semiconductor structure 100 further includes: forming an initial second insulating structure 111 a located between the initial spacer layer 210 a and the substrate 110 .

[0101] During implementation, the second insulating material may be deposited on the surface of the substrate 110 in sequence to form Figure 5 The initial second insulating structure 111a shown in FIG. 111a; a spacer material, a first sacrificial material, and a second sacrificial material are sequentially deposited on the surface of the initial second insulating structure 111a to form a Figure 5 The cycle shown alternately stacks an initial spacer layer 210a, an initial first sacrificial layer 211a, an initial second sacrificial layer 212a, and an initial first sacrificial layer 211a.

[0102] In the embodiment of the present disclosure, the number of the initial spacer layer 210a, the initial first sacrificial layer 211a and the initial second sacrificial layer 212a in the initial stacked structure 300a can be set according to the required capacitance density (or storage density). The more the number of the initial spacer layer 210a, the initial first sacrificial layer 211a and the initial second sacrificial layer 212a, the higher the integration of the formed semiconductor structure 100 and the greater the density of the capacitor structure 190. In implementation, the initial spacer layer 210a can be three layers, the initial first sacrificial layer 211a can be five layers, and the initial second sacrificial layer 212a can be two layers.

[0103] In the embodiment of the present disclosure, the second insulating material can be any insulating material, for example, silicon oxide; the spacer material can be silicon nitride or silicon carbonitride. The first sacrificial material can be, for example, silicon oxide, and the second sacrificial material can be, for example, polysilicon. In this way, under the same etching conditions, the first sacrificial material is easier to be removed than the second sacrificial material.

[0104] In the embodiment of the present disclosure, the initial second insulating structure 111a, the initial spacer layer 210a, the initial first sacrificial layer 211a and the initial second sacrificial layer 212a can be formed by any of the following deposition processes: Chemical Vapor Deposition (CVD) process, Physical Vapor Deposition (PVD) process, Atomic Layer Deposition (ALD) process or other suitable processes.

[0105] Step S1012 , etching the initial stack structure 300 a to form a stack structure 300 .

[0106] During implementation, for example, the initial stacked structure 300a may be etched by a dry etching process or a wet etching process to form a Figure 6 The stacked structure 300 shown includes a spacer layer 210 , a first sacrificial layer 211 , a second sacrificial layer 212 and a first sacrificial layer 211 which are arranged alternately and cyclically along the Z-axis direction.

[0107] Please continue to refer to Figure 6 While etching the initial stacked structure 300 a , the initial second insulating structure 111 a is also etched to form the second insulating structure 111 ; and a portion of the substrate 110 is etched.

[0108] In the embodiment of the present disclosure, after executing step S101, the method for forming the semiconductor structure 100 further includes: depositing a first insulating material between the sub-regions b to form Figure 7 The initial first insulating structure 220a is shown. The first insulating material may be a low-K material. The initial first insulating structure 220a can protect the side surface of the stacked structure 300 along the X-axis direction from being damaged when the stacked structure 300 is subsequently processed.

[0109] Next, refer to Figure 4 , Figures 8 to 13 , executing step S102, forming a word line structure 120 extending through the sub-region b along the Z-axis direction, each word line structure 120 includes a plurality of gate structures 130 sequentially spaced apart along the Z-axis direction.

[0110] In some embodiments, the word line structure 120 extending through the sub-region b along the Z-axis direction may be formed by the following steps S1021 to S1023:

[0111] Step S1021 , etching the sub-region b to form a third trench 173 extending along the Z-axis direction; the third trench 173 exposes the bottommost spacer layer 210 .

[0112] In some embodiments, step S1021 may be formed by the following steps:

[0113] Step S1021a, etching the sub-region b until the bottom spacer layer 210 is exposed, forming an eighth trench 178 extending along the Z-axis direction.

[0114] During implementation, the sub-region b can be etched by a wet etching process (for example, etching with a strong acid such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid) or a dry etching process (for example, a plasma etching process, a reactive ion etching process, or an ion milling process) until the bottom spacer layer 210 is exposed, thereby forming a region extending in the Z-axis direction. Figure 8 An eighth groove 178 is shown.

[0115] Step S1021b, through the eighth groove 178, part of the first sacrificial layer 211 and part of the second sacrificial layer 212 are laterally etched away to form a third groove 173; the third groove 173 wraps the eighth groove 178 and is zigzag-shaped; the size d1 of the third groove 173 located between the first sacrificial layers 211 is larger than the size d2 of the third groove 173 located between the second sacrificial layers 212.

[0116] During implementation, a wet etching process can be used to lateral-etch through the eighth trench 178 to lateral-etch and remove a portion of the first sacrificial layer 211 and a portion of the second sacrificial layer 212 to form a Fig. 9 The third trench 173 is shown; wherein the etching solution may be hydrofluoric acid (DHF), a mixed solution of dilute hydrofluoric acid and ammonia (NH4OH), or a mixed solution of dilute hydrofluoric acid and tetramethylammonium hydroxide (TMAH).

[0117] It should be noted that, since the first sacrificial layer 211 has a larger selective etching ratio than the second sacrificial layer 212, the first sacrificial layer 211 is more easily etched and removed than the second sacrificial layer 212 during the etching process, so when the third trench 173 is formed, the size of the third trench 173 located between the first sacrificial layers 211 is larger than the size of the third trench 173 located between the second sacrificial layers 212. In addition, the size d1 of the third trench 173 located between the first sacrificial layers 211 and the size d2 of the third trench 173 located between the second sacrificial layers 212 can be the size or area in any direction within the substrate plane.

[0118] Step S1022 , forming a first initial active pillar structure 140 a on a portion of the inner wall of the third trench 173 .

[0119] In some embodiments, step S1022 may be formed by the following steps:

[0120] Step S1022 a , forming a second initial active pillar structure 140 b on the inner wall and bottom of the third trench 173 .

[0121] During implementation, active materials may be deposited on the inner wall and bottom of the third trench 173 to form a Fig.10 The second initial active pillar structure 140b is shown. The active material may include an oxide semiconductor, such as indium gallium zinc oxide. The second initial active pillar structure 140b may be formed by any of the following deposition processes: chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process or other suitable process.

[0122] Step S1022b, removing the second initial active pillar structure 140b at the bottom of the third trench 173 and the sidewall of the spacer layer 210 to form a first initial active pillar structure 140a.

[0123] During implementation, the second initial active pillar structure 140b can be etched by a dry etching process or a wet etching process to remove the second initial active pillar structure 140b at the bottom of the third trench 173, the sidewall of the spacer layer 210 and the surface of the topmost spacer layer 210, so as to form Fig.11 A first initial active pillar structure 140a is shown.

[0124] Step S1023 , the first initial active pillar structure 140 a is partially or completely embedded in the first sacrificial layer 211 ; and a word line structure 120 is formed in the third trench 173 having the first initial active pillar structure 140 a .

[0125] It should be noted that if the first initial active column structure 140a is completely embedded in the first sacrificial layer 211, the first trench 171 and the second trench 172 can be formed simultaneously. In other embodiments, if the first initial active column structure 140a is partially embedded in the first sacrificial layer 211, only the first trench 171 or the second trench 172 is formed subsequently. In the embodiment of the present disclosure, the first initial active column structure 140a is completely embedded in the first sacrificial layer 211 as an example for description.

[0126] During implementation, after forming the first initial active pillar structure 140a, a gate insulating material and a conductive material are sequentially deposited in the third trench 173 having the first initial active pillar structure 140a to form a gate insulating material. Fig.12 The gate insulating layer 131 and the gate conductive layer are shown. The gate insulating layer 131 and the gate conductive layer constitute the gate structure 130. The gate conductive layer can be used as Fig.12 A word line structure 120 is shown.

[0127] Here, the gate insulating material may be a high dielectric constant (HK) material or other suitable materials such as silicon oxide, and the high dielectric constant material may include, for example, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO2), zirconium oxide (ZrO2) and aluminum oxide (Al2O3). The conductive material may be any one of cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), platinum (Pt) and palladium (Pd), and the gate insulating layer 131 and the word line structure 120 may be formed by any suitable process.

[0128] Please refer to Fig.13 After forming the word line structure 120, the method for forming the semiconductor structure 100 further includes: removing a portion of the initial first insulating structure 220a to expose a portion of the first sacrificial layer 211. Specifically, a portion of the initial first insulating structure 220a can be removed by a dry etching process or a wet etching process to expose both sides of the first sacrificial layer 211 along the X-axis direction.

[0129] Please continue to refer to Fig.13 After exposing both sides of the first sacrificial layer 211 along the X-axis direction, a portion of the first sacrificial layer 211 is removed along the X-axis direction by lateral etching to expose both sides of the first initial active pillar structure 140a along the X-axis direction.

[0130] Next, refer to Figure 4 , Fig.14 and Fig.15, execute step S103 to form a plurality of active pillar structures 140 surrounding the gate structure 130 and arranged at intervals; at least one end of the active pillar structure 140 along the Y-axis direction has a groove 170 opening toward the Y-axis direction; part of the active pillar structure 140 surrounding the gate structure 130 constitutes a channel structure 150, and part of the active pillar structure 140 located on both sides of the channel structure 150 along the Y-axis direction and adjacent to the groove 170 constitutes a source and a drain.

[0131] In some embodiments, step S103, forming a plurality of active pillar structures 140 surrounding the gate structure 130 and arranged at intervals, includes:

[0132] The portion of the first initial active pillar structure 140a extending between the second sacrificial layer 212 and the spacer layer 210 in the X-axis direction is removed to form a Fig.14 The active pillar structure 140 is shown; wherein, the remaining portion of the first initial active pillar structure 140a embedded between the second sacrificial layer 212 and the spacer layer 210 constitutes the source and drain; the remaining portion of the first initial active pillar structure 140a extending into between the second sacrificial layer 212 and the spacer layer 210 and the area between the first initial active pillar structure 140a located on the side wall of the second sacrificial layer 212 form a groove 170.

[0133] Here, please continue to refer to Fig.14 The groove 170 includes a first groove 171 and a second groove 172 respectively located at two ends of the active column structure 140 along the Y-axis direction; the source and drain include a first source and drain 181 and a second source and drain 182 located at two ends of the active column structure 140 along the Y-axis direction, and the part of the active column structure 140 adjacent to the first groove 171 constitutes the first source and drain 181, and the part of the active column structure 140 adjacent to the second groove 172 constitutes the second source and drain 182.

[0134] During implementation, a portion of the first initial active pillar structure 140a extending between the second sacrificial layer 212 and the spacer layer 210 in the X-axis direction may be removed by lateral etching to form a Fig.14 An active pillar structure 140 is shown.

[0135] In this disclosure, please continue to refer to Fig.14 After the active pillar structure 140 , the method for forming the semiconductor structure 100 further includes: removing the second sacrificial layer 212 exposed in the X-axis direction; exposing both sides of the active pillar structure 140 along the X-axis direction.

[0136] In the embodiment of the present disclosure, after removing the second sacrificial layer 212 exposed in the X-axis direction, a first insulating material is deposited between two adjacent sub-regions b along the X-axis direction to form a Fig.15 A first insulating structure 220 is shown.

[0137] Finally, reference Figure 5 , Figures 16 to 20 , executing step S104 , forming an isolation structure 160 in the trench adjacent to the inner wall of the gate structure 130 .

[0138] In some embodiments, the isolation structure 160 includes a first isolation structure 161 located in the first trench 171 adjacent to the inner wall of the gate structure 130, and a second isolation structure 162 located in the second trench 172 adjacent to the inner wall of the gate structure 130. Step S104 can be formed by the following steps S1041 to S1042:

[0139] Step S1041 , removing the second sacrificial layer 212 between the channel structures 150 to form a first trench 171 and a second trench 172 .

[0140] In some embodiments, the method for forming the semiconductor structure 100 further includes: while forming the first trench 171 and the second trench 172, removing the second sacrificial layer 212 in the stacked structure 300 to form a Fig.16 The fourth groove 174 and the fifth groove 175 are shown; the fourth groove 174 wraps around the first groove 171 , and the fifth groove 175 wraps around the second groove 172 .

[0141] During implementation, the second sacrificial layer 212 may be removed by lateral etching using a wet etching process to form a Fig.16 The fourth groove 174 and the fifth groove 175 are shown.

[0142] In step S1042 , a first isolation structure 161 and a second isolation structure 162 are formed in the first trench 171 and the second trench 172 respectively on inner walls adjacent to the gate structure 130 .

[0143] In some embodiments, step S1042 may be performed by the following steps:

[0144] Step S1042a, after forming the fourth trench 174 and the fifth trench 175, fill the fourth trench 174 and the fifth trench 175 with any insulating material to form a Fig.17 The initial first isolation structure 161a and the initial second isolation structure 162a are shown. Here, the insulating material filled in the fourth trench 174 and the insulating material filled in the fifth trench 175 can be the same or different.

[0145] Step S1042 b , etching the initial first isolation structure 161 a to form the first isolation structure 161 .

[0146] During implementation, the initial first isolation structure 161a can be etched by lateral etching using a wet etching process to form a Fig.18A first isolation structure 161 is shown.

[0147] Here, in the formation Fig.18 At the same time or after the first isolation structure 161 shown in FIG. 1 , the first sacrificial layer 211 on the side close to the first region A along the X-axis direction in the first region A and the second region B is removed to form a first isolation structure 161 shown in FIG. 1 . Fig.18 The sixth trench 176 is shown; the sixth trench 176 wraps the fourth trench 174; and a first source and drain electrode 181 is connected to the sixth trench 176. Fig.19 Bit line 200 is shown.

[0148] The bit lines 200 extend along the X-axis direction, and a row of bit lines 200 arranged along the X-axis direction are connected to each other; a plurality of bit lines 200 arranged along the Z-axis direction form a step structure.

[0149] Step S1042c, etching the initial second isolation structure 162a to form a second isolation structure 162.

[0150] During implementation, the initial first isolation structure 162a can be etched by lateral etching using a wet etching process to form a Fig. 20 A second isolation structure 162 is shown.

[0151] Here, in the formation Fig. 20 After or at the same time as the second isolation structure 162 shown in FIG. 1 , the remaining first sacrificial layer 211 in the stacked structure 300 is removed to form a Fig. 20 The seventh trench 177 shown; the seventh trench 177 wraps the fifth trench 175; a capacitor structure 190 connected to the second source and drain 182 is formed in the seventh trench 177 (refer to Figure 2 ).

[0152] During implementation, the remaining first sacrificial layer 211 in the stacked structure 300 is removed to form a seventh trench 177; then, a first electrode layer 191, a dielectric layer 192, and a second electrode layer 193 are sequentially formed in the seventh trench 177. The first electrode layer 191, the dielectric layer 192, and the second electrode layer 193 constitute a Figure 2 Capacitor structure 190 is shown.

[0153] It should be noted that in the embodiment of the present disclosure, the bit line 200 is formed first, and then the capacitor structure 190 is formed; in other embodiments, the capacitor structure 190 may be formed first, and then the bit line 200 is formed, which is not limited here.

[0154] The method for forming a semiconductor structure provided by the embodiment of the present disclosure has an active pillar structure in the formed semiconductor structure having a groove opening toward the Y-axis direction at at least one end along the Y-axis direction, and a portion of the active pillar structure adjacent to the groove constitutes a source and drain. In this way, not only can the distance between the gate structure and the drain be increased, thereby reducing the generation of GIDL; the contact area between the capacitor structure and the source and drain, as well as the contact area between the bit line and the source and drain, can also be increased, thereby reducing the contact resistance and improving the response speed of the semiconductor structure. In addition, since the inner wall adjacent to the gate structure in the groove has an isolation structure, not only can the GIDL be further reduced; the parasitic capacitance between the gate structure and the capacitor structure, as well as the gate structure and the bit line, can also be reduced, thereby reducing the power consumption of the semiconductor structure.

[0155] The semiconductor structure formed by the method provided in the embodiment of the present disclosure is similar to the semiconductor structure in the above-mentioned embodiment. For the technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above-mentioned embodiment for understanding, and no further details will be given here.

[0156] In the several embodiments provided in the present disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-targeted manner. The structural embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0157] The features disclosed in several method or structural embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0158] The above are only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: substrate; word line structures arranged at intervals along a first direction on the substrate, each of the word line structures comprising a plurality of gate structures sequentially arranged at intervals along a third direction; A plurality of active column structures are arranged on the outer wall of each gate structure; at least one end of the active column structure along the second direction has a groove opening toward the second direction; a portion of the active column structure surrounding the gate structure constitutes a channel structure, and a portion of the active column structure located on both sides of the channel structure along the second direction and adjacent to the groove constitutes a source and a drain; an isolation structure, located in the trench adjacent to an inner wall of the gate structure; The first direction intersects with the second direction and is located in the plane where the substrate is located; the third direction intersects with the plane where the substrate is located.

2. The semiconductor structure according to claim 1, characterized in that: The grooves include a first groove and a second groove respectively located at two ends of the active pillar structure along the second direction; The isolation structure comprises: a first isolation structure and a second isolation structure; The first isolation structure is located in the first trench adjacent to an inner wall of the gate structure, and the second isolation structure is located in the second trench adjacent to an inner wall of the gate structure.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The sidewall of the word line structure along the cross-section of the third direction is sawtooth-shaped, and the word line structure includes gate structures and recessed portions alternately arranged in sequence along the third direction, the size of the gate structure along the second direction is larger than the size of the recessed portion along the second direction, and the size of the gate structure along the first direction is larger than the size of the recessed portion along the first direction.

4. The semiconductor structure according to claim 2, characterized in that: The source and drain electrodes include a first source and drain electrode and a second source and drain electrode located at two ends of the active pillar structure along the second direction; The portion of the active pillar structure adjacent to the first trench constitutes the first source and drain, and the portion of the active pillar structure adjacent to the second trench constitutes the second source and drain.

5. The semiconductor structure according to claim 4, characterized in that: Also includes: bit line and capacitor structures; The bit line is connected to the first source and drain, and is embedded in the first trench and connected to the first isolation structure; The capacitor structure is connected to the second source and drain, and is embedded in the second trench and connected to the second isolation structure.

6. The semiconductor structure according to claim 5, characterized in that: Also includes: Spacer layer; The spacer layer is located between the plurality of bit lines arranged along the third direction, between the plurality of capacitor structures arranged along the third direction, and between the plurality of active pillar structures arranged along the third direction.

7. The semiconductor structure according to claim 5 or 6, characterized in that: The bit lines extend along the first direction, and a row of the bit lines arranged along the first direction are connected to each other; A plurality of bit lines arranged along the third direction form a step structure.

8. A method for forming a semiconductor structure, characterized in that: The method comprises: A substrate is provided, on which a stacking structure is formed; the projection of the stacking structure on the substrate is a comb-tooth shape; the stacking structure includes a first area and a second area arranged along a second direction; the second area includes a plurality of sub-areas arranged at intervals along the first direction; forming a word line structure extending along a third direction and penetrating the sub-region, each of the word line structures comprising a plurality of gate structures sequentially spaced apart along the third direction; A plurality of active pillar structures are formed around the gate structure and are arranged at intervals; at least one end of the active pillar structure along the second direction has a groove opening toward the second direction; a portion of the active pillar structure surrounding the gate structure constitutes a channel structure, and a portion of the active pillar structure located on both sides of the channel structure along the second direction and adjacent to the groove constitutes a source and a drain; forming an isolation structure in the trench adjacent to an inner wall of the gate structure; The first direction intersects with the second direction and is parallel to the plane where the substrate is located, and the third direction is perpendicular to the plane where the substrate is located.

9. The method according to claim 8, characterized in that The stacked structure comprises a spacer layer, a first sacrificial layer, a second sacrificial layer and the first sacrificial layer which are cyclically and alternately arranged along the third direction; The forming of a word line structure extending along the third direction and penetrating the sub-region comprises: Etching the sub-region to form a third groove extending along the third direction; the third groove exposes the bottommost spacer layer; forming a first initial active pillar structure on a portion of the inner wall of the third trench; the first initial active pillar structure is partially or completely embedded in the first sacrificial layer; The word line structure is formed in the third trench having the first preliminary active pillar structure.

10. The method according to claim 9, characterized in that A plurality of active pillar structures are formed surrounding the gate structure and arranged at intervals, including: removing a portion of the first initial active pillar structure extending in the first direction into between the second sacrificial layer and the spacer layer to form the active pillar structure; Wherein, the remaining portion of the first initial active pillar structure embedded between the second sacrificial layer and the spacer layer constitutes the source and drain; The remaining portion of the first initial active pillar structure extending into between the second sacrificial layer and the spacer layer and the region between the first initial active pillar structure located on the sidewall of the second sacrificial layer form the trench.

11. The method according to claim 10, characterized in that The trench comprises a first trench and a second trench respectively located at two ends of the active pillar structure along the second direction; the isolation structure comprises a first isolation structure located in the first trench adjacent to the inner wall of the gate structure, and a second isolation structure located in the second trench adjacent to the inner wall of the gate structure; An isolation structure is formed in the trench adjacent to an inner wall of the gate structure, comprising: removing the second sacrificial layer between the channel structures to form the first trench and the second trench; The first isolation structure and the second isolation structure are respectively formed in the first trench and the second trench adjacent to inner walls of the gate structure.

12. The method according to claim 11, characterized in that The source and drain electrodes include a first source and drain electrode and a second source and drain electrode located at two ends of the active pillar structure along the second direction, and a portion of the active pillar structure adjacent to the first trench constitutes the first source and drain electrode; The method further comprises: While forming the first trench and the second trench, removing the second sacrificial layer in the stacked structure to form a fourth trench and a fifth trench; the fourth trench wraps around the first trench; the fifth trench wraps around the second trench; After or simultaneously with forming the first isolation structure and the second isolation structure, removing the first sacrificial layer on one side of the first region and the second region along the first direction close to the first region to form a sixth trench; the sixth trench wraps the fourth trench; A bit line connected to the first source and drain is formed in the sixth trench.

13. The method according to claim 12, characterized in that The portion of the active pillar structure adjacent to the second trench constitutes the second source and drain; the method further comprises: Removing the remaining first sacrificial layer in the stacked structure to form a seventh groove; the seventh groove wraps the fifth groove; A capacitor structure connected to the second source and drain is formed in the seventh trench.

14. The method according to claim 9, characterized in that A first initial active pillar structure is formed on a portion of the inner wall of the third trench, comprising: forming a second initial active pillar structure on the inner wall and bottom of the third trench; The second initial active pillar structure at the bottom of the third trench and the sidewall of the spacer layer is removed to form the first initial active pillar structure.

15. The method according to any one of claims 9 to 14, characterized in that: The etching of the sub-region to form a third trench extending along the third direction comprises: Etching the sub-region until the bottommost spacer layer is exposed to form an eighth groove extending along the third direction; Through the eighth groove, part of the first sacrificial layer and part of the second sacrificial layer are removed by side etching to form the third groove; the third groove wraps the eighth groove and is zigzag-shaped; the size of the third groove located between the first sacrificial layers is larger than the size of the third groove located between the second sacrificial layers.

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