Memory cell, integrated circuit, memory, logic chip, and electronic device

Abstract

The invention provides a storage unit, an integrated circuit, a memory, a logic chip and electronic equipment. The storage unit comprises a substrate; along the thickness direction of the substrate, the first gate oxide layer is arranged on one side of the substrate, and the control gate is arranged on one side, deviating from the substrate, of the first gate oxide layer; a second gate oxide layer and a floating gate; the second gate oxide layer is arranged on the substrate, the second gate oxide layer and the first gate oxide layer are located on the same side of the substrate in the thickness direction, the second gate oxide layer and the first gate oxide layer are arranged at intervals in the length direction of the substrate, and the floating gate is arranged on the side, away from the substrate, of the second gate oxide layer; wherein the first gate oxide layer comprises a first dielectric layer, and the dielectric constant of the first dielectric layer is greater than 16. By using the storage unit, the problem that a multi-layer MASK needs to be used due to the fact that the storage unit in an existing Flash storage is of a multi-layer vertical structure can be solved, and reduction of the cost of the storage is facilitated.

Description

Technical Field

[0001] The present application relates to the technical field of electronic equipment, and in particular to a storage unit, an integrated circuit, a memory, a logic chip and an electronic device. Background Art

[0002] As an important function in chips, memory has always received widespread attention. There are many types of memory, among which electrical, magnetic, phase change, and resistance can be divided according to the storage principle. Among them, electrical memory is the most widely used. Based on electricity, according to different charge storage media and wafer processes, memory can be further subdivided into Flash memory, SONOS (Silicon-Oxide-Nitride-Oxide-Silicon memory) memory, Logic NVM (Logic Non-Volatile Memory, logical non-volatile memory), etc. Among them, the storage unit of Flash memory is a multi-layer vertical structure, which requires multi-layer masks during preparation, and the process is complex and costly. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a storage unit, an integrated circuit, a memory, a logic chip and an electronic device. The use of the storage unit can solve the problem of needing to use multiple layers of MASK in the existing Flash memory because the storage unit has a multiple-layer vertical structure, which is conducive to reducing the cost of the memory.

[0004] An embodiment of the present application provides a storage unit, the storage unit comprising: substrate; A first gate oxide layer and a control gate, wherein along the thickness direction of the substrate, the first gate oxide layer is arranged on one side of the substrate, and the control gate is arranged on a side of the first gate oxide layer away from the substrate; A second gate oxide layer and a floating gate; the second gate oxide layer is arranged on the substrate and is located on the same side of the substrate along the thickness direction as the first gate oxide layer, the second gate oxide layer and the first gate oxide layer are arranged at intervals along the length direction of the substrate, and the floating gate is arranged on a side of the second gate oxide layer away from the substrate; The first gate oxide layer includes a first dielectric layer, and the dielectric constant of the first dielectric layer is greater than 16.

[0005] In the memory cell of the memory provided in the embodiment of the present application, the first gate oxide layer and the second gate oxide layer are arranged on the same side of the substrate along the thickness direction and are spaced apart along the length direction of the substrate, and a control gate is arranged on the side of the first gate oxide layer facing away from the substrate, and a floating gate is arranged on the side of the second gate oxide layer facing away from the substrate, so as to realize a structure in which the control gate and the floating gate are arranged in a horizontal direction in the lateral direction of the memory cell, that is, a memory cell with a horizontal structure is formed, which solves the problem of the existing Flash memory that a multi-layer MASK needs to be used because the memory cell is a multi-layer vertical structure, thereby reducing the cost of the memory.

[0006] In addition, by providing a first dielectric layer with a high dielectric constant in the first gate oxide layer to increase the dielectric constant of the first gate oxide layer, the capacitance per unit area of ​​the control gate can be increased, and the size of the storage unit can be reduced by reducing the area of ​​the control gate, which is beneficial to reducing the overall size of the memory.

[0007] In a possible implementation, the first gate oxide layer includes a first oxide layer and a first dielectric layer stacked in sequence, the first oxide layer is disposed on the substrate, the first dielectric layer is disposed on a side of the first oxide layer away from the substrate, and the control gate is disposed on a side of the first dielectric layer away from the first oxide layer; Alternatively, the first gate oxide layer is a first dielectric layer, the first dielectric layer is arranged on the substrate, and the control gate is arranged on a side of the first dielectric layer away from the substrate. By setting the first gate oxide layer as a single-layer first dielectric layer, the capacitance increase brought by the first dielectric layer will not be diluted, and the capacitance increase is significant, thereby significantly improving the capacitance value per unit area of ​​the control gate, and further significantly reducing the size of the storage unit; Alternatively, the first gate oxide layer comprises a first oxide layer, a first transition layer and a first dielectric layer which are sequentially stacked, the first oxide layer is arranged on the substrate, the first transition layer is arranged on a side of the first oxide layer away from the substrate, the first dielectric layer is arranged on a side of the first transition layer away from the first oxide layer, and the control gate is arranged on a side of the first dielectric layer away from the first transition layer, wherein the material of the first transition layer comprises the material of the first oxide layer and the material of the first dielectric layer, and the content of the material of the first oxide layer in the first transition layer gradually decreases and the content of the material of the first dielectric layer gradually increases from the first oxide layer to the first dielectric layer; Alternatively, the first gate oxide layer comprises a first dielectric layer and a first oxide layer stacked in sequence, the first dielectric layer is arranged on the substrate, the first oxide layer is arranged on a side of the first dielectric layer away from the substrate, and the control gate is arranged on a side of the first oxide layer away from the first dielectric layer; Alternatively, the first gate oxide layer includes a first dielectric layer, a first transition layer and a first oxide layer which are stacked in sequence, the first dielectric layer is arranged on the substrate, the first transition layer is arranged on the side of the first dielectric layer away from the substrate, the first oxide layer is arranged on the side of the first transition layer away from the first dielectric layer, and the control gate is arranged on the side of the first oxide layer away from the first transition layer, wherein the material of the first transition layer includes the material of the first oxide layer and the material of the first dielectric layer, and the content of the material of the first oxide layer in the first transition layer gradually decreases and the content of the material of the first dielectric layer gradually increases from the first oxide layer to the first dielectric layer.

[0008] In a possible implementation, the thickness of the first dielectric layer is 1 nm to 2 nm. The first dielectric layer with a high dielectric constant has a strong ability to bind electrons. Using a thinner first dielectric layer can also ensure that the first gate oxide layer is not broken down.

[0009] In a possible implementation manner, the material of the first dielectric layer includes HfO 2 As the thickness of the first dielectric layer decreases, HfO 2 The recrystallization temperature of the material will increase from 500°C to 700°C, which can significantly reduce HfO 2 The degree of recrystallization of the material when using the same atomic layer deposition (ALD) process can avoid the problem of long-range Coulomb scattering caused by recrystallization, which in turn causes reduced electron activity, thereby ensuring the performance of the memory.

[0010] In a possible implementation, the second gate oxide layer includes a second dielectric layer, and a dielectric constant of a material of the second dielectric layer is less than 3.

[0011] By setting the second gate oxide layer to include a second dielectric layer with a low dielectric constant, the dielectric constant of the second gate oxide layer is reduced, thereby reducing the capacitance per unit area of ​​the floating gate, increasing the proportion of the capacitance of the control gate, and thus achieving an increase in the coupling coefficient. On the one hand, when the charge of the floating gate remains unchanged, the increase in the coupling coefficient can reduce the voltage applied to the control gate, that is, during the data writing process of the storage unit, the voltage of the control gate is reduced, which is beneficial to improving the long-term reliability of the first gate oxide layer under the control gate, thereby facilitating the life of the storage unit, and further facilitating the long-term use reliability of the memory, while reducing the demand for the write voltage, and achieving the purpose of completing data writing at a relatively low control gate voltage.

[0012] On the other hand, when the voltage of the control gate remains unchanged, the increase in the coupling coefficient can increase the voltage of the second gate oxide layer, that is, the voltage formed on the floating gate is increased, so that the electric field strength of the second gate oxide layer is increased, that is, the amount of electricity written to the floating gate within a certain period of time is increased, so that the speed (current) of data writing within the range that the second gate oxide layer can withstand is significantly improved due to the influence of the electric field strength, thereby achieving an increase in the speed of data writing in the storage unit and improving the efficiency of data writing.

[0013] In a possible implementation, the second gate oxide layer includes a second oxide layer and a second dielectric layer, the second oxide layer is disposed between the substrate and the second dielectric layer, and the floating gate is disposed on the side of the second dielectric layer away from the second oxide layer. A low dielectric constant will cause the second dielectric layer to have a reduced charge binding ability, which is likely to cause additional leakage or data loss. By adding a second oxide layer and arranging the second oxide layer between the substrate and the second dielectric layer, the risk of leakage can be reduced and data loss can be avoided. In addition, the second oxide layer has a high lattice matching with the substrate, which can alleviate the stress caused by lattice distortion during processing, thereby ensuring the integrity of the second oxide layer and further ensuring the performance of the storage unit.

[0014] In a possible implementation manner, the second gate oxide layer further includes a second transition layer, and the second transition layer is disposed between the second oxide layer and the second dielectric layer; The material of the second transition layer includes the material of the second oxide layer and the material of the second dielectric layer. From the second oxide layer to the second dielectric layer, the content of the material of the second oxide layer in the second transition layer gradually decreases, and the content of the material of the second dielectric layer gradually increases.

[0015] By using a second transition layer in the second gate oxide layer, a gradient change of the material of the second dielectric layer in the second gate oxide layer can be achieved, thereby reducing the interface defects generated between the second oxide layer and the second dielectric layer, preventing the interface defects from capturing electrons and causing threshold voltage fluctuations, ensuring the floating gate's ability to retain data and low leakage current, and thereby improving the performance of the storage unit.

[0016] In one possible implementation, the thickness of the second gate oxide layer is greater than that of the first gate oxide layer, which can significantly reduce the capacitance of the floating gate and increase the proportion of the capacitance of the control gate, thereby enabling an increase in the coupling coefficient, thereby achieving the purpose of completing data writing at a relatively low control gate voltage, and achieving the purpose of increasing the amount of charge in the floating gate at the same control gate voltage, thereby increasing the data writing speed of the storage unit.

[0017] An embodiment of the present application also provides an integrated circuit, which includes one or more storage units as described above.

[0018] An embodiment of the present application further provides a memory, which includes a controller and one or more storage units as described above, and the controller is used to control access to the storage unit.

[0019] An embodiment of the present application further provides a logic chip, the logic chip comprising a circuit board and the memory as described above, wherein the memory is integrated in the circuit board.

[0020] An embodiment of the present application also provides an electronic device, which includes a processor and a memory as described above, and the processor is used to access the memory, or the electronic device includes a processor and a logic chip as described above, and the processor is used to access the memory in the logic chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 It is a structural diagram of an existing Flash memory; Figure 2 A schematic diagram of a structure in which a memory provided in an embodiment of the present application is applied to an electronic device; Figure 3 A schematic diagram of a structure in which a memory provided in an embodiment of the present application is applied to a logic chip; Figure 4 A schematic diagram of the structure of a memory provided in an embodiment of the present application; Figure 5 for Figure 4 A schematic diagram of the structure of a storage unit in the memory shown in the first embodiment; Figure 6 for Figure 5 A schematic diagram of a cross-sectional structure of a storage unit shown; Figure 7 for Figure 4 A schematic cross-sectional structure diagram of a storage unit in the memory in the second embodiment; Figure 8 for Figure 4 A schematic cross-sectional structure diagram of a storage unit in the memory shown in the third embodiment; Fig. 9 for Figure 4 A schematic cross-sectional structure diagram of a storage unit in the memory shown in the fourth embodiment; Fig.10 for Figure 4 A schematic cross-sectional structure diagram of a storage unit in the memory shown in the fifth embodiment; Fig.11 for Figure 4 A schematic cross-sectional structure diagram of a storage unit in the memory shown in the sixth embodiment; Fig.12 for Figure 4 A schematic diagram of the cross-sectional structure of a storage unit in the memory shown in the seventh embodiment; Fig.13 for Figure 4 A schematic cross-sectional structure diagram of a storage unit in the memory shown in the eighth embodiment; Fig.14 for Figure 4 A schematic cross-sectional structure diagram of a storage unit in the memory shown in the ninth embodiment; Fig.15 for Figure 4 A schematic diagram of the structure of a storage unit in the memory shown in the tenth embodiment; Fig.16 for Fig.15 Schematic diagram of the cross-sectional structure of the storage unit shown. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0024] See also Figure 1 , Figure 1 It is a schematic diagram of the structure of the existing Flash memory 500.

[0025] like Figure 1 As shown, in the cell structure of a Flash memory 500 formed by a Flash process (a non-volatile storage technology), an oxide layer 530, a floating gate 90, an intermediate layer 540 and a control gate 50 are sequentially stacked on a source 510 and a drain 520. For example, the oxide layer 530 is SiO 2 The floating gate 90 is disposed on the oxide layer 530. The floating gate 90 is a polysilicon layer. The intermediate layer 540 includes a first layer 541, a second layer 542, and a third layer 543 sequentially stacked on the floating gate 90. The first layer 541 is SiO 2 layer, the second layer 542 is Si 3 N 4 layer, the third layer 543 is SiO 2The control gate 50 is disposed on a side of the intermediate layer 540 away from the floating gate 90 , and the control gate 50 is a polysilicon layer.

[0026] from Figure 1 It can be seen that the cell structure of the existing Flash Memory 500 is a multi-layer vertical structure, and the middle layer 540 between the control gate 50 and the floating gate 90 is made of ONO (SiO 2 / Si 3 N 4 / SiO 2 ) for insulation isolation. This Flash memory 500 has a high vertical structure density and fast read and write speed, but compared with the traditional CMOS (Complementary Metal Oxide Semiconductor) process, it requires more than five layers of MASK (mask), and the cost increases by more than 50%. In addition, the Flash memory 500 formed by the Flash process only has a storage function and is not compatible with the logic area, that is, it cannot form a logic chip.

[0027] As the integration of chip technology becomes higher and higher, people hope to integrate some simple storage functions ‌OTP (One Time Programmable) and MTP (Multiple-Time Programmable) functions into logic chips, that is, to implement storage functions through CMOS technology. In this regard, the embodiment of the present application designs a memory 300, which is a LNVM memory (Logic Non-Volatile Memory). The information stored in the memory 300 is usually stored in the memory 300 in the form of "logic 0" or "logic 1".

[0028] Please refer to Figure 2 , Figure 3 and Figure 4 , Figure 2 This is a schematic diagram of the structure of the memory 300 provided in the embodiment of the present application applied to the electronic device 1. Figure 3 This is a schematic diagram of the structure of the memory 300 provided in the embodiment of the present application applied to the logic chip 2. Figure 4 A schematic diagram of the structure of the memory 300 provided in an embodiment of the present application.

[0029] The embodiment of the present application provides an electronic device 1, which can be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product. Among them, the consumer electronic product can be a mobile phone, a tablet computer (pad), a laptop, an e-reader, a personal computer (PC), a personal digital assistant (PDA), a desktop display, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, etc. The home electronic product can be a smart door lock, a television, a remote control, a refrigerator, a rechargeable small household appliance (e.g., a soybean milk machine, a sweeping robot), etc. The vehicle-mounted electronic product can be a vehicle-mounted navigator, a vehicle-mounted high-density digital video disc (DVD), etc. The financial terminal product can be an automated teller machine (ATM), a terminal for self-service handling of services, etc. The communication electronic product can be a communication device such as a server, a radar, and a base station.

[0030] For example, Figure 2 As shown, the electronic device 1 includes a processor 100 and a memory 300. The processor 100 is used to access the memory 300 to write data to the memory 300 or read data from the memory 300. Exemplarily, the processor 100 may be a central processing unit (CPU) of the electronic device 1.

[0031] The embodiment of the present application also provides a logic chip 2, which includes a circuit board 400 and the above-mentioned memory 300, and the memory 300 is arranged on the circuit board 400. There may be multiple memories 300, and the multiple memories 300 include a first memory 310 and a second memory 330. Exemplarily, the first memory 310 is an ‌‌OTP (One Time Programmable) memory, and the second memory 330 is an MTP (Multiple-Time Programmable) memory, so as to integrate the functions of the OTP memory and the MTP memory into the logic chip 2. It can be understood that in some embodiments, the electronic device 1 may also include a processor 100 and a logic chip 2, and the processor 100 is used to access the memory 300 in the logic chip 2.

[0032] The memory 300 includes a memory array and a controller 303, or the memory 300 includes a memory circuit and a controller 303. The memory array or the memory circuit includes one or more memory cells 301. The controller is used to control access to the memory cell 301, write data to the memory cell 301, erase data, and read data from the memory cell 301, so as to implement writing, erasing, and reading of the memory array or the memory circuit. Exemplarily, the memory array includes a plurality of memory cells 301 arranged in an array.

[0033] Based on the storage unit 301 provided in the embodiment of the present application, the embodiment of the present application further provides an integrated circuit (IC), including one or more storage units 301. The specific structure of the storage unit 301 is described below.

[0034] See also Figure 5 and Figure 6 , Figure 5 for Figure 4 The storage unit 301 in the memory 300 is a schematic diagram of the structure of the first embodiment, Figure 6 for Figure 5 A schematic cross-sectional structure diagram of a storage unit 301 is shown.

[0035] For the convenience of description, we define Figure 5 The length direction of the storage unit 301 is the X-axis direction, the width direction is the Y-axis direction, and the thickness direction is the Z-axis direction. The X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other. The vertical direction mentioned in the embodiment of the present application when describing the storage unit 301 is the Z-axis direction, and the horizontal direction is the plane direction formed by the X-axis and the Y-axis, which does not constitute a limitation on the storage unit 301 in actual application scenarios.

[0036] Specifically, the memory cell 301 includes a substrate 10 , a first gate oxide layer 30 , a control gate 50 , a second gate oxide layer 70 and a floating gate 90 .

[0037] The substrate 10 may be a silicon substrate, an epitaxial silicon substrate, a silicon germanium semiconductor substrate, a silicon carbide substrate or a silicon-on-insulator (SOI) substrate. In this embodiment, the substrate 10 is a p-type silicon substrate.

[0038] The substrate 10 includes a first substrate region 11 and a second substrate region 13. The first substrate region 11 and the second substrate region 13 are arranged at intervals along the length direction of the substrate 10. In this embodiment, the first substrate region 11 is a source region, the second substrate region 13 is a drain region, and the source region and the drain region are arranged at intervals along the X-axis direction. Exemplarily, the source region and the drain region can be formed by performing p-type doping in the substrate 10. Exemplarily, the p-type doped element can be B (boron) element.

[0039] In this embodiment, the substrate 10 includes a first surface 15 and a second surface 17 that are arranged opposite to each other in the thickness direction. In this embodiment, the first surface 15 is the surface of the substrate 10 facing the negative direction of the Z axis, and the second surface 17 is the surface of the substrate 10 facing the positive direction of the Z axis. In this embodiment, the substrate 10 may further include a first doped well 101 and a second doped well 103, and the first doped well 101 and the second doped well 103 are arranged at intervals from each other. In this embodiment, the first doped well 101 is an n-doped well (n-well), and the second doped well 103 is an n-doped well (n-well), and an n-doped well can be obtained by forming an n-type doped region on a p-type substrate. The first doped well 101 and the second doped well 103 are arranged at intervals along the X-axis direction, and the first doped well 101 and the second doped well 103 are doped from the second surface 17 of the substrate 10 toward the first surface 15. Among them, the first doped well 101 is located on one side of the positive direction of the X axis, and the second doped well 103 is located on one side of the negative direction of the X axis. In this embodiment, the first substrate region 11 and the second substrate region 13 are both located in the second doped well 103.

[0040] The first gate oxide layer 30 is disposed on one side of the substrate 10 along the thickness direction. In this embodiment, the first gate oxide layer 30 is disposed on the second surface 17 of the substrate 10 and is located on one side of the first doped well 101 along the positive direction of the Z axis, and the projection of the first doped well 101 on the first gate oxide layer 30 covers the first gate oxide layer 30. The control gate 50 is disposed on the side of the first gate oxide layer 30 away from the substrate 10. Exemplarily, the material of the control gate 50 is polysilicon.

[0041] The second gate oxide layer 70 is provided on the substrate 10, and is located on the same side of the substrate 10 along the thickness direction as the first gate oxide layer 30, and is arranged at intervals along the length direction of the substrate 10. In this embodiment, the second gate oxide layer 70 is arranged at intervals with the first gate oxide layer 30 along the X-axis direction. Among them, the first gate oxide layer 30 is located on one side of the positive direction of the X-axis, and the second gate oxide layer 70 is located on one side of the negative direction of the X-axis. In this embodiment, the second gate oxide layer 70 is provided on the second surface 17 of the substrate 10, and is located on one side of the second doped well 103 along the positive direction of the Z-axis, and the projection of the second doped well 103 on the second gate oxide layer 70 covers the second gate oxide layer 70. The floating gate 90 is provided on the side of the second gate oxide layer 70 away from the substrate 10, so as to realize that the floating gate 90 and the control gate 50 are arranged in sequence along the horizontal direction of the storage unit 301. Exemplarily, the material of the floating gate 90 is polysilicon.

[0042] In the embodiment of the present application, the memory cell 301 further includes an STI (shallow trench isolation) layer 91. The STI layer 91 is disposed on the substrate 10 and is located between the first gate oxide layer 30 and the second gate oxide layer 70. The STI layer can be prepared by existing processes and will not be described in detail herein.

[0043] When the memory cell 301 is working, a voltage can be applied to the control gate 50, and then a voltage is formed on the floating gate 90 by capacitive coupling, so that the electrons in the substrate 10 migrate from the second surface 17 of the substrate 10, pass through the second gate oxide layer 70, enter and are stored in the floating gate 90, thereby storing electrons in the floating gate 90, and further writing data in the memory cell 301. By changing the voltage on the floating gate 90, the electrons stored in the floating gate 90 pass through the second gate oxide layer 70 to reach the substrate 10, thereby discharging the electrons stored in the floating gate 90, and further erasing data from the memory cell 301. By applying a voltage difference between the source (S) and the drain (D) of the memory cell 301 and reading the current of the memory cell 301, whether there are electrons in the floating gate 90 will affect the magnitude of the read current, and further used to determine whether the data in the memory cell 301 is "logic 1" or "logic 0".

[0044] In the memory cell 301 of the memory 300 provided in the embodiment of the present application, the first gate oxide layer 30 and the second gate oxide layer 70 are arranged on the same side of the substrate 10 along the thickness direction and are spaced apart along the length direction of the substrate 10, and the control gate 50 is arranged on the side of the first gate oxide layer 30 away from the substrate 10, and the floating gate 90 is arranged on the side of the second gate oxide layer 70 away from the substrate 10, so as to realize a structure in which the control gate 50 and the floating gate 90 are arranged in a horizontal direction in the lateral direction of the memory cell 301, that is, a memory cell 301 with a horizontal structure is formed, thereby solving the problem that a multi-layer MASK needs to be used because the memory cell is a multi-layer vertical structure in the existing Flash memory 500, thereby reducing the cost of the memory 300.

[0045] In addition, the Flash memory formed by the existing Flash process has two layers of Polysilicon, and the CMOS structure formed by the traditional CMOS process has only one layer of gate (Polysilicon) and no ONO isolation structure. Therefore, in order to realize the storage function, the embodiment of the present application makes a MOSCAP capacitor horizontally to control the voltage of the floating gate, that is, the control gate and the floating gate are arranged in the horizontal direction of the storage unit, forming a structure as shown in FIG. Figure 1 The LNVM memory with horizontal structure memory cells is shown. However, the memory cells in this structure are much larger. Taking the 180nm process as an example, the size of the memory cell of an ordinary MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is 0.2μm 2 The size of the Flash memory cell is 0.13μm. 2 (vertical structure), while the memory cell of LNVM memory (horizontal structure) exceeds 50μm 2 This greatly increases the overall area of ​​the logic chip formed by the memory assembly and increases the cost of the logic chip.

[0046] In order to further solve the size problem of the memory cell of the horizontal structure LNVM memory, the present application has studied and analyzed the capacitance C of the control gate 50. CG Reference formula 1: (Formula 1).

[0047] Among them, the capacitance C of the control gate 50 CG A refers to the capacitance formed between the control gate 50 and the substrate 10. 1 represents the area of ​​the control gate 50, d 1 represents the thickness of the first gate oxide layer 30, represents the dielectric constant of the first gate oxide layer 30. It is understood that the dielectric constant of the first gate oxide layer 30 may also be represented by k.

[0048] It can be seen from formula 1 that the capacitance C of the control gate 50 CG Affected by three parts, the thickness d of the first gate oxide layer 30 is 1 , the area A of the control gate 50 1 , the dielectric constant of the first gate oxide layer 30 between the control gate 50 and the substrate 10 The thickness d of the first gate oxide layer 30 is affected by the CMOS process and is usually a fixed value (3.3V IO 7mm). 3.3V IO means that the first gate oxide layer 30 will be broken down at a voltage of 3.3V. Therefore, the area A of the control gate 50 and the dielectric constant of the first gate oxide layer 30 are The larger the capacitance C of the control gate 50 is, CG The larger the dielectric constant of the first gate oxide layer 30 is, the The capacitance per unit area of ​​the control gate 50 is determined.

[0049] Based on the above research and analysis, the embodiment of the present application provides a feasible technical solution to reduce the area of ​​the memory cell 301 of the memory 300. Specifically, the embodiment of the present application provides a memory cell 301 of the memory 300, the first gate oxide layer 30 includes a first dielectric layer 33, and the dielectric constant of the first dielectric layer 33 is greater than 16. Exemplarily, the material of the first dielectric layer 33 can be TiN-ZAZ-TiN, Hf-doped ZrO 2 (HZO) thin film, TiO 2 , Al-doped TiO 2 , Perovskite SrTiO 3 (STO), HfO 2 The present application does not limit the material type of the first dielectric layer 33, and the material type can be selected according to the degree of compatibility with CMOS and the cost. 2 -Al 2 O 3 -ZrO 2 Composite film, ZrO 2 The film layer is a tetragonal phase with a dielectric constant of about 47.

[0050] In the memory cell 301 of the memory 300 provided in the embodiment of the present application, a first dielectric layer 33 having a high dielectric constant is added to the first gate oxide layer 30 to increase the dielectric constant of the first gate oxide layer 30, thereby increasing the capacitance value per unit area of ​​the control gate 50. This can reduce the size of the memory cell 301 by reducing the area A of the control gate 50, thereby facilitating reducing the overall size of the memory 300.

[0051] Specifically, in the storage unit 301 of the first embodiment, the first gate oxide layer 30 includes a first oxide layer 31 and a first dielectric layer 33. The first oxide layer 31 is disposed on the second surface 17 of the substrate 10. The first dielectric layer 33 is disposed on the side of the first oxide layer 31 away from the substrate 10 and is located between the first oxide layer 31 and the control gate 50. In this embodiment, the first oxide layer 31 is SiO 2 For example, the thickness of the first oxide layer 31 is 3 nm, and the thickness of the first dielectric layer 33 is 1 nm. The first dielectric layer 33 has a stronger ability to bind electrons than the first oxide layer 31, so that the insulation effect of the first dielectric layer 33 is better than that of the first oxide layer 31. In this embodiment, the first dielectric layer 33 with a high dielectric constant has a strong ability to bind electrons. The first dielectric layer 33 of about 1 nm and the SiO layer of 3 nm are 2 The layer can ensure that the first gate oxide layer 30 is not broken down.

[0052] In the storage unit 301 of the first embodiment, the first gate oxide layer 30 includes a first oxide layer 31 and a first dielectric layer 33, wherein the first dielectric layer 33 has a higher dielectric constant and can improve the dielectric constant of the first gate oxide layer 30, thereby improving the unit area capacitance of the storage unit 301, and further, the purpose of reducing the size of the storage unit 301 can be achieved by reducing the area A of the control gate 50.

[0053] It can be understood that since the first dielectric layer 33 has a relatively high ability to bind electrons, in other embodiments, the positions of the first oxide layer 31 and the first dielectric layer 33 can also be swapped, that is, the first gate oxide layer 30 can include a first dielectric layer 33 and a first oxide layer 31 stacked in sequence, the first dielectric layer 33 is arranged on the second surface 17 of the substrate 10, the first oxide layer 31 is arranged on the side of the first dielectric layer 33 away from the substrate 10, and the control gate 50 is arranged on the side of the first oxide layer 31 away from the first dielectric layer 33.

[0054] See also Figure 7 , Figure 7 for Figure 4 The cross-sectional structure diagram of the storage unit 301 in the memory 300 in the second embodiment is shown.

[0055] The difference between the memory cell 301 of the second embodiment and the memory cell 301 of the first embodiment is that the first gate oxide layer 30 of the memory cell 301 of the second embodiment does not contain SiO 2 layer.

[0056] The present application has also found that according to the capacitance series calculation formula (Formula 2), the capacitance increase caused by the high dielectric constant first dielectric layer 33 in the first gate oxide layer 30 of the storage unit 301 of the first embodiment will be reduced by the first oxide layer 31 (SiO 2 The capacitance of the capacitor is reduced by about 96%.

[0057] (Formula 2).

[0058] Wherein, C represents the capacitance of the first gate oxide layer 30 , C1 represents the capacitance of the first dielectric layer 33 , and C2 represents the capacitance of the first oxide layer 31 .

[0059] To this end, the embodiment of the present application also provides a storage unit 301 of the second embodiment, the first gate oxide layer 30 is a first dielectric layer 33, the first dielectric layer 33 is arranged on the second surface 17 of the substrate 10, and the control gate 50 is arranged on the side of the first dielectric layer 33 away from the substrate 10, so that the first dielectric layer 33 is arranged between the substrate 10 and the control gate 50. Exemplarily, the thickness of the first dielectric layer 33 is 1nm~2nm.

[0060] Compared with the storage unit 301 of the first embodiment, the first gate oxide layer 30 in the storage unit 301 provided in the second embodiment is a single-layer first dielectric layer 33, which does not contain SiO 2 On the one hand, the capacitance increase brought by the first dielectric layer 33 will not be diluted, and the capacitance increase is significant, so that the capacitance value per unit area of ​​the control gate 50 can be significantly increased, and the size of the storage unit 301 can be significantly reduced. On the one hand, the first dielectric layer 33 with a high dielectric constant has a strong ability to bind electrons, and the use of a thinner first dielectric layer 33 can also ensure that the first gate oxide layer 30 is not broken down. On the other hand, since electrons are only stored in the second gate oxide layer 70 of the floating gate 90 rather than the first gate oxide layer 30 under the control gate 50 when the memory 300 is working, the interface defects of the first dielectric layer 33 with a high dielectric constant have little effect on the performance of the memory 300, and the performance of the memory 300 can be guaranteed. It should be noted that in the storage unit 301 of the first embodiment, although the first oxide layer 31 (SiO 2 The first dielectric layer 33 will greatly dilute the capacitance increase effect brought by the first dielectric layer 33. However, compared with the conventional structure without using the first dielectric layer 33 with a high dielectric constant, the capacitance C of the control gate 50 is reduced. CG There will still be a 123% increase.

[0061] In addition, in the storage unit 301 of the second embodiment, a single-layer first dielectric layer 33 is used, and the thickness of the first dielectric layer 33 is 1nm~2nm. The thickness of the first dielectric layer 33 is ultra-thin, which can significantly increase the capacitance of the control gate 50, thereby significantly increasing the capacitance value per unit area of ​​the control gate 50, and further significantly reducing the size of the storage unit 301.

[0062] In this embodiment, the material of the first dielectric layer 33 is 1nm~2nm HfO 2 (Hafnium dioxide). When the material of the first dielectric layer 33 includes HfO 2 When the thickness of the first dielectric layer 33 decreases, HfO 2 The recrystallization temperature of the material will increase from 500°C to 700°C, which can significantly reduce HfO 2 The degree of recrystallization of the material when using the same atomic layer deposition (ALD) process. The long-range Coulomb scattering caused by recrystallization will significantly reduce the electron activity, thereby causing the performance of the memory 300 to deteriorate. Therefore, compared with other types of high dielectric constant materials, the material of the first dielectric layer 33 includes HfO 2 The memory 300 formed at the same time has better performance.

[0063] See also Figure 8 , Figure 8 for Figure 4 The schematic diagram of the cross-sectional structure of the storage unit 301 in the memory 300 in the third embodiment is shown. Figure 8 The trend chart of the right curve in the middle represents the change trend of the material content in each layer of the first gate oxide layer 30 , the realized curve trend represents the change trend of the material content of the first oxide layer 31 , and the dotted curve trend represents the change area of ​​the material content of the first dielectric layer 33 .

[0064] The difference between the storage unit 301 of the third embodiment and the storage unit 301 of the first embodiment is that the storage unit 301 of the third embodiment further includes a first transition layer 32 .

[0065] Specifically, in the storage unit 301 of the third embodiment, the first gate oxide layer 30 includes a first oxide layer 31, a first transition layer 32 and a first dielectric layer 33 which are stacked in sequence. The first oxide layer 31 is disposed on the second surface 17 of the substrate 10, the first transition layer 32 is disposed on a side of the first oxide layer 31 away from the substrate 10, and the first dielectric layer 33 is disposed on a side of the first transition layer 32 away from the first oxide layer 31. The control gate 50 is disposed on a side of the first dielectric layer 33 away from the first transition layer 32.

[0066] The material of the first transition layer 32 includes the material of the first oxide layer 31 and the material of the first dielectric layer 33. From the first oxide layer 31 to the first dielectric layer 33, that is, in this embodiment along the positive direction of the Z axis, the content of the material of the first oxide layer 31 in the first transition layer 32 gradually decreases (see Figure 8 The solid curve on the right side of the figure shows that the content of the material of the first dielectric layer 33 gradually increases (see Figure 8 The dotted curve on the right side of the graph).

[0067] For example, in this embodiment, the material of the first oxide layer 31 is SiO 2 , the material of the first dielectric layer 33 is HfO 2 For example, the material of the first transition layer 32 includes SiO 2 and HfO 2 , from the first oxide layer 31 to the first dielectric layer 33, the SiO 2 The content of HfO gradually decreases. 2 For example, the first transition layer 32 may be prepared by using the LLDA (Layer by Layer deposition and Annealing) process. Specifically, under high temperature annealing, part of the material of the first dielectric layer 33 may enter the SiO 2 layer, so it can be achieved by 2 The atomic layer deposition of the material of the first dielectric layer 33 is repeatedly performed on the layer surface and synchronous annealing is performed through programming to obtain the first transition layer 32 .

[0068] In the memory cell 301 of the third embodiment, on the one hand, by providing the first dielectric layer 33 with a high dielectric constant in the first gate oxide layer 30, the dielectric constant of the first gate oxide layer 30 is increased, thereby improving the unit area capacitance of the memory cell 301, and further, the purpose of reducing the size of the memory cell 301 can be achieved by reducing the area A of the control gate 50. On the other hand, by providing the first transition layer 32 between the first oxide layer 31 and the first dielectric layer 33, it is equivalent to gradually increasing the concentration of the material of the first dielectric layer 33 with a high dielectric constant in the material of the first oxide layer 31, so as to achieve a gradient change of the material of the first dielectric layer 33 in the first gate oxide layer 30. The first transition layer 32 plays a role of transition buffer between the first oxide layer 31 and the first dielectric layer 33, which can avoid the generation of interface defects between the first oxide layer 31 and the first dielectric layer 33 to a certain extent, thereby helping to improve the performance of the memory cell 301 to a certain extent.

[0069] It can be understood that, since the first dielectric layer 33 has a relatively high ability to bind electrons, in other embodiments, the positions of the first oxide layer 31 and the first dielectric layer 33 can also be swapped, that is, the first gate oxide layer 30 can include a first dielectric layer 33, a first transition layer 32 and a first oxide layer 31 stacked in sequence, the first dielectric layer 33 is arranged on the second surface 17 of the substrate 10, the first transition layer 32 is arranged on the side of the first dielectric layer 33 away from the substrate 10, the first oxide layer 31 is arranged on the side of the first transition layer 32 away from the first dielectric layer 33, and the control gate 50 is arranged on the side of the first oxide layer 31 away from the first transition layer 32.

[0070] In addition, the present application also studies and analyzes that in order to control the charge Q in the floating gate 90 FG , it is necessary to apply a voltage to the control gate 50 and change the voltage of the floating gate 90 by means of capacitive coupling. Among them, the voltage V of the control gate 50 CG and the charge Q of the floating gate 90 FG The relationship between them satisfies Formula 3 and Formula 4: (Formula 3), (Formula 4).

[0071] Among them, V OX V represents the voltage of the second gate oxide layer 70. CG represents the voltage of the control gate 50. V b represents the voltage of the substrate 10. Q FG represents the charge in the floating gate 90 in coulombs, α CG Denotes the coupling coefficient, C CG represents the capacitance of the control gate 50, C FG represents the capacitance of the floating gate 90. In the embodiment of the present application, the capacitance C of the control gate 50 CG It refers to the capacitance formed between the control gate 50 and the substrate 10, and the capacitance C of the floating gate 90 FG It refers to the capacitance formed between the floating gate 90 and the substrate 10.

[0072] It can be understood that the substrate 10 is usually grounded, and the potential of the substrate 10 is zero. b It is zero at this time.

[0073] It can be seen from formula 3 that at V OX 、V b , Q FG Under the condition of keeping unchanged, the voltage V of the control gate 50 CG With the coupling coefficient α CG The voltage V of the control gate 50 decreases with the increase of CG With the coupling coefficient α CGIt can be seen from formula 4 that the coupling coefficient α CG At the same time, the capacitance C of the controlled gate 50 CG and the capacitance C of the floating gate 90 FG The capacitance C of the control gate 50 is CG The larger the proportion, the greater the coupling coefficient α CG The higher the coupling coefficient, the higher the CG If it is too small, a larger voltage will be required on the control gate 50, and too high a voltage will cause serious damage to the first gate oxide layer 30 between the control gate 50 and the substrate 10, and the second gate oxide layer 70 between the floating gate 90 and the substrate 10, thereby causing the entire storage unit 301 to fail.

[0074] By reducing the voltage V CG It can ensure that the first gate oxide layer 30 and the second gate oxide layer 70 are not broken down. At the same time, according to Formula 3, when the voltage V CG When the coupling coefficient α remains unchanged, CG When the floating gate 90 is reduced, the charge Q FG That is, under the same voltage writing, the number of electrons in the floating gate 90 will decrease, thereby greatly increasing the probability of data reading errors in the storage unit 301, making it easy to read "logic 0" as "logic 1", or to read "logic 1" as "logic 0", thereby causing a BIT flip (Bit Flip).

[0075] Based on the above research and analysis, the present application embodiment also provides a feasible technical solution by increasing the coupling coefficient α CG To achieve a relatively low control gate 50 voltage V CG The purpose of data writing is completed under the same control gate voltage V CG The charge Q in the floating gate 90 is increased FG , thereby improving the data writing speed of the storage unit 301.

[0076] Combined with reference Fig. 9 , Fig. 9 for Figure 4 The schematic diagram of the cross-sectional structure of the storage unit 301 in the memory 300 in the fourth embodiment is shown.

[0077] The difference between the memory cell 301 of the fourth embodiment and the memory cell 301 of the first embodiment is that in the memory cell 301 of the fourth embodiment, the second gate oxide layer 70 includes a second dielectric layer 73 , and the dielectric constant of the second dielectric layer 73 is less than 3.

[0078] Specifically, in the storage unit 301 of the fourth embodiment, the first gate oxide layer 30 includes a first oxide layer 31 and a first dielectric layer 33. The first oxide layer 31 is disposed on the second surface 17 of the substrate 10. In this embodiment, the first oxide layer 31 is SiO 2 The first oxide layer 31 has a thickness of 3 nm. The first dielectric layer 33 is disposed on a side of the first oxide layer 31 away from the substrate 10. In this embodiment, the thickness of the first dielectric layer 33 is 1 nm. The control gate 50 is disposed on a side of the first dielectric layer 33 away from the first oxide layer 31.

[0079] The second gate oxide layer 70 includes a second oxide layer 71 and a second dielectric layer 73. The second oxide layer 71 is disposed on the second surface 17 of the substrate 10 and is spaced apart from the first oxide layer 31 along the length direction of the substrate 10. In this embodiment, the second oxide layer 71 is SiO 2 The second dielectric layer 73 is disposed on the side of the second oxide layer 71 facing away from the substrate 10, and the floating gate 90 is disposed on the side of the second dielectric layer 73 facing away from the second oxide layer 71. In this embodiment, the thickness of the second gate oxide layer 70 is greater than the thickness of the first gate oxide layer 30. Exemplarily, the thickness of the second oxide layer 71 is 3 nm, and the thickness of the second dielectric layer 73 is 7 nm. In this embodiment, the thickness of the second dielectric layer 73 is greater than the thickness of the second oxide layer 71.

[0080] Exemplarily, the material of the second dielectric layer 73 may be a silicon-based polymer HSQ (Hydrogensilsesquioxane), MSQ (methyl silsesquioxane), a porous HSQ or a porous MSQ or other low-K materials. The present application does not limit the selection of the material type of the second dielectric layer 73, as long as the capacitance C of the floating gate 90 can be reduced. FG The purpose can be.

[0081] Among them, porous HSQ and porous MSQ are formed by adding nano-scale cavities to HSQ and MSQ respectively. For example, nano-scale cavities are usually achieved by synthesizing block copolymers. Taking the preparation of porous MSQ as an example, MSQ is usually provided in the form of a solution, distributed on a silicon wafer by spin coating, and then heated under a protective atmosphere for cross-linking, and then the pore-generating groups are removed to form a porous structure similar to silica.

[0082] After research and analysis, the present application finds that in the memory cell 301 of the memory 300, the capacitor C of the floating gate 90 FG Refer to formula 5: (Formula 5). Where A 2represents the area of ​​the floating gate 90, d 2 represents the thickness of the second gate oxide layer 70, represents the dielectric constant of the second gate oxide layer 70. It can be understood that the dielectric constant of the second gate oxide layer 70 can also be represented by k.

[0083] Combining Formula 5 and Formula 4, it can be seen that by setting the second dielectric layer 73 to have a lower dielectric constant, the dielectric constant of the second gate oxide layer 70 can be reduced. , thereby reducing the capacitance C per unit area of ​​the floating gate 90 FG , increasing the capacitance C of the control gate 50 CG The proportion of can achieve the coupling coefficient α CG On the one hand, when the charge Q of the floating gate 90 FG When the coupling coefficient α remains unchanged, CG The increase in the voltage V applied to the control gate 50 can CG is reduced, that is, during the data writing process of the memory cell 301, the voltage V CG The voltage V of the control gate 50 is reduced, which is beneficial to improving the long-term reliability of the first gate oxide layer 30 under the control gate 50, thereby improving the life of the storage unit 301, and further improving the long-term reliability of the memory 300. At the same time, the requirement for the write voltage is reduced, and the voltage V of the control gate 50 is relatively low. CG The purpose of data writing is completed.

[0084] On the other hand, the current I of the floating gate 90 FG Satisfies Formula 6 and Formula 7, where I FG represents the current of the floating gate 90, E OX represents the electric field strength of the second gate oxide layer 70, V OX represents the voltage of the second gate oxide layer 70, d 2 represents the thickness of the second gate oxide layer 70 .

[0085] (Formula 6), (Formula 7).

[0086] When the voltage V CG When the coupling coefficient α remains unchanged, CG The increase of can increase the voltage of the second gate oxide layer 70, that is, the voltage formed on the floating gate 90 is increased, so that the electric field strength of the second gate oxide layer 70 is increased, that is, the amount of electricity Q written into the floating gate 90 within a certain period of time is increased. FG, so that the data writing speed (current) within the tolerable range of the second gate oxide layer 70 is significantly improved under the influence of the electric field strength, thereby achieving an increase in the data writing speed of the storage unit 301 and improving the data writing efficiency.

[0087] In addition, the thickness of the second gate oxide layer 70 is greater than the thickness of the first gate oxide layer 30, which can significantly reduce the capacitance C of the floating gate 90. FG , increasing the capacitance C of the control gate 50 CG The proportion of can achieve the coupling coefficient α CG improvement.

[0088] In addition, in the prior art, dielectric materials with a dielectric constant less than 3 are mainly used for filling dielectric layers between metal layers in the back end of the wafer. As the density of integrated circuits (ICs) increases, the number of connections in the back end is also increasing. The resistance and capacitance delay (RC delay) caused by metal connecting lines not only affects the speed of the chip, but also poses a serious threat to working reliability. The speed of circuit signal transmission depends on the product of parasitic resistance and parasitic capacitance. To solve the problem of RC delay, it is necessary to reduce parasitic resistance (copper interconnection instead of aluminum interconnection) and parasitic capacitance. The parasitic capacitance is proportional to the dielectric constant k of the isolation medium of the circuit layer. Therefore, using a low dielectric constant material (dielectric constant k<3) as the isolation medium of different circuit layers can achieve the purpose of reducing parasitic capacitance. In the embodiment of the present application, a second dielectric layer 73 with a dielectric constant less than 3 is applied to the second gate oxide layer 70 to achieve an increase in the coupling coefficient α by reducing the dielectric constant of the second gate oxide layer 70. CG The purpose is to improve the long-term reliability of the memory 300. At a relatively low voltage V of the control gate 50, CG The purpose of data writing is completed under the same control gate voltage V CG The purpose of improving the data writing speed of the storage unit 301 is to improve the data writing speed of the storage unit 301. At the same time, the second dielectric layer 73 with a low dielectric constant in the second gate oxide layer 70 can also achieve the effect of reducing the parasitic capacitance.

[0089] In the memory cell 301 of the fourth embodiment, on the one hand, by setting the first gate oxide layer 30 to include a first dielectric layer 33 with a high dielectric constant, the dielectric constant of the first gate oxide layer 30 is increased, thereby increasing the capacitance per unit area of ​​the control gate 50, and further reducing the area A of the control gate 50 to achieve the purpose of reducing the size of the memory cell 301. On the other hand, by setting the second gate oxide layer 70 to include a second dielectric layer 73 with a low dielectric constant, the dielectric constant of the second gate oxide layer 70 is reduced, thereby reducing the capacitance C of the floating gate 90. FG , achieving an increase in the coupling coefficient α CGThe purpose is to improve the long-term reliability of the memory 300. At a relatively low voltage V CG The purpose of data writing is completed under the same control gate voltage V CG The purpose is to improve the data writing speed of the storage unit 301.

[0090] In addition, the purpose of adding a second dielectric layer 73 with a low dielectric constant in the second gate oxide layer 70 is to reduce the capacitance C of the floating gate 90. FG However, the low dielectric constant will reduce the charge binding ability of the second dielectric layer 73. When the thickness of the second dielectric layer 73 is thin, it is easy to cause additional leakage or data loss. By increasing the thickness of the second dielectric layer 73 and providing the second oxide layer 71 between the substrate 10 and the second dielectric layer 73, the risk of leakage can be reduced and data loss can be avoided. In addition, the second oxide layer 71 (in this embodiment, SiO 2 The lattice matching between the second oxide layer 71 and the substrate 10 (the Si substrate in this embodiment) is high, which can alleviate the stress caused by lattice distortion during processing, thereby ensuring the integrity of the second oxide layer 71 and further ensuring the performance of the storage unit 301.

[0091] In addition, in the memory cell 301 of the fourth embodiment, the first gate oxide layer 30 retains the first oxide layer 31, and the first oxide layer 31 can be grown simultaneously with the second oxide layer 71 in the second gate oxide layer 70, thereby simplifying the processing technology of the memory cell 301. Specifically, in the memory cell 301 of the fourth embodiment, the first gate oxide layer 30 retains about 3 nm of SiO 2 layer, which can be connected with the SiO 2 The layers are generated simultaneously, which simplifies the processing technology of the storage unit 301.

[0092] See also Fig.10 , Fig.10 for Figure 4 The schematic diagram of the cross-sectional structure of the storage unit 301 in the memory 300 in the fifth embodiment is shown. Fig.10 The trend graph of the left curve in the middle represents the change area of ​​the material content in each layer of the second gate oxide layer 70, the solid line curve trend represents the change trend of the material content of the second oxide layer 71, and the dotted line curve trend represents the change trend of the material content of the second dielectric layer 73.

[0093] The memory cell 301 of the fifth embodiment is different from the memory cell 301 of the fourth embodiment in that the second gate oxide layer 70 of the memory cell 301 of the fifth embodiment further includes a second transition layer 72 .

[0094] Specifically, in the storage unit 301 of the fifth embodiment, the first gate oxide layer 30 includes a first oxide layer 31 and a first dielectric layer 33 which are stacked in sequence. The first oxide layer 31 is disposed on the second surface 17 of the substrate 10. In this embodiment, the first oxide layer 31 is SiO 2 The first dielectric layer 33 is disposed on a side of the first oxide layer 31 away from the substrate 10 , and the control gate 50 is disposed on a side of the first dielectric layer 33 away from the first oxide layer 31 .

[0095] The second gate oxide layer 70 includes a second oxide layer 71, a second transition layer 72, and a second dielectric layer 73 which are stacked in sequence. The second oxide layer 71 is disposed on the second surface 17 of the substrate 10 and is spaced apart from the first oxide layer 31 along the length direction of the substrate 10. In this embodiment, the second oxide layer 71 is SiO 2 The second transition layer 72 is disposed on the side of the second oxide layer 71 facing away from the substrate 10. The second dielectric layer 73 is disposed on the side of the second transition layer 72 facing away from the second oxide layer 71. Exemplarily, the thickness of the second oxide layer 71 is 3 nm, the thickness of the second transition layer 72 is 4 nm, and the thickness of the second dielectric layer 73 is 3 nm. The floating gate 90 is disposed on the side of the second dielectric layer 73 facing away from the second transition layer 72.

[0096] The material of the second transition layer 72 includes the material of the second oxide layer 71 and the material of the second dielectric layer 73. From the second oxide layer 71 to the second dielectric layer 73, that is, in the direction along the positive direction of the Z axis in this embodiment, the content of the material of the second oxide layer 71 in the second transition layer 72 gradually decreases (see Fig.10 The solid line curve on the left side of the figure shows that the content of the material of the second dielectric layer 73 gradually increases (see Fig.10 The dotted curve trend on the left side of the figure).

[0097] Exemplarily, in this embodiment, the material of the second oxide layer 71 is SiO 2 For example, the material of the second dielectric layer 73 is HSQ material, and the material of the second transition layer 72 includes SiO 2 and HSQ, from the second oxide layer 71 to the second dielectric layer 73, the SiO 2 The content of HSQ gradually decreases, and the content of HSQ gradually increases. For example, the second transition layer 72 can be prepared by LLDA (Layer by Layer deposition and Annealing) process. Specifically, under high temperature annealing, part of the material of the second dielectric layer 73 will enter the SiO 2 layer, so it can be achieved by 2 The atomic layer deposition of the material of the second dielectric layer 73 is repeatedly performed on the layer surface and synchronous annealing is performed through programming to obtain the second transition layer 72 .

[0098] The present application has found that although the second oxide layer 71 (SiO 2 The lattice matching of the second oxide layer 71 and the substrate 10 (the Si substrate in this embodiment) is high, which can alleviate the stress caused by the lattice distortion during the processing and ensure the integrity of the second oxide layer 71. However, in the processing of the second gate oxide layer 70, interface defects will inevitably be generated at the interface between the second oxide layer 71 and the second dielectric layer 73. In the process of electrons passing through the second gate oxide layer 70 from the substrate 10 and migrating to the floating gate 90, the electrons are likely to be retained at the interface defects, or slowly diffuse into the floating gate 90 again over time, thereby reducing the floating gate 90's ability to retain data (electrons). In the process of reading data from the storage unit 301, it is easy to misread "logic 1" as "logic 0" or "logic 1" as "logic 0", thereby affecting the accuracy of reading data from the storage unit 301.

[0099] In order to further enhance the data (electron) retention capability of the floating gate 90 and alleviate the fluctuation of the threshold voltage caused by the interface defects capturing electrons, the second transition layer 72 is provided between the second oxide layer 71 and the second dielectric layer 73 in the present embodiment, so as to realize that the content of the material of the second oxide layer 71 in the second gate oxide layer 70 gradually decreases and the content of the material of the second dielectric layer 73 gradually increases from the second oxide layer 71 to the second dielectric layer 73, which is equivalent to gradually increasing the concentration of the material of the second dielectric layer 73 with a low dielectric constant in the material of the second oxide layer 71, thereby realizing the gradient change of the material of the second dielectric layer 73 in the second gate oxide layer 70, so that the second transition layer 72 plays a good transition buffer role between the second oxide layer 71 and the second dielectric layer 73, thereby reducing the interface defects between the second oxide layer 71 and the second dielectric layer 73, and further ensuring the data retention capability and low leakage current of the floating gate 90.

[0100] In the memory cell 301 provided in the fifth embodiment, on the one hand, a first dielectric layer 33 with a high dielectric constant is provided in the first gate oxide layer 30 to improve the dielectric constant of the first gate oxide layer 30, thereby improving the unit area capacitance of the memory cell 301, and further reducing the area A of the control gate 50 to achieve the purpose of reducing the size of the memory cell 301. On the other hand, by providing the second gate oxide layer 70 with a second dielectric layer 73 with a low dielectric constant to reduce the dielectric constant of the second gate oxide layer 70, the capacitance C of the floating gate 90 can be reduced. FG , achieving an increase in the coupling coefficient α CG The purpose is to improve the long-term reliability of the memory 300. At a relatively low voltage V CGThe purpose of data writing is completed under the same control gate voltage V CG On the other hand, by arranging the second transition layer 72 between the second oxide layer 71 and the second dielectric layer 73, it is equivalent to gradually increasing the concentration of the material of the second dielectric layer 73 with a low dielectric constant in the material of the second oxide layer 71, so as to achieve a gradient change of the material of the second dielectric layer 73 in the second gate oxide layer 70, thereby reducing the interface defects generated between the second oxide layer 71 and the second dielectric layer 73, preventing the interface defects from capturing electrons and causing threshold voltage fluctuations, ensuring the data retention capability and low leakage current of the floating gate 90, and thus improving the performance of the memory cell 301.

[0101] See also Fig.11 , Fig.11 for Figure 4 The schematic diagram of the cross-sectional structure of the storage unit 301 in the memory 300 in the sixth embodiment is shown.

[0102] The difference between the memory cell 301 of the sixth embodiment and the memory cell 301 of the fourth embodiment is that the first gate oxide layer 30 in the memory cell 301 of the sixth embodiment is a first dielectric layer 33 .

[0103] Specifically, in the memory cell 301 of the sixth embodiment, the first dielectric layer 33 is disposed on the second surface 17 of the substrate 10, and the control gate 50 is disposed on the side of the first dielectric layer 33 facing away from the substrate 10. The second gate oxide layer 70 includes a second oxide layer 71 and a second dielectric layer 73. The second oxide layer 71 is disposed on the second surface 17 of the substrate 10, and is spaced apart from the first dielectric layer 33 along the length direction of the substrate 10. The second dielectric layer 73 is disposed on the side of the second oxide layer 71 facing away from the substrate 10, and the floating gate 90 is disposed on the side of the second dielectric layer 73 facing away from the second oxide layer 71.

[0104] The memory cell 301 provided in the sixth embodiment, on the one hand, by setting the first gate oxide layer 30 as a first dielectric layer 33 with a high dielectric constant, the dielectric constant of the first gate oxide layer 30 is significantly increased, thereby significantly increasing the capacitance per unit area of ​​the control gate 50, and further reducing the area A of the control gate 50 to achieve the purpose of reducing the size of the memory cell 301. On the other hand, by setting the second gate oxide layer 70 to include a second dielectric layer 73 with a low dielectric constant, the dielectric constant of the second gate oxide layer 70 is reduced, thereby reducing the capacitance C of the floating gate 90. FG , achieving an increase in the coupling coefficient α CG The purpose is to improve the long-term reliability of the memory 300. At a relatively low voltage V CGThe purpose of data writing is completed under the same control gate voltage V CG The purpose is to improve the data writing speed of the storage unit 301.

[0105] See also Fig.12 , Fig.12 for Figure 4 The cross-sectional structure diagram of the storage unit 301 in the memory 300 in the seventh embodiment is shown.

[0106] The difference between the memory cell 301 of the seventh embodiment and the memory cell 301 of the fifth embodiment is that the first gate oxide layer 30 in the memory cell 301 of the seventh embodiment is a first dielectric layer 33 .

[0107] Specifically, in the memory cell 301 of the seventh embodiment, the first dielectric layer 33 is disposed on the second surface 17 of the substrate 10, and the control gate 50 is disposed on the side of the first dielectric layer 33 facing away from the substrate 10. The second gate oxide layer 70 includes a second oxide layer 71, a second transition layer 72, and a second dielectric layer 73 stacked in sequence. The second oxide layer 71 is disposed on the second surface 17 of the substrate 10, and is spaced apart from the first dielectric layer 33 along the length direction of the substrate 10. The second transition layer 72 is disposed on the side of the second oxide layer 71 facing away from the substrate 10, the second dielectric layer 73 is disposed on the side of the second transition layer 72 facing away from the second oxide layer 71, and the floating gate 90 is disposed on the side of the second dielectric layer 73 facing away from the second transition layer 72.

[0108] The memory cell 301 provided in the seventh embodiment, on the one hand, by setting the first gate oxide layer 30 as a first dielectric layer 33 with a high dielectric constant, the dielectric constant of the first gate oxide layer 30 is significantly increased, thereby significantly increasing the capacitance per unit area of ​​the control gate 50, and further reducing the area A of the control gate 50 to achieve the purpose of reducing the size of the memory cell 301. On the other hand, by setting the second gate oxide layer 70 to include a second dielectric layer 73 with a low dielectric constant, the dielectric constant of the second gate oxide layer 70 is reduced, thereby reducing the capacitance C of the floating gate 90. FG , achieving an increase in the coupling coefficient α CG The purpose is to improve the long-term reliability of the memory 300. At a relatively low voltage V CG The purpose of data writing is completed under the same control gate voltage V CG The purpose is to improve the data writing speed of the storage unit 301. On the other hand, by setting the second gate oxide layer 70 to include the second transition layer 72, the interface defects between the second oxide layer 71 and the second dielectric layer 73 are avoided, thereby ensuring the data retention capability of the floating gate 90.

[0109] See also Fig.13 , Fig.13 for Figure 4 The cross-sectional structure diagram of the storage unit 301 in the memory 300 in the eighth embodiment is shown.

[0110] The difference between the memory cell 301 of the eighth embodiment and the memory cell 301 of the fourth embodiment is that in the memory cell 301 of the eighth embodiment, the first gate oxide layer 30 includes a first oxide layer 31 , a first transition layer 32 and a first dielectric layer 33 .

[0111] Specifically, in the memory cell 301 of the eighth embodiment, the first oxide layer 31 is disposed on the second surface 17 of the substrate 10, the first transition layer 32 is disposed on the side of the first oxide layer 31 away from the substrate 10, and the first dielectric layer 33 is disposed on the side of the first transition layer 32 away from the first oxide layer 31. The control gate 50 is disposed on the side of the first dielectric layer 33 away from the first transition layer 32.

[0112] The second gate oxide layer 70 includes a second oxide layer 71 and a second dielectric layer 73. The second oxide layer 71 is disposed on the second surface 17 of the substrate 10 and is spaced apart from the first oxide layer 31 along the length direction of the substrate 10. The second dielectric layer 73 is disposed on a side of the second oxide layer 71 away from the substrate 10, and the floating gate 90 is disposed on a side of the second dielectric layer 73 away from the second oxide layer 71.

[0113] In the memory cell 301 of the eighth embodiment, on the one hand, a first dielectric layer 33 with a high dielectric constant is provided in the first gate oxide layer 30 to improve the dielectric constant of the first gate oxide layer 30, thereby improving the unit area capacitance of the memory cell 301, and further reducing the area A of the control gate 50 to achieve the purpose of reducing the size of the memory cell 301. On the one hand, a first transition layer 32 is provided between the first oxide layer 31 and the first dielectric layer 33, which is equivalent to gradually increasing the concentration of the material of the first dielectric layer 33 with a high dielectric constant in the material of the first oxide layer 31, so as to achieve a gradient change of the material of the first dielectric layer 33 in the first gate oxide layer 30, thereby avoiding interface defects and further improving the performance of the memory cell 301. On the other hand, the second gate oxide layer 70 is provided to include a second dielectric layer 73 with a low dielectric constant to reduce the dielectric constant of the second gate oxide layer 70, thereby reducing the capacitance C of the floating gate 90. FG , achieving an increase in the coupling coefficient α CG The purpose is to improve the long-term reliability of the memory 300. At a relatively low voltage V CG The purpose of data writing is completed under the same control gate voltage V CG The purpose is to improve the data writing speed of the storage unit 301.

[0114] See also Fig.14 , Fig.14 for Figure 4 The schematic diagram of the cross-sectional structure of the storage unit 301 in the memory 300 in the ninth embodiment is shown.

[0115] The difference between the memory cell 301 of the ninth embodiment and the memory cell 301 of the eighth embodiment is that the second gate oxide layer 70 in the memory cell 301 of the fifth embodiment further includes a second transition layer 72 .

[0116] Specifically, in the storage unit 301 of the ninth embodiment, the first gate oxide layer 30 includes a first oxide layer 31, a first transition layer 32 and a first dielectric layer 33 which are stacked in sequence. The first oxide layer 31 is disposed on the second surface 17 of the substrate 10, the first transition layer 32 is disposed on a side of the first oxide layer 31 away from the substrate 10, and the first dielectric layer 33 is disposed on a side of the first transition layer 32 away from the first oxide layer 31. The control gate 50 is disposed on a side of the first dielectric layer 33 away from the first transition layer 32.

[0117] The second gate oxide layer 70 includes a second oxide layer 71, a second transition layer 72, and a second dielectric layer 73 which are stacked in sequence. The second oxide layer 71 is disposed on the second surface 17 of the substrate 10, and is spaced apart from the first oxide layer 31 along the length direction of the substrate 10. The second transition layer 72 is disposed on a side of the second oxide layer 71 away from the substrate 10, the second dielectric layer 73 is disposed on a side of the second transition layer 72 away from the second oxide layer 71, and the floating gate 90 is disposed on a side of the second dielectric layer 73 away from the second transition layer 72.

[0118] In the memory cell 301 of the ninth embodiment, on the one hand, by setting the first gate oxide layer 30 as the first dielectric layer 33 with a high dielectric constant, the dielectric constant of the first gate oxide layer 30 is significantly improved, so that the capacitance per unit area of ​​the control gate 50 can be significantly improved, and then the size of the memory cell 301 can be reduced by reducing the area A of the control gate 50. On the other hand, by setting the first transition layer 32 between the first oxide layer 31 and the first dielectric layer 33, it is equivalent to gradually increasing the concentration of the material of the first dielectric layer 33 with a high dielectric constant in the material of the first oxide layer 31, so as to achieve a gradient change of the material of the first dielectric layer 33 in the first gate oxide layer 30, so as to avoid interface defects, and then improve the performance of the memory cell 301.

[0119] On the one hand, by setting the second gate oxide layer 70 to include a second dielectric layer 73 with a low dielectric constant, the dielectric constant of the second gate oxide layer 70 is reduced, thereby reducing the capacitance C of the floating gate 90. FG , achieving an increase in the coupling coefficient α CG The purpose is to improve the long-term reliability of the memory 300. At a relatively low voltage V CGThe purpose of data writing is completed under the same control gate voltage V CG The purpose is to improve the data writing speed of the storage unit 301. On the other hand, by setting the second gate oxide layer 70 to include the second transition layer 72, the interface defects between the second oxide layer 71 and the second dielectric layer 73 are avoided, thereby ensuring the data retention capability of the floating gate 90.

[0120] See also Fig.15 and Fig.16 , Fig.15 for Figure 4 The schematic diagram of the structure of the storage unit 301 in the memory 300 in the tenth embodiment is shown. Fig.16 for Fig.15 A schematic cross-sectional structure diagram of a storage unit 301 is shown.

[0121] The difference between the memory cell 301 of the tenth embodiment and the memory cell 301 of the first embodiment is that in the memory cell 301 of the tenth embodiment, the floating gate 90 and the control gate 50 are located in the same layer.

[0122] Specifically, a polysilicon layer may be provided on the side of the first gate oxide layer 30 and the second gate oxide layer 70 facing away from the substrate 10 , and the floating gate 90 and the control gate 50 are located in different regions of the polysilicon layer along the length direction of the substrate 10 .

[0123] It can be understood that in the memory cell 301 of the tenth embodiment, the first gate oxide layer 30 and the second gate oxide layer 70 can be selected from any structure of the first gate oxide layer 30 and the second gate oxide layer 70 in the memory cells 301 of the first to ninth embodiments.

[0124] The effect of the storage unit 301 provided in the embodiment of the present application is described below in combination with specific calculation data.

[0125] Taking the structure of the memory cell 301 of the second embodiment as an example, compared with the first gate oxide layer 30 which is entirely made of SiO 2 The first gate oxide layer 30 in the memory cell 301 of the second embodiment all uses a dielectric constant When the dielectric material is 30%, the gate oxide capacitance per unit area of ​​the control gate 50 can be increased by more than 5000%. Referring to Formula 1, while ensuring the same capacitance C of the control gate 50 CGIn this case, the area of ​​the control gate 50 can be reduced horizontally to 2% of the original area, a reduction of 98%. Assuming that the structural size of the floating gate 90 is equivalent to the structural size of the control gate 50, the area of ​​the storage unit 301 of the entire memory 300 is reduced to half of the reduction of the control gate 50 structural area, which is about 4%, a reduction of 96%. In the actual storage unit 301 structure, the proportion of the area of ​​the control gate 50 is much larger than the proportion of the area of ​​the floating gate 90, so the overall size reduction of the storage unit 301 will be closer to 2% rather than 4%, and the area of ​​the storage unit 301 is about 1μm 2 This reduction can significantly reduce the area used by MTP memory, OTP memory and other memories on the logic chip 2, and is infinitely close to the area of ​​the storage unit of the vertical Flash memory (about 0.13μm 2 ), thereby expanding the cost advantage of memory 300.

[0126] Taking the structure of the memory cell 301 of the fourth embodiment as an example, it is assumed that the material of the second oxide layer 71 in the second gate oxide layer 70 is SiO2 with a dielectric constant k value of 4. 2 The material of the second dielectric layer 73 has a dielectric constant (k) value is 2 for low dielectric constant materials. If the original coupling coefficient α CG is 60%, referring to Formula 3 and Formula 4, the new coupling coefficient α CG can be increased to 70%, and the total capacitance of the memory cell 301 structure is reduced to 85% of the original. When the charge Q in the floating gate 90 FG When the voltage required to control the gate 50 is kept consistent, it is 5 / 3V ox Reduced to 4 / 3V ox , which is reduced by about 20%. This means that during the data writing process of the storage unit 301, the voltage value applied by the control gate 50 can be reduced by 20% compared with the conventional solution, thereby improving the long-term reliability of the first gate oxide layer 30. Similarly, it is possible to choose not to reduce the voltage V CG , referring to Formula 6 and Formula 7, the speed (current) of data writing within the tolerable range of the second gate oxide layer 70 will be significantly improved under the influence of the electric field strength.

[0127] What is disclosed above is only a preferred embodiment of the present application, and it certainly cannot be used to limit the scope of rights of the present application. Ordinary technicians in this field can understand that all or part of the processes of implementing the above embodiments and equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A storage unit, characterized in that: The storage unit comprises: substrate; A first gate oxide layer and a control gate, wherein along the thickness direction of the substrate, the first gate oxide layer is arranged on one side of the substrate, and the control gate is arranged on a side of the first gate oxide layer away from the substrate; A second gate oxide layer and a floating gate; the second gate oxide layer is provided on the substrate and is located on the same side of the substrate along the thickness direction as the first gate oxide layer, the second gate oxide layer and the first gate oxide layer are spaced apart along the length direction of the substrate, and the floating gate is provided on a side of the second gate oxide layer away from the substrate; The first gate oxide layer includes a first dielectric layer, and the dielectric constant of the first dielectric layer is greater than 16.

2. The storage unit according to claim 1, characterized in that The first gate oxide layer comprises a first oxide layer and a first dielectric layer stacked in sequence, the first oxide layer is arranged on the substrate, the first dielectric layer is arranged on a side of the first oxide layer away from the substrate, and the control gate is arranged on a side of the first dielectric layer away from the first oxide layer; Alternatively, the first gate oxide layer is the first dielectric layer, the first dielectric layer is disposed on the substrate, and the control gate is disposed on a side of the first dielectric layer away from the substrate; Alternatively, the first gate oxide layer comprises a first oxide layer, a first transition layer and a first dielectric layer which are sequentially stacked, the first oxide layer is arranged on the substrate, the first transition layer is arranged on a side of the first oxide layer away from the substrate, the first dielectric layer is arranged on a side of the first transition layer away from the first oxide layer, and the control gate is arranged on a side of the first dielectric layer away from the first transition layer, wherein the material of the first transition layer comprises the material of the first oxide layer and the material of the first dielectric layer, and the content of the material of the first oxide layer in the first transition layer gradually decreases and the content of the material of the first dielectric layer gradually increases from the first oxide layer to the first dielectric layer; Alternatively, the first gate oxide layer includes the first dielectric layer and the first oxide layer stacked in sequence, the first dielectric layer is provided on the substrate, the first oxide layer is provided on a side of the first dielectric layer away from the substrate, and the control gate is provided on a side of the first oxide layer away from the first dielectric layer; Alternatively, the first gate oxide layer includes a first dielectric layer, a first transition layer and a first oxide layer which are stacked in sequence, the first dielectric layer is arranged on the substrate, the first transition layer is arranged on a side of the first dielectric layer away from the substrate, the first oxide layer is arranged on a side of the first transition layer away from the first dielectric layer, and the control gate is arranged on a side of the first oxide layer away from the first transition layer, wherein the material of the first transition layer includes the material of the first oxide layer and the material of the first dielectric layer, and the content of the material of the first oxide layer in the first transition layer gradually decreases and the content of the material of the first dielectric layer gradually increases from the first oxide layer to the first dielectric layer.

3. The storage unit according to claim 1, characterized in that The thickness of the first dielectric layer is 1 nm to 2 nm.

4. The storage unit according to claim 1, characterized in that The material of the first dielectric layer includes HfO2.

5. The storage unit according to any one of claims 1 to 4, characterized in that: The second gate oxide layer includes a second dielectric layer, and the dielectric constant of the material of the second dielectric layer is less than 3.

6. The storage unit according to claim 5, characterized in that The second gate oxide layer includes a second oxide layer and the second dielectric layer. The second oxide layer is arranged between the substrate and the second dielectric layer. The floating gate is arranged on a side of the second dielectric layer away from the second oxide layer.

7. The storage unit according to claim 6, characterized in that The second gate oxide layer further includes a second transition layer, and the second transition layer is arranged between the second oxide layer and the second dielectric layer; The material of the second transition layer includes the material of the second oxide layer and the material of the second dielectric layer. From the second oxide layer to the second dielectric layer, the content of the material of the second oxide layer in the second transition layer gradually decreases, and the content of the material of the second dielectric layer gradually increases.

8. The storage unit according to any one of claims 1 to 4, characterized in that: The thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer.

9. An integrated circuit, characterized in that: The integrated circuit comprises one or more memory cells as claimed in any one of claims 1 to 8.

10. A memory, characterized in that: The memory comprises a controller and one or more storage units according to any one of claims 1 to 8, wherein the controller is used to control access to the storage units.

11. A logic chip, characterized in that: The logic chip includes a circuit board and the memory as claimed in claim 10, wherein the memory is integrated with the circuit board.

12. An electronic device, characterized in that: The electronic device comprises a processor and the memory as claimed in claim 10, wherein the processor is used to access the memory, or the electronic device comprises a processor and the logic chip as claimed in claim 11, wherein the processor is used to access the memory in the logic chip.

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