Method for improving morphology of junction of gate oxides with different thicknesses on STI (shallow trench isolation)

Abstract

The invention provides a method for improving morphology of junctions of gate oxides with different thicknesses on STI (shallow trench isolation), and the method comprises the steps: 1, providing a substrate, forming shallow trench isolation on the substrate, and forming a gate oxide layer on the substrate; step 2, after a photoresist mask layer is formed, etching the exposed gate oxide layer; 3, trimming the photoresist mask layer to adjust the boundary of the photoresist mask layer; 4, etching the exposed gate oxide layer again; and 5, after the photoresist mask layer is removed, forming a grid electrode on the substrate. According to the invention, the boundary of the photoresist mask layer is adjusted step by step through multiple times of finishing of the photoresist mask layer formed on the gate oxide layer, and one time of etching of the gate oxide layer is carried out after each time of finishing, so that a gate-oxide junction with smooth morphology can be obtained, residues formed at the gate-oxide junction in a subsequent process are reduced, and the performance of a device is further improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for improving the morphology of a junction of gate oxides of different thicknesses on a STI. Background Art

[0002] In CMOS device technology, especially in the technology involving high voltage devices and memory devices, it is often necessary to prepare devices with thicker gate oxides. When manufacturing the gate oxides of these devices, it is generally done by Figure 1 The dual gate process shown in the figure will cause different types of devices to form a gate oxide boundary on the shallow trench isolation (STI). If this boundary step is deep or steep, it will cause challenges to subsequent processes, such as the formation of polysilicon (poly) etching residues, spacer etching residues, etc. The presence of these residues may affect the normal operation of the device or circuit. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of this application is to provide a method for improving the morphology of the junction of gate oxides of different thicknesses on STI, so as to solve the problem in the prior art that the poor morphology of the junction of gate oxides of different thicknesses on STI affects device performance.

[0004] To achieve the above-mentioned purpose and other related purposes, the present application provides a method for improving the morphology of the junction of gate oxides of different thicknesses on STI, comprising:

[0005] Step 1, providing a substrate, forming shallow trench isolation on the substrate, and forming a gate oxide layer on the substrate;

[0006] Step 2, after forming a photoresist mask layer, etching the exposed gate oxide layer;

[0007] Step 3, trimming the photoresist mask layer to adjust the boundary of the photoresist mask layer;

[0008] Step 4, etching the exposed gate oxide layer again;

[0009] Step five, after removing the photoresist mask layer, a gate is formed on the substrate.

[0010] Preferably, step three to step four are repeatedly implemented until the morphology of the junction of gate oxides with different thicknesses on the STI is smooth.

[0011] Preferably, the process is repeated at least twice.

[0012] Preferably, each time step 4 is performed, the etching amount of the gate oxide layer is determined according to the total etching amount of the gate oxide layer and the number of repetitions of step 4.

[0013] Preferably, the gate oxide layer is formed by a deposition process.

[0014] Preferably, in step three, the photoresist mask layer is trimmed by a photoresist hardening process.

[0015] Preferably, the photoresist hardening process is implemented by ultraviolet irradiation, heating or plasma bombardment.

[0016] Preferably, the etching of the gate oxide layer is wet etching.

[0017] Preferably, the wet etching solution includes diluted hydrofluoric acid.

[0018] Preferably, in step five, the photoresist mask layer is removed by a stripping process.

[0019] As described above, the method provided in the present application for improving the morphology of the junction between gate oxides of different thicknesses on STI has the following beneficial effects: by gradually adjusting the boundary of the photoresist mask layer by multiple trimmings of the photoresist mask layer formed on the gate oxide layer, and etching the gate oxide layer once after each trimming, a gate oxide junction with a smooth morphology can be obtained, thereby reducing the residue formed at the gate oxide junction in subsequent processes, thereby improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 It is a schematic diagram of the cross-sectional structure of a device in which polysilicon residues are formed at the junction of gate oxides of different thicknesses on STI in the existing dual-gate process;

[0022] Figure 2 A flow chart showing a method for improving the morphology of the junction of gate oxides of different thicknesses on STI provided in an embodiment of the present application;

[0023] Figure 3A-3E It is a schematic diagram of the cross-sectional structure of a device formed after each step is completed in the method for improving the morphology of the junction of gate oxides of different thicknesses on STI provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0025] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0026] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0027] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0028] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0029] like Figure 1 As shown in the figure, after forming gate oxides of different thicknesses in different regions of the substrate, an interface of gate oxides of different thicknesses will be formed on the STI. When a polysilicon gate is subsequently formed, polysilicon residues will be generated at the interface of the gate oxide on the STI. Other subsequent processes will also form residues at the interface of the gate oxide on the STI, such as the sidewall residues generated by the sidewall process, and the above residues will affect the performance of the device.

[0030] In order to solve this problem, the present application provides a method for improving the morphology of the junction between gate oxides of different thicknesses on STI.

[0031] See also Figure 2 , which shows a flow chart of a method for improving the morphology of the junction of gate oxides of different thicknesses on STI provided by an embodiment of the present application.

[0032] like Figure 2 As shown, the method for improving the morphology of the junction of gate oxides with different thicknesses on the STI includes the following steps:

[0033] Step 1, providing a substrate, forming shallow trench isolation on the substrate, and forming a gate oxide layer on the substrate;

[0034] Step 2, after forming a photoresist mask layer, etching the exposed gate oxide layer;

[0035] Step 3, trimming the photoresist mask layer to adjust the boundary of the photoresist mask layer;

[0036] Step 4, etching the exposed gate oxide layer again;

[0037] Step five, after removing the photoresist mask layer, a gate is formed on the substrate.

[0038] In step 1, optionally, the substrate 300 is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the material of the substrate 300 may also include other materials, such as III-V compounds such as gallium arsenide. Those skilled in the art can select the constituent material of the substrate 300 according to the type of device structure formed on the substrate 300, so the type of the substrate 300 should not limit the protection scope of the present invention.

[0039] Shallow trench isolation 301 is formed on the substrate 300 to divide the substrate 300 into a plurality of regions where different types of devices can be formed.

[0040] Exemplarily, the shallow trench isolation 301 is formed by a shallow trench isolation process, and the shallow trench isolation process includes but is not limited to shallow trench etching, oxide filling and oxide planarization.

[0041] Shallow trench etching includes but is not limited to isolation oxide layer, nitride precipitation, shallow trench isolation using mask, and STI shallow trench etching. STI oxide filling includes but is not limited to trench liner silicon oxide, trench CVD (chemical vapor deposition) oxide filling or PVD (physical vapor deposition) oxide filling. The planarization of the silicon wafer surface can be achieved by a variety of methods. The planarization of the silicon wafer can be achieved by filling the gap with SOG (spin-on-glass). SOG can be composed of 80% solvent and 20% silicon dioxide. After deposition, SOG is baked to evaporate the solvent and leave silicon dioxide in the gap. The entire surface can also be reversed to reduce the thickness of the entire silicon wafer. The planarization process can also be effectively performed by CMP process (also known as chemical mechanical polishing process), including but not limited to polishing the trench oxide (chemical mechanical polishing can be used) and nitride removal.

[0042] Illustratively, a gate oxide layer 302 is formed on the substrate 300 by a deposition process.

[0043] In step 2, the step of forming a photoresist mask layer 303 includes: forming a photoresist on the gate oxide layer 302 by a spin coating process; forming a photoresist mask layer 303 by an exposure and development process, and the photoresist mask layer 303 covers the area of ​​the substrate 300 where a thick gate oxide needs to be formed.

[0044] Exemplarily, the etching of the gate oxide layer 302 is wet etching, and the wet etching solution includes diluted hydrofluoric acid.

[0045] In step three, the photoresist mask layer 303 is trimmed by a photoresist hardening process to adjust the boundary of the photoresist mask layer 303 .

[0046] Exemplarily, the photoresist hardening process is implemented by ultraviolet irradiation, heating, plasma bombardment, etc. When the photoresist hardening process is implemented, the photoresist mask layer 303 will shrink to a certain extent, and its boundary will be adjusted.

[0047] In order to make the morphology of the interface between the gate oxide layers 302 of different thicknesses on the shallow trench isolation 301 smooth, step three is repeated at least twice.

[0048] In step 4, the trimmed photoresist mask layer 303 is used as a mask to etch the exposed gate oxide layer 302 again. Exemplarily, the etching is wet etching, and the wet etching solution includes diluted hydrofluoric acid.

[0049] Since the number of repetitions of step 4 is at least two, the etching amount of each etching is determined according to the total etching amount of the gate oxide layer 302 and the number of repetitions of step 4.

[0050] In step five, the photoresist mask layer 303 is removed by a stripping process. Exemplarily, the stripping process includes etching or ashing.

[0051] Next, a gate 305 is formed on the substrate 300. Exemplarily, the material of the gate 305 includes polysilicon.

[0052] As an example, the steps of forming the gate 305 include: forming a gate material layer on the substrate 300 through a deposition process, and the deposition process is preferably a conformal deposition process; forming a mask layer having a gate 305 pattern on the gate material layer through a photolithography and etching process; etching the gate material layer using the mask layer as a mask; and removing the mask layer after the etching is completed.

[0053] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0054] In summary, the method for improving the morphology of the junction of gate oxides of different thicknesses on the STI provided by the present application gradually adjusts the boundary of the photoresist mask layer by multiple trimmings of the photoresist mask layer formed on the gate oxide layer, and performs an etching of the gate oxide layer after each trimming, so as to obtain a gate oxide junction with a smooth morphology, reduce the residue formed at the gate oxide junction in the subsequent process, and thus improve the device performance. Therefore, the present application effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0055] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present application.

Claims

1. A method for improving the morphology of the junction of gate oxides of different thicknesses on STI, characterized in that: The method comprises: Step 1, providing a substrate, wherein shallow trench isolation is formed on the substrate, and a gate oxide layer is formed on the substrate; Step 2, after forming a photoresist mask layer, etching the exposed gate oxide layer; Step three, trimming the photoresist mask layer to adjust the boundary of the photoresist mask layer; Step 4, etching the exposed gate oxide layer again; Step five: after removing the photoresist mask layer, forming a gate on the substrate.

2. The method according to claim 1, characterized in that Repeat step 3 to step 4 until the morphology of the junction of gate oxides with different thicknesses on the STI is smooth.

3. The method according to claim 2, characterized in that The repetition is performed at least twice.

4. The method according to claim 2, characterized in that: Each time the step 4 is performed, the etching amount of the gate oxide layer is determined according to the total etching amount of the gate oxide layer and the number of repetitions of the step 4.

5. The method according to claim 1, characterized in that The gate oxide layer is formed by a deposition process.

6. The method according to claim 1, characterized in that In the step three, the photoresist mask layer is trimmed by a photoresist hardening process.

7. The method according to claim 6, characterized in that The photoresist hardening process is implemented by ultraviolet irradiation, heating or plasma bombardment.

8. The method according to claim 1, characterized in that The etching of the gate oxide layer is wet etching.

9. The method according to claim 8, characterized in that The wet etching solution includes diluted hydrofluoric acid.

10. The method according to claim 1, characterized in that In the step five, the photoresist mask layer is removed by a stripping process.

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