High-voltage level conversion circuit with symmetrical pulse current auxiliary structure

Abstract

The invention discloses a high-voltage level conversion circuit with a symmetric pulse current structure, which belongs to the technical field of integrated circuits and comprises a level conversion module, a symmetric pulse current auxiliary module and a latch output module. According to the level conversion module, the defect that in the prior art, when the voltage of a power supply jumps rapidly, a circuit may be triggered by mistake is overcome, and the immunity of the circuit is improved. According to the symmetrical pulse current auxiliary module, the defect that transmission delays at the rising edge and the falling edge of an input signal are asymmetric in the prior art is overcome, so that the symmetrical pulse current auxiliary module keeps high transmission delay symmetry while ensuring a high transmission speed; and the problem of possible distortion of digital signal input and output in a high-speed circuit is effectively suppressed.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit technology, and further relates to a high-voltage level conversion circuit with a symmetrical pulse current auxiliary structure in the field of conversion circuit technology. The present invention can be used for high-voltage level conversion in high-speed circuits such as DC-DC converters, motor drivers, and gate drivers. Background Art

[0002] With the rapid development of modern microelectronics technology, high-voltage switching power supplies, especially DC-DC step-down converters, are widely used in various industrial and consumer electronic products. High-voltage DC-DC power supply chips are usually composed of low-voltage logic circuits and high-voltage drive circuits. The low-voltage logic is usually around 5V, while the high-voltage drive signal can be as high as tens of volts or even hundreds of volts. Therefore, a level conversion circuit is required to realize the conversion from low-voltage power rails to high-voltage power rails. As a transmission bridge between low-voltage control signals and high-voltage drive signals, the level conversion circuit plays a vital role in the performance of the entire power chip system.

[0003] Traditional high-voltage level conversion circuits mostly use a cross-coupling structure, which can avoid the generation of static current and help reduce system power consumption. However, due to the presence of parasitic capacitance of high-voltage transistors, the traditional cross-coupling structure has the disadvantages of slow conversion speed and asymmetric transmission delay between the rising edge and the falling edge, which results in the problem that high-frequency digital signals are easily distorted during transmission. In addition, in high-voltage DC-DC power supply chips, since the voltage change rate of the switch node VSW is very high, that is, dVSW / dt is very high, the high-voltage level conversion circuit with a traditional cross-coupling structure may have output signal errors, resulting in abnormal shutdown of the power switch and causing dysfunction of the converter system.

[0004] Guilin University of Electronic Technology has published a wide-range, high-speed, dual-output level shift circuit in its patent document "A wide-range, high-speed, dual-output level shift circuit" (application number 202310762526.2, application publication number CN 116633340 A). The circuit adopts a cross-coupling structure and introduces a transient enhancement structure. The transient enhancement structure is used to reduce the delay, so that the input signal can be quickly converted. The pull-up and pull-down circuits are used to further increase the response speed, thereby achieving high-speed level shifting. The design of the dual-output structure enables the circuit to output two logically opposite signals. However, the circuit still has the disadvantage that the pull-up structure in the transient enhancement structure is composed of a resistor and a PMOS, and the pull-down structure is composed of an NMOS. The pull-up speed and the pull-down speed are very different, and the transmission delay of the circuit at the rising edge and the falling edge is asymmetric, which causes the high-frequency digital signal to be distorted during the transmission process.

[0005] Changgong Microelectronics Co., Ltd. disclosed a high-voltage level conversion circuit in its patent document "Level Shift Circuit, Level Shifter and Buck DCDC Converter" (Application No. 202310628578.0, Application Publication No. CN 116722859 A). The circuit includes a signal input port, a rising edge trigger circuit, a falling edge trigger circuit, a first current mirror, a second current mirror, a latch circuit and a shielding circuit. This technology uses the shielding circuit to cut off the first current mirror and the second current mirror when the dVSW / dt is very high, so that the current will not flow to the latch circuit to achieve the effect of current shielding, thereby ensuring that the output of the latch circuit does not go wrong due to excessive dVSW / dt, and improving the reliability of the level conversion circuit. However, the circuit still has two shortcomings. First, due to the introduction of more transmission gates in the shielding circuit, the speed of level conversion is slowed down; in addition, the circuit has the problem of asymmetric transmission delay between the rising edge and the falling edge of the signal, and there are still great limitations on the conversion of high-speed signals.

[0006] Nanjing Weimeng Electronics Co., Ltd. discloses a high-speed, low-power, high-voltage level shifting circuit in its patent document "A high-speed, low-power, high-voltage level shifting circuit" (application number 202310680026.4, application publication number CN 116599517 A). According to the input signal, the circuit uses a dual pulse generation circuit to output a pulse signal, conduct the corresponding path, and transmit the corresponding signal to the dual pulse latch circuit. The dual pulse latch circuit is mainly used to convert the received signal and output it. The circuit uses a resistor with a large resistance value to pull up, which effectively reduces power consumption. The source-drain parasitic diode of the clamped NMOS tube is used to speed up the pull-down speed, so that the level conversion has a higher conversion speed and lower power loss. However, there are still two shortcomings in the circuit. The circuit has a poor anti-interference problem. When dVsw / dt is too high, it may introduce a large noise, resulting in output logic errors; at the same time, because the speed of the resistor pull-up of the circuit is very different from the speed of the NMOS pull-down, the asymmetric transmission delay problem of the rising and falling edges of the circuit is more serious. Summary of the invention

[0007] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and provide a high-voltage level conversion circuit with a symmetrical pulse current auxiliary structure to solve the problems of slow level conversion speed, poor anti-interference and asymmetric transmission delay in the existing level converter circuit.

[0008] The idea of ​​realizing the purpose of the present invention is that the present invention is improved on the basis of the traditional high-voltage level conversion circuit, and a symmetrical pulse current auxiliary structure is added. The symmetrical pulse current auxiliary structure generates corresponding pulse currents at the rising edge and the falling edge of the input signal, respectively, and quickly changes the high and low states of the output node level of the level conversion circuit, thereby solving the problem of slow level conversion in the existing level converter circuit. The present invention adds a symmetrical pulse current auxiliary structure. Since the pulse current auxiliary structure is completely symmetrical, the pulse currents generated at the rising edge and the falling edge of the input signal are exactly the same in size. Therefore, the output node level conversion speed of the level conversion circuit is the same, which solves the problem of asymmetric transmission delay in the prior art. The present invention adds a clamping diode to the level conversion circuit to limit the gate-source voltage of the transistor within the breakdown voltage range of the diode, avoiding the problem of high voltage breakdown and improving the anti-interference of the level conversion circuit.

[0009] In order to achieve the above object, the high voltage level conversion circuit of the present invention comprises a level conversion module, a symmetrical pulse current auxiliary module and a latch output module.

[0010] The level conversion module is used to convert the input signal from the low voltage domain to the high voltage domain;

[0011] The symmetrical pulse current auxiliary module generates pulse currents of the same magnitude at the rising edge and falling edge of the input signal, and quickly changes the high and low states of the output node level of the level conversion circuit;

[0012] The latch output module is used to receive the output signal of the level conversion module and output it as an output signal after shaping;

[0013] The two input ends of the level conversion module, one is connected to the input signal VIN, and the other input end is connected to the output end of the symmetrical pulse current auxiliary module; the output end of the level conversion module is connected to the input end of the latch output module; the input end of the symmetrical pulse current auxiliary module is connected to the input signal VIN, and the output end of the symmetrical pulse current auxiliary module is connected to an input end of the level conversion module; the input end of the latch output module is connected to the output end of the level conversion module, and the output end of the latch output module is connected to the output signal VOUT.

[0014] Compared with the prior art, the present invention has the following advantages:

[0015] First, a pulse current auxiliary structure is introduced into a high-voltage level conversion circuit provided by the present invention, which generates corresponding pulse currents at the rising edge and falling edge of the input signal, respectively, and quickly changes the high and low states of the output node level of the level conversion circuit, thereby overcoming the defect of slow level conversion speed in the existing level converter circuit, so that the present invention improves the speed of level conversion.

[0016] Second, since the pulse current auxiliary structure introduced by the present invention is completely symmetrical and the pulse currents generated are equal in size, the pull-up and pull-down speeds of the output node of the level conversion module are consistent at the rising and falling edges of the input signal, overcoming the defect of the prior art level conversion circuit that the transmission delay at the rising and falling edges of the input signal are unequal, and effectively suppressing the problem of possible distortion of digital signal input and output in high-speed circuits, so that the present invention maintains a high degree of transmission delay symmetry while ensuring a relatively high level conversion speed.

[0017] Third, since the present invention adds a clamping diode to the level conversion circuit, the gate-source voltage of the transistor is limited within the breakdown voltage range of the diode, thereby avoiding the problem of high voltage breakdown that may occur in the prior art, making the present invention have higher anti-interference performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is the electrical schematic diagram of the circuit of the present invention;

[0019] Figure 2 is a circuit diagram of an embodiment of the present invention;

[0020] Figure 3 4 is a waveform diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0022] The technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0023] Reference Figure 1 , the electrical principle of the overall circuit of the present invention is further described.

[0024] The high-voltage level conversion circuit of the present invention comprises a level conversion module, a symmetrical pulse current auxiliary module and a latch output module.

[0025] A level shifting module is used to convert input signals from the low voltage domain to the high voltage domain.

[0026] Symmetrical pulse current auxiliary module: used to generate pulse currents of the same magnitude at the rising and falling edges of the input signal, and input them into the level conversion module to improve the speed of level conversion and the symmetry of transmission delay.

[0027] Latch output module: used to receive the output signal of the level conversion module and output it as an output signal after shaping.

[0028] The level conversion module in the high-voltage level conversion circuit has two input terminals, one of which is connected to the input signal VIN, and the other input terminal is connected to the output terminal of the symmetrical pulse current auxiliary module. The output terminal of the level conversion module is connected to the input terminal of the latch output module, the input terminal of the symmetrical pulse current auxiliary module is connected to the input signal VIN, and the output terminal of the symmetrical pulse current auxiliary module is connected to an input terminal of the level conversion module. The input terminal of the latch output module is connected to the output terminal of the level conversion module, and the output terminal of the latch output module is connected to the output signal VOUT.

[0029] Reference Figure 2 , the structure of a high-voltage level conversion circuit disclosed in an embodiment of the present invention is further described in detail.

[0030] The level conversion module includes a first inverter I1 of a low voltage power rail, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first resistor R1, a second resistor R2, a first diode Z1, and a second diode Z2.

[0031] The input end of the first inverter I1 is connected to the input signal VIN, and the output end is connected to the gate of the first NMOS transistor MN1. The gate of the first NMOS transistor MN1 is connected to the output end of the inverter I1, the source is connected to the ground VSSL of the low voltage domain, and the drain is connected to the source of the third NMOS transistor MN3. The gate of the second NMOS transistor MN2 is connected to the input signal VIN, the source is connected to the ground VSSL of the low voltage domain, and the drain is connected to the source of the fourth NMOS transistor MN4. The gate of the third NMOS transistor MN3 is connected to the power supply VDDL of the low voltage domain, the source is connected to the drain of the first NMOS transistor MN1, and the drain is connected to the drain of the first PMOS transistor MP1. The gate of the fourth NMOS transistor MN4 is connected to the power supply VDDL of the low voltage domain, the source is connected to the drain of the second NMOS transistor MN2, and the drain is connected to the drain of the second PMOS transistor MN2.

[0032] The gate of the first PMOS tube MP1 is connected to the ground VSSH of the high voltage domain, the source is connected to the node A, and the drain is connected to the drain of the third NMOS tube MN3; the gate of the second PMOS tube MP2 is connected to the ground VSSH of the high voltage domain, the source is connected to the node B, and the drain is connected to the drain of the fourth NMOS tube MN2; the gate of the third PMOS tube MP3 is connected to the node B, and the drain is connected to the node A; the gate of the fourth PMOS tube MP4 is connected to the node A, the source is connected to the power supply VDDH of the high voltage domain, and the drain is connected to the node B.

[0033] The anode of the first diode Z1 is connected to the node A, and the cathode is connected to the power supply VDDH of the high voltage domain; the anode of the second diode Z2 is connected to the node B, and the cathode is connected to the power supply VDDH of the high voltage domain.

[0034] Specifically, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the first PMOS transistor MP1, and the second PMOS transistor MP2 are all high-voltage transistors, and the diodes Z1 and Z2 are both Zener diodes.

[0035] The node A and the node B are the output ends of the level conversion module and are also the input ends of the latch output module. The node A includes the source of the first PMOS tube MP1, the drain of the third PMOS tube MP3, the gate of the fourth PMOS tube MP4, the drain of the tenth NMOS tube MN10, the drain of the ninth PMOS tube MP9, the anode of the first diode Z1 and an input end of the first NAND gate N1. The node B includes the source of the second PMOS tube MP2, the gate of the third PMOS tube MP3, the drain of the fourth PMOS tube MP4, the drain of the ninth NMOS tube MP9, the drain of the tenth PMOS tube MP10, the anode of the second diode Z2 and an input end of the second NAND gate N2.

[0036] In one implementation of the embodiments of the present invention, the symmetrical pulse current auxiliary module includes a first pulse generator, a second pulse generator, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9, a tenth NMOS tube MN10, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a tenth PMOS tube MP10, a second inverter I2 in the low voltage domain, a first resistor R1, and a second resistor R2.

[0037] The input end of the first pulse generator is connected to the input signal VIN, and the output end is connected to the gate of the fifth NMOS transistor MN5.

[0038] The gate of the fifth NMOS transistor MN5 is connected to the output end of the first pulse generator, the source is connected to one end of the first resistor R1, and the drain is connected to the drain of the fifth PMOS transistor MP5. The gate and drain of the seventh NMOS transistor MN7 are respectively connected to the drain of the seventh PMOS transistor MP7 and the gate of the ninth NMOS transistor MN9, and the source is connected to the ground VSSH of the high voltage domain. The gate of the ninth NMOS transistor MN9 is respectively connected to the gate and drain of the seventh NMOS transistor MN7 and the drain of the seventh PMOS transistor MP7, the source is connected to the ground VSSH of the high voltage domain, and the drain is connected to the node B.

[0039] The gate and drain of the fifth PMOS tube MP5 are respectively connected to the drain of the fifth NMOS tube MN5, the drain and gate of the fifth PMOS tube MP5, and the gate of the ninth PMOS tube MP9, and the source is connected to the power supply VDDH of the high voltage domain. The gate of the seventh PMOS tube MP7 is respectively connected to the drain of the fifth NMOS tube MN5, the drain and gate of the fifth PMOS tube MP5, and the gate of the ninth PMOS tube MP9, the source is connected to the power supply VDDH of the high voltage domain, and the drain is connected to the gate and drain of the seventh NMOS tube MN7 and the gate of the ninth NMOS tube MN9. The gate of the ninth PMOS tube MP9 is connected to the gate of the seventh PMOS tube MP7, the drain of the fifth NMOS tube MN5, and the drain and gate of the fifth PMOS tube MP5, the source is connected to the power supply VDDH of the high voltage domain, and the drain is connected to the node A. The first resistor R1 is connected between the source of the fifth NMOS tube MN5 and the ground of the low voltage domain.

[0040] The input end of the second inverter I2 is connected to the input signal VIN, and the output end is connected to the input end of the second pulse generator. The input end of the second pulse generator 2 is connected to the output end of the inverter I2, and the output end is connected to the gate of the sixth NMOS transistor MN6.

[0041] The gate of the sixth NMOS transistor MN6 is connected to the output end of the second pulse generator, the source is connected to one end of the second resistor R2, and the drain is connected to the drain of the sixth PMOS transistor MP6. The gate and drain of the eighth NMOS transistor MN8 are respectively connected to the drain of the eighth PMOS transistor MP8 and the gate of the tenth NMOS transistor MN10, and the source is connected to the ground VSSH of the high voltage domain. The gate of the tenth NMOS transistor MN10 is respectively connected to the gate and drain of the eighth NMOS transistor MN8 and the drain of the eighth PMOS transistor MP8, the source is connected to the ground VSSH of the high voltage domain, and the drain is connected to the node A.

[0042] The gate and drain of the sixth PMOS tube MP6 are respectively connected to the drain of the sixth NMOS tube MN6, the drain and gate of the eighth PMOS tube MP8 and the gate of the tenth PMOS tube MP10, and the source is connected to the power supply VDDH of the high voltage domain. The gate of the eighth PMOS tube MP8 is respectively connected to the drain of the sixth NMOS tube MN6, the drain and gate of the sixth PMOS tube MP6, and the gate of the tenth PMOS tube MP10, the source is connected to the power supply VDDH of the high voltage domain, and the drain is connected to the gate and drain of the eighth NMOS tube MN8 and the gate of the tenth NMOS tube MN10. The gate of the tenth PMOS tube MP10 is connected to the gate of the sixth PMOS tube MP6, the drain of the sixth NMOS tube MN6, the drain and gate of the sixth PMOS tube MP6, the source is connected to the power supply VDDH of the high voltage domain, and the drain is connected to the node B. The second resistor R2 is connected between the source of the sixth NMOS tube MN6 and the ground of the low voltage domain.

[0043] Specifically, the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are both high-voltage transistors. The first and second pulse generators are both rising edge triggered, that is, a high level pulse is generated at the rising edge of the input signal.

[0044] The latch output module includes: a first NAND gate N1 and a second NAND gate N2 in the high-voltage domain, and a third inverter I3 in the high-voltage domain.

[0045] One input end of the first NAND gate N1 is connected to node A, the other input end is connected to the output end of the second NAND gate N2, and the output end is connected to the input end of the third inverter I3. One input end of the second NAND gate N2 is connected to node B, the other input end is connected to the output end of the first NAND gate N1, and the output end is connected to one input end of the first NAND gate N1. The input end of the third inverter I3 is connected to the output end of the first NAND gate N1, and the output end serves as the final output signal VOUT.

[0046] The technical solution adopted by the embodiment of the present invention is based on the introduction of a symmetrical pulse current auxiliary module in the traditional high-voltage level conversion circuit to accelerate the speed of level conversion and improve the symmetry of the transmission delay of the rising edge and the falling edge. Therefore, the circuit has the advantages of fast conversion speed and high transmission delay symmetry.

[0047] The function of the embodiment of the present invention is to convert a low voltage input signal into a high voltage output signal. Through the above description of the embodiment of the present invention, Figure 2 As shown in the figure, when the high voltage power rails VDDH, VSSH and the low voltage power rails VDDL, VSSL are fixed values, we can get Figure 3 .

[0048] Figure 3is a waveform diagram of the input signal state flipping of an embodiment of the present invention. Figure 3 It can be seen that the voltage at the input terminal VIN works between VSSL and VDDL, and the voltage at the output terminal VOUT works between VSSH and VDDH.

[0049] Combination Figure 3 The working principle of the embodiment of the present invention is described in detail with reference to the input signal state inversion waveform diagram.

[0050] When the input terminal jumps from low level VSSL to high level VDDL, the second NMOS tube MN2 is turned on and slowly pulls down node B. At the same time, the input signal generates a high level pulse through the first pulse generator in the symmetrical pulse current auxiliary module and turns on the fifth NMOS tube MN5, thereby generating a pulse current Ipulse1. The seventh NMOS tube MN7, the ninth NMOS tube MN9, the fifth PMOS tube MP5, the seventh PMOS tube MP7, and the ninth PMOS tube MP9 form a current mirror, which copies the pulse current and quickly pulls up node A through the ninth PMOS tube MP9, and quickly pulls down node B through the ninth NMOS tube MN9. At this point, the two input terminals of the latched output module are pulled up to VDDH and pulled down to VSSH respectively. Through the latched output structure, the output signal jumps from low level VSSH to high level VDDH. When the pulse current disappears, the high and low level states of the input terminal of the latched output structure are maintained, the pulse current duration is short, and the overall power consumption is low.

[0051] When the input terminal jumps from high level VDDL to low level VSSL, the first NMOS tube MN1 is turned on and slowly pulls down node A. At the same time, the input signal generates a high level pulse through the pulse generator 2 in the symmetrical pulse current auxiliary module and turns on the sixth NMOS tube MN6, thereby generating a pulse current Ipulse2. The eighth NMOS tube MN8, the tenth NMOS tube MN10, the sixth PMOS tube MP6, the eighth PMOS tube MP8, and the tenth PMOS tube MP10 form a current mirror, which copies the pulse current and quickly pulls up node B through the tenth PMOS tube MP10, and the tenth NMOS tube MN10 quickly pulls down node A. At this point, the second and first input terminals of the latched output structure are pulled up to VDDH and pulled down to VSSH respectively. Through the latched output structure, the output signal jumps from high level VDDH to low level VSSH. When the pulse current disappears, the high and low level states of the input terminal of the latched output structure are maintained. Similarly, the pulse current duration is short and the overall power consumption is low.

[0052] For the application of DC-DC power supply chip, when the high voltage power rail VSSH suddenly jumps from high voltage to low voltage, due to the existence of parasitic capacitance, the difference between the gate potential of the third PMOS tube MP3 and the fourth PMOS tube MP4 and VDDH may suddenly increase. At this time, the first diode Z1 and the second diode Z2 reversely break down, and the gate-source voltage of the third PMOS tube MP3 and the fourth PMOS tube MP4 is clamped at about 6V, so that the device will not be damaged, thereby improving the anti-interference degree of the level conversion circuit.

[0053] The above embodiment is only one implementation of the present invention. It should be understood that those skilled in the art can make changes in form and details based on the basic principles and structures of the present invention without creative work. Therefore, the modifications and changes derived from the concept of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A high voltage level conversion circuit with a symmetrical pulse current auxiliary structure, comprising: The level conversion module and latch output module are characterized in that they also include a symmetrical pulse current auxiliary module; wherein, The level conversion module is used to convert the input signal from the low voltage domain to the high voltage domain; The symmetrical pulse current auxiliary module generates pulse currents of the same magnitude at the rising edge and falling edge of the input signal, and quickly changes the high and low states of the output node level of the level conversion circuit; The latch output module is used to receive the output signal of the level conversion module and output it as an output signal after shaping.

2. The high-voltage level conversion circuit with a symmetrical pulse current auxiliary structure according to claim 1, characterized in that: The level conversion module in the high-voltage level conversion circuit has two input terminals, one of which is connected to the input signal VIN, and the other input terminal is connected to the output terminal of the symmetrical pulse current auxiliary module; the output terminal of the level conversion module is connected to the input terminal of the latch output module; the input terminal of the symmetrical pulse current auxiliary module is connected to the input signal VIN, and the output terminal of the symmetrical pulse current auxiliary module is connected to an input terminal of the level conversion module; the input terminal of the latch output module is connected to the output terminal of the level conversion module, and the output terminal of the latch output module is connected to the output signal VOUT.

3. The high voltage level conversion circuit with a symmetrical pulse current auxiliary structure according to claim 1, characterized in that: The level conversion module includes a first inverter I1 of a low voltage power rail, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first resistor R1, a second resistor R2, a first diode Z1, and a second diode Z2; The input end of the first inverter I1 is connected to the input signal VIN, and the output end is connected to the gate of the first NMOS transistor MN1; the source of the first NMOS transistor MN1 is connected to the ground VSSL of the low voltage domain, and the drain is connected to the source of the third NMOS transistor MN3; the gate of the second NMOS transistor MN2 is connected to the input signal VIN, the source is connected to the ground VSSL of the low voltage domain, and the drain is connected to the source of the fourth NMOS transistor MN4; the gate of the third NMOS transistor MN3 is connected to the power supply VDDL of the low voltage domain, the source is connected to the drain of the first NMOS transistor MN1, and the drain is connected to the drain of the first PMOS transistor MP1; the gate of the fourth NMOS transistor MN4 is connected to the power supply VDDL of the low voltage domain, the source is connected to the drain of the second NMOS transistor MN2, and the drain is connected to the drain of the second PMOS transistor MN2; The gate of the first PMOS transistor MP1 is connected to the ground VSSH of the high voltage domain, the source is connected to the node A, and the drain is connected to the drain of the third NMOS transistor MN3; the gate of the second PMOS transistor MP2 is connected to the ground VSSH of the high voltage domain, the source is connected to the node B, and the drain is connected to the drain of the fourth NMOS transistor MN4; the gate of the third PMOS transistor MP3 is connected to the node B, and the drain is connected to the node A; the gate of the fourth PMOS transistor MP4 is connected to the node A, the source is connected to the power supply VDDH of the high voltage domain, and the drain is connected to the node B; The anode of the first diode Z1 is connected to the node A, and the cathode is connected to the power supply VDDH of the high voltage domain; the anode of the second diode Z2 is connected to the node B, and the cathode is connected to the power supply VDDH of the high voltage domain.

4. The high-voltage level conversion circuit with a symmetrical pulse current auxiliary structure according to claim 3, characterized in that: The third NMOS transistor MN3 , the fourth NMOS transistor MN4 , the first PMOS transistor MP1 , and the second PMOS transistor MP2 are all high-voltage transistors.

5. The high-voltage level conversion circuit with a symmetrical pulse current auxiliary structure according to claim 3, characterized in that: The first diode Z1 and the second diode Z2 are both Zener diodes.

6. The high-voltage level conversion circuit with a symmetrical pulse current auxiliary structure according to claim 1, characterized in that: The symmetrical pulse current auxiliary module includes a first pulse generator, a second pulse generator, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9, a tenth NMOS tube MN10, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a tenth PMOS tube MP10, a second inverter I2 in the low voltage domain, a first resistor R1, and a second resistor R2; The input end of the first pulse generator is connected to the input signal VIN, and the output end is connected to the gate of the fifth NMOS transistor MN5; the source of the fifth NMOS transistor MN5 is connected to one end of the first resistor R1, and the drain is connected to the drain of the fifth PMOS transistor MP5; the gate and drain of the seventh NMOS transistor MN7 are respectively connected to the drain of the seventh PMOS transistor MP7 and the gate of the ninth NMOS transistor MN9, and the source is connected to the ground VSSH of the high voltage domain; the gate of the ninth NMOS transistor MN9 is connected to the gate and drain of the seventh NMOS transistor MN7 and the drain of the seventh PMOS transistor MP7, the source is connected to the ground VSSH of the high voltage domain, and the drain is connected to the node B; The gate and drain of the fifth PMOS tube MP5 are connected to the drain of the fifth NMOS tube MN5, the gate of the seventh PMOS tube MP7 and the gate of the ninth PMOS tube MP9, and the source is connected to the power supply VDDH of the high voltage domain; the gate of the seventh PMOS tube MP7 is connected to the drain of the fifth NMOS tube MN5, the drain and gate of the fifth PMOS tube MP5, and the gate of the ninth PMOS tube MP9, the source is connected to the power supply VDDH of the high voltage domain, and the drain is connected to the gate and drain of the seventh NMOS tube MN7 and the gate of the ninth NMOS tube MN9; the gate of the ninth PMOS tube MP9 is connected to the gate of the seventh PMOS tube MP7, the drain of the fifth NMOS tube MN5, the drain and gate of the fifth PMOS tube MP5, the source is connected to the power supply VDDH of the high voltage domain, and the drain is connected to the node A; the first resistor R1 is connected between the source of the fifth NMOS tube MN5 and the ground of the low voltage domain; The input end of the second inverter I2 is connected to the input signal VIN, and the output end is connected to the input end of the second pulse generator 2; the output end of the second pulse generator is connected to the gate of the sixth NMOS transistor MN6; The gate of the sixth NMOS transistor MN6 is connected to the output end of the second pulse generator, the source is connected to one end of the second resistor R2, and the drain is connected to the drain of the sixth PMOS transistor MP6; the gate and drain of the eighth NMOS transistor MN8 are respectively connected to the drain of the eighth PMOS transistor MP8 and the gate of the tenth NMOS transistor MN10, and the source is connected to the ground VSSH of the high voltage domain; the gate of the tenth NMOS transistor MN10 is connected to the gate and drain of the eighth NMOS transistor MN8 and the drain of the eighth PMOS transistor MP8, the source is connected to the ground VSSH of the high voltage domain, and the drain is connected to the node A; The gate and drain of the sixth PMOS tube MP6 are respectively connected to the drain of the sixth NMOS tube MN6, the drain and gate of the sixth PMOS tube MP8 and the gate of the tenth PMOS tube MP10, and the source is connected to the power supply VDDH of the high voltage domain; the gate of the eighth PMOS tube MP8 is respectively connected to the drain of the sixth NMOS tube MN6, the drain and gate of the sixth PMOS tube MP6, and the gate of the tenth PMOS tube MP10, the source is connected to the power supply VDDH of the high voltage domain, and the drain is connected to the gate and drain of the eighth NMOS tube MN8 and the gate of the tenth NMOS tube MN10; the gate of the tenth PMOS tube MP10 is connected to the gate of the sixth PMOS tube MP6, the drain of the sixth NMOS tube MN6, the drain and gate of the sixth PMOS tube MP6, the source is connected to the power supply VDDH of the high voltage domain, and the drain is connected to the node B; the second resistor R2 is connected between the source of the sixth NMOS tube MN6 and the ground of the low voltage domain.

7. The high-voltage level conversion circuit with a symmetrical pulse current auxiliary structure according to claim 4, characterized in that: The seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are both high-voltage transistors.

8. The high-voltage level conversion circuit with a symmetrical pulse current auxiliary structure according to claim 5, characterized in that: The first and second pulse generators are both rising edge triggered, that is, they generate high level pulses at the rising edge of the input signal.

9. The high-voltage level conversion circuit with a symmetrical pulse current auxiliary structure according to claim 1, characterized in that: The latched output module includes a first NAND gate N1 and a second NAND gate N2 in the high-voltage domain, and a third inverter I3 in the high-voltage domain; One input end of the first NAND gate N1 is connected to node A, and the other input end is connected to the output end of the second NAND gate N2, and the output end of the first NAND gate N1 is connected to the input end of the third inverter I3; one input end of the second NAND gate N2 is connected to node B, and the other input end is connected to the output end of the first NAND gate N1, and the output end of the second NAND gate N2 is connected to one input end of the first NAND gate N1; the input end of the third inverter I3 is connected to the output end of the first NAND gate N1, and the output end of the third inverter I3 serves as the final output signal VOUT.

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