Reading control method, system and equipment of embedded flash memory and medium

Abstract

The invention provides a reading control method, system and equipment for an embedded flash memory and a medium. The reading control method comprises the following steps: receiving a reading request signal output by a bus interface; performing logic operation processing on the read request signal by adopting a first number of logic gates to obtain a request type signal; and obtaining a reading control strategy of the embedded flash memory based on the request type signal, and reading the target data based on the reading control strategy. The logic gate performs logic operation on the read request signal output by the bus interface to obtain the request type signal, so that the problems of high design cost, large area and complicated circuit structure when a decoding prediction unit is adopted to process the read request signal in the prior art are solved, the design cost is reduced, the chip area is reduced, and the processing efficiency is improved. The power consumption is reduced, the circuit structure is simple, and the MCU performance is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of embedded flash memory, and in particular to a read control method, system, device and medium of an embedded flash memory. Background Art

[0002] Embedded Flash (eFlash) is a non-volatile memory and is the main carrier for program and data storage in MCU (Microcontroller Unit). Usually, after the chip is powered on and reset, the processor core reads the user program from eFlash and starts running. Compared with the higher operating frequency of the processor core, the reading speed of eFlash is slow, and multiple waiting cycles need to be inserted to completely retrieve the program and data, which seriously restricts the overall performance of the MCU. Therefore, the reading speed of eFlash is very critical, and improving the reading efficiency of eFlash is very important to improve the performance of MCU.

[0003] Currently, the limit of improving the eFlash reading speed by improving the eFlash process has been reached. Therefore, a high-performance hardware eFlash controller is designed to improve the instruction fetch efficiency of the processor core. However, the decoding prediction unit in the controller that processes the read request signal has the problems of high design cost, large area, high power consumption and complex circuit structure. Summary of the invention

[0004] The technical problem to be solved by the present disclosure is to overcome the defects of high design cost, large area, high power consumption and complex circuit structure in the prior art hardware eFlash controller which uses a decoding prediction unit to process the read request signal, and to provide an embedded flash memory read control method, system, device and medium.

[0005] The present invention solves the above technical problems through the following technical solutions:

[0006] The present disclosure provides a read control method for an embedded flash memory, the read control method comprising:

[0007] Receiving a read request signal output by the bus interface;

[0008] Using a first number of logic gates to perform logic operation processing on the read request signal to obtain a request type signal;

[0009] Based on the request type signal, a read control strategy of the embedded flash memory is obtained to read target data based on the read control strategy.

[0010] Preferably, the request type signal is an instruction read request signal;

[0011] The step of obtaining a read control strategy of the embedded flash memory based on the request type signal, and reading target data based on the read control strategy comprises:

[0012] Receiving a read indication signal output by an external processor;

[0013] Using the second number of logic gates to perform logic operation processing on the read indication signal to obtain an indication type signal;

[0014] Obtaining an instruction request address corresponding to the instruction read request signal;

[0015] The read control strategy is obtained based on the instruction request address and the indication type signal, so as to read the target data based on the read control strategy.

[0016] Preferably, the request type signal is a data read request signal;

[0017] The step of obtaining a read control strategy of the embedded flash memory based on the request type signal, and reading target data based on the read control strategy comprises:

[0018] Obtaining a data request address corresponding to the data read request signal;

[0019] In response to the data request address matching a target address in a data cache, the corresponding target data is read based on the target address.

[0020] Preferably, the indication type signal is a sequential instruction indication signal;

[0021] The step of obtaining the read control strategy based on the instruction request address and the indication type signal, and reading the target data based on the read control strategy comprises:

[0022] The target data is obtained based on the instruction request address and a sequential instruction cache corresponding to the sequential instruction indication signal.

[0023] Preferably, the indication type signal is a jump instruction indication signal;

[0024] The step of obtaining the read control strategy based on the instruction request address and the indication type signal, and reading the target data based on the read control strategy comprises:

[0025] In response to the instruction request address matching the target address in the jump instruction cache corresponding to the jump instruction indication signal, the corresponding target data is read based on the target address.

[0026] Preferably, the step of obtaining the target data based on the instruction request address and the sequential instruction cache corresponding to the sequential instruction indication signal comprises:

[0027] In response to the instruction request address matching the target address in the sequential instruction cache, reading the corresponding target data based on the target address;

[0028] In response to the instruction request address not matching the target address in the sequential instruction cache, determining whether the instruction request address matches the current prefetch address of the embedded flash memory; in response to the instruction request address matching the current prefetch address of the embedded flash memory, reading the corresponding target data based on the current prefetch address.

[0029] The present disclosure also provides a read control system for an embedded flash memory, the read control system comprising:

[0030] A read request receiving module, used for receiving a read request signal output by the bus interface;

[0031] a request type acquisition module, configured to perform a logic operation on the read request signal using a first number of logic gates to obtain a request type signal;

[0032] The target data reading module is used to obtain a reading control strategy of the embedded flash memory based on the request type signal, so as to read the target data based on the reading control strategy.

[0033] Preferably, the request type signal is an instruction read request signal;

[0034] The target data reading module comprises:

[0035] An indication signal receiving unit, used for receiving a read indication signal output by an external processor;

[0036] an indication type acquisition unit, configured to perform logic operation processing on the read indication signal using a second number of logic gates to obtain an indication type signal;

[0037] An instruction address acquiring unit, used for acquiring an instruction request address corresponding to the instruction read request signal;

[0038] The first data reading unit is used to obtain the reading control strategy based on the instruction request address and the indication type signal, so as to read the target data based on the reading control strategy.

[0039] Preferably, the request type signal is a data read request signal;

[0040] The target data reading module comprises:

[0041] A data address acquiring unit, used for acquiring a data request address corresponding to the data read request signal;

[0042] The second data reading unit is configured to read the corresponding target data based on the target address in response to the data request address matching the target address in the data cache.

[0043] Preferably, the indication type signal is a sequential instruction indication signal;

[0044] The first data reading unit comprises:

[0045] The first data acquisition subunit is used to obtain the target data based on the instruction request address and the sequential instruction cache corresponding to the sequential instruction indication signal.

[0046] Preferably, the indication type signal is a jump instruction indication signal;

[0047] The first data reading unit comprises:

[0048] The second data acquisition subunit is used for reading the corresponding target data based on the target address in response to the instruction request address matching the target address in the jump instruction cache corresponding to the jump instruction indication signal.

[0049] Preferably, the first data acquisition subunit is further used for reading the corresponding target data based on the target address in response to the instruction request address matching the target address in the sequential instruction cache;

[0050] In response to the instruction request address not matching the target address in the sequential instruction cache, determining whether the instruction request address matches the current prefetch address of the embedded flash memory; in response to the instruction request address matching the current prefetch address of the embedded flash memory, reading the corresponding target data based on the current prefetch address.

[0051] The present disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and used to run on the processor, and the processor implements the above-mentioned embedded flash memory reading control method when executing the computer program.

[0052] The present disclosure also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned embedded flash memory reading control method is implemented.

[0053] The present disclosure also provides a computer program product, including a computer program, wherein when the computer program is executed by a processor, the embedded flash memory reading control method as described above is implemented.

[0054] The present disclosure also provides a chip, on which a computer program is stored. When the computer program is executed by the chip, the embedded flash memory reading control method as described above is implemented.

[0055] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0056] The positive and progressive effects of this disclosure are:

[0057] The present invention performs logical operations on the read request signal output by the bus interface through logic gates to obtain a request type signal, thereby overcoming the problems of high design cost, large area and complex circuit structure in the prior art of using a decoding prediction unit to process the read request signal, reducing the design cost, reducing the chip area, reducing power consumption, and simplifying the circuit structure, thereby improving the MCU performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 This is a flowchart of the embedded flash memory read control method of Embodiment 1 of the present disclosure;

[0059] Figure 2 This is a flowchart of step S13 in the embedded flash memory read control method of embodiment 2 of the present disclosure;

[0060] Figure 3 It is a structural schematic diagram corresponding to the logic gate of Embodiment 2 of the present disclosure;

[0061] Figure 4 This is a flowchart of step S13 in the embedded flash memory read control method of embodiment 2 of the present disclosure;

[0062] Figure 5 This is a first flow chart of step S134 in the embedded flash memory read control method of embodiment 2 of the present disclosure;

[0063] Figure 6 A second flow chart of step S134 in the embedded flash memory read control method of embodiment 2 of the present disclosure;

[0064] Figure 7 A schematic diagram of a module of a controller corresponding to the embedded flash memory reading control method of Embodiment 2 of the present disclosure;

[0065] Figure 8 This is a specific example diagram of the embedded flash memory read control method according to Embodiment 2 of the present disclosure;

[0066] Fig. 9 A specific example diagram of pre-fetch address generation in the embedded flash memory read control method of embodiment 2 of the present disclosure;

[0067] Fig.10 A schematic diagram of the state transition of a read control state machine module in a controller corresponding to the embedded flash memory read control method of Embodiment 2 of the present disclosure;

[0068] Fig.11 This is a module diagram of a reading control system of an embedded flash memory according to Embodiment 3 of the present disclosure;

[0069] Fig.12 This is a module diagram of a reading control system of an embedded flash memory according to Embodiment 4 of the present disclosure;

[0070] Fig.13 This is a schematic diagram of the structure of an electronic device according to Embodiment 5 of the present disclosure. DETAILED DESCRIPTION

[0071] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0072] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0073] In the embodiments of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0074] Example 1

[0075] This embodiment provides a read control method for an embedded flash memory, which is applied to a controller. The controller is electrically connected to an AHB (Advanced High-performance Bus, a bus interface standard) bus, a processor, and a memory. The AHB bus interface is an interactive interface between the AHB bus and the controller, and is responsible for information exchange between the processor core and the controller. The memory is an eFlash storage body.

[0076] like Figure 1 As shown, the reading control method includes:

[0077] S11, receiving a read request signal output by the bus interface;

[0078] S12, using a first number of logic gates to perform logic operation processing on the read request signal to obtain a request type signal;

[0079] S13. Obtaining a read control strategy of the embedded flash memory based on the request type signal, so as to read the target data based on the read control strategy.

[0080] Specifically, in the process of the processor core reading the user program from the eFlash, the reading control method is designed based on the following principles: (1) The program segment of the user program is composed of instruction segments and data segments interspersed with each other; (2) The instruction segment and the data segment are composed of several small sequential segments with different first addresses, and these different small sequential segments are linked by jump instructions and return instructions; (3) Common loop statements such as for (a loop statement in a programming language) and while (a loop statement in a programming language) may execute the same sequential segment multiple times in succession; (4) When the program executes loops such as for and while, the data used may be in one word; (5) During program execution, the frequency of the processor core reading instructions is much greater than the frequency of reading data.

[0081] In this embodiment, a logic operation is performed on the read request signal output by the bus interface through a logic gate to obtain a request type signal, thereby overcoming the problems of high design cost, large area and complex circuit structure in the prior art of using a decoding prediction unit to process the read request signal, reducing the design cost, reducing the chip area, reducing power consumption, and simplifying the circuit structure, thereby improving the MCU performance.

[0082] Example 2

[0083] This embodiment provides a read control method for an embedded flash memory, which is a further improvement on the first embodiment.

[0084] In an implementable solution, the request type signal is an instruction read request signal;

[0085] like Figure 2 As shown, step S13 includes:

[0086] S131, receiving a read indication signal output by an external processor;

[0087] S132, using a second number of logic gates to perform logic operation processing on the read indication signal to obtain an indication type signal;

[0088] S133, obtaining an instruction request address corresponding to the instruction read request signal;

[0089] S134. Obtain a read control strategy based on the instruction request address and the indication type signal, so as to read the target data based on the read control strategy.

[0090] Specifically, the structural schematic diagram corresponding to the first number of logic gates and the second number of logic gates is as follows: Figure 3 As shown, the bus signal is a read request signal, and the request type signal is divided into an instruction read request signal and a data read request signal. The bus signal is input to the first number of logic gates via the AHB bus interface, and is a dedicated path for the processor core to read instructions and data, and includes the address of the instruction or data to be read, the data size, the data type (instruction or data), the transmission type information and other signals, specifically, including a first bus signal (bus signal 1) for characterizing the selection of the slave, a second bus signal (bus signal 2) for characterizing the completion of the transmission of other slaves, a third bus signal (bus signal 3) for characterizing the transmission type, a fourth bus signal (bus signal 4) for characterizing the completion of the transmission, a fifth bus signal (bus signal 5) for characterizing the transmission direction, and a sixth bus signal (bus signal 6) for characterizing the protection control.

[0091] The first bus signal, the second bus signal and the third bus signal are input to the first AND gate to obtain a first intermediate signal, the fifth bus signal is input to the first NOT gate to obtain a second intermediate signal, the first intermediate signal, the second intermediate signal and the fourth bus signal are input to the second AND gate to obtain a third intermediate signal, the sixth bus signal is input to the second NOT gate to obtain a fourth intermediate signal, the third intermediate signal and the fourth intermediate signal are input to the third AND gate to obtain an instruction read request signal, and the third intermediate signal and the sixth bus signal are input to the fourth AND gate to obtain a data read request signal.

[0092] The instruction information provided by the processor core is the read indication signal, which is the information of the previous instruction provided by the processor core, including a forward jump indication, a backward jump indication, a continuous increment instruction fetch indication, etc.

[0093] The read indication signal is input to the third NOT gate to obtain a sequence indication signal, and the read indication signal is used as a jump indication signal.

[0094] In this solution, a logic operation is performed on the read indication signal output by the processor through a logic gate to obtain a type signal, which has a simple circuit structure and low cost.

[0095] In an implementable solution, the request type signal is a data read request signal;

[0096] like Figure 4 As shown, step S13 includes:

[0097] S135, obtaining a data request address corresponding to the data read request signal;

[0098] S136 . In response to the data request address matching the target address in the data cache, read the corresponding target data based on the target address.

[0099] Specifically, the request type signal is divided into a command read request signal and a data read request signal. That is, the read request is divided into two cases: read command and read data. Different acceleration methods are used for read command and read data.

[0100] For data reads, set the cache acceleration mode and set the cache address hit type. According to principles (4) and (5), set the first-level register cache to form a data cache to store the current data address and the data itself. When the next data request arrives, if the data cache is hit, that is, the data request address matches the target address in the data cache, the read-returned data can be directly obtained from the data cache in the next cycle. If the data cache is not hit, the data is obtained from the eFlash storage interface.

[0101] In this solution, when the processor core reads data, if the cache address hits, the read return does not need to wait, and the data is directly obtained from the corresponding data cache in the next cycle, thereby improving the data reading efficiency.

[0102] In an implementable solution, the indication type signal is a sequential instruction indication signal;

[0103] like Figure 5 As shown, step S134 includes:

[0104] S1341. Obtain target data based on the instruction request address and the sequential instruction cache corresponding to the sequential instruction indication signal.

[0105] Specifically, for read instructions, two acceleration modes, sequential prefetch and cache, are set, and three hit types, prefetch address hit, cache sequential address hit, and cache jump address hit, are set.

[0106] For reading sequential instructions, a sequential instruction cache consisting of a three-level register cache is set. According to principle (2), a three-level register cache is set for sequential instruction prefetching to store the addresses and instructions of sequential prefetching respectively, taking into account factors such as performance and area. On the one hand, it is used to handle the situation where the processor core continuously fetches instructions from the same address, and on the other hand, it is used to alleviate the situation where the frequency of prefetching is greater than the frequency of actual reading by the processor core.

[0107] In this solution, a sequential instruction cache is set to read target data corresponding to sequential instructions, thereby improving instruction reading efficiency.

[0108] In an implementable solution, the indication type signal is a jump instruction indication signal;

[0109] like Figure 6 As shown, step S134 includes:

[0110] S1342, in response to the instruction request address matching the target address in the jump instruction cache corresponding to the jump instruction indication signal, reading corresponding target data based on the target address.

[0111] Specifically, for reading jump instructions, according to Principles 2 and 3, a first-level register cache is set to form a jump instruction cache to store the current jump address and instruction. When the next instruction request arrives and the jump instruction indication signal is valid, if the jump instruction cache is hit, that is, the instruction request address matches the target address in the jump instruction cache corresponding to the jump instruction indication signal, the read-returned instruction can be directly obtained from the jump instruction cache in the next cycle. If the jump instruction cache is not hit, the instruction is obtained from the eFlash storage interface.

[0112] In this solution, when the processor core reads a jump instruction, if the cache jump address hits, the read return does not need to wait, and the instruction is directly obtained from the corresponding jump instruction cache in the next cycle, thereby improving the instruction reading efficiency.

[0113] In one feasible solution, step S1341 includes:

[0114] In response to the instruction request address matching the target address in the sequential instruction cache, reading corresponding target data based on the target address;

[0115] In response to the instruction request address not matching the target address in the sequential instruction cache, determining whether the instruction request address matches the current prefetch address of the embedded flash memory; in response to the instruction request address matching the current prefetch address of the embedded flash memory, reading corresponding target data based on the current prefetch address.

[0116] Specifically, for sequential instructions, when the processor core fetches instructions in non-continuous order, the L3 register cache acts as a buffer, recording the three address-instruction pairs previously pre-fetched sequentially, and caches sequential address hits, that is, the instruction request address matches the target address in the sequential instruction cache. The read return does not need to wait, and the instruction is directly fetched from the L3 register cache corresponding to the address in the next cycle;

[0117] When the processor core is fetching instructions in continuous order and the prefetch address hits, that is, the instruction request address matches the current prefetch address of the embedded flash memory, the read return does not need to wait, and the instruction is directly obtained from the eFlash storage interface in the next cycle.

[0118] In this solution, when the processor core reads a sequential instruction, the instruction request address is matched with the target address and the current prefetch address in the sequential instruction cache, thereby obtaining the target data, thereby improving the instruction reading efficiency.

[0119] In addition, when the processor core continuously executes the same sequential segment composed of loop statements such as for and while, several types of hits, including cache address hits, prefetch address hits, cache sequential address hits, and cache jump address hits, all occur. Read returns do not need to wait, thereby improving reading efficiency.

[0120] The controller includes a read control state machine module to set a protection mechanism. When there is no communication between the processor core and the controller, if the read control state machine module is in a non-prefetch state, the controller will be forced to jump to an idle state in the next cycle; if the read control state machine module is already in a prefetch state (instruction prefetch cycle 0 state or instruction prefetch cycle 1 state), the state is maintained until the prefetch is completed (the prefetch instruction is stored in the cache), and the controller will jump to the idle state; when there is no communication between the processor core and the controller, if the read control state machine module is in a non-prefetch state, the controller will be forced to jump to an idle state in the next cycle; if the read control state machine module is already in a prefetch state (instruction prefetch cycle 0 state or instruction prefetch cycle 1 state), the state is maintained until the prefetch is completed (the prefetch instruction is stored in the cache), and the controller will jump to the idle state. By setting this protection mechanism, high prefetch efficiency and low switching power consumption are achieved.

[0121] The working principle of the embedded flash memory read control method of this embodiment is explained below with reference to specific examples:

[0122] like Figure 7 As shown, it is a module diagram of the controller corresponding to the embedded flash memory read control method. The processor is an ARM Cortex-M (a processor core) series processor core, and the controller includes an AHB bus interface, an interface classification and conversion module, a read return arbitration module, a read control state machine module, an instruction acceleration control module, a data acceleration control module, and an eFlash storage interface. The modules are described as follows:

[0123] The AHB bus interface is the interactive interface between the AHB bus and the controller, responsible for the information exchange between the processor core and the controller;

[0124] The interface classification and conversion module generates control signals for indicating prediction and acceleration based on the signals processed by the bus interface (read request signals) and the instruction information (read indication signals) provided by the processor core. The control signals include instruction read request signals, jump instruction indication signals, sequential instruction indication signals, and data read request signals. These control signals are output to the read control state machine module, instruction acceleration control module, and data acceleration control module respectively;

[0125] The read control state machine module is the core timing control unit of the controller. According to the control signals of the interface classification and conversion module and the hit feedback signals of the instruction acceleration control module and the data acceleration control module, control signals of the three modules, the instruction acceleration control module, the data acceleration control module, and the eFlash storage interface, are generated. In addition, in order to achieve efficient prefetching efficiency and low switching power consumption, a protection mechanism is also set up inside the module: when there is no communication between the processor core and the controller, if the read control state machine module is in a non-prefetch state, the next cycle will be forced to jump to the idle state; if the read control state machine module is already in a prefetch state (instruction prefetch cycle 0 state or instruction prefetch cycle 1 state), the state is maintained until the prefetch ends (the prefetch instruction is stored in the cache), and the controller jumps to the idle state;

[0126] The instruction acceleration control module is the main unit for instruction acceleration, which accelerates instruction reading through two strategies: prefetching and caching. The specific description is as follows:

[0127] The hit types inside the instruction acceleration control module are divided into three types: prefetch address hit, cache sequence address hit, and cache jump address hit;

[0128] For sequential instructions, an instruction prefetch address generation and control unit and an instruction prefetch control unit are set. The instruction prefetch address generation and control unit adjusts and generates the next prefetch address in real time according to the current instruction hit situation. If there is a hit (any of the three hit types mentioned above), 1 is added to the current prefetch address (the address of the current sequential instruction or the address of the current jump instruction) as the next prefetch address. If there is a miss, the new address of the sampling bus is used as the next prefetch address. In addition, three-level register caches (sequential instruction address cache and sequential instruction cache) are set respectively to store the addresses and instructions of the previous sequential prefetches. If the subsequent instruction fetch address hits any address in the three-level register cache, the controller directly outputs the instruction corresponding to the hit address from the three-level register cache in the next cycle; if the subsequent instruction fetch address does not hit any address in the three-level register cache, but hits the address that the eFlash storage interface is fetching (prefetch address hit), the controller directly obtains the instruction from the eFlash storage interface in the next cycle;

[0129] For jump instructions, a jump instruction address control unit and a jump instruction control unit are set, and a first-level register cache (jump instruction address cache and jump instruction cache) is designed to store the current jump address and instruction. When the next instruction request arrives and the jump instruction indication signal is valid, if the jump instruction cache is hit, the read-returned instruction can be directly obtained from the jump instruction cache in the next cycle.

[0130] The data acceleration control module is the main unit of data acceleration, which accelerates data reading according to the cache strategy. The specific description is as follows:

[0131] The hit type inside the data acceleration control module is a cache address hit;

[0132] For data acceleration, the data acceleration control module sets up a data address cache control unit and a data cache control unit. The design adopts a data cache strategy and uses a first-level register cache (data address cache and data cache) to store the current data address and the data itself respectively. When the next data request comes, if it hits the data cache, the read-returned data can be directly obtained from the data cache in the next cycle.

[0133] The eFlash storage interface is the interface between the controller and the eFlash storage, responsible for information exchange between the controller and the storage;

[0134] The read return arbitration module determines whether to return instructions or data to the cache or the eFlash storage interface through the address given by the bus interface and the hit information returned by the instruction acceleration control module and the data acceleration control module.

[0135] like Figure 8 As shown in FIG. 1 , a specific example diagram of the embedded flash memory read control method is shown. The controller applies the embedded flash memory read control method, and when read acceleration is enabled, the controller can automatically perform read acceleration on the processor core without program preprocessing or software-assisted intervention, and the acceleration method is simple and efficient; when read acceleration is not enabled, the controller waits for reading through the bus.

[0136] In the read control method, different acceleration methods are adopted for two different request types, instruction and data. For data request, data acceleration strategy is adopted. For instruction acceleration, the controller divides instruction acceleration into sequential instruction acceleration and jump instruction acceleration according to different instruction types, and the corresponding sequential instruction acceleration strategy and jump instruction acceleration strategy are used. For sequential instruction acceleration, sequential prefetching method is adopted, and a three-level register cache is set to store the addresses and instructions of the previous sequential prefetching. If the next instruction request hits any address in the three-level register cache, the instruction returned by the read can be directly obtained from the three-level register cache in the next cycle; if the next instruction request hits the address of the current prefetched instruction, the instruction returned by the read can be obtained from the eFlash output port in the next cycle. For jump instruction acceleration, a first-level register cache is set to store the current jump address and instruction. When the next instruction request arrives and the jump instruction indication signal is valid, if the jump instruction cache is hit, the instruction returned by the read can be directly obtained from the jump instruction cache in the next cycle.

[0137] For data acceleration, the controller uses a first-level register cache to store the current data address and the data itself. When the next data request comes, if it hits the data cache, the read-returned data can be directly obtained from the data cache in the next cycle.

[0138] like Fig. 9 As shown, it is a specific example diagram of pre-fetch address generation in the read control method of embedded flash memory. When the controller read acceleration function is enabled, the type of the current instruction is determined according to the indication type signal generated by the second number of logic gates. When the instruction is a sequential instruction, if the current pre-fetch condition is met, it indicates that the read control state machine module has entered the pre-fetch address stage, then the current pre-fetch address is incremented by 1 to generate the next pre-fetch address; if the condition is not met, it means that the acceleration has not hit, then the new address of the sampling bus is used as the next pre-fetch address. When the instruction is a non-sequential instruction, that is, a jump instruction, if the jump instruction is accelerated, the current jump instruction address is incremented by 1 to generate the next pre-fetch address, otherwise the new address of the sampling bus is used as the next pre-fetch address. Since when the jump instruction hits, the pre-fetch has begun to prepare to read the next instruction (current jump instruction address + 1), if there is no subsequent instruction or data miss, the processor core can achieve no-wait reading.

[0139] like Fig.10 The following is a schematic diagram of the state transition of the read control state machine module. Each state is closely connected. The specific jump process between each state is as follows:

[0140] When the controller is in idle state, upon receiving a read request from the processor core, if there is currently an instruction address hit or a data address hit (condition 1), that is, any of the three: a sequential address hit, a cache jump address hit, or a cache address hit, the read control state machine module jumps to the direct read state, and the instruction returned by the read is directly read from the cache in the next cycle; if there is no hit (condition 2), a read wait cycle is inserted, and the read control state machine module jumps to the bus wait state. When the wait cycle count is completed (condition 4), it jumps to the bus read state, and the instruction returned by the read can be safely obtained from the eFlash storage interface; when the processor core selects the controller but has not yet issued a read request to the controller, if the sequential instruction indication signal is still valid at this time (condition 3), the read control state machine module will jump to the instruction prefetch cycle 0 to perform sequential instruction prefetching, so as to maximize the use of idle cycle prefetching and thus improve the efficiency of read acceleration;

[0141] When the controller is in the bus read state, upon receiving a read request from the processor core, if no cache address (sequential instruction cache, jump instruction cache and data cache) is hit (condition 5), the controller state machine jumps to the bus wait state and inserts a read wait cycle for reading; if there is the above hit (condition 6), it jumps to the direct read state for reading; if there is no read request from the processor core during this period and the sequential instruction indication signal is still valid (condition 7), the controller state machine will jump to instruction prefetch cycle 0 for sequential instruction prefetching to maximize the use of idle cycles, thereby improving the efficiency of read acceleration;

[0142] When the controller is in the instruction prefetch cycle 0 state, when receiving a read request from the processor core, similarly, if no cache address (sequential instruction cache, jump instruction cache and data cache) is hit (condition 11), the controller state machine jumps to the bus wait state; if there is a cache hit (condition 9), it jumps to the direct read state for reading; if there is a hit of the prefetch address (condition 10), it jumps to the instruction prefetch cycle 1 state, and the controller obtains instructions from the eFlash storage interface in the next cycle. Since a complete prefetch is completed above (jumping from instruction prefetch cycle 0 to instruction prefetch cycle 1), the read control state machine module will control the controller during this period to update the newly prefetched instructions and corresponding addresses to the lowest register of each three-level register cache;

[0143] When the controller is in the instruction prefetch cycle 1 state, when receiving a read request from the processor core, similarly, if no cache address (sequential instruction cache, jump instruction cache and data cache) is hit (condition 14), the read control state machine module jumps to the bus waiting state; if there is the above cache hit (condition 12), it jumps to the direct read state for reading; if no read request occurs, and the processor core still selects the controller, but has not yet issued a read request to the controller, if the sequential instruction indication signal is still valid at this time (condition 13), then the read control state machine module jumps to the instruction prefetch cycle 0 to continue sequential prefetching; in order to ensure that when the processor core does not select the controller for a long time, the controller returns to the idle state to reduce the power consumption of register jumps, when there is no communication between the processor core and the controller, if the controller is in the prefetch state, it will maintain this state without being interrupted until the prefetched instruction is stored in the cache (condition 15), and the controller will return to the idle state;

[0144] When the controller is in the direct read state, upon receiving a read request from the processor core, if no cache address (sequential instruction cache, jump instruction cache, and data cache) is hit (condition 16), the read control state machine module jumps to the bus wait state; if a read data request occurs or the read control state machine module detects that the sequential instruction indication signal is invalid, the read control state machine module will also jump to the bus wait state; if there is an instruction hit (prefetch address hit, cache sequential address hit, cache jump address hit), the controller will remain in the direct read state; if the processor core selects the controller but does not issue a read request to the controller (condition 17), the controller will jump to the instruction prefetch cycle 0 state; further, if the processor core does not select the controller (condition 18), the controller will return to the idle state to save power consumption.

[0145] The main advantages of this embodiment are as follows:

[0146] The processor's read requests are classified into instruction requests and data requests. Then, based on the characteristics of the two types of requests, different acceleration methods are used for each type of request to avoid redundant acceleration units.

[0147] The controller adopts a compact controller embedded acceleration circuit to minimize the controller area of ​​the entire given eFlash;

[0148] The prefetch mechanism adjusts and generates the starting address of the next sequential segment in real time based on the current instruction, data hit status and the precise information of the previous instruction from the processor core to ensure efficient and reliable prefetching;

[0149] A smaller register cache is used, balancing factors such as performance and area. A total of five pairs of register caches are used (address and instruction cache composed of the third-level register cache, jump address and instruction cache composed of the first-level register cache, and address and data cache composed of the first-level register cache);

[0150] Built-in protection mechanisms enable the controller to achieve high prefetch efficiency and low switching power consumption.

[0151] In this embodiment, a logic operation is performed on the read request signal output by the bus interface through a logic gate to obtain a request type signal, thereby overcoming the problems of high design cost, large area and complex circuit structure in the prior art of using a decoding prediction unit to process the read request signal, reducing the design cost, reducing the chip area, reducing power consumption, and having a simple circuit structure. It can significantly speed up the speed at which the processor core fetches instructions from the eFlash, especially greatly reducing the read waiting time when reading sequential blocks and jumping loop blocks, thereby improving the MCU performance.

[0152] The execution subject of the embedded flash memory read control method provided in this embodiment may be a separate chip, a chip module or an electronic device, or a chip or a chip module integrated in an electronic device.

[0153] Example 3

[0154] This embodiment provides a read control system for an embedded flash memory, such as Fig.11 As shown, the reading control system includes:

[0155] A read request receiving module 1, used for receiving a read request signal output by a bus interface;

[0156] A request type acquisition module 2, configured to perform a logic operation on the read request signal using a first number of logic gates to obtain a request type signal;

[0157] The target data reading module 3 is used to obtain a reading control strategy of the embedded flash memory based on the request type signal, so as to read the target data based on the reading control strategy.

[0158] In this embodiment, a logic operation is performed on the read request signal output by the bus interface through a logic gate to obtain a request type signal, thereby overcoming the problems of high design cost, large area and complex circuit structure in the prior art of using a decoding prediction unit to process the read request signal, reducing the design cost, reducing the chip area, reducing power consumption, and simplifying the circuit structure, thereby improving the MCU performance.

[0159] Example 4

[0160] This embodiment provides a read control system for an embedded flash memory, which is a further improvement on the third embodiment.

[0161] In an implementable solution, the request type signal is an instruction read request signal;

[0162] like Fig.12 As shown, the target data reading module 3 includes:

[0163] An indication signal receiving unit 31, used for receiving a read indication signal output by an external processor;

[0164] an indication type acquisition unit 32, configured to perform logic operation processing on the read indication signal using a second number of logic gates to obtain an indication type signal;

[0165] An instruction address acquiring unit 33, used for acquiring an instruction request address corresponding to an instruction read request signal;

[0166] The first data reading unit 34 is used to obtain a reading control strategy based on the instruction request address and the indication type signal, so as to read the target data based on the reading control strategy.

[0167] In an implementable solution, the request type signal is a data read request signal;

[0168] The target data reading module 3 includes:

[0169] A data address acquisition unit 35, used to acquire a data request address corresponding to a data read request signal;

[0170] The second data reading unit 36 ​​is configured to read corresponding target data based on the target address in response to the data request address matching the target address in the data cache.

[0171] In an implementable solution, the indication type signal is a sequential instruction indication signal;

[0172] The first data reading unit 34 includes:

[0173] The first data acquisition subunit 341 is used to obtain target data based on the instruction request address and the sequential instruction cache corresponding to the sequential instruction indication signal.

[0174] In an implementable solution, the indication type signal is a jump instruction indication signal;

[0175] The first data reading unit 34 includes:

[0176] The second data acquisition sub-unit 342 is used for reading corresponding target data based on the target address in response to the instruction request address matching the target address in the jump instruction cache corresponding to the jump instruction indication signal.

[0177] In an practicable solution, the first data acquisition subunit 341 is further configured to read corresponding target data based on the target address in response to the instruction request address matching the target address in the sequential instruction cache;

[0178] In response to the instruction request address not matching the target address in the sequential instruction cache, determining whether the instruction request address matches the current prefetch address of the embedded flash memory; in response to the instruction request address matching the current prefetch address of the embedded flash memory, reading corresponding target data based on the current prefetch address.

[0179] In this embodiment, a logic operation is performed on the read request signal output by the bus interface through a logic gate to obtain a request type signal, thereby overcoming the problems of high design cost, large area and complex circuit structure in the prior art of using a decoding prediction unit to process the read request signal, reducing the design cost, reducing the chip area, reducing power consumption, and simplifying the circuit structure, thereby improving the MCU performance.

[0180] As for the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The system embodiment described above is only illustrative, wherein the units described as separate components may or may not be physically separated, and the components as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the disclosed solution.

[0181] In this embodiment, the embedded flash memory reading control system described in the embodiment may specifically be a separate chip, a chip module or an electronic device, or a chip or a chip module integrated in an electronic device. The various modules / units included in the embedded flash memory reading control system may be software modules / units, hardware modules / units, or partly software modules / units and partly hardware modules / units. For example, for various devices and products applied to or integrated in the chip, the various modules / units included therein may all be implemented in the form of hardware such as circuits, or at least some of the modules / units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining modules / units may be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the chip module, the various modules / units included therein may all be implemented in the form of hardware such as circuits, and different modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules / units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module. The element can be implemented in the form of a software program, which runs on a processor integrated inside the chip module, and the remaining modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in electronic devices, the various modules / units contained therein can be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or in different components in the terminal, or, at least some modules / units can be implemented in the form of a software program, which runs on a processor integrated inside the electronic device, and the remaining modules / units can be implemented in the form of hardware such as circuits.

[0182] Example 5

[0183] Fig.13 This is a structural schematic diagram of an electronic device shown in an example embodiment of the present disclosure, the electronic device includes a memory, a processor, and a computer program stored in the memory and used to run on the processor, and when the processor executes the computer program, it implements the embedded flash memory reading control method described in any of the above embodiments. Fig.13 The electronic device 90 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0184] like Fig.13 As shown, the electronic device 90 may be in the form of a general-purpose computing device, for example, it may be a server device. The components of the electronic device 90 may include, but are not limited to: at least one processor 91, at least one memory 92, and a bus 93 connecting different system components (including the memory 92 and the processor 91).

[0185] The bus 93 includes a data bus, an address bus, and a control bus.

[0186] The memory 92 may include a volatile memory, such as a random access memory (RAM) 921 and / or a cache memory 922 , and may further include a read only memory (ROM) 923 .

[0187] The memory 92 may also include a program tool 925 (or utility) having a set (at least one) of program modules 924, such program modules 924 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0188] The processor 91 executes various functional applications and data processing by running the computer program stored in the memory 92, such as the embedded flash memory read control method provided in any of the above embodiments.

[0189] The electronic device 90 may also communicate with one or more external devices 94 (e.g., keyboards, pointing devices, etc.). Such communication may be performed via an input / output (I / O) interface 95. Furthermore, the electronic device 90 may also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter 96. As shown, the network adapter 96 communicates with other modules of the electronic device 90 via a bus 93. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 90, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, and data backup storage systems, etc.

[0190] It should be noted that although several units / modules or sub-units / modules of the electronic device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided into multiple units / modules to be embodied.

[0191] Example 6

[0192] The embodiments of the present disclosure further provide a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the embedded flash memory reading control method provided in any of the above embodiments is implemented.

[0193] The readable storage medium may include but is not limited to: a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device or any suitable combination of the above.

[0194] Example 7

[0195] The embodiment of the present disclosure further provides a computer program product, including a computer program, which implements any of the above-mentioned embedded flash memory reading control methods when executed by a processor.

[0196] Among them, the program code for executing the computer program product of the present disclosure can be written in any combination of one or more programming languages, and the program code can be executed completely on the user device, partially on the user device, as an independent software package, partially on the user device and partially on a remote device, or completely on the remote device.

[0197] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A method for controlling the reading of an embedded flash memory, characterized in that: The reading control method comprises: Receiving a read request signal output by the bus interface; Using a first number of logic gates to perform logic operation processing on the read request signal to obtain a request type signal; Based on the request type signal, a read control strategy of the embedded flash memory is obtained to read target data based on the read control strategy.

2. The embedded flash memory read control method according to claim 1, characterized in that: The request type signal is an instruction read request signal; The step of obtaining a read control strategy of the embedded flash memory based on the request type signal, and reading target data based on the read control strategy comprises: Receiving a read indication signal output by an external processor; Using the second number of logic gates to perform logic operation processing on the read indication signal to obtain an indication type signal; Obtaining an instruction request address corresponding to the instruction read request signal; The read control strategy is obtained based on the instruction request address and the indication type signal, so as to read the target data based on the read control strategy.

3. The embedded flash memory reading control method according to claim 1, characterized in that: The request type signal is a data read request signal; The step of obtaining a read control strategy of the embedded flash memory based on the request type signal, and reading target data based on the read control strategy comprises: Obtaining a data request address corresponding to the data read request signal; In response to the data request address matching a target address in the data cache, the corresponding target data is read based on the target address.

4. The embedded flash memory read control method according to claim 2, characterized in that: The indication type signal is a sequential instruction indication signal; The step of obtaining the read control strategy based on the instruction request address and the indication type signal, and reading the target data based on the read control strategy comprises: The target data is obtained based on the instruction request address and a sequential instruction cache corresponding to the sequential instruction indication signal.

5. The embedded flash memory reading control method according to claim 2, characterized in that: The indication type signal is a jump instruction indication signal; The step of obtaining the read control strategy based on the instruction request address and the indication type signal, and reading the target data based on the read control strategy comprises: In response to the instruction request address matching the target address in the jump instruction cache corresponding to the jump instruction indication signal, the corresponding target data is read based on the target address.

6. The embedded flash memory reading control method according to claim 4, characterized in that: The step of obtaining the target data based on the instruction request address and the sequential instruction cache corresponding to the sequential instruction indication signal comprises: In response to the instruction request address matching the target address in the sequential instruction cache, reading the corresponding target data based on the target address; In response to the instruction request address not matching the target address in the sequential instruction cache, determining whether the instruction request address matches the current prefetch address of the embedded flash memory; in response to the instruction request address matching the current prefetch address of the embedded flash memory, reading the corresponding target data based on the current prefetch address.

7. A read control system for an embedded flash memory, characterized in that: The reading control system comprises: A read request receiving module, used for receiving a read request signal output by the bus interface; a request type acquisition module, configured to perform a logic operation on the read request signal using a first number of logic gates to obtain a request type signal; The target data reading module is used to obtain a reading control strategy of the embedded flash memory based on the request type signal, so as to read the target data based on the reading control strategy.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and used to run on the processor, characterized in that: When the processor executes the computer program, the embedded flash memory reading control method according to any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the embedded flash memory reading control method according to any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the embedded flash memory reading control method according to any one of claims 1 to 6 is implemented.

11. A chip, characterized in that: A computer program is stored on the chip, and when the computer program is executed by the chip, the embedded flash memory reading control method according to any one of claims 1 to 6 is implemented.

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