Chip embedded structure of hybrid integrated circuit and preparation method thereof

Abstract

The invention provides a chip embedding structure of a hybrid integrated circuit and a preparation method thereof, and the structure comprises a packaging substrate (1), the packaging substrate (1) is provided with an embedding groove (11) and BGA solder balls (2), the embedding groove (11) is internally connected with a multi-layer chip interconnection assembly (3), the multi-layer chip interconnection assembly (3) is connected with an AlN substrate (5), the embedding groove (11) is filled with heat-conducting insulation glue (6), and the BGA solder balls (2) are arranged on the packaging substrate (1). The AlN substrate (5) is electrically connected with the package substrate conductor through gold wire ball bonding. According to the preparation method provided by the invention, a multi-layer chip interconnection component embedded structure is adopted, so that the integration efficiency, the function density and the heat dissipation capability of integrated packaging of a chip embedded circuit are obviously improved, the internal structure space is fully utilized, and the high-density integration level and the packaging reliability are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of hybrid integrated circuits, and in particular relates to a hybrid integrated circuit chip and a preparation method thereof. Background Art

[0002] The characteristics of high-density hybrid integrated circuits are that they must have both high-density multi-layer wiring substrates and high-density assembly and interconnection of components represented by chips. Usually, the assembly and interconnection of components such as chips are carried out on the surface of the circuit substrate, but as users and systems have higher requirements for miniaturization and integration of hybrid integrated circuit products, the industry has gradually begun to adopt the method of embedding components such as chips inside the substrate to achieve higher density integration, especially in the field of system integration.

[0003] At present, when embedding a chip inside a packaging substrate, a single-layer chip is usually embedded in the embedded location, and there is a lack of special heat dissipation considerations. For example, in the prior art, a method for reducing the position deviation between chip embedding and photolithography pattern (CN110517961A) and a substrate structure with embedded chips and a light-emitting device using the same (CN11208645A) both involve chip embedding, but they are all for embedding a single chip rather than 3D stacked chip embedding, which is not conducive to fully utilizing the internal structural space of the multi-layer wiring substrate, is not conducive to further improving the integration level and functional density of circuits and systems, lacks effective countermeasures when heat dissipation problems are prominent, and is not conducive to improving the performance and reliability of hybrid integrated packaging. Summary of the invention

[0004] The present invention is to overcome the deficiencies in the prior art and provide a chip embedding structure of a hybrid integrated circuit and a preparation method thereof.

[0005] This application provides the following technical solutions: A method for preparing a chip embedding structure of a hybrid integrated circuit, characterized in that it comprises the following steps: S1, taking a ceramic packaging substrate, on which a buried groove is provided; S2, a group of BGA solder balls are evenly distributed on the bottom surface of the package substrate; S3. A group of heat dissipation holes are evenly distributed on the bottom surface of the buried groove, and heat dissipation metal columns are filled in the heat dissipation holes, which are also used for electrical connection between the front and back sides of the packaging substrate. A conductive metal layer covering the heat dissipation holes is provided on the bottom surface of the buried groove; S4. A multi-layer chip interconnection component is provided on the metal layer, and the multi-layer chip interconnection component includes a top chip, a plurality of stacked chips and a bottom chip distributed vertically from top to bottom. The upper surface of the stacked chip is provided with a PAD welding area, and a group of first conductive bumps corresponding to the PAD welding area are evenly distributed on the lower surface of the top chip and the stacked chip. A group of through silicon vias are provided on the stacked chip and the bottom chip, and a group of blind holes with downward openings are provided on the top chip. The through silicon vias and the blind holes are filled with conductive metal, one end of the conductive metal is electrically connected to the corresponding first conductive bump, and the other end is electrically connected to the PAD welding area, and then a group of second conductive bumps are provided on the bottom surface of the bottom chip, one end of the conductive metal in the bottom chip is electrically connected to the corresponding second conductive bump, and the other end is electrically connected to the PAD welding area; S5. A graphene composite thermal conductive film is placed between the top chip and the topmost stacked chip, between each layer of stacked chips, and between the bottommost stacked chip and the bottom chip. The graphene composite thermal conductive film is provided with a clearance hole distributed corresponding to the first conductive bump. The additive compounded with graphene in the graphene composite thermal conductive film includes fluorinated graphene and polyimide. An insulating adhesive layer is provided on the graphene composite thermal conductive film. An insulating adhesive layer is also provided on the hole wall of the clearance hole. The insulating adhesive layer is doped with amorphous polytetrafluoroethylene and nano aluminum nitride powder. The first welding interconnection is completed between adjacent chips through nano silver paste, and the connection between the upper surface and the lower surface of adjacent chips is achieved through the graphene thermal conductive film adhesive layer, thereby forming a multi-layer chip interconnection component; S6, coating the metal layer with nano silver paste, and then placing the multi-layer chip interconnection assembly so that the second conductive bump contacts the nano silver paste, completing the welding interconnection between the chip interconnection assembly and the metal layer nano silver paste; S7, filling the buried groove with thermally conductive insulating glue, the thermally conductive insulating glue and the epoxy adhesive layer are made of the same material, and the thermally conductive insulating glue is filled in the gap between the multi-layer chip interconnection component and the buried groove wall, and between the multi-layer chip interconnection component and the bottom surface of the buried groove, until the thermally conductive insulating glue is flush with the top surface of the top chip, and then the thermally conductive insulating glue is cured according to the applicable temperature and time, and the thermally conductive insulating glue and the insulating adhesive layer are made of the same material; S8, bonding an AlN substrate with multi-layer wiring on the upper surface of the top chip by using nano silver paste; S9. Use gold wire ball bonding to achieve electrical connection between the PAD area of ​​the AlN substrate and the conductor of the packaging substrate.

[0006] On the basis of the above technical solutions, the following technical solutions can also be provided: During the first welding in step S5, the welding temperature is greater than the temperature during the eutectic welding of the chip interconnection component and the metal layer in step S6.

[0007] The heat dissipation metal column in S3 is silver or silver alloy.

[0008] The metal layer in S3 and S6 is a gold conductor.

[0009] In S5, nano silver paste is coated on the surface of the PAD soldering area, and the total height of the graphene composite thermal conductive film and the insulating adhesive layer is greater than the height of the first conductive bump and less than the sum of the height of the first conductive bump and the coating thickness of the nano silver paste.

[0010] A hybrid integrated circuit chip embedding structure made by a preparation method of a hybrid integrated circuit chip embedding includes: a packaging substrate, a embedding groove is provided on the packaging substrate, and is characterized in that: a group of BGA solder balls are arranged on the bottom surface of the packaging substrate; a multi-layer chip interconnection component is arranged in the embedding groove, the embedding groove is filled with thermal conductive insulating glue, an AlN substrate with multi-layer wiring is arranged on the upper surface of the multi-layer chip interconnection component, and an electrical connection is formed between the AlN substrate and the packaging substrate through gold wire.

[0011] The multi-layer chip interconnection component includes a plurality of stacked chips distributed vertically from top to bottom, a top chip, and a bottom chip, the upper surface of the stacked chips are provided with PAD welding areas, a group of first conductive bumps corresponding to the PAD welding areas are evenly distributed on the lower surface of the stacked chips, a group of through silicon vias are provided on the stacked chips and the bottom chip, a group of blind holes opening downward are provided on the top chip, the through silicon vias and the blind holes are filled with conductive metal, one end of the conductive metal is electrically connected to the corresponding first conductive bumps, and the other end is electrically connected to the PAD welding area, and then a group of second conductive bumps are provided on the bottom surface of the bottom chip, one end of the conductive metal in the bottom chip is electrically connected to the corresponding second conductive bumps, and the other end is electrically connected to the PAD welding area; A graphene composite thermally conductive film is placed between the top chip and the uppermost stacked chip, between each layer of stacked chips, and between the lowermost stacked chip and the bottom chip. The graphene composite thermally conductive film is provided with clearance holes corresponding to the first conductive bumps, the graphene composite thermally conductive film is provided with an insulating adhesive layer, and the hole walls of the clearance holes are also provided with an insulating adhesive layer. The first welding interconnection between adjacent chips is completed by nano silver paste, and the connection between the upper surface and the lower surface of adjacent chips is achieved by the graphene thermally conductive film adhesive layer, thereby forming a multi-layer chip interconnection component.

[0012] The volume of the second conductive bump is larger than that of the first conductive bump.

[0013] A group of heat dissipation holes are evenly distributed on the bottom surface of the buried groove, and heat dissipation metal columns made of silver are filled in the heat dissipation holes. A conductive metal layer covering the heat dissipation holes is provided on the bottom surface of the buried groove.

[0014] Advantages of the invention: The preparation method provided by the present invention adopts a TSV-based embedded structure of a multi-layer chip interconnection component on the one hand; on the other hand, the embedded structure of the multi-layer chip interconnection component has a special packaging design, which significantly improves the integration efficiency, functional density and heat dissipation capacity of the chip embedded circuit, and makes full use of the internal structure space, thereby improving the high-density integration level and packaging reliability of the system-level hybrid integrated package as a whole. Among them, the graphene composite thermal conductive film is used between adjacent chips of the multi-layer chip interconnection component, which has a better heat dissipation effect than thermal conductive glue. The additives composited with graphene in the thermal conductive film include fluorinated graphene and polyimide (PI), thereby improving the flexibility, electrical insulation, thermal conductivity and flame retardancy of the thermal conductive film; a layer of insulating adhesive is coated on the surface of the film, and amorphous polytetrafluoroethylene and nano-aluminum nitride powder are doped in the adhesive layer, which can improve the thermal conductivity and high-frequency performance of the adhesive layer bonding, and ensure the high-performance thermal conductivity of the graphene composite film; insulating adhesive is coated on the upper and lower surfaces of the film and the inner surface of the hole, and at the same time, electrical insulation between the bumps and between the upper and lower surfaces of adjacent chips is ensured; the thickness of the entire film (including the surface adhesive layer) is greater than the bump height, and less than the sum of the bump height and the coating thickness of the nano-silver paste, which can ensure that the adhesive surface of the film is fully in contact and bonded with the chip, and that the first conductive bump is fully in contact and bonded with the nano-silver paste, while meeting the chip heat dissipation and bump connection requirements. The thermally conductive insulating glue in the buried groove is the same as the adhesive glue on the surface of the thermal conductive film, so it can also improve the thermal conductivity and high-frequency performance of the colloid filling. Since the filling glue is the same as the adhesive glue, the thermal matching between the two is guaranteed to the greatest extent, and the thermal stress impact on the multi-layer chip interconnection component is minimized as much as possible. The top chip in the multi-layer chip interconnection component is provided with a semi-through hole, and there is no opening on the upper surface of the chip. The hole is filled with conductive metal, which can realize the thermal conduction and electrical connection of the chip at the same time; the entire upper surface of the top chip is assembled with a multi-layer aluminum nitride substrate with nano silver paste, and the aluminum nitride surface has a metallization layer, which can provide sufficient heat dissipation for the interconnection component chip, and can also realize the three-dimensional electrical interconnection of the packaging substrate through bonding. Filling the chip silicon through hole with conductive metal not only plays the role of conducting electricity on the upper and lower sides of the chip, but also plays the role of providing a heat dissipation channel; the thermal conductive column at the bottom of the packaging substrate plays the role of heat dissipation, and at the same time plays the role of electrical interconnection inside and outside the buried groove of the packaging substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of a chip embedding structure of a hybrid integrated circuit manufactured by adopting a preparation method for embedding a chip of a hybrid integrated circuit provided by the invention; Figure 2 yes Figure 1 A-axis enlarged view. DETAILED DESCRIPTION

[0016] like Figure 1 and 2As shown, a method for preparing a chip embedding structure of a hybrid integrated circuit comprises the following steps: S1 , taking a ceramic package substrate 1 for a chip, on which a buried groove 11 is provided.

[0017] S2. A group of BGA solder balls 2 are evenly prepared on the bottom surface 1 of the packaging substrate.

[0018] S3. A group of heat dissipation holes 12 are evenly distributed on the bottom surface of the buried groove 11. The heat dissipation holes 12 are filled with heat dissipation metal columns 13 made of silver material, which are also used for electrical connection between the front and back sides of the packaging substrate. A conductive metal layer 14 covering the heat dissipation holes 12 is provided on the bottom surface of the buried groove 1, and the metal layer 14 is a gold conductor.

[0019] S4. A multi-layer chip interconnection assembly 3 is provided on the metal layer 13. The multi-layer chip interconnection assembly 3 includes a top chip 3a, a plurality of stacked chips 3b and a bottom chip 3e located at the bottom layer, which are vertically distributed from top to bottom.

[0020] Each stacked chip 3b is provided with a PAD pad on the upper surface, and a group of first conductive bumps 3c are evenly distributed on the lower surface corresponding to the PAD pad. A group of through silicon vias 3h are provided on the stacked chip 3b, and a group of blind vias 3k with downward openings are provided on the top chip 3a. The through silicon vias 3h and the blind vias 3k are filled with conductive metal 3d, and the conductive metal 3d is a copper columnar structure.

[0021] One end of the conductive metal 3d contacts the corresponding first conductive bump 3c, and the other end contacts the PAD pad, so that the first conductive bump 3c and the PAD pad are electrically connected to each other through the conductive metal 3d.

[0022] A group of second conductive bumps 4 are provided on the bottom surface of the bottom chip 3e, and the volume of the second conductive bumps 4 is larger than the volume of the first conductive bumps 3c. One end of the conductive metal 3d in the bottom chip 3e is electrically connected to the corresponding second conductive bumps 4, and the other end is electrically connected to the PAD pad.

[0023] S5. A graphene composite thermal conductive film 3g is placed between the top chip and the topmost stacked chip, between each stacked chip, and between the bottommost stacked chip 3b and the bottom chip 3e. The additive compounded with graphene in the film body includes fluorinated graphene and polyimide (PI). The graphene composite thermal conductive film 3g is provided with a corresponding distribution of holes formed with the first conductive bumps 3c. An epoxy adhesive layer 13g is also coated on the surface of the graphene composite thermal conductive film 3g and the inner wall of the hole, and amorphous polytetrafluoroethylene and nano aluminum nitride powder are also doped in the epoxy adhesive layer 13g.

[0024] A solder layer 3j made of nano silver paste is also placed between the first conductive bump 3c and the bottom chip 3e. Assuming that the height of the first conductive bump 3c of the chip is d1 and the thickness of the solder layer 3j made of nano silver paste is d2, the thickness of the entire graphene composite thermal conductive film plus the epoxy adhesive layer 13g is between d1 and d1+d2. The first welding interconnection is completed between adjacent chips 3a through the nano silver paste, and the bonding and heat dissipation connection between adjacent chips is achieved through the graphene composite thermal conductive film 3g, thereby forming a multi-layer chip interconnection component 3.

[0025] S6, coating the metal layer 14 with nano silver paste, and then placing the multi-layer chip interconnection component 3 into the buried groove 11, so that the second conductive bump 4 is in contact with the nano silver paste, and then completing the interconnection of the chip interconnection component 3 and the metal layer 14 through nano silver paste welding in a vacuum state in a eutectic welding furnace. The welding temperature used in this eutectic welding is 30°C-40°C lower than the first welding temperature in step S5.

[0026] S7, filling the thermally conductive insulating adhesive 6 around the multi-layer chip interconnection assembly 3 in the buried groove 11, so that the thermally conductive insulating adhesive 6 fills the gaps between the chips of different layers of the multi-layer chip interconnection assembly 3 and between the embedded groove 11 and the groove wall, until the thermally conductive insulating adhesive 6 is flush with the upper surface of the top chip 3a, and then the thermally conductive insulating adhesive 6 is cured according to the applicable temperature and time. The thermally conductive insulating adhesive 6 and the epoxy adhesive layer 13g are made of the same material (ingredients), so as to keep the thermal expansion coefficients of the two the same, and avoid problems caused by different thermal expansion coefficients of the contact surfaces of the two.

[0027] S8. The AlN substrate 5 with multi-layer wiring is bonded to the upper surface of the topmost stacked chip 3b via the nano silver paste 8.

[0028] S9. Use gold wire ball bonding to electrically connect the PAD area on the AlN substrate with the conductor on the packaging substrate 1 through the gold wire 7, thereby obtaining a chip embedding structure of a hybrid integrated circuit.

[0029] A chip embedding structure of a hybrid integrated circuit comprises: a ceramic packaging substrate 1 for the chip, an embedding groove 11 is arranged on the packaging substrate 1, and a group of BGA solder balls 2 are arranged on the bottom surface 1 of the packaging substrate.

[0030] A group of heat dissipation holes 12 are evenly distributed on the bottom surface of the buried groove 11 . The heat dissipation holes 12 are filled with heat dissipation metal columns 13 made of silver. A conductive metal layer 14 covering the heat dissipation holes 12 is provided on the bottom surface of the buried groove 11 .

[0031] A multi-layer chip interconnection component 3 is connected to the metal layer 14, and the multi-layer chip interconnection component 3 includes a top chip 3a, a plurality of stacked chips 3b and a bottom chip 3e distributed vertically from top to bottom, and a PAD welding area is provided on the upper surface of the stacked chip 3b, and a group of first conductive bumps 3c corresponding to the PAD welding area are evenly distributed on the lower surfaces of the top chip 3a and the stacked chip 3b, and a group of through silicon vias 3h are provided on the stacked chip 3b and the bottom chip 3e, and a group of blind holes 3k with openings facing downward are provided on the top chip 3a, and conductive metal 3d is filled in the through silicon vias 3h and the blind holes 3k, one end of the conductive metal 3d is electrically connected to the corresponding first conductive bump 3c, and the other end is electrically connected to the PAD welding area, and then a group of second conductive bumps 4 are provided on the bottom surface of the bottom chip 3e, and one end of the conductive metal 3d in the bottom chip 3e is electrically connected to the corresponding second conductive bump 4, and the other end is electrically connected to the PAD welding area; A graphene composite thermal conductive film 3g is placed between the top chip 3a and the uppermost stacked chip 3b, between each layer of stacked chips, and between the lowermost stacked chip 3b and the bottom chip 3e. The graphene composite thermal conductive film 3g is provided with makeshift holes (not shown in the figure) distributed corresponding to the first conductive bumps 3c.

[0032] An insulating adhesive layer 13g is provided on the graphene composite thermal conductive film 3g, and an insulating adhesive layer is also provided on the hole wall of the clearance hole. The first welding interconnection is completed between adjacent chips through nano silver paste, and the connection between the upper surface and the lower surface of adjacent chips is achieved through the graphene thermal conductive film adhesive layer, thereby forming a multi-layer chip interconnection component 3.

[0033] The buried groove 11 is filled with a heat-conducting insulating adhesive 6, a multi-layer wiring AlN substrate 5 is bonded to the upper surface of the multi-layer chip interconnection component 3, and an electrical connection is formed between the AlN substrate 5 and the conductor on the packaging substrate 1 through a gold wire 7.

Claims

1. A method for preparing a chip embedding structure of a hybrid integrated circuit, characterized in that: It includes the following steps: S1, taking a ceramic packaging substrate (1), and providing an embedded groove (11) on the packaging substrate (1); S2, a group of BGA solder balls (2) are evenly distributed on the bottom surface of the packaging substrate (1); S3. A group of heat dissipation holes (12) are evenly distributed on the bottom surface of the buried groove (11), and heat dissipation metal columns (13) are filled in the heat dissipation holes (12) and are used for electrical connection between the front and back sides of the packaging substrate. A conductive metal layer (14) covering the heat dissipation holes (12) is provided on the bottom surface of the buried groove (11); S4. A multi-layer chip interconnection component (3) is provided on the metal layer (14). The multi-layer chip interconnection component (3) includes a top chip (3a), a plurality of stacked chips (3b) and a bottom chip (3e) which are longitudinally distributed from top to bottom. The top surface of the stacked chip (3b) is provided with a PAD welding area. A group of first conductive bumps (3c) corresponding to the PAD welding area are uniformly distributed on the bottom surface of the top chip (3a) and the stacked chip (3b). A group of through silicon vias (3h) are provided on the stacked chip (3b) and the bottom chip (3e). A group of blind holes (3k) opening downward are provided on the top chip (3a). The through silicon vias (3h) and the blind holes (3k) are filled with conductive metal (3d). One end of the conductive metal (3d) is electrically connected to the corresponding first conductive bump (3c), and the other end is electrically connected to the PAD welding area. Then, a group of second conductive bumps (4) are provided on the bottom surface of the bottom chip (3e). One end of the conductive metal (3d) in the bottom chip (3e) is electrically connected to the corresponding second conductive bump (4), and the other end is electrically connected to the PAD welding area; S5, a graphene composite thermal conductive film is placed between the top chip (3a) and the topmost stacked chip (3b), between each stacked chip (3b), and between the bottommost stacked chip (3b) and the bottom chip (3e); a clearance hole corresponding to the first conductive bump (3c) is provided on the graphene composite thermal conductive film (3g); an additive compounded with graphene in the graphene composite thermal conductive film (3g) comprises fluorinated graphene and polyimide; an insulating adhesive layer (13g) is provided on the graphene composite thermal conductive film; an insulating adhesive layer (13g) is also provided on the hole wall of the clearance hole; amorphous polytetrafluoroethylene and nano aluminum nitride powder are doped in the insulating adhesive layer (13g); adjacent chips are connected to each other by first welding through nano silver paste, and the upper surface and the lower surface of adjacent chips are connected by the graphene thermal conductive film adhesive layer, thereby forming a multi-layer chip interconnection component (3); S6, coating the metal layer (14) with a nano silver paste, and then placing the multi-layer chip interconnection component (3) so that the second conductive bump (4) is in contact with the nano silver paste, thereby completing the nano silver paste welding interconnection between the chip interconnection component (3) and the metal layer (14); S7, filling the buried groove (11) with a thermally conductive insulating adhesive (6), the thermally conductive insulating adhesive (6) filling the gap between the multi-layer chip interconnection component (3) and the wall of the buried groove (11), and the gap between the multi-layer chip interconnection component (3) and the bottom surface of the buried groove (11), until the thermally conductive insulating adhesive (6) is flush with the upper surface of the top chip (3a), and then the thermally conductive insulating adhesive (6) is cured at an appropriate temperature and time, and the thermally conductive insulating adhesive (6) and the insulating adhesive layer (13g) are made of the same material; S8, bonding an AlN substrate (5) having a multi-layer wiring to the upper surface of the top chip (3a) by using a nano silver paste; S9. Use gold wire ball bonding to achieve electrical connection between the PAD area of ​​the AlN substrate and the conductor of the packaging substrate.

2. The method for preparing a chip embedding structure of a hybrid integrated circuit according to claim 1, characterized in that: During the first welding in step S5, the welding temperature is greater than the temperature during the eutectic welding of the chip interconnection component (3) and the metal layer (14) in step S6.

3. The method for preparing a chip embedding structure of a hybrid integrated circuit according to claim 1, characterized in that: The heat dissipation metal column (13) in S3 is silver or a silver alloy.

4. The method for preparing a chip embedding structure of a hybrid integrated circuit according to claim 1, characterized in that: The metal layer (14) in S3 and S6 is a gold conductor.

5. The method for preparing a chip embedding structure of a hybrid integrated circuit according to claim 1, characterized in that: In the S5, nano silver paste is coated on the surface of the PAD soldering area, and the total height of the graphene composite thermal conductive film (3g) and the insulating adhesive layer (13g) is greater than the height of the first conductive bump (3c) and less than the sum of the height of the first conductive bump (3c) and the coating thickness of the nano silver paste.

6. A chip embedding structure of a hybrid integrated circuit manufactured by the method for embedding a chip of a hybrid integrated circuit according to claim 1, comprising: A packaging substrate (1) is provided with an embedded groove (11) on the packaging substrate (1), characterized in that: a group of BGA solder balls (2) are evenly arranged on the bottom surface (1) of the packaging substrate; a multi-layer chip interconnection component (3) is arranged in the embedded groove (11), the embedded groove (11) is filled with a thermal conductive insulating adhesive (6), an AlN substrate (5) with multi-layer wiring is arranged on the upper surface of the multi-layer chip interconnection component (3), and an electrical connection is formed between the AlN substrate (5) and the packaging substrate (1) through a gold wire (7).

7. A chip embedding structure of a hybrid integrated circuit according to claim 6, characterized in that: The multi-layer chip interconnection component (3) comprises a top chip (3a), a plurality of stacked chips (3b) and a bottom chip (3e) which are longitudinally distributed from top to bottom. The top surface of the stacked chip (3b) is provided with a PAD welding area. A group of first conductive bumps (3c) corresponding to the PAD welding area are uniformly distributed on the bottom surfaces of the top chip (3a) and the stacked chip (3b). A group of through-silicon vias (3h) are provided on the stacked chip (3b) and the bottom chip (3e). A group of blind holes (3k) opening downward are provided on the top chip (3a). The through-silicon vias (3h) and the blind holes (3k) are filled with conductive metal (3d). One end of the conductive metal (3d) is electrically connected to the corresponding first conductive bump (3c), and the other end is electrically connected to the PAD welding area. Then, a group of second conductive bumps (4) are provided on the bottom surface of the bottom chip (3e). One end of the conductive metal (3d) in the bottom chip (3e) is electrically connected to the corresponding second conductive bump (4), and the other end is electrically connected to the PAD welding area; A graphene composite thermally conductive film (3g) is placed between a top chip (3a) and the topmost stacked chip (3b), between each stacked chip layer, and between the bottommost stacked chip (3b) and the bottom chip (3e). The graphene composite thermally conductive film (3g) is provided with clearance holes distributed corresponding to the first conductive bumps (3c). An insulating adhesive layer (13g) is provided on the graphene composite thermally conductive film (3g). An insulating adhesive layer (13g) is also provided on the hole wall of the clearance hole. A first welding interconnection is completed between adjacent chips through nano silver paste, and the connection between the upper surface and the lower surface of adjacent chips is achieved through the graphene thermally conductive film adhesive layer, thereby forming a multi-layer chip interconnection component (3).

8. A chip embedding structure of a hybrid integrated circuit according to claim 7, characterized in that: The volume of the second conductive bump (4) is larger than that of the first conductive bump (3c).

9. A chip embedding structure of a hybrid integrated circuit according to claim 7, characterized in that: A group of heat dissipation holes (12) are evenly distributed on the bottom surface of the buried groove (11), the heat dissipation holes (12) are filled with heat dissipation metal columns (13) made of silver material, and a conductive metal layer (14) covering the heat dissipation holes (12) is provided on the bottom surface of the buried groove (11).

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