Multi-channel synchronous acquisition system for weak signals

Abstract

The invention relates to a multi-channel synchronous acquisition system for weak signals, which realizes the functions of acquisition, processing, storage and transmission of the weak signals and transmits the processed data to an upper computer through an interactive communication interface. According to the system, weak source data from the sensor is preprocessed through the signal conditioning module, and a digital signal processing module DSP is added in the signal conditioning module, so that the signal conditioning circuit has strong digital processing and adaptive adjustment capabilities, and the performance is improved while more flexibility and expandability are increased. Through synchronous clock management and control of control signal generation, the clock synchronization problem of a plurality of acquisition channels is solved, time delay caused by switching among the channels is avoided, and the acquisition speed is improved; and the security of data transmission among different modules is ensured through data cross-clock domain transmission management.

Description

Technical Field

[0001] The invention belongs to the field of data acquisition, data processing and transmission, and in particular relates to a weak signal multi-channel synchronous acquisition system. Background Art

[0002] Data acquisition is an important way to obtain information. Multi-channel synchronous acquisition can avoid the waiting time of asynchronous AD acquisition system for each analog signal acquisition, solve the problems of poor phase consistency between channels and data alignment in data acquisition, and improve the synchronization and real-time performance of the system. In the field of information technology, with the development of technology, it gradually presents the characteristics of fast speed and large bandwidth, and multi-channel synchronous data acquisition technology has become one of the key technologies.

[0003] Weak signals refer to extremely weak useful signals buried in background noise, such as those with extremely small amplitudes and small signal-to-noise ratios in acoustic and electrical signals, which are difficult to be discovered and monitored. Weak signal detection is to extract weak signals submerged in strong background noise through signal processing or noise suppression.

[0004] At present, there is a certain amount of technical accumulation in the system design for weak signal acquisition, but it lacks versatility and scalability, and there are still shortcomings in the acquisition resolution, making it impossible to achieve high-precision data acquisition. Summary of the invention

[0005] In view of the technical problems existing in the above-mentioned prior art, the present invention provides a weak signal multi-channel synchronous acquisition system, which realizes the acquisition, processing, storage and transmission functions of weak signals, and transmits the processed data to the host computer through an interactive communication interface. The system described in the present invention pre-processes the weak source data from the sensor through a signal conditioning module. A digital signal processing module DSP is added to the signal conditioning module, so that the signal conditioning circuit has powerful digital processing and adaptive adjustment capabilities, which improves the performance while adding more flexibility and scalability. Through synchronous clock management, control signals are generated for control, which solves the clock synchronization problem of multiple acquisition channels, avoids the delay caused by switching between channels, and improves the acquisition speed; through data transmission management across clock domains, the security of data transmission between different modules is guaranteed.

[0006] A weak signal multi-channel synchronous acquisition system of the present invention comprises: a sensor for acquiring original weak signal source data, a signal conditioning module for amplifying and filtering the acquired weak signal source data, a multi-channel synchronous acquisition module, an FPGA core module, a power management module and a host computer; The sensor, signal conditioning module, multi-channel synchronous acquisition module, FPGA core module and host computer are electrically connected in sequence; the power management module is electrically connected to the signal conditioning module, multi-channel synchronous acquisition module and FPGA core module respectively; The signal conditioning module includes a single-ended to differential circuit, a programmable amplifier circuit, a programmable low-pass filter circuit, an analog-to-digital converter ADC, a digital signal processing module DSP, and a digital-to-analog converter DAC, which are electrically connected in sequence; the sensor is a multi-channel sensor, and the original weak signals collected by the sensor include physical signals and chemical signals; The weak signal source data is sequentially conditioned by the single-ended to differential circuit, the program-controlled amplifier circuit and the program-controlled low-pass filter to obtain a first signal, and the first signal enters the analog-to-digital converter ADC to be converted into a digital signal; the digital signal processing module DSP filters, adjusts the gain and performs spectrum analysis operations on the real-time input digital signal according to the parameters set by itself to obtain a second signal, and the second signal is converted into an analog signal by the digital-to-analog converter DAC to obtain the target electrical signal source data; The multi-channel synchronous acquisition module acquires the target electrical signal source data to obtain target digital signal source data, and passes the target digital signal source data to the FPGA core module for filtering and downsampling to obtain target digital signal data, and then passes the target digital signal data to the host computer for display.

[0007] In the present invention, under normal circumstances, the parameters set by the digital signal processing module DSP itself include: a low-pass filter with a cutoff frequency set to 550Hz, a band-pass filter with a frequency range of 90-310Hz, a dynamic gain range of 0-60dB, a gain adjustment step of 1dB, a target amplitude close to the ADC full scale of 2.4V, an FFT spectrum analysis point number of 1024, a Hanning window function spectrum refresh rate of 10Hz, a filter order of 10, and a temperature drift compensation coefficient of 0.001V / °C.

[0008] In the present invention, the sensor acquires raw data. The signal conditioning module is used to connect to the sensor, and the main function of the signal conditioning module is to amplify and filter the weak signal source data collected by the sensor, adjust the amplitude of the weak signal to the voltage range of the multi-channel synchronous acquisition module input, and suppress the noise to improve the quality of the weak signal, so as to facilitate the acquisition of the multi-channel synchronous acquisition module; The multi-channel synchronous acquisition module performs multi-channel synchronous acquisition and converts the analog signal output by the signal conditioning module into a digital signal, so as to facilitate FPGA to process and transmit the data.

[0009] In the present invention, the functions of each circuit in the signal conditioning module are as follows: The single-ended to differential circuit converts the single-ended input signal into a differential signal to reduce common-mode noise and provide a purer differential signal for subsequent amplification and filtering; The program-controlled amplifier circuit performs preliminary amplification on the signal and provides dynamic gain adjustment to adapt to the dynamic range of the input signal; The programmable low-pass filter circuit is used to filter out high-frequency noise and retain the low-frequency components in the signal; the cutoff frequency of the filter in the programmable low-pass filter circuit can be programmable to adapt to different signal frequency requirements and make the signal components in the target frequency range more prominent; The analog-to-digital converter ADC converts the analog signal into a digital signal so that the digital signal processing module DSP module can process it; The digital signal processing module DSP is used to pre-process the data, and the pre-processing includes: filter filtering, gain adjustment, spectrum analysis, adaptive signal processing and data correction and compensation.

[0010] Among them, filter filtering: various digital filtering (such as low-pass, band-pass, band-stop, adaptive filtering, etc.) can be implemented to further suppress noise; Among them, gain adjustment: the signal gain can be adjusted in the digital domain, and signals of different frequency bands can be amplified in stages according to needs; Among them, spectrum analysis: through algorithms such as fast Fourier transform (FFT), the spectrum components of the signal are analyzed in real time to help detect specific frequencies or signal characteristics; Among them, adaptive signal processing: can dynamically adjust the filter parameters or gains according to the changes in the input signal, so that the system can achieve the best signal-to-noise ratio in various environments; Among them, data correction and compensation: compensate for temperature drift, offset and other factors through correction algorithms to improve measurement accuracy and long-term stability; The digital-to-analog converter DAC converts the digital signal processed by the digital signal processing module DSP back into an analog signal to facilitate sampling by a subsequent system.

[0011] Further, in the weak signal multi-channel synchronous acquisition system of the present invention, the FPGA core module includes the following seven modules: BUS_MUX multiplexing, parameter management, sampling control, clock management, data storage, power-on self-test and interactive communication; The sampling control is connected to the multi-channel synchronous acquisition module, the parameter management is connected to the sampling control, the BUS_MUX multiplexing is respectively connected to the sampling control, data storage, power-on self-test and interactive communication, the clock management is respectively connected to the sampling control, data storage, BUS_MUX multiplexing and interactive communication, and the interactive communication is also connected to the host computer.

[0012] In the present invention, the FPGA core module controls each module in the entire weak signal multi-channel synchronous acquisition system, filters and downsamples the data at the same time, and transmits the processed target data to the host computer; the host computer module realizes the software host computer display to visualize the target data; the power management module is used to control the power of all modules in the entire weak signal multi-channel synchronous acquisition system.

[0013] In the present invention, the BUS_MUX multiplexing module is used for the management between the internal modules of the FPGA core module, ensuring that the data and control signals between different modules can be reasonably shared and switched, and providing efficient resource allocation between modules; The parameter management module is used to manage the parameters of each module inside the FPGA core module, such as the number of sampling channels, sampling rate, data format, data bit width and system startup mode, and supports dynamic configuration and update to improve system flexibility; The sampling control is used to control the front-stage multi-channel synchronous acquisition module, process the collected data information, and package the data according to the parameter configuration information; Further, in the weak signal multi-channel synchronous acquisition system described in the present invention, the single-ended to differential circuit uses an AD8138 chip, the program-controlled amplifier circuit uses a PGA281 chip, and the program-controlled low-pass filter circuit uses an LTC1068 chip; the analog-to-digital converter ADC uses a first chip, which is an AD7606 chip; the digital signal processing module DSP uses a TMS320C6748 chip; the digital-to-analog converter DAC uses an AD5781 chip; Furthermore, in the weak signal multi-channel synchronous acquisition system described in the present invention, the multi-channel synchronous acquisition module uses a second chip for synchronous acquisition, and each of the channels is equipped with a sampling and holding circuit for ensuring synchronous sampling of each channel; the second chip is an AD7606 chip.

[0014] Furthermore, in the weak signal multi-channel synchronous acquisition system described in the present invention, the sampling control adopts a third chip, and the third chip is an AD7606 chip; the data stored in the data is stored through EEPROM; the power-on self-test executes a self-test program when the system is powered on to check the initialization status of the main functional modules.

[0015] Furthermore, in the weak signal multi-channel synchronous acquisition system described in the present invention, the first chip, the second chip and the third chip all have the function of supporting 8-channel synchronous acquisition with a resolution of 16 bits, and have three interfaces: parallel interface, high-speed serial interface, and parallel byte interface.

[0016] Further, in the weak signal multi-channel synchronous acquisition system of the present invention, the clock management controls the clock synchronization management of the multi-channel synchronous sampling module through the CONVST pulse signal; The clock management performs cross-clock domain management on data transmission between different modules directly connected to the clock management in the FPGA core module through the CONVST pulse signal; The CONVST pulse signal is a CONVST_A signal and a CONVST_B signal generated by the sampling control process; The cross-clock domain includes a bus clock domain, an ADC acquisition clock domain, an EEPROM storage clock domain and an interactive communication clock domain; The bus clock domain is multiplexed by the BUS_MUX to realize data interaction between modules and provide unified data routing services; The ADC acquisition clock domain is used for the sampling control and is responsible for generating a control signal that triggers an ADC sampling event; The EEPROM storage clock domain is used to provide an independent clock for the data storage, supporting cross-clock domain storage after data acquisition is completed; The interactive communication clock domain is used for the interactive communication and provides an interface for data reading and transmission.

[0017] In the present invention, clock management is responsible for the synchronous clock management in the entire weak signal multi-channel synchronous acquisition system, including clock division, phase correction and jitter control functions, to ensure the stability of clock synchronization between system modules and cross-clock domain data transmission.

[0018] In the present invention, the power-on self-check executes a series of self-check programs when the entire weak signal multi-channel synchronous acquisition system is powered on, checks the initialization status of the main functional modules, and ensures that the system runs in a stable state.

[0019] Furthermore, in the weak signal multi-channel synchronous acquisition system described in the present invention, the interactive communication is a dual-channel parallel structure, and the dual channels are a UART data transmission path supporting low-speed communication and an Ethernet data transmission path supporting high-speed communication.

[0020] In the present invention, the interactive communication module is used to connect external communication hardware, such as UART, Ethernet and other interfaces, to provide data uploading and control command receiving functions for the entire weak signal multi-channel synchronous acquisition system, and to support multiple communication protocols to adapt to different application requirements; the dual-channel parallel structure corresponds to the UART and Ethernet transmission paths respectively, to ensure independent data caching and processing for each channel; the communication mode selection control logic selects or switches the communication mode through system parameter configuration to ensure seamless connection of different modes; the clock configuration is used to unify the clock source and manage data transmission between different clock domains to ensure the stability of the system and the accuracy of transmission.

[0021] Furthermore, in the weak signal multi-channel synchronous acquisition system described in the present invention, the host computer uses LabVIEW software to perform data processing and visual display, and the main program flow of the host computer uses an interrupt-triggered data receiving mechanism.

[0022] In the present invention, LabVIEW software can provide a friendly graphical interface, facilitate real-time monitoring of collected multi-channel synchronous data, and support real-time processing, analysis and storage of data; the host computer can also generate data reports, waveform displays and spectrum analysis according to needs, and users can dynamically observe data changes in different channels by adjusting parameters, thereby improving the usability and interactivity of the system.

[0023] In the present invention, the power management module provides a stable and reliable power supply for the entire weak signal multi-channel synchronous acquisition system; the power management module can allocate appropriate voltage and current according to the power requirements of different modules to ensure stable operation of the system; the power management module also has overcurrent protection, overvoltage protection and temperature monitoring functions to prevent system failures caused by power supply abnormalities; the power management module can realize dynamic power control, automatically adjust power consumption according to the system working status, effectively extend the system life and improve energy efficiency.

[0024] Furthermore, in the weak signal multi-channel synchronous acquisition system described in the present invention, the power-on self-test uses a finite state machine FSM to control the entire self-test process.

[0025] Compared with the prior art, the present invention has the following beneficial technical effects: The invention discloses a weak signal multi-channel synchronous acquisition system, which is used for the multi-channel synchronous acquisition of weak signals. The system of the invention pre-processes the weak source data from the sensor through a signal conditioning module, and a digital signal processing module DSP is added to the signal conditioning module, so that the signal conditioning circuit has powerful digital processing and adaptive adjustment capabilities, which improves the performance and increases more flexibility and scalability.

[0026] The data after passing through the multi-channel synchronous acquisition device is used as the input of the FPGA core module. In the FPGA core module, the data is filtered and downsampled according to the parameter settings. After the processed data is packaged, it is transmitted to the host computer software through the interactive communication interface for display.

[0027] Through synchronous clock management, control signals are generated for control, which solves the clock synchronization problem of multiple acquisition channels, avoids the delay caused by switching between channels, and improves the acquisition speed; through data transmission management across clock domains, the security of data transmission between different modules is guaranteed.

[0028] The present invention provides a UART-based low-speed transmission and an Ethernet-based high-speed transmission interface in interactive communication, which is convenient for selection according to different requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a structural schematic diagram of the weak signal multi-channel synchronous acquisition system of the present invention; Figure 2 It is a data flow change flow chart of the weak signal multi-channel synchronous acquisition system of the present invention; Figure 3 This is a schematic diagram of a synchronous multi-channel sampling process of a multi-channel synchronous acquisition module in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the structure of a signal conditioning module according to Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the structure of the FPGA core module of Example 1 of the present invention; Figure 6 A schematic diagram of a self-test process of a power-on self-test module according to Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the main program flow of the host computer of Example 1 of the present invention; Wherein: 100, weak signal multi-channel synchronous acquisition system, 110, sensor, 120, signal conditioning module, 130, multi-channel synchronous acquisition module, 140, FPGA core module, 160, power management module, 150, host computer; D210, parameter electrical signal source data, D220, target electrical signal source data, D230, target digital signal source data, D240, target digital signal data; 310, sampling control, 320, parameter management, 330, data storage, 340, power-on self-test, 350, clock management, 360, interactive communication, 370, BUS_MUX multiplexing; T420, configured with ADC conversion mode, T410, CONVST signal, T430, read data, 210, differential driver AD8138, 220, PGA281, 230, variable gain amplifier AD8367, 240, LTC1068, 250, AD7606, 260, TMS320C6748, 270, digital-to-analog converter AD5781; U400, FSM enters self-test state, U410, clock and reset signal detection, U420, configuration and initialization detection, U430, module self-test, U440, peripheral detection, U450, self-test results; S310, main program initialization, S320, data processing, display, storage, S330, whether the process is completed, S340, interrupt instruction, S360, data cache, S350, file saving. DETAILED DESCRIPTION

[0030] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, the specific implementation methods of the present invention are now described in detail with reference to the accompanying drawings. The described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. If the specific conditions are not specified in the specific implementation methods, they shall be carried out according to the conventional conditions or the conditions recommended by the manufacturer.

[0031] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described exemplarily below do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims. The terms used in the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0032] A weak signal multi-channel synchronous acquisition system of the present invention comprises: a sensor for acquiring original weak signal source data, a signal conditioning module for amplifying and filtering the acquired weak signal source data, a multi-channel synchronous acquisition module, an FPGA core module, a power management module and a host computer; The above-mentioned sensor, signal conditioning module, multi-channel synchronous acquisition module, FPGA core module and host computer are electrically connected in sequence; the above-mentioned power management module is electrically connected to the above-mentioned signal conditioning module, multi-channel synchronous acquisition module and FPGA core module respectively; The signal conditioning module includes a single-ended to differential circuit, a programmable amplifier circuit, a programmable low-pass filter circuit, an analog-to-digital converter ADC, a digital signal processing module DSP, and a digital-to-analog converter DAC, which are electrically connected in sequence; the sensor is a multi-channel sensor, and the original weak signals collected by the sensor include physical signals and chemical signals; The weak signal source data is sequentially conditioned by the single-ended to differential circuit, the program-controlled amplifier circuit and the program-controlled low-pass filter to obtain a first signal, and the first signal enters the analog-to-digital converter ADC to be converted into a digital signal; The digital signal processing module DSP performs filtering, gain adjustment and spectrum analysis on the real-time input digital signal according to the parameters set by itself to obtain a second signal, and the second signal is converted into an analog signal by the digital-to-analog converter DAC to obtain the target electrical signal source data; The multi-channel synchronous acquisition module acquires the target electrical signal source data to obtain target digital signal source data, and transmits the target digital signal source data to the FPGA core module for filtering and downsampling to obtain target digital signal data, and then transmits the target digital signal data to the host computer for display.

[0033] In the present invention, under normal circumstances, the parameters set by the above-mentioned digital signal processing module DSP itself include: a low-pass filter with a cutoff frequency set to 550Hz, a band-pass filter with a frequency range of 90-310Hz, a dynamic gain range of 0-60dB, a gain adjustment step of 1dB, a target amplitude close to the ADC full scale of 2.4V, an FFT spectrum analysis point number of 1024, a Hanning window function spectrum refresh rate of 10Hz, a filter order of 10, and a temperature drift compensation coefficient of 0.001V / °C.

[0034] In the present invention, the sensor acquires raw data. The signal conditioning module is used to connect to the sensor. The main function of the signal conditioning module is to amplify and filter the weak signal source data collected by the sensor, adjust the amplitude of the weak signal to the voltage range of the multi-channel synchronous acquisition module input, and suppress the noise, so as to improve the quality of the weak signal and facilitate the acquisition by the multi-channel synchronous acquisition module. The multi-channel synchronous acquisition module performs multi-channel synchronous acquisition and converts the analog signal output by the signal conditioning module into a digital signal, so as to facilitate FPGA to process and transmit the data.

[0035] In the present invention, the functions of each circuit in the above signal conditioning module are as follows: The above-mentioned single-ended to differential circuit converts the single-ended input signal into a differential signal to reduce common-mode noise and provide a purer differential signal for subsequent amplification and filtering; The above-mentioned program-controlled amplifier circuit performs preliminary amplification on the signal and provides dynamic gain adjustment to adapt to the dynamic range of the input signal; The above-mentioned programmable low-pass filter circuit is used to filter out high-frequency noise and retain the low-frequency components in the signal; the cutoff frequency of the filter in the above-mentioned programmable low-pass filter circuit can be programmable to adapt to different signal frequency requirements and make the signal components in the target frequency range more prominent; The analog-to-digital converter ADC converts the analog signal into a digital signal so that the digital signal processing module DSP module can process it; The digital signal processing module DSP is used to pre-process the data, and the pre-processing includes: filter filtering, gain adjustment, spectrum analysis, adaptive signal processing and data correction and compensation.

[0036] Among them, filter filtering: various digital filtering (such as low-pass, band-pass, band-stop, adaptive filtering, etc.) can be implemented to further suppress noise; Among them, gain adjustment: the signal gain can be adjusted in the digital domain, and signals of different frequency bands can be amplified in stages according to needs; Among them, spectrum analysis: through algorithms such as fast Fourier transform (FFT), the spectrum components of the signal are analyzed in real time to help detect specific frequencies or signal characteristics; Among them, adaptive signal processing: can dynamically adjust the filter parameters or gains according to the changes in the input signal, so that the system can achieve the best signal-to-noise ratio in various environments; Among them, data correction and compensation: compensate for temperature drift, offset and other factors through correction algorithms to improve measurement accuracy and long-term stability; The digital-to-analog converter DAC converts the digital signal processed by the digital signal processing module DSP back into an analog signal to facilitate sampling by a subsequent system.

[0037] In some implementations, the FPGA core module includes the following seven modules: BUS_MUX multiplexing, parameter management, sampling control, clock management, data storage, power-on self-test, and interactive communication; The above-mentioned sampling control is connected to the above-mentioned multi-channel synchronous acquisition module, the above-mentioned parameter management is connected to the above-mentioned sampling control, the above-mentioned BUS_MUX multiplexing is respectively connected to the above-mentioned sampling control, data storage, power-on self-test and interactive communication, the above-mentioned clock management is respectively connected to the above-mentioned sampling control, data storage, BUS_MUX multiplexing and interactive communication, and the above-mentioned interactive communication is also connected to the above-mentioned host computer.

[0038] In the present invention, the FPGA core module controls each module in the entire weak signal multi-channel synchronous acquisition system, filters and downsamples the data, and transmits the processed target data to the host computer; the host computer module implements the software host computer display to visualize the target data; the power management module is used to control the power of all modules in the entire weak signal multi-channel synchronous acquisition system.

[0039] In the present invention, the BUS_MUX multiplexing module is used for the management between the internal modules of the FPGA core module, ensuring that the data and control signals between different modules can be reasonably shared and switched, and providing efficient resource allocation between modules; The parameter management module is used to manage the parameters of each module inside the FPGA core module, such as the number of sampling channels, sampling rate, data format, data bit width and system startup mode, and supports dynamic configuration and update to improve system flexibility; The above sampling control is used to control the front-stage multi-channel synchronous acquisition module, process the collected data information, and package the data according to the parameter configuration information; In some embodiments, the single-ended to differential circuit uses an AD8138 chip, the program-controlled amplifier circuit uses a PGA281 chip, and the program-controlled low-pass filter circuit uses an LTC1068 chip; the analog-to-digital converter ADC uses a first chip, and the first chip is an AD7606 chip; the digital signal processing module DSP uses a TMS320C6748 chip; the digital-to-analog converter DAC uses an AD5781 chip; In some implementations, the multi-channel synchronous acquisition module uses a second chip for synchronous acquisition, and each of the channels is equipped with a sample-and-hold circuit for ensuring synchronous sampling of each channel; the second chip is an AD7606 chip.

[0040] In some embodiments, the sampling control uses a third chip, which is an AD7606 chip; the data stored in the data is stored via EEPROM; and the power-on self-test executes a self-test program when the system is powered on to check the initialization status of the main functional modules.

[0041] In some implementations, the first chip, the second chip, and the third chip all have the function of supporting 8-channel synchronous acquisition with a resolution of 16 bits, and have three interfaces: a parallel interface, a high-speed serial interface, and a parallel byte interface.

[0042] In some implementations, the clock management controls the clock synchronization management of the multi-channel synchronous sampling module via a CONVST pulse signal; The clock management performs cross-clock domain management on data transmission between different modules directly connected to the clock management in the FPGA core module through the CONVST pulse signal; The above-mentioned CONVST pulse signal is a CONVST_A signal and a CONVST_B signal generated by the above-mentioned sampling control process; The above-mentioned cross-clock domains include bus clock domain, ADC acquisition clock domain, EEPROM storage clock domain and interactive communication clock domain; The bus clock domain is multiplexed by the BUS_MUX to realize data interaction between modules and provide unified data routing services; The ADC acquisition clock domain is used for the sampling control and is responsible for generating a control signal that triggers an ADC sampling event. The EEPROM storage clock domain is used to provide an independent clock for the data storage, and supports cross-clock domain storage after data acquisition is completed; The interactive communication clock domain is used for the interactive communication and provides an interface for data reading and transmission.

[0043] In the present invention, clock management is responsible for the synchronous clock management in the entire weak signal multi-channel synchronous acquisition system, including clock division, phase correction and jitter control functions, to ensure the stability of clock synchronization between system modules and cross-clock domain data transmission.

[0044] In the present invention, the power-on self-check executes a series of self-check programs when the entire weak signal multi-channel synchronous acquisition system is powered on, checks the initialization status of the main functional modules, and ensures that the system runs in a stable state.

[0045] In some implementations, the interactive communication is a dual-channel parallel structure, and the dual channels are a UART data transmission path supporting low-speed communication and an Ethernet data transmission path supporting high-speed communication.

[0046] In the present invention, the interactive communication module is used to connect external communication hardware, such as UART, Ethernet and other interfaces, to provide data uploading and control command receiving functions for the entire weak signal multi-channel synchronous acquisition system, and to support multiple communication protocols to adapt to different application requirements; the dual-channel parallel structure corresponds to the UART and Ethernet transmission paths respectively, to ensure independent data caching and processing for each channel; the communication mode selection control logic selects or switches the communication mode through system parameter configuration to ensure seamless connection of different modes; the clock configuration is used to unify the clock source and manage data transmission between different clock domains to ensure the stability of the system and the accuracy of transmission.

[0047] In some implementations, the host computer uses LabVIEW software for data processing and visualization, and the main program flow of the host computer uses an interrupt-triggered data receiving mechanism.

[0048] In the present invention, LabVIEW software can provide a friendly graphical interface, which is convenient for real-time monitoring of the collected multi-channel synchronous data and supports real-time processing, analysis and storage of data; the above-mentioned host computer can also generate data reports, waveform displays and spectrum analysis according to needs, and users can dynamically observe data changes in different channels by adjusting parameters, thereby improving the usability and interactivity of the system.

[0049] In the present invention, the power management module provides a stable and reliable power supply for the entire weak signal multi-channel synchronous acquisition system; the power management module can allocate appropriate voltage and current according to the power requirements of different modules to ensure stable operation of the system; the power management module also has overcurrent protection, overvoltage protection and temperature monitoring functions to prevent system failures caused by power supply abnormalities; the power management module can realize dynamic power control, automatically adjust power consumption according to the system working status, effectively extend the system life and improve energy efficiency.

[0050] In some implementations, the power-on self-test uses a finite state machine (FSM) to control the entire self-test process.

[0051] The present invention is further described in detail below in conjunction with specific embodiments.

[0052] Embodiment 1: like Figure 1 As shown, a weak signal multi-channel synchronous acquisition system 100 of the present invention includes: a sensor 110 for acquiring original weak signal source data, a signal conditioning module 120 for amplifying and filtering the acquired weak signal source data, and a multi-channel synchronous acquisition module 130, an FPGA core module 140, a power management module 160 and a host computer 150.

[0053] The sensor 110, the signal conditioning module 120, the multi-channel synchronous acquisition module 130, the FPGA core module 140 and the host computer 150 are electrically connected in sequence; the power management module 160 is electrically connected to the signal conditioning module 120, the multi-channel synchronous acquisition module 130 and the FPGA core module 140 respectively.

[0054] Among them, the signal conditioning module 120 includes a single-ended to differential circuit, a programmable amplification circuit, a programmable low-pass filter circuit, an analog-to-digital converter ADC, a digital signal processing module DSP, and a digital-to-analog converter DAC, which are electrically connected in sequence; the sensor 110 is a multi-channel sensor, and the original weak signals collected by the sensor 110 include physical signals or chemical signals, such as: acoustic signals, optical signals, and magnetic signals.

[0055] The power management module 160 is involved in the power supply of the internal logic circuit, I / O, ADC and signal conditioning auxiliary modules of the FPGA core module 140 .

[0056] like Figure 2 As shown, the weak signal source data is the parameter electrical signal source data D210. The parameter electrical signal source data D210 is initially conditioned by a single-ended to differential circuit, a programmable amplifier circuit and a programmable low-pass filter in sequence to obtain a first signal. The first signal enters the analog-to-digital converter ADC and is converted into a digital signal. The digital signal processing module DSP adopts a signal processing method combining a low-pass filter and a band-pass filter. The cutoff frequency of the low-pass filter is set to 550Hz, the frequency range of the band-pass filter is set to 90-310Hz, the dynamic gain range is 0-60dB, the gain adjustment step is 1dB, the target amplitude is close to the ADC full scale 2.4V, supports FFT spectrum analysis, the number of points is 1024, the Hanning window function is used, the spectrum refresh rate is 10Hz, the adaptive signal processing is based on the LMS algorithm, the filter order is 10th order, and it includes a temperature drift compensation coefficient of 0.001V / °C and an offset compensation function to filter, gain adjust and spectrum analyze the real-time input digital signal to obtain a second signal. The second signal is converted into an analog signal through a digital-to-analog converter DAC to obtain the target electrical signal source data D220.

[0057] The multi-channel synchronous acquisition module 130 acquires the target electrical signal source data D220 to obtain the target digital signal source data D230, and passes the target digital signal source data D230 to the FPGA core module 140 for filtering and downsampling to obtain the target digital signal data D240, and then passes the target digital signal data D240 to the host computer 150 for display.

[0058] like Figure 1 and Figure 5 As shown, the FPGA core module 140 includes the following seven modules: BUS_MUX multiplexing 370, parameter management 320, sampling control 310, clock management 350, data storage 330, power-on self-test 340 and interactive communication 360; The sampling control is connected to the multi-channel synchronous acquisition module 130, the parameter management is connected to the sampling control, the BUS_MUX multiplexing is respectively connected to the sampling control, data storage, power-on self-test and interactive communication, the clock management is respectively connected to the sampling control, data storage, BUS_MUX multiplexing and interactive communication, and the interactive communication is also connected to the host computer 150.

[0059] In this embodiment 1, the AD8138 chip is used in the single-ended to differential circuit, the PGA281 chip is used in the programmable amplifier circuit, and the LTC1068 chip is used in the programmable low-pass filter circuit; the first chip is used in the analog-to-digital converter ADC, and the first chip is the AD7606 chip; the TMS320C6748 chip is used in the digital signal processing module DSP, and the AD5781 chip is used in the digital-to-analog converter DAC.

[0060] The multi-channel synchronous acquisition module 130 uses a second chip for synchronous acquisition, and each channel is equipped with a sample-and-hold circuit for ensuring synchronous sampling of each channel; the second chip is an AD7606 chip.

[0061] The sampling control adopts the third chip, which is the AD7606 chip; the data stored is stored through EEPROM; the power-on self-test executes the self-test program when the system is powered on to check the initialization status of the main functional modules.

[0062] The first chip, the second chip and the third chip all have the function of supporting 8-channel synchronous acquisition with a resolution of 16 bits, and have three interfaces: parallel interface, high-speed serial interface and parallel byte interface.

[0063] The clock management module is responsible for generating the basic clock signal and the CONVST pulse signal used to control sampling, ensuring the synchronization of multi-channel sampling. The CONVST_A signal and CONVST_B signal of the CONVST pulse signal are used to control the sampling trigger of channels 1-4 and channels 5-8 respectively, thereby realizing the synchronous control of the multi-channel sampling module; The clock management performs cross-clock domain management when data is transmitted between different modules directly connected to the FPGA core module 140 by generating a CONVST pulse signal; Cross-clock domains include bus clock domain, ADC acquisition clock domain, EEPROM storage clock domain and interactive communication clock domain: Bus clock domain: Provides unified data routing services, and the BUS_MUX multiplexing module realizes data interaction between modules. Through the cross-clock domain synchronization mechanism, it coordinates data transmission in different clock domains to ensure the stability and consistency of communication between modules in the system; ADC acquisition clock domain: used for sampling control, responsible for generating control signals (such as CONVST_A / B) that trigger ADC sampling events, and passing the collected sampling data from the ADC module to the main data processing module through the cross-clock domain signal control mechanism. This clock domain emphasizes high-speed, accurate triggering and data acquisition synchronization; EEPROM storage clock domain: provides an independent clock for data storage and supports cross-clock domain storage after data acquisition is completed. This domain implements stable writing and reading of data through a synchronization mechanism and can process data from different sampling modules or communication modules to ensure data integrity and access efficiency; Interactive communication clock domain: used for interactive communication, providing an interface for data reading and transmission. By reading data from the storage module or sampling module and transmitting it across the clock domain to the communication interface such as UART or Ethernet, the requirements of different communication rates and protocols within the system can be met.

[0064] The pulse signal control generated by the FPGA core module realizes efficient timing control, ensures data consistency, and avoids phase misalignment caused by time delay. The AD7606 chip has high precision and high sampling rate, which can meet the needs of high-performance data acquisition. One AD7606 chip can complete the sampling of 8 channels, reducing the number and complexity of components on the circuit board, and reducing the cost and power consumption of the system.

[0065] like Figure 5 As shown, the interactive communication is a dual-channel parallel structure 380, and the dual channels are a UART data transmission path supporting low-speed communication and an Ethernet data transmission path supporting high-speed communication.

[0066] The host computer 150 uses LabVIEW software for data processing and visualization display, and the main program flow of the host computer 150 uses an interrupt-triggered data receiving mechanism.

[0067] like Figure 3 As shown, it is a flowchart of the implementation of synchronous multi-channel sampling of the multi-channel synchronous acquisition module 130. The multi-channel synchronous acquisition module 130 is configured with an ADC conversion mode T420. The multi-channel synchronous acquisition module 130 is connected to the FPGA core module 140 to generate an accurate CONVST signal T410 to ensure that each sampling starts at the same time. Among them, the connection CONVST signal T410 of the multi-channel synchronous acquisition module 130 can start the sampling of all channels at the same time by applying a synchronous pulse signal to the CONVST_A and CONVST_B pins of the FPGA core module 140; Configure ADC conversion mode T420. Under high-frequency acquisition requirements, set the AD7606 of the multi-channel synchronous acquisition module 130 to continuous sampling mode, and maintain sampling stability through a high-frequency CONVST pulse; Reading data T430 means that after receiving the sampling control CONVST signal from the FPGA core module 140, the AD7606 of the multi-channel synchronous acquisition module 130 will enter the sampling and holding mode, complete the data acquisition of 8 channels through the triggering of the sampling control module, and latch the acquired data into the EEPROM register inside the FPGA core module 140; when the BUSY pin of the BUS_MUX multiplexer becomes low, it means that the analog-to-digital conversion inside the AD7606 is completed, and the data can be read through its parallel or serial interface. At this time, the sampling data of the 8 channels of the AD7606 has been locked as synchronous data, ensuring that the multi-channel data is collected at the same time; The output data T440 is output to the FPGA by selecting a suitable interface after the multi-channel synchronous acquisition module 130 completes data acquisition.

[0068] like Figure 4 As shown, in this embodiment 1, in the signal conditioning module 120, the single-ended to differential circuit adopts the low-distortion differential driver AD8138 210. The program-controlled amplifier circuit adopts PGA281 220 to realize the program-controlled amplification function, and the program-controlled amplifier circuit adopts the variable gain amplifier AD8367 230 to realize automatic gain control. The function of the program-controlled amplifier circuit is to keep the amplitude of the output signal within a stable range regardless of how the strength of the input signal changes, thereby avoiding distortion or noise caused by too weak or too strong signals. The program-controlled low-pass filter circuit adopts LTC1068 240 to realize the low-pass filter function, filter out high-frequency noise, and retain the low-frequency components in the signal. The analog-to-digital converter ADC adopts AD7606 250 to convert the analog signal into a digital signal for processing by subsequent modules. The digital signal processing module DSP adopts TMS320C6748 260 to process the digital signal, further suppress the noise, and perform hierarchical amplification of the signal according to the needs. The digital-to-analog converter DAC uses a high-precision digital-to-analog converter AD5781 270 to restore the processed digital signal into an analog signal for easy collection by the subsequent system.

[0069] Compared with the prior art, this embodiment 1 makes the input of source data more general through the variable gain amplifier AD8367 230. The high-performance DSP architecture, hardware acceleration, rich interfaces and optimized algorithm support of TMS320C6748 260 have significant advantages in the collection, real-time processing and feature extraction of weak signals, and improves the sampling capability and quality of the system.

[0070] like Figure 5As shown, in this embodiment 1, the FPGA core module 140 includes the following seven modules: BUS_MUX multiplexing 370, parameter management 320, sampling control 310, clock management 350, data storage 330, power-on self-test 340 and interactive communication 360.

[0071] The sampling control 310 is an AD7606 sampling control, which has the function of driving control and assembling and caching the data input to the FPGA core module 140 according to a series of parameters read in advance from the parameter management 320. The parameter management 320 implements the management of the number of sampling channels and the baud rate, and implements the management of the data packet format of the packet header, data, and packet tail. The parameter management can increase the versatility and flexibility of the system. The data storage 330 adopts the AT24C64 driver to realize the storage of the processing data and configuration parameters in the EEPROM, which is convenient for reading resources after powering on again after power failure. The power-on self-test 340 can automatically perform a self-diagnosis process when the system is powered on, check the basic functions and availability of the equipment hardware, and ensure that the basic components of the system are working properly. The clock management 350 is used to synchronize the clock management of the multi-channel synchronous sampling module 130 by generating a CONVST pulse signal to realize the synchronous acquisition function and to realize cross-clock domain management when data is transmitted between different modules to ensure data transmission security, involving the management of the bus clock domain, ADC acquisition clock domain, EEPROM storage clock domain, and interactive communication clock domain.

[0072] like Figure 5 As shown, the interactive communication 360 is provided with a dual-channel parallel structure 380, a communication mode selection control 390, and a clock configuration 300. The dual-channel parallel structure 380 realizes the design of supporting both UART for low-speed communication and Ethernet data transmission for high-speed communication, and different data transmission interfaces can be selected according to different needs and usage environments; the design of the dual-channel parallel structure 380 corresponds to the UART and Ethernet transmission paths respectively, allowing each channel to cache and process data independently to ensure the independence and efficiency of communication. The design of the communication mode selection control 390 can select or switch the communication mode through system parameter configuration to ensure seamless connection of different modes. The design of the clock configuration 300 is used to unify the internal clock source and manage data transmission between different clock domains to ensure the stability of the system and the accuracy of transmission.

[0073] BUS_MUX multiplexer 370 realizes signal selection and bus sharing, realizes interconnection between modules, reduces the number of lines, optimizes resource utilization, and improves system flexibility.

[0074] The power-on self-test 340 enhances the reliability of the system during use.

[0075] Parameter management 320 allows flexible control of the parameters of each module during system use, and can be configured according to actual needs.

[0076] like Figure 6 As shown, it is a power-on self-test flow chart of the power-on self-test 340 module of this embodiment 1. The power-on self-test 340 uses a finite state machine FSM to control the entire self-test process. When the weak signal multi-channel synchronous acquisition system 100 is powered on or reset, the FSM enters the self-test state U400, and gradually tests each module of the weak signal multi-channel synchronous acquisition system 100. The FSM enters the self-test state U400, and performs clock and reset signal detection U410, configuration and initialization detection U420, module self-test U430, and peripheral detection U440 in sequence; then, the self-test result U450 is output. If the self-test result U450 is 1, the working state of each module is normal, and the self-test ends; if it is 0, it returns.

[0077] like Figure 6 As shown, the clock and reset signal detection U410 is used to check whether the main clock source and reset signal are normal, ensuring that the working clock of each module is stable. The phase-locked loop PLL module of the FPGA core module 140 can be used to monitor and detect the stability of the clock signal, and the internal counter is used to check whether the reset signal is released on schedule to ensure correct timing. The configuration and initialization detection U420 is used to check the configuration register value of the FPGA to confirm whether the configuration is successful. The module self-test U430 is used to test the functions of each module. The present invention mainly involves parameter management, sampling control, communication interface and data storage detection. The peripheral detection U440 is used to check the conversion function by outputting a known signal and reading its return value; the present invention mainly involves the detection of ADC. If the self-test result U450 is 1, the working status of each module is normal and the self-test ends; if it is 0, it returns.

[0078] like Figure 7 As shown, the main program flow chart of the host computer 150 of this embodiment 1, the host computer 150 adopts an interrupt-triggered data receiving mechanism.

[0079] like Figure 7As shown, the main program flow of the host computer 150 is as follows: the main program is initialized S310, including device initialization, interface initialization, data buffer allocation and interrupt enablement, etc.; after receiving data, the main program reads data from the buffer and processes, displays and stores data S320, and then determines whether the process ends S330. If the process ends Y, the main program is initialized S310, otherwise N determines the interrupt instruction S340; if the interrupt Y is executed, data is cached S360; otherwise N saves the file S350, and then repeats the same operation again. This interrupt processing method allows the system to respond in time according to the priority of the current process, reduce unnecessary CPU burden, and improve resource utilization efficiency and response speed.

[0080] The present invention is described by the above-mentioned specific implementation methods and embodiments, and it should be understood by those skilled in the art that various changes and equivalent substitutions may be made to the present invention without departing from the scope of the present invention. The parts not described in detail in the present specification are known to those skilled in the art. In addition, various modifications may be made to the present invention for specific situations or specific circumstances without departing from the scope of the present invention. Therefore, the present invention is not limited to the disclosed specific embodiments, but should include all implementation methods falling within the scope of the claims of the present invention.

Claims

1. A weak signal multi-channel synchronous acquisition system, characterized in that: include: A sensor for collecting original weak signal source data, a signal conditioning module for amplifying and filtering the collected weak signal source data, a multi-channel synchronous acquisition module, an FPGA core module, a power management module and a host computer; The sensor, signal conditioning module, multi-channel synchronous acquisition module, FPGA core module and host computer are electrically connected in sequence; the power management module is electrically connected to the signal conditioning module, multi-channel synchronous acquisition module and FPGA core module respectively; The signal conditioning module includes a single-ended to differential circuit, a programmable amplifier circuit, a programmable low-pass filter circuit, an analog-to-digital converter ADC, a digital signal processing module DSP, and a digital-to-analog converter DAC, which are electrically connected in sequence; the sensor is a multi-channel sensor, and the original weak signals collected by the sensor include physical signals and chemical signals; The weak signal source data is sequentially conditioned by the single-ended to differential circuit, the program-controlled amplifier circuit and the program-controlled low-pass filter to obtain a first signal, and the first signal enters the analog-to-digital converter ADC to be converted into a digital signal; the digital signal processing module DSP filters, adjusts the gain and performs spectrum analysis operations on the real-time input digital signal according to the parameters set by itself to obtain a second signal, and the second signal is converted into an analog signal by the digital-to-analog converter DAC to obtain the target electrical signal source data; The multi-channel synchronous acquisition module acquires the target electrical signal source data to obtain target digital signal source data, and passes the target digital signal source data to the FPGA core module for filtering and downsampling to obtain target digital signal data, and then passes the target digital signal data to the host computer for display.

2. The weak signal multi-channel synchronous acquisition system according to claim 1, characterized in that: The FPGA core module includes the following seven modules: BUS_MUX multiplexing, parameter management, sampling control, clock management, data storage, power-on self-test and interactive communication; The sampling control is connected to the multi-channel synchronous acquisition module, the parameter management is connected to the sampling control, the BUS_MUX multiplexing is respectively connected to the sampling control, data storage, power-on self-test and interactive communication, the clock management is respectively connected to the sampling control, data storage, BUS_MUX multiplexing and interactive communication, and the interactive communication is also connected to the host computer.

3. The weak signal multi-channel synchronous acquisition system according to claim 2 is characterized in that: The single-ended to differential circuit uses an AD8138 chip, the program-controlled amplifier circuit uses a PGA281 chip, and the program-controlled low-pass filter circuit uses an LTC1068 chip; The analog-to-digital converter ADC adopts a first chip, which is an AD7606 chip; the digital signal processing module DSP adopts a TMS320C6748 chip; and the digital-to-analog converter DAC adopts an AD5781 chip.

4. The weak signal multi-channel synchronous acquisition system according to claim 3 is characterized in that: The multi-channel synchronous acquisition module uses a second chip for synchronous acquisition, and each channel is equipped with a sample-and-hold circuit for ensuring synchronous sampling of each channel; the second chip is an AD7606 chip.

5. The weak signal multi-channel synchronous acquisition system according to claim 4 is characterized in that: The sampling control adopts a third chip, which is an AD7606 chip; the data stored in the data is stored through EEPROM; the power-on self-test executes a self-test program when the system is powered on to check the initialization status of the main functional modules.

6. The weak signal multi-channel synchronous acquisition system according to claim 5, characterized in that: The first chip, the second chip and the third chip all have the function of supporting 8-channel synchronous acquisition with a resolution of 16 bits, and have three interfaces: parallel interface, high-speed serial interface and parallel byte interface.

7. The weak signal multi-channel synchronous acquisition system according to claim 6, characterized in that: The clock management controls the clock synchronization management of the multi-channel synchronous sampling module through the CONVST pulse signal; The clock management performs cross-clock domain management on data transmission between different modules directly connected to the clock management in the FPGA core module through the CONVST pulse signal; The CONVST pulse signal is a CONVST_A signal and a CONVST_B signal generated by the sampling control process; The cross-clock domain includes a bus clock domain, an ADC acquisition clock domain, an EEPROM storage clock domain and an interactive communication clock domain; The bus clock domain is multiplexed by the BUS_MUX to realize data interaction between modules and provide unified data routing services; The ADC acquisition clock domain is used for the sampling control and is responsible for generating a control signal that triggers an ADC sampling event; The EEPROM storage clock domain is used to provide an independent clock for the data storage, supporting cross-clock domain storage after data acquisition is completed; The interactive communication clock domain is used for the interactive communication and provides an interface for data reading and transmission.

8. The weak signal multi-channel synchronous acquisition system according to claim 7, characterized in that: The interactive communication is a dual-channel parallel structure, and the dual channels are a UART data transmission path supporting low-speed communication and an Ethernet data transmission path supporting high-speed communication.

9. The weak signal multi-channel synchronous acquisition system according to claim 8, characterized in that: The host computer uses LabVIEW software to process data and perform visual display, and the main program flow of the host computer uses an interrupt-triggered data receiving mechanism.

10. The weak signal multi-channel synchronous acquisition system according to claim 9, characterized in that: The power-on self-test uses a finite state machine FSM to control the entire self-test process.

Images