High electron mobility transistor and preparation method thereof

Abstract

The invention provides a high electron mobility transistor and a preparation method thereof, and relates to the technical field of transistor design. Comprising a substrate, a nucleating layer, a buffer layer and an electrode layer which are stacked in sequence, at least one set of multi-channel structure is arranged between the buffer layer and the electrode layer, the multi-channel structure comprises a plurality of heterojunction structure layers and a cap layer, all the heterojunction structure layers are stacked, and the cap layer is located on the upper surface of the uppermost heterojunction structure layer; each heterojunction structure layer comprises a GaN channel layer and an AlScN barrier layer which are arranged in a stacked mode, the GaN channel layers and the AlScN barrier layers of every two adjacent heterojunction structure layers are alternately stacked, and the GaN channel layers and the AlScN barrier layers are connected to form a heterojunction and form an interface with a two-dimensional electron gas channel. According to the high-electron-mobility transistor, the performance of the transistor is improved by changing the material forming the heterojunction and designing a multi-communication structure, so that the requirements of high frequency and high power are better met.

Description

Technical Field

[0001] The present invention relates to the technical field of transistor design, and in particular to a high electron mobility transistor and a preparation method thereof. Background Art

[0002] A high electron mobility transistor, also known as a modulation-doped field-effect transistor, is a type of field-effect transistor. It uses two materials with different energy gaps to form a heterojunction to provide a channel for carriers. It is an indispensable device in most power electronic products. Existing high electron mobility transistors generally use AlGaN and GaN materials to form a heterojunction and are often designed as a single-channel structure with only one layer of heterojunction. As a result, existing high electron mobility transistors are difficult to meet the needs of high frequency and high power.

[0003] There is currently no effective technical solution to the above problems. Summary of the invention

[0004] The purpose of the present invention is to provide a high electron mobility transistor and a method for preparing the same, by changing the material constituting the heterojunction and designing a multi-channel structure to improve the transistor performance, thereby better meeting the requirements of high frequency and high power.

[0005] In a first aspect, the present invention provides a high electron mobility transistor, comprising a substrate, a nucleation layer, a buffer layer and an electrode layer stacked in sequence, at least one group of multi-channel structures is arranged between the buffer layer and the electrode layer, the multi-channel structure comprises a plurality of heterojunction structure layers and a cap layer, all the heterojunction structure layers are stacked, and the cap layer is located on the upper surface of the uppermost heterojunction structure layer; The heterojunction structure layer includes a stacked GaN channel layer and an AlScN barrier layer, and the GaN channel layers and the AlScN barrier layers of two adjacent heterojunction structure layers are alternately stacked. The GaN channel layer and the AlScN barrier layer are connected to form a heterojunction and form an interface with a two-dimensional electron gas channel.

[0006] The high electron mobility transistor provided by the present invention uses AlScN and GaN materials to form a heterojunction and is designed into a multi-channel structure in which multiple heterojunctions are stacked, thereby improving the performance of the transistor and enabling it to better meet the requirements of high frequency and high power.

[0007] Furthermore, a plurality of groups of the multi-channel structures are arranged between the buffer layer and the electrode layer, and all the multi-channel structures are stacked.

[0008] Furthermore, all the multi-channel structures include the same number of heterojunction structure layers.

[0009] Furthermore, all the multi-channel structures include different numbers of heterojunction structure layers.

[0010] Furthermore, a portion of the multi-channel structures include the same number of heterojunction structure layers, and another portion of the multi-channel structures include a different number of heterojunction structure layers.

[0011] Furthermore, a first multi-channel structure and a second multi-channel structure are provided between the buffer layer and the electrode layer, the first multi-channel structure includes a first heterojunction structure layer, a second heterojunction structure layer and a first cap layer, the first heterojunction structure layer includes a first GaN channel layer and a first AlScN barrier layer, and the second heterojunction structure layer includes a second GaN channel layer and a second AlScN barrier layer; The second multi-channel structure includes a third heterojunction structure layer, a fourth heterojunction structure layer, a fifth heterojunction structure layer and a second cap layer, the third heterojunction structure layer includes a third GaN channel layer and a third AlScN barrier layer, the fourth heterojunction structure layer includes a fourth GaN channel layer and a fourth AlScN barrier layer, and the fifth heterojunction structure layer includes a fifth GaN channel layer and a fifth AlScN barrier layer; Among them, the first GaN channel layer is stacked on the upper surface of the buffer layer, the second GaN channel layer is stacked on the upper surface of the first AlScN barrier layer; the third GaN channel layer is stacked on the upper surface of the first cap layer, the fourth GaN channel layer is stacked on the upper surface of the third AlScN barrier layer, and the fifth GaN channel layer is stacked on the upper surface of the fourth AlScN barrier layer; the electrode layer is stacked on the upper surface of the second cap layer.

[0012] Furthermore, the electrode layer includes a source, a gate and a drain arranged at intervals, and the interval between the source and the gate, and the interval between the gate and the drain are covered with a passivation layer, and the passivation layer is stacked on the upper surface of the second cap layer.

[0013] Furthermore, the nucleation layer is made of AlN material; the buffer layer is made of GaN material; the first cap layer and the second cap layer are both made of BaTiO3 material; and the passivation layer is made of Si3N4 material.

[0014] Furthermore, the source electrode and the drain electrode are both made of Ti-Al-Ni-Au alloy material, and the gate electrode is made of Ni-Au alloy material.

[0015] In a second aspect, the present invention provides a method for preparing the high electron mobility transistor described above, comprising the following steps: S1. Based on metal organic chemical vapor deposition, the nucleation layer and the buffer layer are sequentially formed on the upper surface of the substrate; S2. All the multi-channel structures are sequentially manufactured on the upper surface of the buffer layer, and the following steps S21-S22 are performed when manufacturing each multi-channel structure: S21. According to the number of heterojunction structure layers to be set, the following step S211 is executed in a loop until all the heterojunction structure layers are completed and the loop is exited: S211. Based on a metal organic chemical vapor deposition method, a GaN channel layer and a new AlScN barrier layer are sequentially formed on the upper surface of the buffer layer or the upper surface of the previous AlScN barrier layer; S22. Based on the pulsed laser deposition method, a cap layer is formed on the upper surface of the uppermost heterojunction structure layer; S3. Fabricating the electrode layer on the upper surface of the uppermost multi-channel structure.

[0016] From the above, it can be seen that the high electron mobility transistor provided by the present invention uses AlScN and GaN materials to form a heterojunction, which can effectively improve the saturated drain current density of the transistor, so that the transistor can meet higher frequency requirements. The present invention also stacks multiple heterojunctions to obtain more two-dimensional electron gas channels, which is beneficial for the transistor to obtain more two-dimensional electron gas, so that the transistor can achieve a larger current and thus meet higher power requirements.

[0017] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or be understood by implementing the embodiments of the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic structural diagram of a high electron mobility transistor provided in an embodiment of the present invention.

[0019] Figure 2 A flow chart of a preparation method provided in an embodiment of the present invention.

[0020] Description of labels: 100, substrate; 200, nucleation layer; 300, buffer layer; 410, heterojunction structure layer; 411, GaN channel layer; 412, AlScN barrier layer; 420, cap layer; 500, electrode layer; 510, source; 520, gate; 530, drain; 610, first heterojunction structure layer; 611, first GaN channel layer; 612, first AlScN barrier layer; 620, second heterojunction structure layer; 621, second GaN channel layer; 62 2. The second AlScN barrier layer; 630. The first cap layer; 710. The third heterojunction structure layer; 711. The third GaN channel layer; 712. The third AlScN barrier layer; 720. The fourth heterojunction structure layer; 721. The fourth GaN channel layer; 722. The fourth AlScN barrier layer; 730. The fifth heterojunction structure layer; 731. The fifth GaN channel layer; 732. The fifth AlScN barrier layer; 740. The second cap layer; 800. The passivation layer. DETAILED DESCRIPTION

[0021] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0022] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0023] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0024] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0025] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplicity and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides various specific examples of processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0026] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.

[0027] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0028] As a type of field effect transistor, high electron mobility transistor plays a key role in power electronic products. However, existing high electron mobility transistors usually use a single-channel structure with a single heterojunction composed of AlGaN and GaN materials. This design has obvious limitations in meeting high-frequency and high-power requirements. Specifically, the single-channel structure limits the current density and power density of the device, making it difficult to achieve higher operating frequencies and greater output power. In addition, the traditional AlGaN / GaN heterojunction structure also has certain bottlenecks in terms of carrier density and two-dimensional electron gas concentration, which restricts further improvement of device performance.

[0029] This problem is particularly prominent in the application of RF power amplifiers in 5G communication base stations. The base station needs to process signals in multiple frequency bands at the same time, requiring the power amplifier to have high-frequency broadband and high-power output capabilities. For example, in a 5G base station in the 3.5 GHz band, the power amplifier needs to provide at least 50 W of output power in a bandwidth range of 20 MHz to 100 MHz while maintaining high efficiency and good linearity. However, it is difficult for power amplifiers using existing high electron mobility transistor technology to meet these requirements at the same time. In practical applications, problems such as insufficient output power, reduced efficiency or deteriorated linearity may occur. Specifically, when the operating frequency is increased to above 3 GHz, the high electron mobility transistor with a traditional single-channel structure may experience a significant power drop, and the efficiency may drop from the ideal 60% to 40% or even lower, which seriously affects the coverage and energy efficiency of the base station.

[0030] Reference Figure 1 The present invention provides a high electron mobility transistor, comprising a substrate 100, a nucleation layer 200, a buffer layer 300 and an electrode layer 500 stacked in sequence, at least one set of multi-channel structures is arranged between the buffer layer 300 and the electrode layer 500, the multi-channel structure comprises a plurality of heterojunction structure layers 410 and a cap layer 420, all the heterojunction structure layers 410 are stacked, and the cap layer 420 is located on the upper surface of the uppermost heterojunction structure layer 410; The heterojunction structure layer 410 includes a stacked GaN channel layer 411 and an AlScN barrier layer 412, and the GaN channel layer 411 and the AlScN barrier layer 412 of two adjacent heterojunction structure layers 410 are alternately stacked, and the GaN channel layer 411 and the AlScN barrier layer 412 are connected to form a heterojunction and form an interface with a two-dimensional electron gas channel.

[0031] In this embodiment, each heterojunction structure layer 410 includes a GaN channel layer 411 and an AlScN barrier layer 412 stacked in sequence. The GaN channel layer 411 and the AlScN barrier layer 412 are connected to form a heterojunction, and an interface with a two-dimensional electron gas channel is formed at the interface. The design of the multi-channel structure can significantly improve the current density and power density of the device. For example, at the same device area, the three-channel structure can provide up to 3 times the current density than the single-channel structure. This design enables the device to operate at a higher frequency while maintaining a low on-resistance.

[0032] At the same time, the combination of the GaN channel layer 411 and the AlScN barrier layer 412 has a higher carrier density than the conventional AlGaN / GaN structure. Experimental data show that the AlScN / GaN heterojunction can generate up to 3×10 13 cm 2 The 2D electron gas concentration is more than 50% higher than that of the conventional AlGaN / GaN structure. This high concentration of 2D electron gas helps to increase the saturated drain current density, thereby increasing the operating frequency of the device.

[0033] In addition, the introduction of the AlScN barrier layer is a key innovation of this application. AlScN has a larger bandgap (about 6.0-6.3eV) and a higher polarization effect. These characteristics enable the AlScN / GaN interface to produce a higher concentration of two-dimensional electron gas, while increasing the breakdown voltage of the device. For example, using Al0.7Sc0.3N as a barrier layer can increase the breakdown voltage of the device to more than 200V, while the traditional AlGaN / GaN structure can usually only reach 100-150V.

[0034] In addition, the stacking design of multiple heterojunction structure layers 410 is another important feature. By precisely controlling the thickness and doping concentration of each layer, the coordinated operation of multiple two-dimensional electron gas channels can be achieved. For example, the thickness of the GaN channel layer 411 can be set within the range of 10-20nm, while the thickness of the AlScN barrier layer 412 can be adjusted between 3-5nm. This multilayer structure not only increases the total amount of two-dimensional electron gas, but also effectively reduces the on-resistance of the device.

[0035] Finally, the provision of the cap layer 420 further enhances the performance of the device. The cap layer 420 can be made of a material with a high dielectric constant, such as BaTiO3. This material can provide a stronger electric field confinement effect and further increase the concentration of the two-dimensional electron gas. At the same time, the cap layer 420 can also serve as an effective surface passivation layer to reduce the impact of surface states on device performance. In addition, the cap layer 420 can increase the lateral breakdown voltage of the device and further meet the high-power working requirements. There is a close relationship and interaction between the various parts of the high electron mobility transistor structure. The substrate 100, the nucleation layer 200 and the buffer layer 300 provide a good crystal growth foundation for the entire device, ensuring the high quality of the heterojunction structure. The various heterojunction structure layers 410 in the multi-channel structure achieve an optimized distribution of the two-dimensional electron gas channel through carefully designed thickness and composition. The cap layer 420 works in conjunction with the top heterojunction structure layer 410 to enhance the electron confinement effect and provide surface protection.

[0036] Overall, this new high electron mobility transistor structure has successfully improved the high-frequency and high-power performance of the device through multi-channel design and the introduction of new materials. For example, in applications in the 3.5GHz frequency band, devices using this structure can achieve a power density of more than 100W / mm while maintaining a power added efficiency of more than 50%. This performance level far exceeds that of traditional single-channel AlGaN / GaN devices and can effectively meet the needs of 5G communication systems for high-frequency and high-power devices.

[0037] This multi-channel structure design significantly improves the current density of the device. Experimental tests show that under the same gate size, the maximum saturation current density of the dual-group multi-channel structure (a total of 6 heterojunction structure layers) of this application is about 5 times higher than that of the traditional single-channel structure, reaching 3A / mm. This high current density directly translates into higher output power, allowing the device to achieve a power density of more than 15W / mm in the 3.5GHz frequency band while maintaining a power added efficiency of more than 50%.

[0038] Compared with the prior art, the high electron mobility transistor of the present application has significant advantages in many aspects. First, the design of the multi-channel structure overcomes the limitation of the traditional single-channel structure in terms of current density. By increasing the number of heterojunction structure layers 410, the total current carrying capacity of the device is effectively improved, thereby significantly improving the output power.

[0039] Secondly, the use of AlScN as the barrier layer material is a key innovation of this application. Compared with traditional AlGaN materials, AlScN has a larger bandgap and a stronger polarization effect. This enables the AlScN / GaN interface to produce a higher concentration of two-dimensional electron gas. Experimental data show that the Al0.7Sc0.3N / GaN heterojunction can produce up to 3×10 13 cm 2 The 2D electron gas concentration is about 50% higher than that of the conventional Al0.3Ga0.7N / GaN structure. This high concentration of 2D electron gas not only increases the current density of the device, but also improves its high-frequency performance.

[0040] In addition, the capping layer design introduced in this application further enhances the device performance. The BaTiO3 capping layer 420 not only provides effective surface passivation, but also enhances the confinement effect on the two-dimensional electron gas due to its high dielectric constant (εr>300). This design enables the device to better suppress the short channel effect and maintain good transconductance characteristics when operating at high frequencies. It also improves the lateral breakdown voltage of the device to better meet the high-power working requirements.

[0041] In practical applications, high electron mobility transistors show excellent large signal characteristics. In the 3.5GHz frequency band, the device can operate stably at a drain-source voltage of 100V, with an output power density exceeding 15W / mm, while maintaining a power added efficiency of more than 50%. This performance level far exceeds that of traditional AlGaN / GaN single-channel devices, which can usually only achieve a power density of 5-8W / mm and an efficiency of about 40% under the same conditions.

[0042] In certain embodiments, referring to Figure 1 A plurality of groups of multi-channel structures are arranged between the buffer layer 300 and the electrode layer 500, and all the multi-channel structures are stacked.

[0043] In some embodiments, all multi-channel structures include the same number of heterojunction structure layers 410 .

[0044] In some embodiments, all multi-channel structures include different numbers of heterojunction structure layers 410 .

[0045] In some embodiments, a portion of the multi-channel structures include the same number of heterojunction structure layers 410 , and another portion of the multi-channel structures include different numbers of heterojunction structure layers 410 .

[0046] In certain embodiments, referring to Figure 1, a first multi-channel structure and a second multi-channel structure are arranged between the buffer layer 300 and the electrode layer 500, the first multi-channel structure includes a first heterojunction structure layer 610, a second heterojunction structure layer 620 and a first cap layer 630, the first heterojunction structure layer 610 includes a first GaN channel layer 611 and a first AlScN barrier layer 612, and the second heterojunction structure layer 620 includes a second GaN channel layer 621 and a second AlScN barrier layer 622; The second multi-channel structure includes a third heterojunction structure layer 710, a fourth heterojunction structure layer 720, a fifth heterojunction structure layer 730 and a second cap layer 740, the third heterojunction structure layer 710 includes a third GaN channel layer 711 and a third AlScN barrier layer 712, the fourth heterojunction structure layer 720 includes a fourth GaN channel layer 721 and a fourth AlScN barrier layer 722, and the fifth heterojunction structure layer 730 includes a fifth GaN channel layer 731 and a fifth AlScN barrier layer 732; Among them, the first GaN channel layer 611 is stacked on the upper surface of the buffer layer 300, the second GaN channel layer 621 is stacked on the upper surface of the first AlScN barrier layer 612; the third GaN channel layer 711 is stacked on the upper surface of the first cap layer 630, the fourth GaN channel layer 721 is stacked on the upper surface of the third AlScN barrier layer 712, and the fifth GaN channel layer 731 is stacked on the upper surface of the fourth AlScN barrier layer 722; the electrode layer 500 is stacked on the upper surface of the second cap layer 740.

[0047] In the first specific embodiment, the thickness of the nucleation layer 200 is 1 nm, the thickness of the buffer layer 300 is 300 nm, the thickness of the first GaN channel layer 611 is 200 nm, the thickness of the first AlScN barrier layer 612 is 18 nm, the thickness of the second GaN channel layer 621 is 200 nm, the thickness of the second AlScN barrier layer 622 is 18 nm, the thickness of the first cap layer 630 is 20 nm, the thickness of the third GaN channel layer 711 is 200 nm, the thickness of the third AlScN barrier layer 712 is 18 nm, the thickness of the fourth GaN channel layer 721 is 200 nm, the thickness of the fourth AlScN barrier layer 722 is 18 nm, the thickness of the fifth GaN channel layer 731 is 200 nm, the thickness of the fifth AlScN barrier layer 732 is 20 nm, and the thickness of the second cap layer 740 is 20 nm.

[0048] In the second specific embodiment, the thickness of the first AlScN barrier layer 612 is 20 nm, the thickness of the second AlScN barrier layer 622 is 20 nm, the thickness of the third AlScN barrier layer 712 is 20 nm, the thickness of the fourth AlScN barrier layer 722 is 20 nm, and the thickness of the remaining layer structures is the same as that of the first specific embodiment.

[0049] In the third specific embodiment, the thickness of the first AlScN barrier layer 612 is 22 nm, the thickness of the second AlScN barrier layer 622 is 22 nm, the thickness of the third AlScN barrier layer 712 is 22 nm, the thickness of the fourth AlScN barrier layer 722 is 22 nm, and the thickness of the remaining layer structures is the same as that of the first specific embodiment.

[0050] In certain embodiments, referring to Figure 1 The electrode layer 500 includes a source electrode 510, a gate electrode 520 and a drain electrode 530 which are arranged at intervals. The interval between the source electrode 510 and the gate electrode 520, and the interval between the gate electrode 520 and the drain electrode 530 are both covered with a passivation layer 800, and the passivation layer 800 is stacked on the upper surface of the second cap layer 740.

[0051] In the first specific embodiment, the widths of the source electrode 510 and the drain electrode 530 are 8 μm, the width of the gate electrode 520 is 5 μm, and the distance between the gate electrode 520 and the drain electrode 530 is 8 μm; the thickness of the passivation layer 800 is 60 nm.

[0052] In the second specific embodiment, the width of the gate 520 is 3 μm, and the parameters of the source 510 , the drain 530 and the passivation layer 800 are the same as those of the first specific embodiment.

[0053] In the third specific embodiment, the width of the gate 520 is 1 μm, and the parameters of the source 510 , the drain 530 and the passivation layer 800 are the same as those of the first specific embodiment.

[0054] In some embodiments, the nucleation layer 200 is made of AlN material; the buffer layer 300 is made of GaN material; the first cap layer 630 and the second cap layer 740 are both made of BaTiO 3 material; and the passivation layer is made of Si 3 N 4 material.

[0055] In some embodiments, the source electrode 510 and the drain electrode 530 are both made of a Ti—Al—Ni—Au alloy material, and the gate electrode 520 is made of a Ni—Au alloy material.

[0056] Reference Figure 2 The present invention provides a method for preparing the high electron mobility transistor in the above embodiment, comprising the following steps: S1. Based on metal organic chemical vapor deposition, a nucleation layer and a buffer layer are sequentially formed on the upper surface of the substrate; S2. All multi-channel structures are sequentially fabricated on the upper surface of the buffer layer, and the following steps S21-S22 are performed when fabricating each multi-channel structure: S21. According to the number of heterojunction structure layers to be set, the following step S211 is executed in a loop until all heterojunction structure layers are completed and the loop is exited: S211. Based on a metal organic chemical vapor deposition method, a GaN channel layer and a new AlScN barrier layer are sequentially formed on the upper surface of the buffer layer or the upper surface of the previous AlScN barrier layer; S22. Based on the pulsed laser deposition method, a cap layer is formed on the upper surface of the uppermost heterojunction structure layer; S3. Fabricate an electrode layer on the upper surface of the uppermost multi-channel structure.

[0057] In some embodiments, the specific steps in step S3 include: S31. Photolithography is performed on the upper surface of the cap layer in the uppermost multi-channel structure to form a source and drain preparation area and serve as a first preparation area; S32. Based on the electron beam evaporation method, Ti-Al-Ni-Au alloy is evaporated in the first preparation area, and the electron beam energy is 3kv and the vacuum degree is ≤10 -3 Pa; S33. The photoresist is stripped using acetone and the device is annealed in a N2 atmosphere to obtain a source and a drain; S34. Photolithography is performed again on the upper surface of the cap layer in the uppermost multi-channel structure using a controllable CF4 etching source to form a gate preparation region and serve as a second preparation region; S35. Based on the electron beam evaporation method, Ni-Au alloy is evaporated in the second preparation area, and the electron beam energy is 3kv and the vacuum degree is ≤10 -3 Pa; S36. Use acetone to strip off the photoresist again to obtain a gate.

[0058] In some embodiments, after step S3, the preparation method further comprises the steps of: S4. Forming a passivation layer on the upper surface of the uppermost multi-channel structure.

[0059] The specific steps in step S4 include: S41. The upper surface of the cap layer in the uppermost multi-channel structure is photolithographically formed to form a preparation area for a passivation layer and serve as a third preparation area; the third preparation area covers the interval between the source and the gate, and the interval between the gate and the drain; S42. Based on the low-pressure chemical vapor deposition method, a passivation layer is deposited on the third preparation area.

[0060] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0061] Descriptions with reference to the terms "one embodiment", "certain embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" are intended to mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0062] The above description is only an embodiment of the present invention and is not intended to limit the protection scope of the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A high electron mobility transistor, comprising a substrate (100), a nucleation layer (200), a buffer layer (300) and an electrode layer (500) stacked in sequence, characterized in that: At least one group of multi-channel structures is arranged between the buffer layer (300) and the electrode layer (500), the multi-channel structure comprising a plurality of heterojunction structure layers (410) and a cap layer (420), all the heterojunction structure layers (410) are stacked, and the cap layer (420) is located on the upper surface of the uppermost heterojunction structure layer (410); The heterojunction structure layer (410) comprises a GaN channel layer (411) and an AlScN barrier layer (412) which are stacked, and the GaN channel layer (411) and the AlScN barrier layer (412) of two adjacent heterojunction structure layers (410) are alternately stacked, and the GaN channel layer (411) and the AlScN barrier layer (412) are connected to form a heterojunction and form an interface with a two-dimensional electron gas channel.

2. The high electron mobility transistor according to claim 1, characterized in that: A plurality of groups of the multi-channel structures are arranged between the buffer layer (300) and the electrode layer (500), and all the multi-channel structures are stacked.

3. The high electron mobility transistor according to claim 2, characterized in that: All the multi-channel structures comprise the same number of heterojunction structure layers (410).

4. The high electron mobility transistor according to claim 2, characterized in that: All the multi-channel structures comprise different numbers of the heterojunction structure layers (410).

5. The high electron mobility transistor according to claim 2, characterized in that: A portion of the multi-channel structures comprises the same number of heterojunction structure layers (410), and another portion of the multi-channel structures comprises a different number of heterojunction structure layers (410).

6. The high electron mobility transistor according to claim 4, characterized in that: A first multi-channel structure and a second multi-channel structure are provided between the buffer layer (300) and the electrode layer (500), the first multi-channel structure comprising a first heterojunction structure layer (610), a second heterojunction structure layer (620) and a first cap layer (630), the first heterojunction structure layer (610) comprising a first GaN channel layer (611) and a first AlScN barrier layer (612), and the second heterojunction structure layer (620) comprising a second GaN channel layer (621) and a second AlScN barrier layer (622); The second multi-channel structure comprises a third heterojunction structure layer (710), a fourth heterojunction structure layer (720), a fifth heterojunction structure layer (730) and a second cap layer (740); the third heterojunction structure layer (710) comprises a third GaN channel layer (711) and a third AlScN barrier layer (712); the fourth heterojunction structure layer (720) comprises a fourth GaN channel layer (721) and a fourth AlScN barrier layer (722); and the fifth heterojunction structure layer (730) comprises a fifth GaN channel layer (731) and a fifth AlScN barrier layer (732); The first GaN channel layer (611) is stacked on the upper surface of the buffer layer (300), and the second GaN channel layer (621) is stacked on the upper surface of the first AlScN barrier layer (612); the third GaN channel layer (711) is stacked on the upper surface of the first cap layer (630), the fourth GaN channel layer (721) is stacked on the upper surface of the third AlScN barrier layer (712), and the fifth GaN channel layer (731) is stacked on the upper surface of the fourth AlScN barrier layer (722); and the electrode layer (500) is stacked on the upper surface of the second cap layer (740).

7. The high electron mobility transistor according to claim 6, characterized in that: The electrode layer (500) comprises a source electrode (510), a gate electrode (520) and a drain electrode (530) which are arranged at intervals, the interval between the source electrode (510) and the gate electrode (520), and the interval between the gate electrode (520) and the drain electrode (530) are both covered with a passivation layer (800), and the passivation layer (800) is stacked on the upper surface of the second cap layer (740).

8. The high electron mobility transistor according to claim 7, characterized in that: The nucleation layer (200) is made of AlN material; the buffer layer (300) is made of GaN material; the first cap layer (630) and the second cap layer (740) are both made of BaTiO3 material; and the passivation layer is made of Si3N4 material.

9. The high electron mobility transistor according to claim 7, characterized in that: The source electrode (510) and the drain electrode (530) are both made of a Ti-Al-Ni-Au alloy material, and the gate electrode (520) is made of a Ni-Au alloy material.

10. A method for preparing a high electron mobility transistor as claimed in any one of claims 1 to 9, characterized in that: The following steps are involved: S1. Based on metal organic chemical vapor deposition, the nucleation layer and the buffer layer are sequentially formed on the upper surface of the substrate; S2. All the multi-channel structures are sequentially manufactured on the upper surface of the buffer layer, and the following steps S21-S22 are performed when manufacturing each multi-channel structure: S21. According to the number of heterojunction structure layers to be set, the following step S211 is executed in a loop until all the heterojunction structure layers are completed and the loop is exited: S211. Based on a metal organic chemical vapor deposition method, a GaN channel layer and a new AlScN barrier layer are sequentially formed on the upper surface of the buffer layer or the upper surface of the previous AlScN barrier layer; S22. Based on the pulsed laser deposition method, a cap layer is formed on the upper surface of the uppermost heterojunction structure layer; S3. Fabricating the electrode layer on the upper surface of the uppermost multi-channel structure.

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