Comprehensive detection system for new energy automobile chip

Abstract

The invention discloses a comprehensive detection system for a new energy automobile chip. The comprehensive detection system comprises a data acquisition module used for acquiring operation data of the new energy automobile chip; the signal processing module is used for converting the analog signal into a digital signal and processing the signal; the fault analysis module is used for analyzing the operation data through a machine learning algorithm and constructing high-sensitivity features strongly related to faults; the safety test module is used for carrying out HBM, CDM and EMC tests to evaluate the safety performance of the chip; the performance test module is used for evaluating the performance of the chip under set extreme conditions through a high temperature life test HTOL and an early life failure test ELFR; and the data storage and analysis module is used for storing test data. According to the scheme provided by the invention, the prediction accuracy, the measurement efficiency and the anomaly detection capability are improved according to the measured electrical variable and the measured magnetic variable, so that the performance, the safety and the reliability of the chip can be comprehensively evaluated.

Description

Technical Field

[0001] The present invention generally relates to the field of chip detection technology. More specifically, the present invention relates to a comprehensive detection system for new energy vehicle chips. Background Art

[0002] With the development of new energy vehicles and intelligent vehicles, the new energy vehicle industry is bursting with great vitality, and the automotive electronic chip market has broad prospects. A vehicle is equipped with multiple sensors, and the central controller can simultaneously control the data collection and processing of these sensors to achieve efficient data sharing and processing. Chips used in cars can be called on-board chips. On-board chips generally include four categories: computing control, power, sensor, and storage chips. Each type of chip is responsible for its own functions and application scenarios.

[0003] The on-board computing control chip needs to handle complex calculations and make decisions, etc. It is the core brain of smart cars and widely covers the five classic domains of smart cars: body domain, cockpit domain, chassis domain, power domain and intelligent driving domain. After automobile manufacturers purchase different models of chips produced by different manufacturers and assemble them into cars, the compatibility issues between chips affect driving safety and vehicle performance. At present, there is no platform or evaluation agency in China that can cover all levels of chip testing, and there is a lack of certification for autonomous automotive chip products. For example, on-board computing chips need to calculate a large amount of data, so they must have strong computing power (computing power), and they also need high-speed communication interfaces to interact with the outside world. The computing power requirements of the body domain computing chip are relatively low, mainly because there are more communication interfaces to interact with external data. The computing chips in the power domain and chassis domain are related to the safety of people's lives and property, and require higher stability and functional safety levels. Therefore, the detection of new energy vehicle chips is particularly important. On-board chips are related to the safety of people's lives and property, and require higher stability and functional safety levels.

[0004] In view of this, there is an urgent need to provide a comprehensive detection system for new energy vehicle chips in order to improve detection efficiency and accuracy. Summary of the invention

[0005] In order to at least solve one or more of the technical problems mentioned above, the present invention proposes a comprehensive detection system for new energy vehicle chips in multiple aspects.

[0006] In a first aspect, the present invention provides a comprehensive detection system for new energy vehicle chips, comprising: a data acquisition module: used to collect operating data of the new energy vehicle chip, wherein the operating data includes multi-dimensional key parameters; a signal processing module: used to convert analog signals into digital signals and process the signals; a fault analysis module: used to analyze the operating data through a machine learning algorithm, construct a high-sensitivity feature that is strongly correlated with the fault, and convert and combine the high-sensitivity feature through a neural network to predict and identify potential faults; a safety test module: used to perform a human body model test HBM, a charged conductor model test CDM and an electromagnetic compatibility test EMC to evaluate the safety performance of the chip, wherein the safety performance includes anti-static and anti-electromagnetic interference; a performance test module: used to evaluate the performance of the chip under set extreme conditions through a high temperature life test HTOL and an early life failure test ELFR, wherein the extreme conditions include setting a temperature and voltage higher than a threshold; a data storage and analysis module: used to store test data and perform in-depth analysis to optimize the test process.

[0007] In some embodiments, the key parameters of the new energy vehicle chip are collected, including: a voltage collection unit: configuring a specific integrated chip for voltage collection, wherein the specific integrated chip includes: integrating multiple measurement pins to be connected to the battery cell; the collection step includes: determining the sampling point and sampling harness of the new energy vehicle chip to ensure that the voltage parameters of each battery cell can be accurately collected; initializing the chip through the I2C communication protocol, and configuring the relevant chip registers; constructing a read function to read the original voltage value in the chip register, and then multiplying it by the LSB value of the chip and converting it into volts; a current collection unit: used to collect the voltage across the shunt resistor, combined with a known resistance value, to determine the size of the circuit current; a magnetic variable collection unit: configuring an intelligent sensor to record the magnetic detection data of the magnetic chip, including magnetic field strength and magnetic flux changes; a temperature collection unit: used to use a negative temperature coefficient thermistor element to convert temperature into a voltage output.

[0008] In some embodiments, the operation data is analyzed by a machine learning algorithm to construct a highly sensitive feature that is strongly related to battery failure, and the highly sensitive feature is converted and combined by a neural network to predict and identify potential faults, including: a data preprocessing unit: used to extract characteristic parameters related to fault diagnosis from the operation data to obtain highly sensitive features; the characteristic parameters include the change trend, statistical characteristics and characteristic values ​​of the battery voltage, current, temperature and magnetic variables; a feature dimension reduction unit: used to reduce the feature dimension of the highly sensitive feature using a principal component analysis algorithm; a fault diagnosis model training unit: used to train a fault diagnosis model based on a neural network algorithm using the highly sensitive feature after dimension reduction to learn the linear relationship between the highly sensitive feature and the fault; adjust the fault diagnosis model parameters by cross-validation to optimize the model performance; and increase the dimension of the highly sensitive feature by adding hidden layers and the number of neurons to the neural network to process nonlinear relationships. The highly sensitive feature is deeply converted and combined by the neural network to extract more complex feature interactions; a model application unit: used to use the trained fault diagnosis model to predict and identify faults according to the real-time operation data of the chip.

[0009] In a second aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by one or more processors, the comprehensive detection system for new energy vehicle chips as described in any one of the embodiments of the first aspect is implemented.

[0010] Through a comprehensive detection system for new energy vehicle chips as provided above, the embodiment of the present invention provides comprehensive chip operation status information by monitoring multiple key parameters such as voltage, current, temperature, and magnetic variables. Using machine learning and statistical analysis methods, the system can deeply explore patterns and anomalies in the data and improve the accuracy of fault prediction. Further, through HTOL and ELFR tests, the stability and reliability of the chip in long-term operation are evaluated. Through HBM, CDM and EMC tests, the safety performance of the chip under various environmental interferences is ensured. The machine learning algorithm is applied to analyze the operating data, and a highly sensitive feature that is strongly correlated with battery failure is constructed to improve the fault identification capability. The comprehensive detection system for new energy vehicle chips provided by the present invention integrates multiple modules and technologies, and improves the prediction accuracy, measurement efficiency and anomaly detection capability based on the measurement of electrical variables and magnetic variables, so that the performance, safety and reliability of the chip can be comprehensively evaluated. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein: Figure 1 An exemplary structural block diagram of a comprehensive detection system for new energy vehicle chips according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0013] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0014] Figure 1 An exemplary structural block diagram of a comprehensive detection system 100 for new energy vehicle chips according to an embodiment of the present invention is shown.

[0015] like Figure 1 As shown, in the integrated detection system 100, it includes: a data acquisition module 101: used to collect the operating data of the new energy vehicle chip, wherein the operating data includes multi-dimensional key parameters. For example, the voltage, current and temperature data of the chip are collected using the AFE and ADC chips.

[0016] In one embodiment, collecting the operating data of the new energy vehicle chip includes: Voltage acquisition unit: A specific integrated chip is configured for voltage acquisition, wherein the specific integrated chip includes: integrating multiple measurement pins to be connected to the battery cell. The voltage V can be obtained by measuring the potential difference between the two ends of the battery cell. The specific integrated chip can integrate multiple functions, such as power management, signal processing, implementation of specific algorithms, etc. In new energy vehicle chips, the specific integrated chip can also include functions such as battery protection and balancing control.

[0017] The specific collection steps include: determining the sampling points and sampling harnesses of the new energy vehicle chip to ensure that the voltage parameters of each battery cell can be accurately collected; initializing the chip through the I2C communication protocol and configuring the relevant chip registers; constructing a read function to read the original voltage value in the chip register, and then multiplying it by the LSB value of the chip and converting it into volts.

[0018] Current acquisition unit: used to determine the current size of the circuit by collecting the voltage across the shunt resistor and combining it with the known resistance value.

[0019] The current I can be calculated by Ohm's law I=V / R, where V is the voltage across the shunt and R is the resistance of the shunt. Use an ADC chip to convert the voltage signal across the shunt into a digital signal, and then calculate the current value using the above formula.

[0020] Magnetic variable acquisition unit: configures intelligent sensors to record magnetic detection data of magnetic chips, including magnetic field strength and magnetic flux changes. In one embodiment scenario, a magnetic variable measurement method based on intelligent sensing can be used to record the magnetic detection data of magnetic chips through sensors and compare them with standard data. The change in magnetic signals is used to determine whether the detection result is an abnormal magnetic value, thereby achieving rapid early warning.

[0021] Temperature acquisition unit: used to use negative temperature coefficient thermistor elements to convert temperature into voltage output. The specific temperature T can be obtained through the voltage-temperature relationship of the negative temperature coefficient thermistor. Calculate, where is the reference voltage, is the resistance of the negative temperature coefficient thermistor, is the resistance of the fixed resistor.

[0022] According to the characteristic curve of the negative temperature coefficient thermistor, the voltage value is converted into a temperature value. Generally, the characteristic of the resistance value of the negative temperature coefficient thermistor changing with temperature can be approximately expressed by the following formula: ,in, is the resistance at 25°C, B is the material constant, and T is the temperature in Celsius.

[0023] Before the above acquisition units work, as a basis for work, it is necessary to design a voltage acquisition circuit to ensure that the cell voltage can be accurately measured. Design a current acquisition circuit, including a shunt and a signal conditioning circuit. Design a temperature acquisition circuit, including a negative temperature coefficient thermistor and a reference resistor. Design a magnetic variable acquisition circuit, including an intelligent sensor.

[0024] In addition, during the design process, multiple factors need to be considered, including sampling accuracy, number of channels, number and type of internal ADCs, architecture, and matching with application scenarios. For example, according to national standards and OEM requirements, the accuracy requirement for single cell voltage is ±0.5%FS, and the absolute value of the maximum error should not exceed 10mV. In terms of the number of channels, select an AFE chip with a sufficient number of channels based on the number of cells in the battery pack. The AFE chip needs to have enough sampling channels to cover the voltage acquisition of all cells in the battery module. For example, if a battery module is 10 strings of cells, at least 10 sampling channels are required to monitor the voltage of each cell separately. In addition, the AFE chip should meet the requirements of functional safety, including overvoltage, undervoltage, overcurrent and other protection functions.

[0025] Furthermore, in the signal processing module 102: it is used to convert the analog signal into a digital signal and process the signal. In one embodiment, the collected analog signal can be converted into a digital signal through the ADC inside the AFE chip, and then the digital signal is filtered, amplified, etc. to improve the signal quality.

[0026] Furthermore, in the fault analysis module 103: it is used to analyze the operating data through a machine learning algorithm, construct high-sensitivity features that are strongly related to faults, and convert and combine the high-sensitivity features through a neural network to predict and identify potential faults.

[0027] In one embodiment, the operating data is analyzed by a machine learning algorithm to construct highly sensitive features that are strongly correlated with battery failures, and the highly sensitive features are converted and combined by a neural network to predict and identify potential failures, including: Data preprocessing unit: used to extract characteristic parameters related to fault diagnosis from the operating data to obtain high-sensitivity features; the characteristic parameters include the change trend, statistical characteristics and characteristic values ​​of the battery voltage, current, temperature and magnetic variables.

[0028] Feature dimension reduction unit: used to reduce the feature dimension of the high-sensitivity feature using the principal component analysis algorithm. In one embodiment, the principal component analysis algorithm is used to reduce the feature dimension of the high-sensitivity feature, including combining multiple factors for weighted analysis to reduce the feature dimension of the high-sensitivity feature. The formula may include: Construct the weighting matrix: , Where X is the data matrix, each row represents a sample, each column represents a feature, and W is the weight diagonal matrix, which is used to adjust the influence of different features in the weighted matrix. The elements on the diagonal are It represents the weight of the i-th feature, which can be set according to the importance of the feature or prior knowledge. m is the number of samples.

[0029] Fault diagnosis model training unit: used to train fault diagnosis models based on neural network algorithms using highly sensitive features after dimensionality reduction to learn the linear relationship between highly sensitive features and faults; adjust the fault diagnosis model parameters through cross-validation to optimize model performance; increase the dimensionality of highly sensitive features by adding hidden layers and neurons to the neural network to handle nonlinear relationships. Deeply transform and combine the features after dimensionality increase through neural networks to extract more complex feature interactions.

[0030] When there is a nonlinear relationship between the high-sensitivity feature and the fault, in one embodiment, the high-sensitivity feature is dimensionally increased by adding hidden layers and neurons to the neural network to handle the nonlinear relationship, including using a graph neural network to capture the complex relationship between the features. The formula includes: The number of neurons is , where c is a constant with a value between [2,10], which is used to control the number of neurons in the hidden layer; the input layer size is n, the output layer size is m, the number of samples is s, the number of hidden layers is L, and the number of neurons in each hidden layer is , is the number of hidden layers.

[0031] In order to help the technical personnel understand the solution of the present invention more clearly, the above formula is explained as an example: the number of input features n=10, such as 10 different performance parameters of new energy vehicle chips. The number of output categories m=3, such as 3 levels of chip performance. The number of samples s=1000, that is, the total number of samples in the test data set. The constant c=5 is used to adjust the number of hidden layer neurons. According to the above parameters, the number of neurons in the first hidden layer can be calculated as: .

[0032] Using graph neural networks to capture complex relationship formulas between features: , in, is the adjacency matrix, which represents the connection structure of the graph; is the original adjacency matrix A plus the identity matrix The results after Indicates that each node is connected to itself (self-connected). The purpose of this is to include the node's own information in the graph convolution.

[0033] is a diagonal matrix with elements on the diagonal Represents the degree of node i, that is, the number of edges connected to node i, which includes self-connections.

[0034] is the node feature matrix of the lth layer. It is an N×H matrix, where N is the number of nodes and H is the number of features in the hidden layer. Each row represents the feature representation of a node in layer l.

[0035] Expressed as The node feature matrix of the layer is obtained by graph convolution operation and nonlinear activation function σ from Calculated.

[0036] For the The weight matrix of the layer is an H×H matrix used to map the features of the lth layer to the (l+1)th layer.

[0037] X is the node feature matrix, which is an N×C matrix, where N is the number of nodes and C is the number of features of each node. For example, in the context of new energy vehicle chips, X can contain features such as voltage, current, and temperature.

[0038] E is the edge feature matrix, which is an E×F matrix, where E is the number of edges and F is the number of features for each edge. For example, E can contain features such as communication delay or data flow.

[0039] and is the weight matrix from node features and edge features to hidden layer features. is a C×H matrix, is a F×H matrix. They are used to map node features and edge features to the hidden layer feature space.

[0040] The following example illustrates that there is a performance test graph for a new energy vehicle chip, where nodes represent different parts of the chip (such as sensors, processors, etc.), and edges represent data flows or communications between these parts.

[0041] : Node feature matrix, where N is the number of nodes and C is the number of features per node. For example, for new energy vehicle chips, X can contain features such as voltage, current, and temperature.

[0042] : edge feature matrix, where E is the number of edges and F is the number of features per edge. For example, E can contain features such as communication delay or data flow.

[0043] and : They are the weight matrices from node features and edge features to hidden layer features.

[0044] : The weight matrix from the hidden layer to the output layer, where H is the number of features in the hidden layer and F is the number of output categories.

[0045] In one embodiment, assume that a new energy vehicle chip has 4 key parts (nodes), each part has 3 performance parameters (features), there are 2 communication links (edges), and each link has 1 communication feature. Then: N=4, C=3, E=2, F=1. X is a 4×3 matrix, and E is a 2×1 matrix.

[0046] is a 3×10 matrix, is a 1×10 matrix, is a 10×2 matrix (assuming the hidden layer has 10 features and the output layer has 2 categories).

[0047] Through the above scheme, by increasing the number of hidden layers and neurons in the neural network, the highly sensitive features are upgraded, nonlinear relationships are processed, and the expression ability of the model is enhanced. By building a multi-layer graph neural network that can process multi-factor time series data of new energy vehicle chips, the accuracy and efficiency of chip performance and anomaly detection are improved.

[0048] Model application unit: used to use the trained fault diagnosis model to predict and identify faults based on the real-time operation data of the chip. By monitoring multiple key parameters such as voltage, current, and temperature, the operation data is analyzed to build highly sensitive features that are strongly related to battery failures and improve fault identification capabilities. At the same time, abnormal conditions during the test can be fed back instantly to speed up the response to fault problems.

[0049] Furthermore, in the safety test module 104: it is used to perform a human body model test HBM, a charged conductor model test CDM and an electromagnetic compatibility test EMC to evaluate the safety performance of the chip, wherein the safety performance includes anti-static and anti-electromagnetic interference.

[0050] In one embodiment, HBM, CDM and EMC tests are performed to evaluate the safety performance of the chip, including: HBM test unit: used to simulate human body discharge, use HBM simulator to test the chip, and record the discharge times and chip response data.

[0051] CDM test unit: used to simulate the discharge of charged equipment, use the CDM simulator to test the chip, and evaluate the performance of the chip under contact discharge conditions.

[0052] Anti-electromagnetic interference test EMC test unit: Configuration includes: Radiation immunity test: In an electromagnetic compatibility test environment, use a radiation interference source to test the chip to evaluate its ability to resist radiation interference; Conducted immunity test: Evaluate the conducted immunity of the chip by injecting interference signals of specific frequency and amplitude into the power line or signal line.

[0053] Furthermore, in the performance test module 105: it is used to evaluate the performance of the chip under set extreme conditions through a high temperature life test HTOL and an early life failure test ELFR, wherein the extreme conditions include setting a temperature and a voltage higher than a threshold.

[0054] In one embodiment, the performance of a chip under set extreme conditions is evaluated through HTOL and ELFR tests, which may include: a HTOL test unit, an ELFR test unit, a performance test data collection unit, and a performance test analysis unit. Specifically: HTOL test unit: used to set up an environmental chamber to simulate operating conditions above the threshold temperature. The chip is set to operate at a voltage not less than the maximum operating voltage to evaluate the chip's stability at high temperatures.

[0055] HTOL testing is usually performed under conditions higher than the normal use temperature of the product, such as 125°C or higher. The environmental chamber needs to be able to accurately control and maintain this temperature range, and a high-temperature furnace or climate chamber is usually used to simulate this high temperature condition. During the test, the chip will be subjected to the maximum operating voltage (Vcc max) or a voltage slightly higher than this value, which can be achieved through a power supply and precision voltage regulation equipment to ensure the stability and accuracy of the voltage throughout the test process. According to the JESD22-A108B standard, the aging time is usually 1000 hours. This means that the chip will continue to work under high temperature and high voltage conditions for 1000 hours to accelerate the chip aging process and simulate its long-term stability in actual use. During the test process, functional backtesting is usually performed by automated test equipment (ATE) at 168 hours and 500 hours to automatically detect the performance changes of the chip under high temperature conditions to monitor whether the working status of the chip is normal.

[0056] ELFR test unit: used to preheat the chip to reach the preset temperature and preset voltage environment required for the test, and then run the chip for a preset time to evaluate the performance of the chip under the preset temperature and preset voltage environment.

[0057] According to the JESD22-A108 standard, the ELFR test conditions require that the junction temperature (Tj) reach at least 125°C, the voltage Vcc that the chip is subjected to during the test should be at least equal to the maximum operating voltage Vccmax, and the test time is usually 48 to 168 hours to ensure sufficient stress conditions to induce early failure.

[0058] ELFR testing is designed to quickly discover and eliminate early-stage failures and improve the overall quality and reliability of products by running chips under accelerated aging conditions.

[0059] Through the above-mentioned ELFR test unit provided by the present invention, the comprehensive detection system can effectively evaluate the performance of new energy vehicle chips under preset temperature and voltage environments, ensure the reliability and safety of the chips, and thus improve the performance and safety of the entire vehicle.

[0060] Acquisition performance test data unit: used to collect key parameters such as voltage, current, temperature, magnetic variables, etc. of the chip during the test process.

[0061] In one implementation scenario, a high-precision ADC can be used for an eight-channel, 2MSPS / channel synchronous sampling data acquisition (DAQ) system based on an 18-bit successive approximation register (SAR) architecture. The ADC supports multi-channel parallel operation, reduces test time and cost, and has high channel density and synchronous sampling capabilities, which is suitable for measuring PMU (parameter measurement unit) analog outputs. Temperature sensors (such as thermocouples, RTDs, and thermistors), pressure sensors (such as strain gauges, capacitive sensors, and piezoelectric sensors), and voltage and current sensors (such as voltage dividers, current transformers, and shunt resistors) are deployed to measure parameters such as voltage, current, temperature, and magnetic variables. The operating status of the chip is monitored in real time through the sensor, and the analog signal is transmitted to the signal conditioner for conditioning, and then converted into a digital signal through the ADC.

[0062] According to the performance test data acquisition unit provided by the technical solution of the present invention, by running multiple channels of ADC in parallel, the test time is reduced and the test efficiency is improved. Furthermore, by classifying and screening the collected data, the reliability of the data and the accuracy of the analysis are improved. Therefore, the performance and stability of the chip can be comprehensively evaluated by measuring parameters such as voltage, current, temperature and magnetic variables through this unit.

[0063] Performance test analysis unit: used to analyze test data using statistical analysis methods to evaluate the safety performance of the chip.

[0064] Based on the key parameter data collected from the performance test, including voltage, current, temperature, and magnetic variables, the chip is monitored and recorded in real time by high-precision sensors and data acquisition systems (such as ADC) during the test. Then, the collected data is analyzed using statistical analysis methods to evaluate the safety performance of the chip.

[0065] In one embodiment, the statistical analysis method includes: the mean, median and standard deviation of parameters such as voltage, current and temperature can be calculated to understand the central trend and distribution of the parameters, so as to analyze the 2 / 5 / 10 criteria of response time, that is, the experience of user response time of 2 seconds, 5 seconds and 10 seconds, and calculate the throughput, that is, the number of requests processed per unit time. The percentile of the parameter, such as the 95th percentile, can be determined to evaluate the performance of the chip under extreme conditions. It is also possible to analyze whether the parameter follows a normal distribution and identify outliers that are beyond the range of the normal distribution, which may indicate potential failures.

[0066] In one embodiment, the chip reliability assessment can use the statistical method of Inline Defective Part Average Test (I-PAT) to identify chips with a higher probability of reliability failure. I-PAT identifies abnormal parts by comparing the performance parameters of each chip with the data distribution of a large number of products.

[0067] In the test data processing, data processing technologies such as Excel, pandas in Python, numpy and other libraries are used to perform statistical analysis on performance data. For example, the mean and maximum values ​​of CPU utilization and memory usage are calculated using Python code to provide detailed support for performance analysis. Finally, a detailed performance test report is generated, including key performance indicators such as response time, request success rate, and throughput. The report can help developers quickly discover performance bottlenecks in the system and optimize server configuration.

[0068] Furthermore, in the data storage and analysis module 106: it is used to store the test data and perform in-depth analysis to optimize the test process.

[0069] In one embodiment, module 106 specifically includes: Data stream access unit: used to collect chip operation data by setting the frequency during the test and access the data stream using the message queue.

[0070] In one embodiment, the key parameters of the chip, such as voltage, current, temperature, and magnetic variables, can be collected once per second. In order to efficiently process the high-frequency collected data, message queue technology can be used to process real-time data streams with high throughput through a distributed stream processing platform.

[0071] Through the data stream access unit, the comprehensive detection system provided by the present invention can efficiently process the large amount of data generated by the new energy vehicle chip during the test process, ensure the real-time and integrity of the data, and provide a solid foundation for subsequent performance test analysis.

[0072] Storage test data unit: used for storing unstructured, semi-structured or structured data in the data stream by using a distributed and scalable big data storage system.

[0073] Test real-time analysis unit: used to perform real-time data analysis using a large data stream processing system, and to identify changes in chip indicators in a test environment through real-time processing of operating data.

[0074] In one embodiment, a big data stream processing system is used to perform real-time data analysis, including: combining the analysis method of multi-factor time series data to build a comprehensive multi-factor anomaly detection model. The abnormal data is analyzed to obtain anomaly detection results. The algorithm formula of the anomaly detection model includes: Local outlier factor algorithm: , in, is the set of points in the kth distance neighborhood of point p, and dist(p,o) is the distance between points p and o.

[0075] Factor weights: , in, Is a factor The weight of Is a factor Information entropy.

[0076] Multivariate time series analysis: , in, and They represent the values ​​of the central data X and the influencing factor Y at the i-th time, respectively. X is the performance parameter of the new energy vehicle chip, including voltage, current, and temperature; Y is the external factor affecting the chip performance, including ambient temperature and humidity; and Represent the deviations of the central data and influencing factors at the i-th time point respectively.

[0077] Anomaly Score: , Among them, α and β are adjustment factors, which are used to balance the impact of local abnormal factors and multi-factor deviations on abnormal scores. is the weight of the ith factor, is the deviation of the ith factor.

[0078] Feedback unit: used to feed back the test results and analysis data to the safety test module or the performance test module so as to adjust the test parameters and conditions and optimize the test process.

[0079] Based on the above, the present invention further discloses a computer-readable storage medium, on which a computer program is stored. When the computer-readable program is executed by one or more processors, the module functions described in the foregoing embodiments or implementation methods are implemented.

[0080] In summary, the comprehensive detection system for new energy vehicle chips provided by the present invention integrates multiple modules and technologies, and improves the prediction accuracy, measurement efficiency and abnormality detection capability based on the measurement of electrical variables and magnetic variables, thereby being able to comprehensively evaluate the performance, safety and reliability of the chip.

[0081] Although multiple embodiments of the present invention have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may conceive of many changes, modifications, and alternatives without departing from the thought and spirit of the present invention. It should be understood that in the process of practicing the present invention, various alternatives to the embodiments of the present invention described herein may be adopted. The appended claims are intended to define the scope of protection of the present invention, and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A comprehensive detection system for new energy vehicle chips, characterized in that: include: Data acquisition module: used to collect the operating data of the new energy vehicle chip, wherein the operating data includes multi-dimensional key parameters; Signal processing module: used to convert analog signals into digital signals and process the signals; Fault analysis module: used to analyze the operation data through machine learning algorithms, construct highly sensitive features that are strongly related to faults, and convert and combine the highly sensitive features through neural networks to predict and identify potential faults; Safety test module: used to perform human body model test HBM, charged conductor model test CDM and electromagnetic compatibility test EMC to evaluate the safety performance of the chip, including anti-static and anti-electromagnetic interference; Performance test module: used to evaluate the performance of the chip under set extreme conditions through high temperature life test HTOL and early life failure test ELFR. The extreme conditions include setting the temperature and voltage higher than the threshold; Data storage and analysis module: used to store test data and conduct in-depth analysis to optimize the test process.

2. The integrated detection system according to claim 1, characterized in that: The collecting of the operating data of the new energy vehicle chip includes: Voltage acquisition unit: configure a specific integrated chip for voltage acquisition, wherein the specific integrated chip includes: integrating multiple measurement pins to be connected to the battery cell; the acquisition steps include: determining the sampling point and sampling harness of the new energy vehicle chip to ensure that the voltage parameters of each battery cell can be accurately acquired; initializing the chip through the I2C communication protocol and configuring the relevant chip registers; constructing a read function to read the original voltage value in the chip register, and then multiplying it by the LSB value of the chip and converting it into volts; Current acquisition unit: used to determine the current size of the circuit by collecting the voltage across the shunt resistor and combining it with the known resistance value; Magnetic variable acquisition unit: configure intelligent sensors to record magnetic detection data of magnetic chips, including magnetic field intensity and magnetic flux changes; Temperature acquisition unit: used to convert temperature into voltage output using negative temperature coefficient thermistor elements.

3. The comprehensive detection system according to claim 1, characterized in that: The operating data is analyzed by a machine learning algorithm to construct highly sensitive features that are strongly correlated with battery failures, and the highly sensitive features are converted and combined by a neural network to predict and identify potential failures, including: Data preprocessing unit: used to extract characteristic parameters related to fault diagnosis from the operating data to obtain high-sensitivity features; the characteristic parameters include the change trend, statistical characteristics and characteristic values ​​of the battery voltage, current, temperature and magnetic variables; Feature Dimensionality Reduction Unit: used to reduce the feature dimensions of highly sensitive features using principal component analysis algorithm; Fault diagnosis model training unit: used to train the fault diagnosis model based on the neural network algorithm using the highly sensitive features after dimensionality reduction to learn the linear relationship between the highly sensitive features and the faults; adjust the fault diagnosis model parameters through cross-validation to optimize the model performance; increase the dimensionality of the highly sensitive features by adding hidden layers and the number of neurons to the neural network to handle nonlinear relationships; Through neural networks, the features after dimensionality increase are deeply transformed and combined to extract more complex feature interactions; Model application unit: used to use the trained fault diagnosis model to perform prediction and fault identification according to the real-time operation data of the chip.

4. The comprehensive detection system according to claim 3, characterized in that: The principal component analysis algorithm is used to reduce the feature dimension of the high-sensitivity feature, including combining multiple factors for weighted analysis to reduce the feature dimension of the high-sensitivity feature. The formula includes: Construct the weighting matrix: , X is the data matrix, each row represents a sample, each column represents a feature, W is the weight diagonal matrix, and m is the number of samples.

5. The comprehensive detection system according to claim 3, characterized in that: By increasing the number of hidden layers and neurons in the neural network, the highly sensitive features are dimensionally upgraded to handle nonlinear relationships, including using graph neural networks to capture complex relationships between features. The formulas include: The number of neurons is , where c is a constant with a value between [2,10], which is used to control the number of neurons in the hidden layer; the input layer size is n, the output layer size is m, the number of samples is s, and the number of neurons in each hidden layer is , is the number of hidden layers; Using graph neural networks to capture complex relationship formulas between features: ， in, is the adjacency matrix, which represents the connection structure of the graph; It is a diagonal matrix, and the elements on its diagonal represent the degree of the nodes; Expressed as The node feature matrix of the layer; For the The weight matrix of the layer; X is the node feature matrix, including voltage, current, and temperature; E is the edge feature matrix, including communication delay or data flow; and is the weight matrix from node features and edge features to hidden layer features.

6. The comprehensive detection system according to claim 1, characterized in that: The human body model test HBM, charged conductor model test CDM and electromagnetic compatibility test EMC are performed to evaluate the safety performance of the chip, including: HBM test unit: used to simulate human body discharge, use HBM simulator to test the chip, and record the discharge times and chip response data; CDM test unit: used to simulate the discharge of charged equipment, use the CDM simulator to test the chip, and evaluate the performance of the chip under contact discharge; Anti-electromagnetic interference test EMC test unit: Configuration includes: Radiation immunity test: In an electromagnetic compatibility test environment, use a radiation interference source to test the chip to evaluate its ability to resist radiation interference; Conducted immunity test: Evaluate the conducted immunity of the chip by injecting interference signals of specific frequency and amplitude into the power line or signal line.

7. The integrated detection system according to claim 1, characterized in that: The high temperature life test HTOL and early life failure test ELFR are used to evaluate the performance of the chip under set extreme conditions, including: HTOL test unit: used to set up an environmental chamber to simulate working conditions above the threshold temperature, and to evaluate the chip's stability at high temperatures by setting the chip to operate at no less than the maximum operating voltage; ELFR test unit: used to preheat the chip to reach the preset temperature and voltage environment required for the test, and then run the chip for a preset time to evaluate the performance of the chip under the preset temperature and voltage environment; Performance test data acquisition unit: used to acquire key parameters of voltage, current and temperature of the chip during the test; Performance test analysis unit: used to analyze test data using statistical analysis methods to evaluate the safety performance of the chip.

8. The comprehensive detection system according to claim 1, characterized in that: The test data is stored and analyzed in depth to optimize the test process, including: Data stream access unit: used to collect chip operation data by setting the frequency during the test and access the data stream using the message queue; A test data storage unit: used for storing unstructured, semi-structured or structured data in the data stream by using a distributed and scalable big data storage system; Test real-time analysis unit: used to perform real-time data analysis using a large data stream processing system, and to identify changes in chip indicators under a test environment by real-time processing of operating data; Feedback unit: used to feed back the test results and analysis data to the safety test module or the performance test module so as to adjust the test parameters and conditions and optimize the test process.

9. The integrated detection system according to claim 8, characterized in that: The real-time data analysis using a large data stream processing system includes: Combined with the analysis method of multi-factor time series data, a comprehensive multi-factor anomaly detection model is constructed to analyze the abnormal data to obtain anomaly detection results, wherein the algorithm formula of the anomaly detection model includes: Local outlier factor algorithm: , in, is the set of points in the kth distance neighborhood of point p, dist(p,o) is the distance between points p and o; Factor weights: , in, Yes Factor The weight of Yes Factor Information entropy of Multivariate time series analysis: , in, and They represent the values ​​of the central data X and the influencing factor Y at the i-th time, respectively. X is the performance parameter of the new energy vehicle chip, including voltage, current, and temperature; Y is the external factor affecting the chip performance, including ambient temperature and humidity; and Respectively represent the deviation of the central data and influencing factors at the i-th time point; Anomaly Score: , Among them, α and β are adjustment factors used to balance the impact of local abnormal factors and multi-factor deviations on abnormal scores. is the weight of the ith factor, is the deviation of the ith factor.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by one or more processors, the comprehensive detection system for new energy vehicle chips as described in any one of claims 1 to 9 is implemented.

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