Rapid optimization method suitable for radio frequency heterogeneous integrated microsystem interconnection structure

Abstract

The invention provides a rapid optimization method suitable for a radio frequency heterogeneous integrated microsystem interconnection structure, and the method comprises the steps: constructing an equivalent circuit model of a complex interconnection structure required by a system based on an equivalent circuit model of a basic interconnection structure unit or an equivalent circuit model library of the basic interconnection structure unit; parameter information such as the physical size of the interconnection structure is obtained by rapidly optimizing the constructed equivalent circuit model, then corresponding physical size parameters serve as initial values of the electromagnetic simulation model of the interconnection structure, and the electromagnetic simulation model of the interconnection structure is obtained by combining the trend and rule of the constructed equivalent circuit model changing along with the physical size of the interconnection structure. The optimization and design process of three-dimensional electromagnetic simulation of the interconnection structure is guided and accelerated; the design method effectively solves the problems that the efficiency is low and the resource overhead is high when a traditional three-dimensional electromagnetic simulation optimization design is adopted for the interconnection structure of the integrated microsystem, and rapid deployment of the radio frequency integrated microsystem is achieved.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency integrated microsystems, and in particular to an optimization design method for heterogeneous and heterogeneous vertical interconnection structural units, horizontal interconnection structural units, and hybrid interconnection structural units. Background Art

[0002] In the past, the device size of RF integrated circuits continued to shrink according to Moore's Law, and the circuit integration and high-frequency performance grew rapidly at the same time. However, when the size of semiconductor manufacturing processes gradually reached the physical limit, Moore's Law gradually became invalid. In order to maintain the rapid growth of integrated circuit performance, RF heterogeneous interconnect structures with high density, low loss and low thermal resistance have promoted RF integrated microsystems to achieve more complex and excellent circuit functions while reducing system manufacturing costs, reducing circuit size and improving functional reliability. RF integrated microsystems not only pursue the miniaturization of individual devices, but also use high-density three-dimensional stacking to improve system integration. The vertical interconnection between the layers of the microsystem is realized through structures such as copper pillars, microbumps, and ball grid array solder balls, and the horizontal interconnection of chips is realized through structures such as microstrip lines, coplanar waveguides, and gold wire bonding lines. But at the same time, high-density heterogeneous interconnect structures bring severe challenges to three-dimensional electromagnetic field simulation.

[0003] Heterogeneous interconnect structures are an important part of RF integrated microsystems. Accelerating the design and simulation process of interconnect structures and improving the electrical performance of interconnect structures can greatly promote the development and deployment of modern RF integrated microsystems. Traditional three-dimensional electromagnetic simulation optimization methods for interconnect structures have the problems of long time consumption, low efficiency, and high resource consumption. How to achieve performance indicators mainly depends on the design experience of RF circuit engineers. Summary of the invention

[0004] In order to overcome the deficiencies of the prior art, the present invention provides a rapid optimization method suitable for the interconnection structure of a radio frequency heterogeneous integrated microsystem.

[0005] In order to achieve the above object, the present invention provides a rapid optimization method for the interconnection structure of a radio frequency heterogeneous integrated microsystem, and the specific steps include:

[0006] Based on the designed initial RF heterogeneous interconnect structure, the initial RF heterogeneous interconnect structure is split into multiple substructures; based on the equivalent circuit model of the basic interconnect structure unit or the physical base equivalent circuit model library of the interconnect substructure, an equivalent circuit model corresponding to the substructure is obtained;

[0007] Obtaining a circuit schematic diagram of the substructure, performing EM simulation on the substructure and simulating the circuit schematic diagram, and if the circuit schematic simulation result is consistent with the EM simulation result, cascading the schematic diagram of the substructure;

[0008] Optimize the schematic diagram after cascading to obtain the corresponding physical size information of the schematic diagram of the cascaded substructure and the behavior change trend information of the interconnection structure when the corresponding physical size information is changed;

[0009] The physical dimension information is used as the initial value and input into the complete structure, and EM simulation is performed. Then, the parameters of the complete structure are adjusted to meet the design indicators according to the behavior change trend information of the interconnect structure when the corresponding physical dimension information is changed.

[0010] Preferably, when the schematic diagram of the cascaded substructure is obtained, the parasitic components generated by the high-frequency signal coupling effect after the cascade of the interconnected substructure are analyzed according to the structure of the three-dimensional model of the initial RF heterogeneous interconnected structure. After compensating for the parasitic components, the complete physical-based equivalent circuit model of the interconnected structure is established according to the topology of the physical-based equivalent circuit model of the secondary cascaded interconnected substructure. The physical-based equivalent circuit refers to an equivalent circuit that characterizes the physical working mechanism; the parasitic components include: resistance, capacitance and mutual inductance.

[0011] Preferably, when simulating a substructure, if the circuit schematic simulation result is inconsistent with the EM simulation result, the values ​​of the parasitic component parameters in the physical basis equivalent circuit model of the substructure are adjusted; for the accuracy and error of the substructure at different sizes, by changing the adjustable physical characteristic quantity in the interconnected substructure, after obtaining new EM simulation, test results or one or a combination of data, by comparing the simulation result errors of the physical basis equivalent circuit model of the substructure at other size parameters, the accuracy and error of the model at different sizes are verified.

[0012] Preferably, when simulating the substructure, if the simulation accuracy of the physical base equivalent circuit model of the substructure is high and meets the error requirements of the equivalent circuit model of the interconnection structure of the RF integrated microsystem, it indicates that the equivalent circuit model can realize the prediction of one or a combination of EM simulation and test results of the interconnected substructure with changed structural parameters, that is, the substructure equivalent circuit model is scalable, and at this time, the behavior change trend information of the interconnection structure when the model parameters are changed can be obtained; the physical model of the corresponding interconnected substructure and the physical base equivalent circuit model are loaded into the basic interconnected substructure unit principle model library to make it a scalable or reusable interconnected substructure model, which can be used for the design of other RF integrated microsystem interconnection structure models in the future, that is, the model library has self-evolution capability; if the simulation accuracy is low, the adjustable physical characteristic quantities (variable geometric structure parameters, substrate material thickness, dielectric constant, conductivity, etc.) in the equivalent circuit model are adjusted to control the EM simulation results or test results to be consistent with the simulation results of the equivalent circuit model.

[0013] Preferably, when simulating the substructure, the equivalent circuit model and the EM simulation results are verified by setting revision coefficients of the physical formulas.

[0014] Preferably, the process of optimizing the complete structure is:

[0015] Based on the equivalent model corresponding to the complete structure, according to the design indicators (design requirements of the interconnection structure of the RF integrated microsystem and the system link performance indicators, the active chips or passive devices that need to be interconnected in the RF integrated microsystem can be cascaded, etc.), the optimization target (input / output return loss, forward / reverse insertion loss / gain, etc.), optimization parameters (physical size, material physical characteristics, etc.) and parameter optimization range of the equivalent circuit model are set; the corresponding physical size parameters are used as the initial values ​​of the electromagnetic simulation model of the interconnection structure, and multiple groups of size parameter combinations near the design indicators (close to or exceeding the technical indicator requirements) are optimized as the initial values ​​of the physical size of the complete interconnection structure EM simulation or test processing;

[0016] The obtained multiple sets of dimensional parameter combinations are brought into the complete structure and subjected to 3D EM simulation. Based on the difference between the simulation results and the design goals, the design is adjusted according to the behavioral change trend information of the interconnect structure when the corresponding physical dimensional information is changed to achieve the design goals.

[0017] Preferably, when performing EM simulation on a complete structure, the specific process of adjusting the design according to the behavior change trend information of the interconnect structure when the corresponding physical size information is changed is: combining the trend information of the constructed equivalent circuit model with the change of the physical size of the interconnect structure, determining the size parameter attributes that affect the overall performance index, the change relationship between the size parameter and the simulation result, adjusting the size parameters in the equivalent circuit model of the interconnect structure, and bringing the corresponding size parameters into the EM simulation of the complete interconnect structure to guide and accelerate the optimization and design process of the three-dimensional electromagnetic simulation of the interconnect structure; after repeated iterations of the schematic diagram guiding the electromagnetic simulation optimization process, obtaining the final size parameter values ​​of the interconnect structure, and establishing an interconnect structure that meets the performance design indicators of the radio frequency integrated microsystem.

[0018] Preferably, when there is no equivalent circuit model library, a three-dimensional structural model of the RF integrated microsystem interconnection structure is established in the three-dimensional electromagnetic simulation software to facilitate subsequent EM simulation or test processing of the interconnection structure, or a three-dimensional model of the interconnection structure that meets the interconnection requirements is quickly built based on the substructure three-dimensional model in the physical base equivalent circuit model library of the established basic interconnection substructure.

[0019] Preferably, when there is no equivalent circuit model library, a physical model of the interconnected substructure is established based on electromagnetic field theory and the adjustable physical characteristics (physical dimensions, material physical characteristics, etc.) of any interconnected structure, and its high-frequency parasitic effects (parasitic self-inductance / mutual inductance / resistance of metal wires, parasitic capacitance / conductance between metal layers / dielectric layers, etc.) are analyzed, and the values ​​of the equivalent circuit lumped or distributed elements of any structure are calculated. It is required that the physical formulas used are associated with the adjustable physical characteristics of the structure (including multi-dimensional size parameters, substrate material thickness, dielectric constant, conductivity, etc.), and a physical basis equivalent circuit model of the interconnected substructure is established.

[0020] Preferably, when splitting substructures, except for the structure built based on the substructure three-dimensional model in the basic interconnect structure unit model library, the remaining structures are split into multiple secondary cascaded interconnect substructures according to the shape characteristics, functional characteristics and structural three-dimensional electromagnetic simulation / test characteristics of the interconnect structure.

[0021] Preferably, the initial RF heterogeneous interconnect structure is an interconnect structure model that meets the interconnection requirements of the RF integrated microsystem and the process manufacturing requirements based on the active chip / passive device layout requirements, the DC bias requirements of the active chip, and the RF signal transmission requirements between the active chip and the passive device in the RF integrated microsystem. The initial RF heterogeneous interconnect structure provides a structural description (orthographic projection engineering drawing), components, and local structural features / details of the RF heterogeneous integrated microsystem interconnect structure model.

[0022] The invention provides a rapid optimization method for the interconnection structure of a radio frequency heterogeneous integrated microsystem, which has the following beneficial effects:

[0023] 1. According to the interconnection requirements between RF heterogeneous integrated microsystem chips, the required vertical / horizontal / hybrid interconnection substructures can be selected from the scalable / reusable basic interconnection structure unit principle model library and cascaded into a complex interconnection structure. According to the system transmission index requirements, the corresponding physical size parameters are used as the initial values ​​of the electromagnetic simulation model of the interconnection structure, and the optimization target is set to obtain the optimized interconnection structure size information; the optimized physical size parameters are substituted into the electromagnetic simulation model to optimize the electromagnetic simulation results and accelerate the optimization design process, solving the problems of low efficiency and high resource overhead in traditional methods.

[0024] 2. Develop a scalable / reusable physically interpretable model library for vertical / horizontal / hybrid interconnect structures in RF integrated microsystems. The model formulas characterize the basic physical phenomena of the interconnect structures of RF integrated microsystems. The established equivalent circuit model has strong scalability, a wide range of dimensional parameters, high model accuracy and low computational overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A flow chart of a rapid optimization method for an interconnect structure of a radio frequency heterogeneous integrated microsystem provided by the present invention;

[0026] Figure 2 A schematic diagram of a structure 1 provided in Embodiment 1 of the present invention;

[0027] Figure 3 A schematic diagram of a structure 2 provided in Embodiment 1 of the present invention;

[0028] Figure 4 A schematic diagram of the division of a reusable substructure of a structure provided in Embodiment 1 of the present invention;

[0029] Figure 5 A schematic diagram of the division of the reusable substructures of the structure 2 provided in the first embodiment of the present invention;

[0030] Figure 6 A comparison diagram of the substrate structure and material parameter scanning results of the structure 1 provided in the first embodiment of the present invention;

[0031] Figure 7 A simulation result diagram of an equivalent circuit model after optimization of a principle model of a structure provided in Embodiment 1 of the present invention;

[0032] Figure 8 A simulation result diagram of an equivalent circuit model after optimization of the second principle model of the structure provided in the first embodiment of the present invention;

[0033] Fig. 9 Comparison of the simulation results of the structure model provided in the first embodiment of the present invention with the initial EM simulation results;

[0034] Fig.10 The simulation results of the second structure model provided in Example 1 of the present invention are compared with the initial EM simulation results.

[0035] Fig.11 A three-dimensional diagram of a vertical interconnection structure in a first example substructure equivalent model established in an equivalent model library;

[0036] Fig.12 A side view of a vertical interconnection structure in a first example substructure equivalent model established in an equivalent model library;

[0037] Fig.13 A three-dimensional diagram of a horizontal interconnection structure in a first example substructure equivalent model established in an equivalent model library;

[0038] Fig.14 A top view of a horizontal interconnection structure in a first example substructure equivalent model established in an equivalent model library;

[0039] Fig.15A top view of through holes arranged around a vertical interconnection structure in a first example substructure equivalent model established in an equivalent model library;

[0040] Fig.16 A circuit schematic diagram of a vertical interconnect structure (copper pillar) in a first example substructure equivalent model established in an equivalent model library;

[0041] Fig.17 A circuit schematic diagram of a horizontal interconnect structure (coplanar waveguide wire) in the first example substructure equivalent model established in the equivalent model library;

[0042] Fig.18 Comparison of EM simulation results (left) and error (right) between the vertical interconnect structure and the equivalent circuit schematic. DETAILED DESCRIPTION

[0043] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0044] like Figure 1 As shown, the invention proposes a design method based on a rapid optimization design method of a radio frequency integrated microsystem interconnection structure. To better explain and verify the feasibility of the method, the invention provides an embodiment, which is as follows:

[0045] Embodiment 1:

[0046] The interconnection requirements of the RF integrated microsystem and the performance index requirements of the interconnection structure transmission structure are set, requiring the realization of hybrid interconnection of MMIC (monolithic microwave circuit) chips using gallium arsenide substrates, with an operating frequency band of DC to 50GHz, and requiring the input / output return loss to be better than -20dB within the band. The design process is as follows:

[0047] Step 1: Design an interconnect structure that meets the interconnect requirements of RF integrated microsystems.

[0048] The specific three-dimensional structure diagram is as follows Figure 2 , 3As shown. Among them, structure one: the dark green block is the GaAs-based MMIC mentioned in the requirements, which is bonded to the horizontal interconnect structure (coplanar waveguide) through gold wires, and connected to the vertical interconnect structure (copper pillar) to the output port; structure two: the first GaAs-based MMIC is bonded to the horizontal interconnect structure (coplanar waveguide) through gold wires, and connected to the vertical interconnect structure (copper pillar) to the next level of horizontal interconnect structure (coplanar waveguide), and bonded to the second GaAs-based MMIC through gold wires.

[0049] Step 2: Establish an equivalent circuit model based on the model library.

[0050] After completing the three-dimensional structural design of the RF integrated microsystem interconnection structure, according to its geometric structure characteristics and simulation method requirements, the structure body 1 is divided into the following three structures: copper pillar substructure, coplanar waveguide substructure, gold wire bonding line substructure, and all substructures have multiplexing functions. Similarly, the structure body 2 is divided into the following five structures: copper pillar substructure, coplanar waveguide line 1 substructure (coplanar waveguide line located on the same layer as the gold wire bonding line 1 substructure), coplanar waveguide line 2 substructure (coplanar waveguide line located on the same layer as the gold wire bonding line 2 substructure), gold wire bonding line 1 substructure (i.e., the first GaAs-based MMIC), gold wire bonding line 2 substructure (i.e., the second GaAs-based MMIC), and all substructures have multiplexing functions.

[0051] In addition, the indicators of the interconnected structure are required to be within the DC to 50GHz frequency band, with an input return loss better than -20dB. The variable parameters of the structure include: substrate thickness, substrate dielectric constant, surface gold layer thickness, bottom gold layer thickness, surface metal bandwidth, surface line spacing, gold wire length, hole radius, hole interconnection PAD radius, hole interconnection PAD spacing, bottom PAD radius, bottom PAD spacing. After determining the substructure division of the structure, the required vertical / horizontal / hybrid interconnection substructures can be selected from the RF integrated microsystem scalable / reusable basic interconnection structure unit principle model library, and cascaded into the corresponding structure equivalent circuit. The equivalent circuit diagram of the structure after cascading is shown as follows: Figure 4 As shown, the equivalent circuit diagram of the structure after the second cascade is as follows Figure 5 shown.

[0052] The model size parameters and symbol descriptions of structures 1 and 2 are shown in Tables 1 and 2.

[0053]

[0054]

[0055] Table 1 Dimensional parameters and symbol description of structure 1

[0056]

[0057] Table 2 Dimensional parameters and symbol description of structure 2

[0058] Step 4: Correct and calibrate the equivalent circuit models of structures one and two.

[0059] The electromagnetic simulation size of the structure used for model correction and verification is set, and the circuit model accuracy of structures one and two is verified based on the parameter scanning results of substrate structure and material parameters, coplanar waveguide interconnection structure and layer hole radius.

[0060] The circuit model simulation results of the structure 1 and the electromagnetic simulation results of the coplanar waveguide interconnection structure parameter scanning (surface metal width W, surface metal spacing S, surface metal line length L) are compared, such as Figure 6 As shown. Among them, the blue is the EM simulation result, and the red is the current model simulation result of structure one. The simulation results show that the established circuit model is scalable with high accuracy for the coplanar waveguide interconnection structure parameters of structure one. Then, the circuit model of structure one and the electromagnetic simulation parameter scanning results of substrate structure and material parameters, as well as layer hole radius are compared. The results show that the established circuit model of structure one is scalable with high accuracy for the 13 physical dimensions and electrical parameters of the above three aspects. The circuit model can be used to predict and optimize the electromagnetic simulation results of structure one.

[0061] The circuit model of Structure 2 and the electromagnetic simulation parameter scanning results of three aspects, namely substrate structure and material parameters, coplanar waveguide interconnection structure and layer hole radius, are compared. The results show that the 24 physical dimensions and electrical parameters of the established circuit model of Structure 2 in the above three aspects are scalable with high accuracy. The circuit model can be used to predict and optimize the electromagnetic simulation results of Structure 2.

[0062] Step 5: Rapidly optimize the design of the structural equivalent circuit model.

[0063] Based on the equivalent circuit model of the established structure 1, the structural index requirements of the interconnection transmission unit of the three-dimensional integrated process and 13 scanning parameters are optimized and simulated; among them, the 13 scanning parameters include: substrate thickness H1, substrate dielectric constant T, surface gold layer thickness H2, bottom gold layer thickness H3, surface metal bandwidth W, surface line spacing S, 25μm gold wire length L, hole radius R1, hole interconnection PAD radius R2, hole interconnection PAD spacing R3, bottom PAD radius R4, bottom PAD spacing R5. The optimization target is input return loss |S11| and output return loss |S22|, and the optimization index is |S11| and |S22| is less than -40dB in the required frequency band (DC~50GHz). 50,000 sets of parameter combinations are obtained by optimization, and the optimization time required to achieve the index is 5 minutes. The value range of the optimized size parameters of structure 1 is shown in Table 3. In this embodiment, the optimization algorithm is preferably a random algorithm. In addition, other existing optimization methods can also be used to optimize the parameters.

[0064]

[0065] Table 3 Optimized size parameter scanning range of structure 1 (unit: μm)

[0066] Based on the established equivalent circuit model of structure 2, the structural index requirements of the interconnection transmission unit in the three-dimensional integrated process and 24 scanning parameters (L0_B metal layer thickness H0_1, L0_Via dielectric layer thickness H0_2, L0_T metal layer thickness H0_3, L1_Via DPC layer thickness H1_1, L2_B metal layer thickness H2_1, L2_Via dielectric layer thickness H2_2, L2_T metal layer thickness H2_3, L0_Via relative dielectric constant T1, L2_Via relative dielectric constant T2, 25μm gold wire length (L2_T), 25μm gold wire length (L1_T), L2_T metal layer width W2, L2_T metal layer spacing S2, L2_T metal layer length L2, L0_T metal layer width W1, L0_T metal layer spacing S1, L0_T metal layer length L1, hole radius R1, L0_T hole interconnection PAD semi-circular The optimization simulation is carried out for the input return loss |S11| and the output return loss |S22|. The optimization index is that |S11| and |S22| are less than -20dB in the required frequency band (DC to 50GHz). The optimization algorithm is a random algorithm with 100,000 parameter combinations. The optimization time required to achieve the best broadband return loss is 10 minutes. The value range of the optimized size parameters of structure 2 is shown in Table 4.

[0067]

[0068]

[0069] Table 4 Optimized size parameter scanning range of structure 2 (unit: μm)

[0070] After optimization, six sets of interconnection structure unit size parameters that meet the input return loss of better than -20dB are obtained from the principle model of structure one. The simulation results of size one are as follows: Figure 7 As shown, its in-band input / output return loss from DC to 50GHz is less than -38.07dB, meeting the specification requirements.

[0071] After optimization, six sets of interconnection structure unit size parameters that meet the input return loss of better than -20dB from DC to 40GHz were obtained from the principle model of structure 2. The simulation results of size 1 are as follows: Figure 8 As shown, its in-band input / output return loss from DC to 40GHz is less than -20.62dB, meeting the specification requirements.

[0072] Step 6: Use equivalent circuit model to guide electromagnetic simulation to quickly optimize the design.

[0073] Based on the transmission structure parameter combination (6 groups) of structure one and the transmission structure parameter combination (6 groups) of structure two, the initial values ​​of the structural parameters for electromagnetic simulation are used, and 3D EM simulation verification is performed, and the structural parameters are fine-tuned to meet the design index requirements. The structural parameters obtained by optimizing the principle model of structure one are used as the initial values ​​and brought into the electromagnetic simulation of the interconnection transmission structure. The results are as follows Fig. 9 shown.

[0074] The structural parameters obtained by optimizing the principle model of structure 2 are used as initial values ​​and brought into the electromagnetic simulation of the interconnection transmission structure. The results are as follows: Fig.10 shown.

[0075] Based on a rapid optimization method suitable for RF heterogeneous integrated microsystem interconnection structures, Structure 1 and Structure 2 are established according to system requirements. The former can achieve excellent return loss from DC to 50 GHz or even higher frequencies, and the EM simulation times of this design case is 1, and the indicators can be achieved without fine-tuning and optimization; the latter can achieve excellent return loss in an ultra-wideband from DC to 40 GHz, and the EM simulation times of this design case is 1, and the indicators can be achieved without fine-tuning and optimization.

[0076] This design case verifies the process of guiding the circuit model from the physical theoretical model and then guiding the electromagnetic simulation, forming a process of quickly iterating the device size parameters / process parameters to obtain simulation data; the circuit model in the case supports the simultaneous optimization of multiple (24 parameters for the second structure model) process parameters and electrical parameters, and then obtains the initial value that supports the electromagnetic simulation. Based on the initial value, a good target electromagnetic optimization result can be obtained with short time consumption and high accuracy. Combined with the trend and law of the constructed equivalent circuit model changing with the physical size of the interconnection structure, the traditional electromagnetic simulation optimization process is accelerated; the rapid optimization design method from physical theoretical formulas to circuit models is based on basic common electrical structures (copper pillars, microstrip lines, coplanar waveguides, microbumps, ball grid array solder balls, etc.), which can be used for the simulation design of complex structures and has strong scalability.

[0077] In the present invention, when building an equivalent circuit model library, based on electromagnetic field theory and the adjustable physical characteristics (physical dimensions, material physical characteristics, etc.) of any structure, the equivalent circuit lumped or distributed element values ​​of the structure are calculated, and the physical formula used in the calculation is associated with the adjustable physical characteristics of the structure (including parameters of four dimensions, substrate material thickness, dielectric constant, conductivity, etc.). Based on the calculated size information and material information, an equivalent circuit model of each substructure is constructed, and then the equivalent circuit model of each substructure is stored in the equivalent circuit model library.

[0078] Based on the above process, the present invention provides an example of two substructures establishing corresponding equivalent circuit processes, namely, the first example substructure: a vertical interconnection structure, and the second example substructure: a horizontal interconnection structure; for better analysis, an interconnection structure formed by combining a horizontal interconnection structure and a vertical interconnection structure is provided in this embodiment, and the specific structure of the structure is only used as an example.

[0079] Figures 11 to 14 As shown, the structure includes from top to bottom: metal layers arranged at the top and bottom, multiple ground through holes connecting the top and bottom metal layers, and ceramic dielectrics are filled between the top and bottom metal layers; at least two through holes are arranged on the top and bottom metal layers, and at least two through holes are connected on opposite sides; at least two through holes contain arc-shaped metal layers, and the opposite sides of the arc-shaped metal layers are connected by long metal layers, and the top and bottom arc-shaped metal layers are connected by copper pillars; in the vertical direction, the top and bottom metal layers, ground through holes and copper pillars form a vertical interconnection structure; in the horizontal direction, the two arc-shaped metal layers in the through holes and the long metal layers connecting the arc-shaped metal layers form a horizontal interconnection structure. Among them, as Fig.11 In the coordinate direction shown, the horizontal interconnection structure is a structure arranged along the X direction (ie, the horizontal direction), and the vertical interconnection structure is a structure arranged along the Y direction (ie, the vertical direction).

[0080] Based on the above interconnect structure, in this embodiment, for the vertical interconnect structure, the inductance and loss problems on the signal path are analyzed, and the specific analysis content includes:

[0081] S1: Calculate the loss of copper pillars and arc metal layers:

[0082] S10: The height h of the copper column is known TSV and the radius r TSV , calculate the DC loss R of the copper column dc,TSV , the formula is:

[0083]

[0084] Among them, ρ TSV is the resistivity of the copper pillar material;

[0085] S11: Calculate the skin depth δ based on the signal frequency and copper pillar material properties skin depth,TSV , the distance p between the copper pillar and the center of the through holes around it is known TSV , calculate the AC loss R of the copper column ac,TSV :

[0086]

[0087] Where f is the RF signal frequency; μ TSV is the relative magnetic permeability of the copper column material;

[0088] S12: Given the DC and AC losses of the copper column, calculate its loss R at different frequencies TSV :

[0089]

[0090] The calculation method of the arc metal layer loss is the same as that of the copper pillar loss. After completing the calculation of the ohmic loss, analyze the inductance value of the upper arc metal layer (i.e. the arc metal layer at the top) Bump and the copper pillar, that is:

[0091] S2: Calculate the inductance of the copper pillar and the upper arc-shaped metal layer. The inductance includes: self-inductance component and mutual inductance component. The specific steps include:

[0092] S20: Set the equidistant distance p around the copper column TSV Distribute multiple ground holes (take six as an example), the top view is as follows Fig.15 The calculation of the inductance value of the upper arc-shaped metal layer bump is consistent with the classic coaxial line model. hole , calculate the inductance value L of the upper arc metal layer Bump :

[0093]

[0094] Among them, h Bump is the height of the metal layer, r Bump is the radius of the arc-shaped metal layer;

[0095] S21: Calculate the self-inductance L of the copper column self and mutual inductance M(p), where the calculation of the copper column self-inductance is consistent with the parallel conductor model, and the calculation method of mutual inductance is consistent with that of self-inductance:

[0096]

[0097] Among them, h TSV is the height of the copper column, r TSV is the radius of the copper column; p is the distance between the center of the copper column and the center of the ground through hole;

[0098] The function F(x) is:

[0099]

[0100] Where μ0 is the magnetic permeability of vacuum; μ TSV is the relative magnetic permeability of the copper column material; F(x) is the relationship between the inductance of the copper column and its size characteristics.

[0101] S22: Based on the distribution of copper pillars, taking ground via No. 1 as an example, its inductance values ​​include: its distance to ground via No. 4 and No. 5 is The mutual inductance M2 of the copper pillar and the mutual inductance M3 of the ground via hole No. 6 with a distance of 2p is used to calculate the potential distribution of the copper pillar and the ground via hole. The specific formula is:

[0102]

[0103] Among them, M n The corresponding mutual inductance value between the copper pillar and the ground via n;

[0104] The current of the copper pillar is divided equally by the other ground vias, and the current direction is opposite. At this time, the inductor loop potential V Loop for:

[0105] I1=I2=I3=I4=I5=I6=I0 / 6(A);

[0106]

[0107] Among them, I n Correspondingly, the current intensity in the through hole n, I0 is the copper column current intensity, V S is the copper column potential; V G is the ground through-hole potential; L self is the self-inductance of the copper pillar; M1(p) is the mutual inductance of ground through hole No. 1; The distance between the No. 1 ground through hole and the No. 4 and No. 5 ground through holes is M3(2p) is the mutual inductance between ground via No. 1 and ground via No. 6 with a distance of 2p;

[0108] The inductance value L of the copper column is obtained from the loop potential TSV,signal for:

[0109]

[0110] Among them, R TSV is the copper pillar loss.

[0111] After completing the calculation of the inductance and loss on the signal copper pillar path, analyze the parasitic components from the copper pillar to the ground. The steps are as follows:

[0112] S3: Calculate the parasitic components from the copper column to the ground:

[0113] S30: Capacitor C with air as the medium between the arc-shaped metal layer Bump and the metal layer Bump :

[0114]

[0115] Among them, h Bump is the height of the metal layer, ε0 is the dielectric constant of vacuum, ε r,air is the dielectric constant of air, r hole is the radius of the via on the metal layer, r Bump is the radius of the curved metal layer;

[0116] S31: The copper column is surrounded by a ceramic dielectric, whose dielectric constant is greater than that of the air dielectric, resulting in a larger bypass parasitic capacitance of the copper column. At this time, the loss of the ceramic dielectric is:

[0117]

[0118] Among them, σ ceramic is the conductivity of the ceramic medium, ε r,ceramic is the relative dielectric constant of the ceramic medium, tanδ c,ceramic is the loss tangent of the ceramic medium; C sub is the parasitic capacitance of the ceramic substrate; C IMD It is the parasitic capacitance caused by the ceramic dielectric between the copper pillar and the ground via; TSV h is the distance between the center of the copper column and the center of the ground through hole; TSV is the height of the copper column, r TSV is the radius of the copper column; G Sub is the parasitic loss conductance of the ceramic substrate.

[0119] According to the calculation and analysis of the above formula, the physical equivalent circuit model of the vertical interconnect structure (copper pillar) is established. The circuit schematic diagram is as follows: Fig.16 shown.

[0120] For the horizontal interconnect structure (coplanar waveguide), it is a coplanar waveguide composed of a central conductor strip located on the plane of the dielectric substrate and a conductor plane (as ground) adjacent to the central conductor strip (that is, it is composed of a method of making a central conductor strip on one surface of the dielectric substrate and making conductor planes on both sides adjacent to the central conductor strip). Compared with conventional microstrip transmission lines, coplanar waveguides have the advantages of being easy to make, easy to realize series and parallel connection of passive and active devices in microwave circuits, and easy to increase circuit density. The coplanar waveguide modeled in this example has different shapes at both ends compared to conventional coplanar waveguides. The metal sheets at both ends are arc-shaped, similar to the through silicon via / copper pillar structure.

[0121] The modeling of the coplanar waveguide line mainly considers the influence of the arc metal layers at both ends on the electrical performance. The specific influencing factors include: the air capacitance C generated by the air medium between the signal line and the bottom line air and resistor R air ; Parasitic inductance L generated by lossy signal lines during signal transmission sig and resistor R sig ; Parasitic capacitance C formed by the medium between the signal line and the substrate su b and resistor R su b. Based on the above effects, a physical equivalent circuit model of the horizontal interconnect structure (coplanar waveguide) is established, and its circuit schematic diagram is shown in Fig.17 shown.

[0122] For the air capacitor C air The calculation of is derived from the general arc parallel plate capacitance calculation formula. The resistance R of the air medium between the signal line and the bottom line air The value itself is very large, so a sufficiently large resistor is used here for equivalent. For the parasitic inductance L generated by the lossy signal line during signal transmission sig and resistor R sig Since the structure of the arc metal layer is relatively complex, the formula is obtained by fitting the test data in this embodiment. air The calculation of can refer to the conventional arc parallel plate capacitance calculation formula, which is:

[0123]

[0124] Where C is the capacitance to be measured, ε is the dielectric constant, θ is the central angle of the arc, and R out is the radius of the outer plate, R inis the radius of the inner plate, and t is the plate height. The outer plate is the metal layer outside the arc-shaped metal layer, i.e., the ground wire, and the inner plate is the arc-shaped metal layer.

[0125] For the C generated by the air medium between the actual signal line and the bottom line air In terms of calculation, determining the center angle θ is the key to the formula calculation. Therefore, when calculating the center angle θ corresponding to the arc, the specific steps include:

[0126] Assume that θ1 and θ2 are the corresponding center angles of the inner and outer plates at both ends of the coplanar waveguide, respectively, and R1 and R2 are the corresponding inner and outer plate radii, respectively. For CPWs of different shapes, there are the following two situations: θ1>θ2—the center angle corresponding to the arc of the arc-shaped metal layer of the signal line is greater than the center angle corresponding to the arc of the outer ground line; θ1≤θ2—the center angle corresponding to the arc of the arc-shaped metal layer of the signal line is less than or equal to the center angle corresponding to the arc of the outer ground line. At this time, the calculation formulas for the center angle θ1 corresponding to the inner plates at both ends of the coplanar waveguide and the center angle θ2 corresponding to the outer plates at both ends of the coplanar waveguide are as follows:

[0127]

[0128] Among them, w RDL is the width of the coplanar waveguide signal line, S RDL is the distance between the signal line and the ground line of the coplanar waveguide. According to the geometric structure of the arc-shaped metal layer, the larger value of θ1 and θ2 is selected as the value of the central angle of the arc parallel plate capacitance calculation formula, and the air capacitance C can be obtained. air The calculation formula is:

[0129]

[0130] Where ε0 is the dielectric constant of vacuum, ε r,air is the dielectric constant of air, t RDL is the thickness of the metal layer;

[0131] The parasitic capacitance C formed by the dielectric between the signal line and the substrate sub The calculation formula is:

[0132]

[0133] Among them, ε r,ceramic is the dielectric constant of ceramics, h sub is the height of the dielectric layer.

[0134] The resistance R formed by the medium between the signal line and the substrate sub The calculation formula is:

[0135]

[0136] Among them, σ ceramic is the conductivity of the ceramic medium, ε r,ceramic is the relative dielectric constant of the ceramic medium, tanδ c,ceramic is the loss tangent of the ceramic dielectric.

[0137] Based on the established vertical interconnection equivalent model, its testability is verified, that is, the corresponding physical size parameters are used as the initial values ​​of the electromagnetic simulation model of the interconnection structure, the variable parameters in the equivalent circuit model are adjusted, the real physical characteristics of the interconnection structure are extracted, and the EM simulation is performed on the structure. The difference in the results between the circuit model and the EM simulation is compared to determine whether the equivalent circuit model can achieve the prediction of the behavior of the structure under the change of structural parameters, that is, the substructure equivalent circuit model is scalable.

[0138] The comparison and error of EM and equivalent circuit S-parameter simulation results of vertical interconnect structures of different sizes after model verification are shown, such as Fig.18 shown.

[0139] The results of model modification and verification show that the physical base model of the vertical interconnect structure (copper pillar) has a TSV The physical size scaling function has an average absolute error of less than 15% in the key working frequency band (24-28GHz), with high accuracy. A model library based on the principle of scalable or reused basic interconnection structure units can be added later.

[0140] Optimize the EM simulation results of the interconnect structure to achieve the index requirements: Based on the equivalent circuit model, the corresponding physical size parameters are used as the initial values ​​of the electromagnetic simulation model of the interconnect structure, and the optimization target and optimization parameters of the model (including parameters in four dimensions, substrate material thickness, dielectric constant, conductivity, etc.) are set to optimize the parameter combination that is close to or exceeds the technical index requirements. The optimization parameters are brought into the interconnect structure and EM simulation is performed to compare the differences between the 3D EM and equivalent circuit simulation results. If the EM simulation results are close to the technical indicators, the interconnect structure parameters can be fine-tuned, and the trend and law of the constructed equivalent circuit model changing with the physical size of the interconnect structure can be combined to guide and accelerate the optimization and design process of the three-dimensional electromagnetic simulation of the interconnect structure, so as to achieve the interconnect structure design that meets the performance technical indicators of the RF integrated microsystem.

[0141] The above description is only a specific example of the present invention and does not constitute any limitation to the present invention. Obviously, for professionals in this field, after understanding the content and principle of the present invention, it is possible to make various modifications and changes to the specific structure of the RF integrated microsystem interconnection structure without departing from the principle and structure of the present invention, but these modifications and changes based on the idea of ​​the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A rapid optimization method for interconnection structure of radio frequency heterogeneous integrated microsystem, characterized in that: The specific steps include: Based on the designed initial RF heterogeneous interconnect structure, the initial RF heterogeneous interconnect structure is split into multiple substructures; based on the equivalent circuit model of the basic interconnect structure unit or the physical base equivalent circuit model library of the interconnect substructure, an equivalent circuit model corresponding to the substructure is obtained; Obtaining a circuit schematic diagram of the substructure, performing EM simulation on the substructure and simulating the circuit schematic diagram, and if the circuit schematic diagram simulation result is consistent with the EM simulation result, cascading the schematic diagram of the substructure; Optimize the schematic diagram after cascading to obtain the corresponding physical size information of the schematic diagram of the cascaded substructure and the behavior change trend information of the interconnection structure when the corresponding physical size information is changed; The physical dimension information is used as the initial value and input into the complete structure, and EM simulation is performed. Then, the parameters of the complete structure are adjusted to meet the design indicators according to the behavior change trend information of the interconnect structure when the corresponding physical dimension information is changed.

2. The rapid optimization method for the interconnection structure of a radio frequency heterogeneous integrated microsystem according to claim 1, characterized in that: When drawing the schematic diagram of the cascaded substructure, according to the structure of the three-dimensional model of the initial RF heterogeneous interconnect structure, the parasitic components generated by the high-frequency signal coupling effect after the interconnect substructure is cascaded are analyzed. After compensating for the parasitic components, the complete physical base equivalent circuit model of the interconnect structure is established according to the topology of the physical base equivalent circuit model of the secondary cascaded interconnect substructure.

3. The rapid optimization method for the interconnection structure of a radio frequency heterogeneous integrated microsystem according to claim 2, characterized in that: When simulating a substructure, if the circuit schematic simulation result is inconsistent with the EM simulation result, the parasitic component parameter values ​​in the physical basis equivalent circuit model of the substructure are adjusted; for the accuracy and error of the substructure at different sizes, by changing the adjustable physical characteristic quantity in the interconnected substructure, after obtaining one of the new EM simulation, test results or combined data, the simulation result error of the physical basis equivalent circuit model of the substructure under other size parameters is compared.

4. The rapid optimization method for the interconnection structure of a radio frequency heterogeneous integrated microsystem according to claim 3 is characterized in that: When simulating a substructure, If the simulation accuracy of the physical-based equivalent circuit model of the substructure is high and meets the error requirements of the equivalent circuit model of the interconnection structure of the radio frequency integrated microsystem, the behavior change trend information of the interconnection structure when the model parameters are changed is obtained; the physical model of the corresponding interconnection substructure and the physical-based equivalent circuit model are loaded into the basic interconnection substructure unit principle model library; If the simulation accuracy is low, the adjustable physical characteristic quantity in the equivalent circuit model is adjusted to control the EM simulation result or the test result to be consistent with the simulation result of the equivalent circuit model.

5. The rapid optimization method for the interconnection structure of a radio frequency heterogeneous integrated microsystem according to claim 4, characterized in that: When simulating a substructure, the equivalent circuit model and EM simulation results are verified by setting revision coefficients of the physical formulas.

6. The rapid optimization method for the interconnection structure of a radio frequency heterogeneous integrated microsystem according to claim 1, characterized in that: The process of optimizing the complete structure is: Based on the equivalent model corresponding to the complete structure, the optimization target, optimization parameters and parameter optimization range of the equivalent circuit model are set according to the design index; the corresponding physical size parameters are used as the initial values ​​of the electromagnetic simulation model of the interconnection structure, and multiple groups of size parameter combinations near the design index are optimized; The obtained multiple sets of dimensional parameter combinations are brought into the complete structure and subjected to 3D EM simulation. Based on the difference between the simulation results and the design goals, the design is adjusted according to the behavioral change trend information of the interconnect structure when the corresponding physical dimensional information is changed to achieve the design goals.

7. The rapid optimization method for the interconnection structure of a radio frequency heterogeneous integrated microsystem according to claim 6, characterized in that: When performing EM simulation on a complete structure, the specific process of adjusting the design based on the behavior change trend information of the interconnect structure when the corresponding physical size information is changed is as follows: combining the trend information of the constructed equivalent circuit model with the change of the physical size of the interconnect structure, determining the size parameter attributes that affect the overall performance indicators, the change relationship between the size parameters and the simulation results, adjusting the size parameters in the equivalent circuit model of the interconnect structure, bringing the corresponding size parameters into the EM simulation of the complete interconnect structure, obtaining the final size parameter values ​​of the interconnect structure, and establishing an interconnect structure that meets the performance design indicators of the RF integrated microsystem.

8. The rapid optimization method for radio frequency heterogeneous integrated microsystem interconnection structure according to claim 1, characterized in that: When there is no equivalent circuit model library, a three-dimensional structural model of the RF integrated microsystem interconnection structure is established in the three-dimensional electromagnetic simulation software, or a three-dimensional model of the substructure in the physical base equivalent circuit model library of the established basic interconnection substructure is used to build a three-dimensional model of the interconnection structure that meets the interconnection requirements.

9. The rapid optimization method for the interconnection structure of a radio frequency heterogeneous integrated microsystem according to claim 8, characterized in that: When there is no equivalent circuit model library, a physical model of the interconnected substructure is established based on electromagnetic field theory and the adjustable physical characteristics of any interconnected structure, its high-frequency parasitic effects are analyzed, and the values ​​of the equivalent circuit lumped or distributed elements of any structure are calculated. It is required that the physical formulas used be associated with the adjustable physical characteristics of the structure to establish a physical basis equivalent circuit model of the interconnected substructure.

10. The rapid optimization method for radio frequency heterogeneous integrated microsystem interconnection structure according to claim 1, characterized in that: When splitting substructures, except for the structure built based on the substructure three-dimensional model in the basic interconnect structure unit model library, the remaining structures are split into multiple secondary cascaded interconnect substructures according to the shape characteristics, functional characteristics and structural three-dimensional electromagnetic simulation or test characteristics of the interconnect structure.

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