Decision tree algorithm-based EDA design rule inspection method and system

Abstract

The invention discloses an EDA design rule checking method and system based on a decision tree algorithm. According to the method, geometric, topological and other features in design layout are extracted, a decision tree model is trained based on the features, and rule violation terms in design are automatically identified and judged. Compared with a traditional DRC method based on a hard coding rule, automation and intellectualization of the checking process are achieved through the machine learning technology, and the method can adapt to complex rule sets and large-scale layout design. According to the method, the inspection speed is increased, meanwhile, high accuracy is kept, the requirement for manual intervention is reduced, the design period is remarkably shortened, and the method has wide industrial application value and market prospects.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design automation (EDA), and in particular to an EDA design rule checking method and system based on a decision tree algorithm in EDA. Background Art

[0002] In the field of electronic design automation (EDA), design rule checking (DRC) is an important part of integrated circuit design, which is used to ensure that the design layout meets the requirements of the manufacturing process. With the advancement of technology, the design of integrated circuits has become more and more complex, and the number of design rules has increased. This poses great challenges to traditional DRC methods.

[0003] Traditional DRC tools rely on fixed rule sets and logical operations. Although they performed well in early technology nodes, they are now unable to cope with modern complex design rules. They mainly face the following problems: Complex rules: With the advancement of technology, design rules have become more complex, covering multiple aspects such as geometric dimensions and spacing, which are difficult to be effectively handled by traditional inspection methods.

[0004] Increased design size: Integrated circuit designs are getting larger and larger, and the number of components they contain is increasing dramatically, resulting in low efficiency, long calculation time, and high resource consumption of traditional methods when checking large-scale designs.

[0005] Market demand for rapid iteration: Today, the market requires rapid product updates, and design tools must complete checks faster, but traditional tools have limited ability to improve speed.

[0006] Poor adaptability: New process nodes bring more complex rules. Traditional methods cannot flexibly respond to these changes and appear rigid and difficult to expand. Summary of the invention

[0007] In view of the deficiencies of the above-mentioned prior art, the purpose of the present invention is to provide an EDA design rule checking method and system based on a decision tree algorithm; the present invention adopts a decision tree algorithm, which can automatically process complex design rules and perform hierarchical violation detection and analysis on the layout to be tested. The system organically combines data preparation, rule extraction, global detection and local analysis through modular design to form a set of efficient, accurate and adaptable design rule checking processes. Compared with the traditional DRC method based on hard-coded rules, the present invention realizes the automation and intelligence of the inspection process through machine learning technology, and can adapt to complex rule sets and large-scale layout designs. While improving the inspection speed, the method of the present invention maintains a high accuracy, reduces the need for manual intervention, significantly shortens the design cycle, and has broad industrial application value and market prospects.

[0008] The technical solution of the present invention is specifically described as follows.

[0009] The present invention provides an EDA design rule checking method based on a decision tree algorithm, using the decision tree algorithm to check The integrated circuit layout is subjected to design rule checking; the following steps are included: S1: Data Preparation Use historical design data to mark compliant and noncompliant layouts as a training set for the decision tree model; obtain the geometric features, topological features, and process-related information of the layout to be tested; S2: Rule Extraction Decompose the design rules of the layout to be tested into multi-level geometric, topological and process features, and use these features as inputs to the decision tree model to help the decision tree model determine whether the layout meets the design rules; S3: Global Violation Detection Based on the global features outputted in step S2, a decision tree model is used to check the design rules of the layout to be tested, to determine whether there are any violations, and to preliminarily determine the categories (e.g., geometric violations, topological violations, process violations) and approximate locations of the violations; S4: Local Violation Analysis For potential violations found in the global violation detection step, the decision tree model is further used to analyze local geometric and topological features to accurately locate the location and type of violation (such as specific geometric dimension violation, specific topological structure violation).

[0010] In the present invention, in step S1, the geometric features include the coordinates, area, and side length information of each geometric unit in the layout; the topological features include the adjacent relationship, overlap, and spacing information of the geometric units in the layout; and the process-related information includes metal layer and thickness limitation information.

[0011] In the present invention, in step S2, the geometrical level features include the minimum line width and the maximum area; the topological level features include the minimum spacing and the maximum spacing; and the process level features include the metal layer thickness and the electrical isolation requirements.

[0012] In the present invention, in step S3, the training method of the decision tree model is as follows: supervised learning is performed on the annotated historical design data, and multiple classification nodes are generated for different types of design rules to distinguish between compliant and illegal layouts; the design rules include geometric rules, topological rules and process rules.

[0013] In the present invention, in step S3, the global violation detection module quickly checks the large-scale design data through a decision tree model. The root node of the decision tree is used to perform preliminary classification according to the input features (geometry, topology, process) to determine whether there are any violations, and the leaf nodes represent specific violation types (geometry violation, topology violation or process violation).

[0014] In the present invention, in step S4, the training method of the decision tree model is as follows: in order to perform supervised learning on the potential violations marked in the global violation detection step, new classification nodes are generated according to local geometric features and topological structures to accurately locate the specific location and type of the violations.

[0015] In the present invention, in step S4, the suspicious area marked in the global violation detection is analyzed, and based on the local geometric features and topological features, the location and type of the violation (specific geometric dimension violation, specific topological structure violation) are accurately identified, and detailed analysis data is provided for the designer to repair.

[0016] The present invention also provides a system for the above-mentioned EDA design rule checking method, comprising the following modules: The data preparation module uses historical design data to mark compliant and noncompliant layouts as a training set for the decision tree model; it obtains geometric features, topological features, and process-related information of the layout to be tested; The rule extraction module decomposes the design rules of the layout to be tested into multi-level geometric, topological and process features, and uses these features as input to the decision tree model to help the decision tree model determine whether the layout meets the design rules; The global violation detection module uses a decision tree model to check the design rules of the layout to be tested based on the global features output by the rule extraction module to determine whether there are any violations and preliminarily determine the category (such as geometric violation, topological violation, process violation) and approximate location of the violation; The local violation analysis module further uses the decision tree model to analyze the local geometric and topological features of potential violations found in the global violation detection step, and accurately locates the location and type of violation (such as specific geometric size violation, specific topological structure violation).

[0017] Compared with the prior art, the advantages of the present invention are: The present invention improves the speed and accuracy of design rule checking through the intelligent classification capability of the decision tree algorithm, and at the same time has strong adaptability and can be adjusted according to different design rules and process nodes. Compared with the traditional design rule checking method, the present invention provides a more intelligent and automated solution, significantly reduces the design cycle, and improves the inspection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 : The integrated circuit design rule checking flow chart based on the decision tree algorithm of the present invention. Figure 1 The overall inspection process of the present invention is demonstrated, including four main steps: data preparation, rule extraction, global violation detection and local violation analysis.

[0019] Figure 2 : Schematic diagram of the decision tree algorithm structure. Figure 2 The structure of the decision tree model is demonstrated, explaining how to make classification decisions layer by layer based on the input features, ultimately determining whether there are rule violations in the design layout, and outputting preliminary detection results of the violations.

[0020] Figure 3 : Schematic diagram of local violation analysis. Figure 3 The detailed workflow of the local violation analysis module is demonstrated, including how to perform further geometric and topological feature analysis on the violation areas marked by global detection to accurately locate the violations. DETAILED DESCRIPTION

[0021] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and examples, so as to better understand the design rule checking method and its workflow of the present invention.

[0022] Figure 1 : The integrated circuit design rule checking flow chart based on the decision tree algorithm of the present invention.

[0023] The system of the present invention realizes efficient inspection of complex rules in integrated circuit design by introducing a decision tree algorithm. The system includes a data preparation module, a rule extraction module, a global violation detection module and a local violation analysis module.

[0024] Data preparation module: The data preparation module is the basis of design rule checking. It is responsible for obtaining geometric features, topological information and process-related information from the layout to be tested, and processing them into input data acceptable to the decision tree model. Through this module, the system can generate data on compliant and illegal layouts, and convert them into vector input form suitable for the decision tree model as the basis for subsequent rule extraction and violation detection. Its specific contents include: Geometric feature extraction: Extract the size information of each geometric unit (such as area, side length, coordinates, etc.) from the layout.

[0025] Topological information extraction: collects the adjacency, overlap and spacing information of geometric units in the layout; Process-related information: Extract layout rules and constraints related to the manufacturing process (such as metal layer thickness, electrical isolation requirements, etc.); Historical data integration: Combine historical design data to mark compliant and noncompliant layouts, generate more noncompliant and compliant sample data through perturbation technology, increase the diversity and coverage of training data, and thus improve the accuracy and generalization ability of the decision tree model.

[0026] The rule extraction module is responsible for decomposing complex design rules into multi-level features to provide effective input for the decision tree model. Through the rule extraction module, complex design rules are decomposed into manageable features and converted into input vectors of the decision tree model to ensure that the model can flexibly handle the combination of different rules. Its specific contents include: Geometric rule decomposition: feature extraction of geometric constraints (such as minimum line width, maximum area, etc.); Topological rule extraction: extract topological rules such as minimum spacing and maximum spacing in the layout; Process rule extraction: Extract the requirements related to the manufacturing process as features (such as metal layer thickness, electrical isolation requirements, etc.) to ensure that the design can be manufactured correctly and meet various process constraints; Multi-level feature generation: Based on different levels of process requirements, feature vectors suitable for the decision tree model are generated, including features at the geometric, topological and process levels, to help the decision tree model more comprehensively evaluate whether the layout design meets the multi-dimensional design rule requirements.

[0027] The global violation detection module is the core of the design rule check. It is used to perform comprehensive violation detection on the layout and quickly determine whether there are any violations in the design. The global violation detection module can efficiently check the layout as a whole, ensure that potential violations are screened out in a short time, and provide a basis for subsequent local analysis. Its specific contents include: Global feature summary: Integrate the geometric features, topological features and process features of the layout to be tested output by the rule extraction module to form a global vector; Application of decision tree model: Based on the summarized global features, the pre-trained decision tree model is applied to determine whether there are any design rule violations in the entire layout; Preliminary location of violations: During the global detection process, areas where violations may exist are marked, and the category and approximate location of the violations are preliminarily identified.

[0028] The local violation analysis module is used to further analyze the potential violations found by the global detection to ensure the accuracy of the violation location. The role of the local violation analysis module is to ensure that each marked violation can be accurately identified and located, thereby providing a detailed basis for design repair. Its specific contents include: Deep analysis of local features: Detailed geometric and topological feature analysis of the areas marked in global detection; Accurate violation location: Use the decision tree model to further refine the location of the violation and determine the specific violation type; Violation Cause Analysis: Identify the specific design features that caused the violation and provide possible remediation directions.

[0029] The following are the specific implementations of each module: 1. Data Preparation Input and output of the data preparation module: The input of the data preparation module is the layout file of the integrated circuit to be tested, which contains the geometric information, topological relationship and process data of the layout. The output is a data format suitable for the input of the decision tree model, including the feature vectors of compliant and illegal layouts.

[0030] Data extraction and annotation: First, collect compliant layout samples from historical design data. Use perturbation techniques to perturb these samples to generate compliant and noncompliant layout samples (e.g. Figure 3 Perturbations involve making small adjustments to the length, spacing, and position of polygons to simulate errors that may occur in actual designs.

[0031] Feature extraction: Extract geometric features (such as area, edge length, coordinates), topological relationships (such as adjacency and spacing information), and process-related information (such as metal layer and thickness restrictions) from layout data. These features are encoded into vector form for use by the decision tree model.

[0032] 2. Rule extraction Function of the rule extraction module: The rule extraction module decomposes the design rules into multi-level features to ensure that the decision tree model can make detailed judgments on different types of violations.

[0033] Feature decomposition of geometric rules: including minimum line width, maximum area, shape restrictions, etc. For example, for metal lines in the layout, their width, length, curvature, etc. are extracted as features.

[0034] Feature extraction of topological rules: Extract the minimum spacing, maximum spacing and other constraints between different geometric objects in the layout to be tested. Spacing data is particularly important between multiple design layers and can significantly affect the performance and manufacturing yield of the circuit.

[0035] Extraction of process features: Extract process-related features from the layout to be tested, including metal layer thickness, electrical isolation requirements, etc. These features are used to ensure that the design can be accurately produced during actual manufacturing and meet process requirements. For example, the thickness of the metal layer must meet specific standards, otherwise it may affect the electrical performance of the circuit or the feasibility of the manufacturing process.

[0036] 3. Model training and global violation detection Figure 2 : Schematic diagram of the decision tree model structure of the global violation detection module.

[0037] Figure 2 The structure of the decision tree model of the global violation detection module is shown, showing how to make decisions layer by layer through different feature nodes to determine the design rule violations in the layout. The decision tree model classifies the input features layer by layer, ultimately determines whether the design is compliant or violates the rules, and outputs the preliminary judgment results.

[0038] Training process: The decision tree model is trained by using a large number of labeled compliance and violation samples. During the training process, the decision tree model will automatically generate multiple nodes based on the distribution and classification effect of the input features, and each node corresponds to a feature decision. The decision tree model uses a loss function to evaluate the performance of the model. Common loss functions for classification tasks include cross entropy loss, which adjusts the model parameters by comparing the difference between the predicted output and the true label to reduce the probability of classification errors. During the training process, the loss value gradually decreases, and the decision tree model is refined layer by layer, eventually forming a model with good classification capabilities.

[0039] Operation of the global violation detection module: When using the global violation detection module, first integrate the global feature data output by the rule extraction module to form a global feature vector of the layout to be tested. Then, the decision tree model quickly scans the entire layout, classifies and decides on each feature, and identifies potential violation areas.

[0040] Preliminary judgment: The global violation detection module outputs the mark of the suspicious area and gives a preliminary judgment of the violation category (such as geometric violation, topological violation and process violation). For example, if the spacing characteristics of a certain area do not meet the design rules, the decision tree model will mark the area as a topological violation.

[0041] 4. Local Violation Analysis Figure 3 : Schematic diagram of local violation analysis.

[0042] Figure 3 The detailed workflow of the local violation analysis module is demonstrated, including how to perform further geometric and topological feature analysis on the violation areas marked by global detection to accurately locate the violations. Specifically, the local violation analysis module will perform more refined feature extraction on the areas that may violate the rules, and conduct in-depth analysis layer by layer in the decision tree model to ensure that each marked violation can be accurately identified and located.

[0043] Local analysis input: The input of this module is the suspicious areas marked by global detection and their related feature data. The system performs a more fine-grained analysis on these marked areas.

[0044] Detailed geometry and topology analysis: During the local analysis, the decision tree model reanalyzes the detailed geometry (such as specific polygon size, boundary distance) and topology (such as connectivity, overlap) of these areas. This stage of analysis can identify subtle violation features and ensure comprehensive detection.

[0045] Precise location of violations: Through local analysis, the system can accurately determine the specific location and type of violating polygons (such as specific geometric size violations, specific topological structure violations). For example, if the geometric size of a certain area is violated, the system will specify the size of the violating polygon in that area in detail; if there is a topological structure violation, the specific topological relationship or overlap problem will be pointed out.

[0046] Violation Cause Analysis: In addition to locating the violation items, the local analysis module can also provide possible violation cause analysis and generate preliminary repair suggestions. This helps designers quickly find problems and make modifications in subsequent design optimization.

[0047] The data preparation module and rule extraction module ensure the standardization and integrity of the input data and guarantee the input quality of the decision tree model.

[0048] The global violation detection module can quickly screen out potential violation areas and provide quick feedback to designers, effectively improving inspection efficiency.

[0049] The local violation analysis module further analyzes the suspicious area and provides precise analysis of the location and type of violations, ensuring the accuracy of the detection results.

[0050] Example 1

[0051] In this embodiment, we use the characteristics of FreePDK 45nm process node and combine it with decision tree algorithm to realize efficient and accurate integrated circuit design rule checking (DRC). The implementation of this method is based on Python programming language, and uses the decision tree model in scikit-learn library, while combining data processing tools such as pandas and numpy for feature extraction and data preprocessing.

[0052] First, we collected a large amount of compliant and noncompliant 45nm design data and performed perturbation operations on the data to generate compliant and noncompliant design samples. We cleaned and organized the data using pandas, and used numpy to generate feature vectors, which included geometric features (such as area, edge length), topological information (such as neighboring relationships), and process parameters (such as minimum spacing). These data were converted into the input format of the decision tree model for subsequent model training.

[0053] We use the decision tree algorithm in scikit-learn to supervise the data and generate a decision tree model through a large number of sample training. The model generates classification nodes layer by layer according to different features, thus forming the ability to classify violations. After training, we use the model to perform global violation detection, quickly scan the feature data of the design layout, and determine whether there are any violations of design rules. This process can complete the initial screening within 1 minute and mark suspicious areas.

[0054] For suspicious areas marked in global detection, we further use the local violation analysis module for in-depth inspection. Based on the same decision tree model, local analysis recalculates the detailed geometric and topological features of these areas to accurately locate specific violations and their causes. Combined with visualization tools such as matplotlib, we provide an intuitive display of the violation location to help designers quickly understand the problem.

[0055] In this embodiment, the decision tree model has a combined accuracy of over 95% in global and local analysis. The global detection module quickly identifies potential violations, while the local analysis module provides accurate violation location and cause analysis, providing designers with a comprehensive inspection solution. Through the implementation of Python and its related libraries, we can complete multi-level inspections of large-scale designs in a short period of time, effectively balancing speed and accuracy, and providing an efficient and flexible automated solution for integrated circuit design rule checking.

Claims

1. An EDA design rule checking method based on a decision tree algorithm, characterized in that: A decision tree algorithm is used to perform design rule checking on the IC layout under test; the following steps are included: S1: Data Preparation Use historical design data to mark compliant and noncompliant layouts as a training set for the decision tree model; obtain the geometric features, topological features, and process-related information of the layout to be tested; S2: Rule Extraction Decompose the design rules of the layout to be tested into multi-level geometric, topological and process features; S3: Global Violation Detection Based on the global features outputted in step S2, a decision tree model is used to perform a design rule check on the layout to be tested, to determine whether there are any violations, and to preliminarily determine the categories and locations of the violations, where the categories of the violations are divided into geometric violations, topological violations, and process violations; S4: Local Violation Analysis For potential violations found in the global violation detection step, the decision tree model is further used to analyze local geometric and topological features to accurately locate the location and type of violation, which includes specific geometric size violations or specific topological structure violations.

2. The EDA design rule checking method according to claim 1, characterized in that: In step S1, the geometric features include the coordinates, area, and side length information of each geometric unit in the layout; Topological features include the neighboring relationship, overlap, and spacing information of geometric units in the layout; Process related information includes metal layer and thickness limit information.

3. The EDA design rule checking method according to claim 1, characterized in that: In step S2, the geometrical level features include the minimum line width and the maximum area; the topological level features include the minimum spacing and the maximum spacing; and the process level features include the metal layer thickness and the electrical isolation requirements.

4. The EDA design rule checking method according to claim 1, characterized in that: In step S3, the training method of the decision tree model is as follows: supervised learning is performed on the annotated historical design data, and multiple classification nodes are generated for different types of design rules to distinguish between compliant and illegal layouts; the design rules include geometric rules, topological rules and process rules.

5. The EDA design rule checking method according to claim 1, characterized in that: In step S3, the global violation detection module quickly checks the large-scale design data through a decision tree model. The root node of the decision tree is used to make a preliminary classification based on the input features to determine whether there are any violations, while the leaf nodes represent the specific violation types.

6. The EDA design rule checking method according to claim 1, characterized in that: In step S4, the training method of the decision tree model is as follows: in order to perform supervised learning on the potential violations marked in the global violation detection step, new classification nodes are generated based on local geometric features and topological structures to accurately locate the specific location and type of the violations.

7. The EDA design rule checking method according to claim 1, characterized in that: In step S4, the suspicious areas marked in the global violation detection are analyzed, and the locations and types of violations are accurately identified based on local geometric features and topological features, and detailed analysis data is provided for designers to repair.

8. A system for the EDA design rule checking method according to claim 1, characterized in that: Includes the following modules: The data preparation module uses historical design data to mark compliant and noncompliant layouts as a training set for the decision tree model; it obtains geometric features, topological features, and process-related information of the layout to be tested; The rule extraction module decomposes the design rules of the layout to be tested into multi-level geometric, topological and process features; The global violation detection module uses a decision tree model to check the design rules of the layout to be tested based on the global features output by the rule extraction module, to determine whether there are any violations, and to preliminarily determine the category and approximate location of the violations; The local violation analysis module further uses the decision tree model to analyze the local geometric and topological features of the potential violations found in the global violation detection step, and accurately locates the location and type of violation.

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