Reference voltage output circuit

Abstract

The invention relates to the technical field of electronics, and discloses a reference voltage output circuit which comprises a digital-to-analog converter which comprises a divider resistor string, first multiplexers and second multiplexers and is used for generating divided voltages of multiple bits and outputting the divided voltages to the first multiplexers in groups; the level conversion circuit is used for carrying out voltage boosting on the divided voltage output by the digital-to-analog converter in a low-power-consumption mode; the selection module comprises a third multiplexer and is used for receiving the boosted divided voltage output by the level conversion circuit or the divided voltage output by the digital-to-analog converter, and selecting the boosted divided voltage based on a mode selection signal; in the low-power-consumption mode, the boosted divided voltage is selected for differential output, or in the non-low-power-consumption mode, the divided voltage output by the digital-to-analog converter is selected for differential output; and the output buffer comprises a biasing circuit, an operational amplifier and an output stage circuit, the operational amplifier receives the differential voltage output by the selection module and amplifies the differential voltage, and the output stage circuit converts the amplified differential voltage into single-end voltage and outputs the single-end voltage as reference voltage. According to the invention, the reference voltage suitable for different standards at the same time can be provided.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a reference voltage output circuit. Background Art

[0002] When a device with a DRAM (Dynamic Random Access Memory) subsystem is powered on, or when a device with a NAND physical layer controller (PHY Controller) or DDR (Double Data Rate Synchronous Dynamic Random Access Memory) physical layer controller subsystem is powered on, the subsystem needs to perform a series of initialization operations before reaching an operational state. According to the state machine in the Joint Electron Device Engineering Council (JEDEC) specification, the initialization process that the subsystem goes through from power-on to an operational state can be simply classified into four different stages: 1. Power-on and initialization; 2. ZQ calibration (Zero Quiet Calibration); 3. Reference voltage (VREF DQ, or VREF for short) calibration; 4. Read and write training.

[0003] The present invention mainly relates to a VREF calibration process, which refers to the process of calibrating the reference voltage in a memory module, thereby ensuring that during data transmission, the signal level has an accurate reference voltage, optimizing the electrical characteristics of signal transmission, reducing signal noise and interference, and thus improving the accuracy and reliability of data transmission.

[0004] VREF calibration usually involves setting the voltage range and step (1LSB) size of VREF, and adjusting it as needed to ensure that the signal level is within an acceptable range. According to the specifications published by JEDEC, the present invention designs a VREF output circuit that is universally applicable to the five standards of DDR4, DDR5, LPDDR4, LPDDR5, and LPDDR4X. When the VDDQ voltage is at different voltage standards of 0.3, 0.5, 0.6, 1.1, and 1.2V, and taking into account the changes in PVT (Process, Voltage, Temperature), the design can obtain different ranges of variation of VREF reference voltages corresponding to different protocols, different step sizes, etc. as specified in the JEDEC specifications.

[0005] This section is intended to provide a background or context for understanding the embodiments of the present application and is for reference only. The applicant should not be considered to admit that this section belongs to the prior art that has been disclosed before the filing date of the present application. Summary of the invention

[0006] The purpose of the present application is to provide a reference voltage output circuit and to design a VREF output circuit that is universally applicable to different standards.

[0007] The present application discloses a reference voltage output circuit, comprising:

[0008] A digital-to-analog converter, the digital-to-analog converter comprising a voltage-dividing resistor string, a plurality of first multiplexers and a second multiplexer, wherein a first power supply terminal supplies power to the voltage-dividing resistor string, the voltage-dividing resistor string generates a plurality of bits of divided voltage according to a mode selection signal and a reference voltage control signal, the plurality of bits of divided voltage are grouped and output to each of the first multiplexers, the outputs of the plurality of first multiplexers are coupled to the second multiplexer, and the plurality of first multiplexers and the second multiplexer each selectively output the divided voltage according to the mode selection signal and the reference voltage output selection signal;

[0009] A level conversion circuit, the level conversion circuit is coupled to the digital-to-analog converter and raises the voltage of the divided voltage output by the digital-to-analog converter in a low power consumption mode;

[0010] a selection module, the selection module comprising a third multiplexer, the third multiplexer receiving the boosted divided voltage output by the level conversion circuit or the divided voltage output by the digital-to-analog converter, and selecting the boosted divided voltage for differential output in a low power mode or selecting the divided voltage output by the digital-to-analog converter for differential output in a non-low power mode based on the mode selection signal; and

[0011] An output buffer, wherein the output buffer comprises a bias circuit, an operational amplifier and an output stage circuit, wherein the bias circuit provides a bias voltage for the operational amplifier, the operational amplifier receives the differential voltage output by the selection module and performs operational amplification on the differential voltage, the output stage circuit converts the amplified differential voltage into a single-ended voltage and outputs it as a reference voltage, and the reference voltage is output to the level conversion circuit and the selection module.

[0012] In a preferred example, the output stage circuit includes a Class AB amplifier, which includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, the gates of the first NMOS transistor and the second NMOS transistor are respectively coupled to a pair of differential amplified divided voltages output by the operational amplifier, the sources of the first PMOS transistor and the second PMOS transistor are both coupled to a second power supply terminal, the gate and drain of the first PMOS transistor, the gate of the second PMOS transistor and the drain of the first NMOS transistor are connected, the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected and output the reference voltage, and the drains of the first NMOS transistor and the second NMOS transistor are both coupled to the ground terminal.

[0013] In a preferred example, the voltage-dividing resistor string includes first to seventh fixed resistors, an adjustable resistor and ninth to seventeenth fixed resistors sequentially connected between the first power supply terminal and the ground terminal, both ends of the first to seventh fixed resistors are sequentially coupled to the first power supply terminal through first to eighth switches, and both ends of the ninth to sixteenth fixed resistors are sequentially coupled to the ground terminal through first to eighth switches, and the voltage-dividing resistor string generates a 7-bit divided voltage according to a mode selection signal and a reference voltage control signal.

[0014] In a preferred example, the digital-to-analog converter includes eight first multiplexers, each of which receives a 4-bit divided voltage in sequence, and the first multiplexer is a 16-to-1 selector.

[0015] In a preferred example, the second multiplexer receives eight divided voltages formed by outputs of the eight first multiplexers, and the second multiplexer is an 8-to-1 selector.

[0016] In a preferred example, the mode selection signal is a 3-bit digital signal, and the reference voltage control signal is a 1-bit digital signal.

[0017] When the mode selection signal is 000, the working mode of the reference voltage output circuit is DDR4, the first switch is turned on when the reference voltage control signal is 0, and the second switch is turned on when the reference voltage control signal is 1;

[0018] When the mode selection signal is 001, the working mode of the reference voltage output circuit is LPDDR4, the third switch is turned on when the reference voltage control signal is 0, and the fourth switch is turned on when the reference voltage control signal is 1;

[0019] When the mode selection signal is 010, the working mode of the reference voltage output circuit is DDR5, and the fifth switch is turned on;

[0020] When the mode selection signal is 011, the working mode of the reference voltage output circuit is LPDDR5, and the sixth switch is turned on;

[0021] When the mode selection signal is 100, the working mode of the reference voltage output circuit is LPDDR4X, the seventh switch is turned on when the reference voltage control signal is 0, and the eighth switch is turned on when the reference voltage control signal is 1.

[0022] In a preferred example, the output voltage selection signal is a 7-bit digital signal VSEL<6:0>, and a control codeword OP<6:0> is generated according to the mode selection signal and the reference voltage output selection signal, wherein OP<3:0> controls the plurality of first multiplexers, and OP<6:4> controls the second multiplexer;

[0023] When the mode selection signal is 000, 001, 011 or 100, OP<5:0> is VSEL<5:0>, OP<5:0> is <6> is 0;

[0024] When the mode selection signal is 010, OP<5:0> is VSELB<5:0>, OP <6> For VSELB <6> , where VSELB<6:0> is the inverted result of VSEL<6:0>.

[0025] In a preferred example, the level conversion circuit includes a third PMOS transistor, a fourth PMOS transistor, a first resistor and a second resistor, wherein the sources of the third PMOS transistor and the fourth PMOS transistor are coupled to a second power supply terminal, the gate of the third PMOS transistor receives the divided voltage output by the digital-to-analog converter, the drain of the third PMOS transistor is coupled to one end of the first resistor, the gate of the fourth PMOS transistor receives the reference voltage, the drain of the fourth PMOS transistor is coupled to one end of the second resistor, and the other ends of the first resistor and the second resistor are both coupled to the ground terminal, wherein the sources of the third PMOS transistor and the fourth PMOS transistor respectively output a pair of differential raised divided voltages.

[0026] In a preferred example, the selection module includes two third multiplexers, which are 2-to-1 selectors; one input end of one of the third multiplexers receives one of a pair of differential boosted divided voltages, and the other input end receives the reference voltage; one input end of the other third multiplexer receives the other of the pair of differential boosted divided voltages, and the other input end receives the divided voltage output by the digital-to-analog converter.

[0027] In a preferred example, the two third multiplexers output according to the mode selection signal, and the mode selection signal is a 3-bit digital signal.

[0028] When the mode selection signal is 000, the control signals of the two third multiplexers are 1;

[0029] When the mode selection signal is 001, the control signals of the two third multiplexers are 0;

[0030] When the mode selection signal is 010, the control signals of the two third multiplexers are 1;

[0031] When the mode selection signal is 011, the control signals of the two third multiplexers are 0;

[0032] When the mode selection signal is 100, the control signals of the two third multiplexers are 0.

[0033] Compared with the existing design scheme, the present invention is more universal and more flexible in applicable specifications. It can support five standards, namely DDR4, DDR5, LPDDR4, LPDDR5, and LPDDR4X, and support a wider range of power supply VDDQ changes. After the user sets the control code corresponding to the current device operating mode, the corresponding voltage range and step under the corresponding operating mode can be obtained. Furthermore, the present invention maximizes the reduction of area cost and improves the portability and reuse rate of the circuit by reusing the resistor string and the output buffer.

[0034] In addition, the present invention can have a variety of usage scenarios, such as a VREF reference voltage output circuit that only supports a single standard, or a VREF reference voltage output circuit that supports 2-4 standards (arbitrarily select a single or a combination of multiple), or a VREF reference voltage output circuit that supports five standards. Under the premise of not consuming the same proportion of circuit resources, the present invention can support circuit usage scenarios with strong flexibility and adaptability, and achieve accurate output of reference levels.

[0035] Each technical feature disclosed in the above invention content, each technical feature disclosed in each implementation mode and example below, and each technical feature disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should be deemed to have been recorded in this specification), unless such combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, while the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a block diagram of a reference voltage output circuit according to an embodiment of the present application.

[0037] Figure 2 It is a structural schematic diagram of a digital-to-analog converter according to one embodiment of the present application.

[0038] Figure 3 It is a schematic diagram of the structure of a level conversion circuit, a selection circuit and an output buffer according to an embodiment of the present application.

[0039] Figure 4 It is a simplified equivalent circuit diagram in low power consumption mode according to one embodiment of the present application.

[0040] Figure 5 It is a simplified equivalent circuit diagram in a normal power consumption mode according to an embodiment of the present application.

[0041] Figure 6 This is an equivalent circuit diagram of a DAC when the working mode is DDR4 and the range is selected as range1 in an embodiment of the present application.

[0042] Figure 7 It is an equivalent circuit diagram of a DAC when the working mode is DDR5 according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0044] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0045] The embodiment of the present application relates to a reference voltage output circuit, the block diagram of which is shown in FIG. Figure 1 As shown, the reference voltage output circuit includes a digital-to-analog converter (DAC) 101, a level shift circuit (Level shift) 102, a selection module 103, and an output buffer (Buf) 104. DAC 101 is used to generate a divided voltage VDAC according to the setting, and output the divided voltage VDAC to the level shift circuit 102. The level shift circuit 102 determines whether to raise the divided voltage VDAC according to the selected mode, and outputs a pair of differential divided voltages VOUTA and VOUTB to the selection module 103. It should be noted that the level shift circuit 102 is only used in low power mode. The selection module 103 receives the differential voltages VOUTA and VOUTB and outputs the voltages INN and INP to the output buffer 104. The output buffer 104 performs output stage amplification on the voltages INN and INP, converts the differential voltage into a single-ended voltage, and outputs the required reference voltage VREF.

[0046] DAC 101 includes a voltage-dividing resistor string 105, a plurality of first multiplexers MUX1, and a second multiplexer MUX2. The voltage-dividing resistor string 105 is connected between a first power supply terminal VDDQ and a ground terminal GND, and the first power supply terminal VDDQ supplies power to the voltage-dividing resistor string. The voltage-dividing resistor string 105 generates a plurality of bits of voltage-dividing voltage VR according to a mode selection signal MODE_SEL and a reference voltage control signal, wherein a switch control signal can be obtained by performing a logical operation on the mode selection signal MODE_SEL and the reference voltage control signal, and the switch control signal can be used to control the connection relationship of the voltage-dividing resistors in the voltage-dividing resistor string 105, thereby generating a corresponding voltage-dividing voltage VR. The plurality of bits of voltage-dividing voltage VR are grouped and output to the corresponding first multiplexer MUX1, and the outputs of the plurality of first multiplexers MUX1 are coupled to the second multiplexer MUX2, and the plurality of first multiplexers MUX1 and the second multiplexer MUX2 selectively output the voltage-dividing voltage VDAC according to the mode selection signal MODE_SEL and the reference voltage output selection signal.

[0047] The level conversion circuit 102 is coupled to the DAC 101, and raises the voltage of the divided voltage VDAC output by the DAC 101 in the low power mode. The selection module 103 includes a third multiplexer (not shown in the figure), which receives the raised divided voltage output by the level conversion circuit 102 or the divided voltage VDAC output by the DAC 101, and selects the raised divided voltage output in the low power mode or the divided voltage VDAC output by the DAC 101 in the non-low power mode based on the mode selection signal MODE_SEL. The output buffer 104 includes a bias circuit, an operational amplifier and an output stage circuit, the bias circuit provides a bias voltage for the operational amplifier, the operational amplifier receives the divided voltage output by the selection module 103 and amplifies the divided voltage, the output stage circuit outputs the amplified divided voltage as a reference voltage VREF, and outputs the reference voltage VREF to the level conversion circuit 102 and the selection module 103. The output end of the output stage circuit is coupled with a voltage stabilizing capacitor Cs for stabilizing the VREF voltage. . The output buffer 104 will be described in detail below.

[0048] Figure 2 1 is a schematic diagram of the structure of a digital-to-analog converter 200 according to an embodiment of the present application. The digital-to-analog converter (DAC) 200 includes a voltage-dividing resistor string 201, a plurality of first multiplexers 202.1 to 202.N, and a second multiplexer 203. In this embodiment, the DAC 200 may include eight first multiplexers 202, that is, N is equal to 8.

[0049] The voltage-dividing resistor string 202 includes the first to seventh fixed resistors R11 to R17, an adjustable resistor Rq, and the ninth to seventeenth fixed resistors R21 to R28, which are sequentially connected between the first power supply terminal VDDQ and the ground terminal. The resistance values ​​of the first to seventh fixed resistors R11 to R17 are different or the same. The resistance values ​​of the ninth to seventeenth fixed resistors R21 to R28 are different or the same. Both ends of the first to seventh fixed resistors R11 to R17 are sequentially coupled to the first power supply terminal VDDQ through the first switch G0 to the eighth switch G7, that is, the first switch G0 to the eighth switch G7 respectively control whether the first to seventh fixed resistors R11 to R17 are connected to the first power supply terminal VDDQ. Both ends of the ninth to sixteenth fixed resistors R21 to R27 are sequentially coupled to the ground terminal through the first switch G0 to the eighth switch G7, that is, the first switch G0 to the eighth switch G7 each control whether the ninth to sixteenth fixed resistors R11 to R17 are connected to the ground terminal. The voltage-dividing resistor string 201 generates a 7-bit divided voltage VR<127:0>, that is, 128 divided voltages, according to the mode selection signal MODE_SEL and the reference voltage control signal RANGE. It should be noted that the first switch G0 to the eighth switch G7 in this embodiment refer to switches that are closed or opened by the first switch control signal G0 to the eighth switch control signal G7, that is, the first switch G0 is closed or opened by the first switch control signal G0, the second switch G1 is closed or opened by the second switch control signal G1, and so on. Therefore, the first fixed resistor R11 and the ninth fixed resistor R21 are controlled by the same logic, and the second fixed resistor R12 and the tenth fixed resistor R22 are controlled by the same logic, and so on.

[0050] Continue to refer Figure 2 As shown, DAC 200 includes eight first multiplexers 202.1 to 202.8, and the 7-bit divided voltage VR<127:0> is grouped and output to the corresponding first multiplexers. Each first multiplexer receives 4-bit divided voltages (i.e., 16) in sequence. For example, the 4-bit divided voltages are output to the corresponding first multiplexers 202.1 to 202.8 in order from low to high. Specifically, the first multiplexer 202.1 receives the divided voltage VR<15:0>, the first multiplexer 202.2 receives the divided voltage VR<31:16>, and so on. In one embodiment, the first multiplexers 202.1 to 202.8 are all 16-to-1 selectors (MUX16TO1). Each of the first multiplexers 202.1 to 202.8 outputs a divided voltage according to the selection signal OP<1:3>. For example, output MUX from low to high <7> To MUX <0> , forming a 3-bit divided voltage MUX<7:0>.

[0051] In one embodiment, the second multiplexer 203 receives a 3-bit divided voltage MUX<7:0> composed of the outputs of the eight first multiplexers 202.1 to 202.8, and outputs a divided voltage according to the selection signal OP<4:6>, that is, the final divided voltage VDAC. In one embodiment, the second multiplexer 203 is an 8-to-1 selector (MUX8TO1).

[0052] In one embodiment, the mode selection signal MODE_SEL<2:0> is a 3-bit digital signal, and the reference voltage control signal RANGE is a 1-bit digital signal.

[0053] When the mode selection signal MODE_SEL<2:0> is 000, the working mode of the reference voltage output circuit is DDR4, the first switch G0 is turned on when the reference voltage control signal RANGE is 0, and the second switch G2 is turned on when the reference voltage control signal RANGE is 1. When the mode selection signal MODE_SEL<2:0> is 001, the working mode of the reference voltage output circuit is LPDDR4, the third switch G3 is turned on when the reference voltage control signal RANGE is 0, and the fourth switch G4 is turned on when the reference voltage control signal RANGE is 1. When the mode selection signal MODE_SEL<2:0> is 010, the working mode of the reference voltage output circuit is DDR5, and the fifth switch G5 is turned on. When the mode selection signal MODE_SEL<2:0> is 011, the working mode of the reference voltage output circuit is LPDDR5, and the sixth switch G6 is turned on. When the mode selection signal MODE_SEL<2:0> is 100, the working mode of the reference voltage output circuit is LPDDR4X, the seventh switch G6 is turned on when the reference voltage control signal RANGE is 0, and the eighth switch G7 is turned on when the reference voltage control signal RANGE is 1.

[0054] In one embodiment, the output voltage selection signal is a 7-bit digital signal VSEL<6:0>, and the OP<6:0> control codeword is generated according to the mode selection signal MODE_SEL<2:0> and the reference voltage output selection signal VSEL<6:0>, wherein OP<3:0> controls the plurality of first multiplexers 202.1 to 202.8, and OP<6:4> controls the second multiplexer 203. When the mode selection signal MODE_SEL<2:0> is 000, 001, 011, 100, OP<5:0> is VSEL<5:0>, OP<6:4> controls the second multiplexer 203. <6> When the mode selection signal MODE_SEL<2:0> is 010, OP<5:0> is VSELB<5:0>, OP <6> For VSELB <6> , where VSELB<6:0> is the inverted result of VSEL<6:0>.

[0055] Figure 3 The structure diagram of the output buffer is shown. The output buffer 303 includes a bias circuit (CONSTANTGM) 304, an operational amplifier (AMPLIFIER) 305 and an output stage circuit 306. The output stage circuit 306 includes a Class AB amplifier, and the Class AB amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1 and a second NMOS transistor MN2. The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are respectively coupled to a pair of differential amplified divided voltages OUTP and OUTN output by the operational amplifier 305, the sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both coupled to the second power supply terminal VDDH, the gate and drain of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2 and the drain of the first NMOS transistor MN1 are connected, the drain of the second PMOS transistor MP2 and the drain of the second NMOS transistor MN2 are connected and output the reference voltage VREF, and the drains of the first NMOS transistor MN1 and the second NMOS transistor MN2 are both coupled to the ground terminal.

[0056] Continue to refer Figure 3 As shown, the level conversion circuit 301 includes a third PMOS transistor MPA, a fourth PMOS transistor MPB, a first resistor R1 and a second resistor R2. The sources of the third PMOS transistor MPA and the fourth PMOS transistor MPB are coupled to the second power supply terminal VDDH, the gate of the third PMOS transistor MPA receives the divided voltage VDAC output by the digital-to-analog converter, the drain of the third PMOS transistor MPA is coupled to one end of the first resistor R1, the gate of the fourth PMOS transistor MPB receives the reference voltage VREF, the drain of the fourth PMOS transistor MPB is coupled to one end of the second resistor R2, the other ends of the first resistor R1 and the second resistor R2 are both coupled to the ground, and the sources of the third PMOS transistor MPA and the fourth PMOS transistor MPB respectively output a pair of differential raised divided voltages VOUTA and VOUTB.

[0057] Furthermore, the selection module 302 includes two third multiplexers 307.1 and 307.2, and the third multiplexers 307.1 and 307.2 are both 2-to-1 selectors (MUX2TO1). One input end of one of the third multiplexers 307.1 receives one divided voltage VOUTB in a pair of differential boosted divided voltages, and the other input end receives the reference voltage VREF. One input end of the other third multiplexer 307.2 receives the other divided voltage VOUTA in the pair of differential boosted divided voltages, and the other input end receives the divided voltage VDAC output by the digital-to-analog converter.

[0058] In one embodiment, the two third multiplexers 307.1 and 307.2 output according to the mode selection signal, which is a 3-bit digital signal MODE_SEL<2:0>. When the mode selection signal MODE_SEL<2:0> is 000, the control signals of the two third multiplexers 307.1 and 307.2 are 1; when the mode selection signal MODE_SEL<2:0> is 001, the control signals of the two third multiplexers 307.1 and 307.2 are 0; when the mode selection signal MODE_SEL<2:0> is 010, the control signals of the two third multiplexers 307.1 and 307.2 are 1; when the mode selection signal MODE_SEL<2:0> is 011, the control signals of the two third multiplexers 307.1 and 307.2 are 0; when the mode selection signal MODE_SEL<2:0> is 100, the control signals of the two third multiplexers 307.1 and 307.2 are 0.

[0059] The present invention proposes a VREF output circuit that supports five standards, namely DDR4, DDR5, LPDDR4, LPDDR5, and LPDDR4X. It has stronger universality, more flexible applicable specifications, and supports a wider range of power supply VDDQ changes. After the user sets the control codeword corresponding to the current device operating mode (for example, mode selection signal MODE_SEL<2:0>, reference voltage control signal RANGE, output voltage selection signal VSEL<6:0>), the corresponding operating mode, corresponding voltage range and step can be obtained. In addition, the present invention maximizes the reduction of area cost and improves the portability and reuse rate of the circuit by reusing the resistor string and the output buffer.

[0060] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0061] Combination Figures 1 to 3, the top-level structure of the VREF output circuit is mainly composed of four sub-modules, namely DAC, level conversion circuit, selection module and output buffer. In the top-level overall circuit, only the power supply of the voltage divider resistor string in the DAC is VDDQ, while the power supply of all other modules, including MUX16TO1, MUX8TO1, level conversion circuit, selection module and output buffer, is VDDH. Doing so can not only achieve VREF reference voltage output that supports a wide range of VDDQ power supplies (0.3, 0.5, 0.6, 1.1, 1.2V) under different standards, but also reduce the design difficulty of other module circuits, because VDDH is a fixed power supply that only varies within a range of ±10% under PVT.

[0062] The DAC submodule outputs different VDAC voltages by logically controlling the voltage divider ratio of the resistor string. Different control code words can selectively select the switches of G0-G7. The resistor strings R11-R17 and R21-R28 are fixed resistors, and Rq is a programmable resistor. The on / off signals of G0-G7 are controlled by the mode selection signal (MODE_SEL) and the VREF reference voltage control signal (RANGE). The truth table is shown in Table 1 below:

[0063]

[0064] Table 1 Truth table of switch control signal Switch_Gate_Open

[0065] It should be noted that in the definition of DDR5 JESD79-5 and LPDDR5 JESD209-5B standard specifications, the VREF reference voltage output is a continuous full range, so under these two standard protocols, the output range of the VREF reference voltage has nothing to do with the control word VREF Range. Among them, when the control code word RANGE is 0, range1 is selected, and when the control code word RANGE is 1, range2 is selected.

[0066] OP<3:0> is the strobe control signal of MUX16TO1, and OP<6:4> is the strobe control signal of MUX8TO1. The 7-bit control code word OP<6:0> is obtained by logical operation of the Vref output voltage selection signal VSEL<6:0> and the working mode selection signal MODE_SEL<2:0>. The truth table is shown in Table 2 below:

[0067]

[0068] Table 2 Truth table of multiplexer control signal OP<6:0>

[0069] Among them, RE_EN is an intermediate signal used to mark whether the VREF reference voltage output range should be reversed. This is because the present invention takes into account that in the definition of the DDR5 JESD79-5 standard specification, the VREF reference voltage output range is from 97.5% to 35% (decreasing), while the VREF reference voltage output range of other modes (for example, DDR4, LPDDR4, LPDDR5, LPDDR4X) is increasing. Therefore, only when the working mode is selected as DDR5, the RE_EN flag is high, and the output range can smoothly achieve reverse / decreasing output.

[0070] Under different standards, the VDDQ voltage value is different. The specific value can be found in Table 3 below:

[0071]

[0072] Table 3 Corresponding values ​​and ranges of power supply VDDQ under different standards

[0073] Obviously, when the working mode is LPDDR4, LPDDR5, LPDDR4X (i.e. low power mode), the VDDQ power supply is often relatively low, so the VDAC value obtained by the DAC module through the VDDQ resistor voltage divider is also lower. In order for the VDAC input operational amplifier module to work normally in low power mode, the VDAC voltage needs to be boosted.

[0074] In the present invention, a level conversion module is used to raise the fixed gate-source voltage value of the low voltage VDAC and the feedback voltage VREF, and then the raised voltage values ​​(VOUTA and VOUTB) are selected by the selection module as the operational amplifier inputs INP and INN respectively. The equivalent simplified circuit is as follows: Figure 4 shown.

[0075] When the working mode is DDR4 and DDR5 (i.e. normal power consumption mode), the VDAC voltage does not need to be raised. At this time, the selection module selects VDAC and VREF as the input INP and INN of the operational amplifier respectively. That is, the level conversion module is bypassed at this time. The equivalent simplified circuit is as follows: Figure 5 shown.

[0076] The selection signal LS_BP_EN in the selection module can be implemented by the logic operation of the mode selection signal MODE_SEL<2:0>, or by other methods. The following Table 4 is a truth table corresponding to the implementation method of the present invention.

[0077]

[0078] Table 4 Truth table of selection signal LS_BP_EN

[0079] The buffer module consists of three parts: bias circuit CONSTANT GM, operational amplifier circuit AMPLIFIER, and output stage circuit classABoutput. The ClassAB output structure can achieve better load capacity and output voltage range close to rail-to-rail, providing better support for different VREF outputs in different working modes.

[0080] Figure 6 The equivalent circuit diagram of the DAC in an embodiment is shown when the working mode is DDR4 and the range selection range1 (i.e., the mode selection signal is 010 and RANGE is 0), wherein the switch control signal Switch_Gate_Open selects G0 to open. The range of VDAC output by the DAC is between the minimum value VRmin and the maximum value VRmax, and depends on the value of OP<5:0>. VRmax and VRmin are obtained by the following formulas, respectively, where RA0 is the equivalent resistance of R11 to R17, RB0 is the equivalent resistance of R21 to R28, and Rq_min and Rq_max are the minimum and maximum values ​​of the adjustable resistance Rq.

[0081]

[0082] It should be noted that the same formula can be used to calculate the output range of VDAC for LPDDR4, LPDDR5 and LPDDRX.

[0083] Figure 7 An equivalent circuit diagram of a DAC in an embodiment when the working mode is DDR5 (ie, the mode selection signal is 010) is shown, wherein the switch control signal Switch_Gate_Open selects G4 to open.

[0084]

[0085] The range of VDAC output by the DAC is between the minimum value VRmin and the maximum value VRmax, and depends on the value of OP<5:0>. VRmax and VRmin are obtained by the following formulas, where RA1 is the equivalent resistance of R11 to R17, RB1 is the equivalent resistance of R21 to R28, and Rq_min and Rq_max are the minimum and maximum values ​​of the adjustable resistor Rq.

[0086] The above embodiment describes a circuit in which VREF supports five standards at the same time, but the present invention can also have a variety of usage scenarios, such as supporting only a single standard VREF reference voltage, or supporting 2-4 standards (arbitrarily selecting a single or a combination of multiple) VREF reference voltage. For the case where only a single protocol is satisfied, the switch control signal Switch_Gate_Open is fixed to a single selection signal. According to the specific protocol type selection required to be supported, the 16-selection gate MUX16TO1 in the DAC is replaced by a 4-selection gate MUX4TO1, and the 8-selection gate MUX8TO1 is replaced by a 2-selection gate MUX2TO1. For the case where two protocols are satisfied, the switch control signal Switch_Gate_Open is fixed to a two-selection selection signal. According to the specific protocol type selection required to be supported, the 16-selection gate MUX16TO1 in the DAC is replaced by an 8-selection gate MUX8TO1, and the 8-selection gate MUX8TO1 is replaced by a 4-selection gate MUX2TO1. Under the premise of not consuming the same proportion of circuit resources, the present invention can support circuit usage scenarios with high flexibility and adaptability, and realizes accurate output of reference levels.

[0087] It should be noted that, in the present application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "include one" do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In the present application, if it is mentioned that a certain action is performed according to a certain element, it means at least the meaning of performing the action according to the element, which includes two situations: performing the action only according to the element and performing the action according to the element and other elements. Multiple, multiple, multiple, etc. expressions include 2, 2 times, 2 kinds and more than 2, more than 2 times, more than 2 kinds.

[0088] The term "coupled to" and its derivatives may be used herein. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.

[0089] This specification includes combinations of the various embodiments described herein. Individual references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments"); however, these embodiments are not mutually exclusive unless indicated as mutually exclusive or it is clear to a person skilled in the art that they are mutually exclusive. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

[0090] All documents mentioned in this specification are considered to be included in the disclosure of this application as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

Claims

1. A reference voltage output circuit, characterized in that: include: A digital-to-analog converter, the digital-to-analog converter comprising a voltage-dividing resistor string, a plurality of first multiplexers and a second multiplexer, wherein a first power supply terminal supplies power to the voltage-dividing resistor string, the voltage-dividing resistor string generates a plurality of bits of divided voltage according to a mode selection signal and a reference voltage control signal, the plurality of bits of divided voltage are grouped and output to each of the first multiplexers, the outputs of the plurality of first multiplexers are coupled to the second multiplexer, and the plurality of first multiplexers and the second multiplexer each selectively output the divided voltage according to the mode selection signal and the reference voltage output selection signal; A level conversion circuit, the level conversion circuit is coupled to the digital-to-analog converter and raises the voltage of the divided voltage output by the digital-to-analog converter in a low power consumption mode; a selection module, the selection module comprising a third multiplexer, the third multiplexer receiving the boosted divided voltage output by the level conversion circuit or the divided voltage output by the digital-to-analog converter, and selecting the boosted divided voltage for differential output in the low power mode or selecting the divided voltage output by the digital-to-analog converter for differential output in the non-low power mode based on the mode selection signal; as well as An output buffer, wherein the output buffer comprises a bias circuit, an operational amplifier and an output stage circuit, wherein the bias circuit provides a bias voltage for the operational amplifier, the operational amplifier receives the differential voltage output by the selection module and performs operational amplification on the differential voltage, the output stage circuit converts the amplified differential voltage into a single-ended voltage and outputs it as a reference voltage, and the reference voltage is output to the level conversion circuit and the selection module.

2. The reference voltage output circuit according to claim 1, characterized in that: The output stage circuit includes a Class AB amplifier, which includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The gates of the first NMOS transistor and the second NMOS transistor are respectively coupled to a pair of differential amplified divided voltages output by the operational amplifier. The sources of the first PMOS transistor and the second PMOS transistor are both coupled to a second power supply terminal. The gate and drain of the first PMOS transistor, the gate of the second PMOS transistor, and the drain of the first NMOS transistor are connected. The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and outputs the reference voltage. The drains of the first NMOS transistor and the second NMOS transistor are both coupled to the ground terminal.

3. The reference voltage output circuit according to claim 1, characterized in that: The voltage-dividing resistor string includes first to seventh fixed resistors, an adjustable resistor and ninth to seventeenth fixed resistors sequentially connected between the first power supply terminal and the ground terminal. Both ends of the first to seventh fixed resistors are sequentially coupled to the first power supply terminal through first to eighth switches, and both ends of the ninth to sixteenth fixed resistors are sequentially coupled to the ground terminal through first to eighth switches. The voltage-dividing resistor string generates a 7-bit divided voltage according to a mode selection signal and a reference voltage control signal.

4. The reference voltage output circuit according to claim 3, characterized in that: The digital-to-analog converter includes eight first multiplexers, each of which receives a 4-bit divided voltage in sequence, and the first multiplexer is a 16-to-1 selector.

5. The reference voltage output circuit according to claim 4, characterized in that: The second multiplexer receives eight divided voltages formed by the outputs of the eight first multiplexers, and the second multiplexer is an 8-to-1 selector.

6. The reference voltage output circuit according to claim 3, characterized in that: The mode selection signal is a 3-bit digital signal, and the reference voltage control signal is a 1-bit digital signal. When the mode selection signal is 000, the working mode of the reference voltage output circuit is DDR4, the first switch is turned on when the reference voltage control signal is 0, and the second switch is turned on when the reference voltage control signal is 1; When the mode selection signal is 001, the working mode of the reference voltage output circuit is LPDDR4, the third switch is turned on when the reference voltage control signal is 0, and the fourth switch is turned on when the reference voltage control signal is 1; When the mode selection signal is 010, the working mode of the reference voltage output circuit is DDR5, and the fifth switch is turned on; When the mode selection signal is 011, the working mode of the reference voltage output circuit is LPDDR5, and the sixth switch is turned on; When the mode selection signal is 100, the working mode of the reference voltage output circuit is LPDDR4X, the seventh switch is turned on when the reference voltage control signal is 0, and the eighth switch is turned on when the reference voltage control signal is 1.

7. The reference voltage output circuit according to claim 1, wherein: The output voltage selection signal is a 7-bit digital signal VSEL<6:0>, and a control codeword OP<6:0> is generated according to the mode selection signal and the reference voltage output selection signal, wherein OP<3:0> controls the plurality of first multiplexers, and OP<6:4> controls the second multiplexer; When the mode selection signal is 000, 001, 011 or 100, OP<5:0> is VSEL<5:0>, OP<5:0> is <6> is 0; When the mode selection signal is 010, OP<5:0> is VSELB<5:0>, OP <6> For VSELB <6> , where VSELB<6:0> is the inverted result of VSEL<6:0>.

8. The reference voltage output circuit according to claim 1, wherein: The level conversion circuit includes a third PMOS transistor, a fourth PMOS transistor, a first resistor and a second resistor, wherein the sources of the third PMOS transistor and the fourth PMOS transistor are coupled to a second power supply terminal, the gate of the third PMOS transistor receives the divided voltage output by the digital-to-analog converter, the drain of the third PMOS transistor is coupled to one end of the first resistor, the gate of the fourth PMOS transistor receives the reference voltage, the drain of the fourth PMOS transistor is coupled to one end of the second resistor, and the other ends of the first resistor and the second resistor are both coupled to a ground terminal, wherein the sources of the third PMOS transistor and the fourth PMOS transistor respectively output a pair of differential raised divided voltages.

9. The reference voltage output circuit according to claim 1, wherein: The selection module includes two third multiplexers, which are 2-to-1 selectors; one input end of one of the third multiplexers receives one of a pair of differential boosted divided voltages, and the other input end receives the reference voltage; one input end of the other third multiplexer receives the other of the pair of differential boosted divided voltages, and the other input end receives the divided voltage output by the digital-to-analog converter.

10. The reference voltage output circuit according to claim 9, characterized in that: The two third multiplexers output according to the mode selection signal, wherein the mode selection signal is a 3-bit digital signal, When the mode selection signal is 000, the control signals of the two third multiplexers are 1; When the mode selection signal is 001, the control signals of the two third multiplexers are 0; When the mode selection signal is 010, the control signals of the two third multiplexers are 1; When the mode selection signal is 011, the control signals of the two third multiplexers are 0; When the mode selection signal is 100, the control signals of the two third multiplexers are 0.

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