Formation method of semiconductor structure
By forming a dielectric wall and a shielding layer in the semiconductor structure, the problem of improving the performance of the fully enclosed gate structure device is solved, and the protection of the second device region is achieved, the damage probability is reduced, thereby improving the performance of the semiconductor structure.
Patent Information
- Application Number
- CN202311137039.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-04
- Publication Date
- 2025-03-07
AI Technical Summary
With the further reduction of the size of semiconductor devices, it is becoming increasingly difficult and challenging to improve the performance of fully enclosed gate structure devices.
In the method of forming a semiconductor structure, a dielectric wall is formed at the junction of the first device region and the second device region, and a shading layer is formed in a spatial position opposite to the adjacent channel layer, and the shading layer covers the top and side walls of the work function layer and the dielectric wall, thereby reducing the probability of damage to the second device region during the removal of the shading layer and the work function layer.
Through the protection of the dielectric wall, the method reduces the influence of the process of removing the first device area shading layer and the work function layer on the second device area, thereby improving the performance of the semiconductor structure.
Smart Images
Figure CN119584626A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art
[0002] With the rapid development of semiconductor manufacturing technology, semiconductor transistors are moving towards higher component density and higher integration, and semiconductor process nodes are continuously decreasing in accordance with Moore's Law. Transistors, as the most basic semiconductor transistors, are currently being widely used. Therefore, with the increase in component density and integration of semiconductor transistors, in order to adapt to the reduction of process nodes, the channel length of transistors must be continuously shortened.
[0003] In order to better adapt to the requirement of proportional reduction of transistor size, semiconductor processes have gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors. Among them, gate-all-around transistors include vertical gate-all-around transistors and horizontal gate-all-around transistors. In a gate-all-around transistor, the gate surrounds the area where the channel is located from all sides. Compared with planar transistors, the gate of a gate-all-around transistor has a stronger control ability over the channel and can better suppress the short channel effect.
[0004] As device size continues to shrink, improving the performance of all-around gate structure devices becomes increasingly difficult and challenging. Summary of the invention
[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to further improve the performance of the semiconductor structure.
[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first device region and a second device region adjacent to each other, a channel structure layer being suspended on the top of the substrate in the first device region and the second device region along the normal direction of the substrate surface, the channel structure layer comprising one or more channel layers spaced apart in the longitudinal direction; forming a gate dielectric layer and a work function layer surrounding and covering the gate dielectric layer on part of the top, part of the sidewall and part of the bottom of the channel layer; forming a dielectric wall on the top of the substrate at the junction of the first device region and the second device region; forming a shielding layer at the spatial position where the adjacent channel layers are opposite to each other, at the spatial position where the bottommost channel layer is opposite to the substrate and on the substrate where the channel structure layer is exposed, the shielding layer covering the top and sidewalls of the work function layer and the top and sidewalls of the dielectric wall; removing the shielding layer and the work function layer in the first device region; removing the shielding layer in the dielectric wall and the shielding layer in the second device region.
[0007] Optionally, the step of forming a dielectric wall includes: forming a dielectric material layer covering the top and side walls of the channel structure layer on the substrate where the channel structure layer is exposed, the dielectric material layer also filling the spatial position where the channel structure layer of the first device area and the channel structure layer of the second device area are opposite to each other; removing the dielectric material layer of the first device area and the second device area, and the remaining dielectric material layer located at the junction of the first device area and the second device area serves as the dielectric wall.
[0008] Optionally, the process of removing the dielectric material layer in the first device region and the second device region includes a wet etching process.
[0009] Optionally, the etching solution used in the wet etching process includes H3PO4.
[0010] Optionally, after forming the work function layer and before forming the dielectric wall, it also includes: forming a protective layer on the top surface of the substrate exposed by the channel structure layer, the top, sidewall and bottom of the channel structure layer, and the protective layer surrounds and covers the work function layer; in the step of forming the dielectric wall, the dielectric wall is located on the top of the protective layer at the junction of the first device area and the second device area; in the step of removing the dielectric material layer of the first device area and the second device area, the etching selectivity ratio of the dielectric material layer to the protective layer is greater than 50:1.
[0011] Optionally, the process of forming the protective layer includes an atomic layer deposition process.
[0012] Optionally, after forming the dielectric wall and before forming the shielding layer, the method further includes: removing the protective layers of the first device region and the second device region.
[0013] Optionally, the process of removing the protective layers of the first device region and the second device region includes a dry etching process.
[0014] Optionally, the etching gas used in the dry etching process includes a mixed gas of HF and NH 3 .
[0015] Optionally, in the step of removing the protective layer of the first device region and the second device region, an etching selectivity ratio between the protective layer and the work function layer is greater than 100:1.
[0016] Optionally, the step of removing the shielding layer and the work function layer in the first device region includes: removing the shielding layer in the first device region; and removing the work function layer in the first device region using the shielding layer in the second device region as a mask.
[0017] Optionally, the step of removing the shielding layer in the first device region includes: forming a mask layer on top of the shielding layer in the second device region, the mask layer exposing the first device region; and removing the shielding layer in the first device region using the mask layer as a mask.
[0018] Optionally, the process of removing the shielding layer of the first device region includes an ashing process.
[0019] Optionally, the process of removing the work function layer in the first device region includes a wet etching process.
[0020] Optionally, the step of removing the dielectric wall and the shielding layer of the second device region includes: removing the dielectric wall; and after removing the dielectric wall, removing the shielding layer of the second device region.
[0021] Optionally, the process of removing the dielectric wall includes an anisotropic dry etching process.
[0022] Optionally, the material of the shielding layer includes one or both of BARC and SARC.
[0023] Optionally, the material of the dielectric wall includes one or more of silicon nitride, amorphous silicon and polysilicon.
[0024] Optionally, in the step of forming a gate dielectric layer and a work function layer, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; the material of the work function layer includes one or more of TiN, TaN, TiAl, TiSiN and TiAlC.
[0025] Optionally, after removing the shielding layer of the second device area, the method for forming the semiconductor structure also includes: forming a gate electrode layer spanning the channel layer on the top of the substrate of the first device area and the second device area, wherein the gate electrode layer in the first device area surrounds and covers the gate dielectric layer, and the gate electrode layer in the second device area surrounds and covers the work function layer.
[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0027] An embodiment of the present invention provides a method for forming a semiconductor structure, wherein a dielectric wall is formed on the top of a substrate at the junction of a first device region and a second device region, and a shielding layer is formed at a spatial position directly opposite to adjacent channel layers, a spatial position directly opposite to the bottom channel layer and the substrate, and on the substrate where the channel structure layer is exposed, wherein the shielding layer covers the top and side walls of the work function layer and the top and side walls of the dielectric wall. Accordingly, in the subsequent step of removing the shielding layer in the first device region, the dielectric wall can protect the shielding layer in the second device region, thereby reducing the probability that the process of removing the shielding layer in the first device region causes consumption of the shielding layer in the second device region, thereby reducing the risk of the work function layer in the second device region being exposed, and in the subsequent step of removing the work function layer in the first device region, the probability of the work function layer in the second device region being damaged is also reduced, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figures 1 to 6It is a structural schematic diagram corresponding to a semiconductor structure;
[0029] Figures 7 to 18 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0030] The performance of current semiconductor structures needs to be improved. The reasons why the performance needs to be improved are analyzed in combination with a semiconductor structure.
[0031] Figures 1 to 6 It is a structural schematic diagram corresponding to a semiconductor structure.
[0032] refer to Figure 1 A substrate 10 is provided, the substrate 10 includes a first device area 10A and a second device area 10B adjacent to each other, a channel structure layer 16 is suspended on the top of the substrate 10 between the first device area 10A and the second device area 10B along the normal direction of the surface of the substrate 10, the channel structure layer 16 includes one or more channel layers 15 spaced apart in the vertical direction, a gate dielectric layer 18 is formed on part of the top, part of the sidewall and part of the bottom of the channel layer 15, and a work function layer 19 surrounding and covering the gate dielectric layer 18 is formed.
[0033] refer to Figure 2 A shielding layer 20 covering the work function layer 19 is formed on the substrate 10 where the channel structure layer 16 is exposed.
[0034] refer to Figure 3 , in the first device region 10A, the blocking layer 20 on the sidewall of the channel structure layer 16 is removed.
[0035] refer to Figure 4 After removing the shielding layer 20 on the sidewall of the channel structure layer 16, in the first device area 10A, the shielding layer 20 located in the spatial position directly opposite to the adjacent channel layer 15 and in the spatial position directly opposite to the channel layer 15 and the substrate 10 is removed.
[0036] refer to Figure 5 , remove the work function layer 19 of the first device region 10A.
[0037] refer to Figure 6 After removing the work function layer 19 of the first device region 10A, the shielding layer 20 of the second device region 10B is removed.
[0038] Research has found that after removing the blocking layer 20 on the side wall of the channel structure layer 16, in the first device area 10A, in the process of removing the blocking layer 20 located in the spatial position opposite to the adjacent channel layer 15 and the spatial position opposite to the channel layer 15 and the substrate 10, the etching process used is likely to cause excessive consumption of the blocking layer 20 in the second device area 10B, and accordingly, increase the risk of the work function layer 19 in the second device area 10B being exposed. In the subsequent step of removing the work function layer 19 in the first device area 10A, the probability of the work function layer 19 in the second device area 10B being damaged is increased, thereby affecting the performance of the semiconductor structure.
[0039] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a first device region and a second device region adjacent to each other, along the normal direction of the substrate surface, a channel structure layer is suspended on the top of the substrate in the first device region and the second device region, the channel structure layer includes one or more channel layers spaced apart in the longitudinal direction; forming a gate dielectric layer and a work function layer surrounding and covering the gate dielectric layer on part of the top, part of the sidewall and part of the bottom of the channel layer; forming a dielectric wall on the top of the substrate at the junction of the first device region and the second device region; forming a shielding layer at the spatial position opposite to the adjacent channel layers, the spatial position opposite to the bottom channel layer and the substrate, and on the substrate where the channel structure layer is exposed, the shielding layer covering the top and sidewalls of the work function layer and the top and sidewalls of the dielectric wall; removing the shielding layer and the work function layer in the first device region; removing the shielding layer in the dielectric wall and the second device region.
[0040] An embodiment of the present invention provides a method for forming a semiconductor structure, wherein a dielectric wall is formed on the top of a substrate at the junction of a first device region and a second device region, and a shielding layer is formed at a spatial position directly opposite to adjacent channel layers, a spatial position directly opposite to the bottom channel layer and the substrate, and on the substrate where the channel structure layer is exposed, wherein the shielding layer covers the top and side walls of the work function layer and the top and side walls of the dielectric wall. Accordingly, in the subsequent step of removing the shielding layer in the first device region, the dielectric wall can protect the shielding layer in the second device region, thereby reducing the probability that the process of removing the shielding layer in the first device region causes consumption of the shielding layer in the second device region, thereby reducing the risk of the work function layer in the second device region being exposed, and in the subsequent step of removing the work function layer in the first device region, the probability of the work function layer in the second device region being damaged is also reduced, thereby improving the performance of the semiconductor structure.
[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0042] Figures 7 to 18 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0043] refer to Figure 7 , providing a substrate (not shown), the substrate includes an adjacent first device region 100A and a second device region 100B, along the normal direction of the substrate surface, a channel structure layer 106 is suspended on the top of the substrate of the first device region 100A and the second device region 100B, and the channel structure layer includes one or more channel layers 105 spaced apart in the longitudinal direction.
[0044] The substrate is used to provide a process platform for subsequent process steps.
[0045] In this embodiment, the substrate is a three-dimensional structure, and includes a substrate 100 and fins 101 separated from the first device region 100A and the second device region 100B on the substrate 100. In other embodiments, the substrate may also be a planar substrate.
[0046] In this embodiment, the substrate 100 is a silicon substrate 100. In other embodiments, the substrate may also be a silicon-germanium combination.
[0047] In this embodiment, the fin 101 is made of the same material as the substrate 100 , that is, silicon.
[0048] In this embodiment, the first device region 100A is used to form a first-type transistor, and the second device region 100B is used to form a second-type transistor. The first-type transistor and the second-type transistor have different channel conductivity types. Specifically, the first-type transistor is an NMOS transistor, and the second-type transistor is a PMOS transistor; in other embodiments, the first-type transistor is a PMOS transistor, and the second-type transistor is an NMOS transistor.
[0049] The channel layer 105 is used as a conductive channel of the first device region 100A and the second device region 100B.
[0050] In this embodiment, both the first-type transistor and the second-type transistor are all-around-gate transistors, and therefore, the channel layer 105 and the substrate are spaced apart in the vertical direction.
[0051] In this embodiment, the material of the channel layer 105 includes one or more of silicon, silicon germanium, germanium and III-V semiconductor materials. The material of the channel layer 105 of the first device region 100A is determined according to the performance of the first type transistor, and the material of the channel layer 105 of the second device region 100B is determined according to the performance of the second type transistor. As an example, the material of the channel layer 105 of the first device region 100A and the second device region 100B is silicon.
[0052] In this embodiment, the number of the channel layers 105 is three. In other embodiments, the number of the channel layers may be other numbers.
[0053] In this embodiment, the method for forming a semiconductor structure further includes: before forming the channel structure layer 106 , forming an isolation layer 102 on the substrate 100 where the fin 101 is exposed, wherein the isolation layer 102 covers the sidewalls of the fin 101 .
[0054] The isolation layer 102 is used to isolate the adjacent first device region 100A and the second device region 100B. To this end, the material of the isolation layer 102 is a dielectric material, and the material of the isolation layer 102 may include silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation layer 102 is silicon oxide.
[0055] In this embodiment, in the step of providing a substrate, an interlayer dielectric layer (not shown) covering the channel structure layer 106 is also formed on the substrate, and a gate opening 107 spanning the channel structure layer 106 is formed in the interlayer dielectric layer, and the gate opening 107 exposes part of the top and part of the side wall of the channel structure layer 106.
[0056] The interlayer dielectric layer is used to isolate adjacent devices. The material of the interlayer dielectric layer is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer is silicon oxide.
[0057] In this embodiment, the gate opening 107 provides a process window for subsequent process steps.
[0058] refer to Figure 8 A gate dielectric layer 108 and a work function layer 109 surrounding and covering the gate dielectric layer 108 are formed on a portion of the top, a portion of the sidewall and a portion of the bottom of the channel layer 105 .
[0059] The gate dielectric layer 108 is used to reduce the probability of leakage current in the semiconductor device, thereby improving the reliability of the semiconductor device.
[0060] In this embodiment, in the step of forming the gate dielectric layer 108 , the gate dielectric layer 108 is formed on a portion of the top, a portion of the sidewall, and a portion of the bottom of the channel layer 105 exposed by the gate opening 107 .
[0061] In this embodiment, the material of the gate dielectric layer 108 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.
[0062] Specifically, the gate dielectric layer 108 includes a gate oxide layer that conformally covers a portion of the top, a portion of the sidewall, and a portion of the bottom of the channel layer 105, and a high-k gate dielectric layer 108 that conformally covers the gate oxide layer. The material of the high-k gate dielectric layer 108 is a high-k dielectric material, which refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide.
[0063] In this embodiment, the process of forming the gate dielectric layer 108 includes an atomic layer deposition process.
[0064] The work function layer 109 is used to adjust the threshold voltage of the second-type transistor.
[0065] In this embodiment, the material of the work function layer 109 includes one or more of TiN, TaN, TiAl, TiSiN and TiAlC. The specific material of the work function layer 109 is determined according to the performance of the second-type transistor.
[0066] In this embodiment, the process of forming the work function layer 109 includes an atomic layer deposition process.
[0067] refer to Fig. 9 After forming the work function layer 109 and before subsequently forming the dielectric wall, it also includes: forming a protective layer 190 on the top surface of the substrate exposed by the channel structure layer 106, the top, sidewall and bottom of the channel structure layer 106, and the protective layer 190 surrounds and covers the work function layer 109.
[0068] It should be noted that in the subsequent process of forming the dielectric wall, it is necessary to remove the dielectric material layer of the first device area 100A and the second device area 100B. The protective layer 190 can reduce the probability of damage to the work function layer 109 in the process of removing the dielectric material layer of the first device area 100A and the second device area 100B, so that the threshold voltage of the semiconductor structure can meet the process requirements.
[0069] It should also be noted that, by forming the protective layer 190, the protective layer 190 can occupy in advance the spatial region directly opposite to the adjacent channel layer 105, as well as the top and side walls of the channel layer 105. Accordingly, in the subsequent process of removing the dielectric material layer of the first device area 100A and the second device area 100B, and retaining the dielectric material layer at the junction of the first device area 100A and the second device area 100B, the protective layer 190 can protect the side walls of the dielectric material layer at the junction of the first device area 100A and the second device area 100B, thereby reducing the probability of excessive consumption of the dielectric material layer at the junction of the first device area 100A and the second device area 100B in the process of removing the dielectric material layer of the first device area 100A and the second device area 100B, thereby making the quality of the subsequently formed dielectric wall higher, thereby improving the performance of the semiconductor structure.
[0070] In this embodiment, the process of forming the protection layer 190 includes an atomic layer deposition process.
[0071] The atomic layer deposition process includes performing multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the protective layer 190 and enabling the protective layer 190 to cover the exposed substrate top surface of the channel structure layer 106, the top, sidewalls and bottom of the channel structure layer 106. In other embodiments, the protective layer can also be formed by a chemical vapor deposition process (CVD).
[0072] In this embodiment, the material of the protection layer 190 includes silicon oxide.
[0073] Silicon oxide has a large etching selectivity ratio with the material used for the subsequently formed dielectric wall. In the process of removing the dielectric material layer of the first device area 100A and the second device area 100B, the protective layer 190 is not easily removed, so that the protective layer 190 plays a better protective role on the work function layer 109 of the first device area 100A and the second device area 100B, thereby improving the performance of the semiconductor structure.
[0074] refer to Figure 10 to Figure 11 A dielectric wall 191 is formed on the top of the substrate at the junction of the first device region 100A and the second device region 100B.
[0075] It should be noted that in the subsequent step of removing the shielding layer of the first device area 100A, the dielectric wall 191 can protect the shielding layer in the second device area 100B, thereby reducing the probability that the process of removing the shielding layer of the first device area 100A will cause consumption of the shielding layer in the second device area 100B, thereby reducing the risk of the work function layer 109 in the second device area 100B being exposed. In the subsequent step of removing the work function layer 109 of the first device area 100A, the probability of the work function layer 109 in the second device area 100B being damaged is also reduced, thereby improving the performance of the semiconductor structure.
[0076] In this embodiment, the step of forming the dielectric wall 191 includes: forming a dielectric material layer 192 covering the top and side walls of the channel structure layer 106 on the substrate where the channel structure layer 106 is exposed, and the dielectric material layer 192 also fills the spatial position where the channel structure layer 106 of the first device area 100A and the channel structure layer 106 of the second device area 100B are opposite to each other; removing the dielectric material layer 192 of the first device area 100A and the second device area 100B, and the remaining dielectric material layer 192 located at the junction of the first device area 100A and the second device area 100B serves as the dielectric wall 191.
[0077] In this embodiment, the process of forming the dielectric material layer 192 includes an atomic layer deposition process.
[0078] In this embodiment, the process of removing the dielectric material layer 192 in the first device region 100A and the second device region 100B includes a wet etching process.
[0079] Specifically, the wet etching process is an isotropic etching process, and its lateral etching rate is much greater than the longitudinal etching rate, and it has the characteristics of simple operation and high process efficiency. By adopting the wet etching process to remove the dielectric material layer 192 of the first device area 100A and the second device area 100B, the dielectric material layer 192 of the first device area 100A and the second device area 100B can be completely removed.
[0080] In this embodiment, in the step of forming the dielectric wall 191 , the dielectric wall 191 is located on the top of the protection layer 190 at the junction of the first device region 100A and the second device region 100B.
[0081] It should be noted that the dielectric wall 191 is located on the top of the protective layer 190 at the junction of the first device area 100A and the second device area 100B, that is, in the process of removing the dielectric material layer 192 of the first device area 100A and the second device area 100B, the protective layer 190 can protect the side walls of the dielectric material layer 192 at the junction of the first device area 100A and the second device area 100B, thereby reducing the probability of excessive consumption of the dielectric material layer 192 at the junction of the first device area 100A and the second device area 100B in the process of removing the dielectric material layer 192 of the first device area 100A and the second device area 100B, thereby making the morphology quality of the side walls of the dielectric wall 191 higher, thereby improving the performance of the semiconductor structure.
[0082] In this embodiment, the material of the dielectric wall 191 includes one or more of silicon nitride, amorphous silicon and polysilicon.
[0083] Specifically, in the subsequent process of removing the blocking layer of the first device area 100A, there is a large etching selectivity ratio between silicon nitride, amorphous silicon and polycrystalline silicon and the material selected for the blocking layer, so that while satisfying the removal of the blocking layer of the first device area 100A, the dielectric wall 191 can be retained, and the dielectric wall 191 can protect the blocking layer in the second device area 100B, thereby reducing the probability that the process of removing the blocking layer of the first device area 100A will cause consumption of the blocking layer in the second device area 100B.
[0084] In the present embodiment, in the step of removing the dielectric material layer 192 of the first device area 100A and the second device area 100B, the etching selectivity ratio of the dielectric material layer 192 to the protective layer 190 should not be too small. If the etching selectivity of the dielectric material layer 192 to the protective layer 190 is too small, it is easy to cause the protective layer 190 to be completely removed during the process of removing the dielectric material layer 192, thereby exposing the work function layer 109 of the first device area 100A and the second device area 100B, and further increasing the probability of damage to the work function layer 109 during the process of removing the dielectric material layer 192, so that the performance of the semiconductor structure is affected. For this reason, in the present embodiment, in the step of removing the dielectric material layer 192 of the first device area 100A and the second device area 100B, the etching selectivity ratio of the dielectric material layer 192 to the protective layer 190 is greater than 50:1.
[0085] In this embodiment, the etching solution used in the wet etching process includes H3PO4.
[0086] H3PO4 is a commonly used etching solution for removing the dielectric material layer 192 in a wet etching process, and can completely remove the dielectric material layer 192 in the first device region 100A and the second device region 100B.
[0087] refer to Fig.12 After forming the dielectric wall 191 and before subsequently forming the shielding layer, the method further includes: removing the protective layer 190 of the first device region 100A and the second device region 100B.
[0088] The protective layer 190 of the first device region 100A and the second device region 100B is removed to provide a space for subsequently forming a shielding layer in the first device region 100A and the second device region 100B.
[0089] In this embodiment, the process of removing the protection layer 190 of the first device region 100A and the second device region 100B includes a dry etching process.
[0090] As an example, the etching gas used in the dry etching process includes a mixed gas of HF and NH 3 .
[0091] Selecting a mixed gas of HF and NH3 to remove the protective layer 190 of the first device area 100A and the second device area 100B can achieve a greater etching selectivity ratio between the protective layer 190 and the dielectric wall 191, so that the dielectric wall 191 can be completely retained while removing the protective layer 190. At the same time, the mixed gas of HF and NH3 causes less damage to the work function layer 109, which can reduce the probability of damage to the work function layer 109 of the semiconductor structure.
[0092] It should be noted that in the step of removing the protective layer 190 of the first device area 100A and the second device area 100B, the etching selectivity ratio between the protective layer 190 and the work function layer 109 should not be too small. If the etching selectivity ratio between the protective layer 190 and the work function layer 109 is too small, the probability of the work function layer 109 being etched and removed is increased during the process of removing the protective layer 190 of the first device area 100A and the second device area 100B, thereby affecting the threshold voltage of the semiconductor structure, and further affecting the electrical properties of the semiconductor structure. For this reason, in the present embodiment, in the step of removing the protective layer 190 of the first device area 100A and the second device area 100B, the etching selectivity ratio between the protective layer 190 and the work function layer 109 is greater than 100:1.
[0093] refer to Fig.13 A shielding layer 115 is formed at the spatial position where adjacent channel layers 105 are opposite to each other, at the spatial position where the bottom channel layer 105 is opposite to the substrate, and on the substrate where the channel structure layer 106 is exposed. The shielding layer 115 covers the top and side walls of the work function layer 109 and the top and side walls of the dielectric wall 191.
[0094] Specifically, by forming a shielding layer 115 at the spatial positions where adjacent channel layers 105 are opposite to each other, at the spatial positions where the bottommost channel layer 105 is opposite to the substrate, and on the substrate where the channel structure layer 106 is exposed, in the subsequent process of removing the shielding layer 115 of the first device area 100A, the shielding layer 115 located in the second device area 100B protects the work function layer 109. At the same time, in the subsequent process of removing the work function layer 109 of the first device area 100A, the shielding layer 115 located in the second device area 100B acts as an etching mask.
[0095] In this embodiment, the material of the shielding layer 115 includes one or more of BARC (bottom anti-reflective coating) and SARC (sacrificial anti-reflective coating).
[0096] Specifically, the BARC and SARC materials have a large etching selectivity ratio with the material of the work function layer 109. In the subsequent step of removing the work function layer 109 of the first device area 100A, the blocking layer 115 of the second device area 100B can be used as an etching mask. At the same time, both the BARC and SARC materials are organic materials. In the subsequent step of removing the blocking layer 115, the process difficulty of removing the blocking layer 115 is reduced, thereby improving the performance of the semiconductor structure.
[0097] refer to Figures 14 to 16 , remove the blocking layer 115 and the work function layer 109 of the first device region 100A.
[0098] Specifically, removing the blocking layer 115 , the sacrificial layer and the work function layer 109 of the first device region 100A is beneficial to the subsequent formation of a gate electrode layer spanning the channel layer 105 .
[0099] Combined with reference Figures 14 to 16 , the steps of removing the blocking layer 115 and the work function layer 109 of the first device region 100A are described in detail.
[0100] refer to Figure 14 to Figure 15 , remove the blocking layer 115 of the first device region 100A.
[0101] Specifically, the blocking layer 115 of the first device region 100A is removed to expose the channel layer 105 of the first device region 100A, thereby providing a process basis for subsequently removing the channel layer 105 in the first device region 100A.
[0102] In this embodiment, the step of removing the blocking layer 115 of the first device area 100A includes: forming a mask layer 118 on the top of the blocking layer 115 of the second device area 100B, the mask layer 118 exposing the first device area 100A; using the mask layer 118 as a mask, removing the blocking layer 115 of the first device area 100A.
[0103] In this embodiment, the material of the mask layer 118 is photoresist.
[0104] In this embodiment, the process of removing the blocking layer 115 of the first device region 100A includes an ashing process.
[0105] The ashing process is a commonly used process for removing organic materials, and can completely remove the shielding layer 115 in the first device area 100A. At the same time, in the process of removing the shielding layer 115 in the first device area 100A, the dielectric wall 191 also protects the shielding layer 115 in the second device area 100B, reducing the probability of the shielding layer 115 in the second device area 100B being consumed and exposing the work function layer 109.
[0106] refer to Fig.16 , using the blocking layer 115 of the second device region 100B as a mask, the work function layer 109 of the first device region 100A is removed.
[0107] In this embodiment, the process of removing the work function layer 109 of the first device region 100A includes a wet etching process.
[0108] Specifically, the wet etching process has the characteristics of simple operation and high process efficiency, and can completely remove the work function layer 109 in the first device area 100A, thereby reducing the probability of residual work function layer 109 in the first device area 100A.
[0109] It should be noted that after removing the shielding layer 115 and the work function layer 109 of the first device region 100A, the process further includes: removing the mask layer 118 .
[0110] Specifically, the process of removing the mask layer 118 includes one or both of a wet etching process and an ashing process.
[0111] refer to Fig.17 , remove the dielectric wall 191 and the blocking layer 115 of the second device region 100B.
[0112] The dielectric wall 191 and the blocking layer 115 of the second device region 100B are removed to provide a space for the subsequent formation of a gate electrode layer surrounding and covering the work function layer 109 in the first device region 100A and the second device region 100B.
[0113] In this embodiment, the step of removing the dielectric wall 191 and the shielding layer 115 of the second device region 100B includes: removing the dielectric wall 191; and after removing the dielectric wall 191, removing the shielding layer 115 of the second device region 100B.
[0114] In this embodiment, the process of removing the dielectric wall 191 includes an anisotropic dry etching process.
[0115] The dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, so its longitudinal etching rate is much greater than the lateral etching rate. While being able to obtain fairly accurate pattern transfer, it is beneficial to ensure the sidewall morphology quality of the shielding layer 115 of the second device area 100B, and is beneficial to ensure that the shielding layer 115 of the second device area 100B can completely cover the work function layer 109, thereby reducing damage to the work function layer 109 in the second device area 100B during the dry etching process.
[0116] In this embodiment, the process of removing the blocking layer 115 of the second device region 100B includes an ashing process.
[0117] Specifically, the ashing process has the characteristics of low process cost and simple operation. By adopting the ashing process to remove the blocking layer 115 in the second device area 100B, it is beneficial to completely remove the blocking layer 115 in the second device area 100B, thereby reducing the probability of residual blocking layer 115 in the second device area 100B, thereby improving the performance of the semiconductor structure.
[0118] It should be noted that the process of removing the dielectric wall 191 also includes removing the protective layer 190 at the bottom of the dielectric wall 191 , that is, the dielectric wall 191 and the protective layer 190 are removed in the same step.
[0119] In other embodiments, the dielectric wall and the protection layer may be removed separately in different steps.
[0120] refer to Fig.18 After removing the blocking layer 115 of the second device area 100B, the method for forming the semiconductor structure also includes: forming a gate electrode layer 130 across the channel layer 105 on the top of the substrate of the first device area 100A and the second device area 100B, wherein the gate electrode layer 130 in the first device area 100A surrounds and covers the gate electrode layer 108, and the gate electrode layer 130 in the second device area 100B surrounds and covers the work function layer 109.
[0121] The gate electrode layer 130 is used for subsequent electrical connection with external structures.
[0122] The material of the gate electrode layer 130 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. In this embodiment, the material of the gate electrode layer 130130 includes W.
[0123] In the present embodiment, the process of forming the gate electrode layer 130 across the channel layer 105 on the top of the substrate in the first device region 100A and the second device region 100B includes a chemical vapor deposition process.
[0124] It should be noted that, with the work function layer 109 formed as described above as the first work function layer, before forming the gate electrode layer 130, it may also include: forming a second work function layer (not shown) surrounding and covering the gate electrode layer 108 in the first device area 100A, and the second work function layer is used to adjust the threshold voltage of the first type transistor.
[0125] As an example, the first-type transistor is an NMOS transistor, the second work function layer 109 is an N-type work function layer 109 , and the material of the second work function layer 109 includes one or more of TiAl, Mo, MoN, AlN and TiAlC.
[0126] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first device region and a second device region adjacent to each other, wherein a channel structure layer is suspended on the top of the substrate in the first device region and the second device region along a normal direction of the substrate surface, and the channel structure layer comprises one or more channel layers spaced apart in a longitudinal direction; forming a gate dielectric layer on a portion of the top, a portion of the sidewall and a portion of the bottom of the channel layer, and a work function layer surrounding and covering the gate dielectric layer; forming a dielectric wall on the top of the substrate at the junction of the first device region and the second device region; Forming a shielding layer at the spatial position where the adjacent channel layers are opposite to each other, at the spatial position where the bottom channel layer is opposite to the substrate, and on the substrate where the channel structure layer is exposed, wherein the shielding layer covers the top and side walls of the work function layer and the top and side walls of the dielectric wall; removing the shielding layer and the work function layer of the first device region; The dielectric wall and the shielding layer of the second device region are removed.
2. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the dielectric wall includes: forming a dielectric material layer covering the top and sidewalls of the channel structure layer on the substrate where the channel structure layer is exposed, and the dielectric material layer also fills the spatial position where the channel structure layer of the first device area and the channel structure layer of the second device area are opposite to each other; removing the dielectric material layer of the first device area and the second device area, and the remaining dielectric material layer located at the junction of the first device area and the second device area serves as the dielectric wall.
3. The method for forming a semiconductor structure according to claim 2, wherein: The process of removing the dielectric material layers in the first device region and the second device region includes a wet etching process.
4. The method for forming a semiconductor structure according to claim 3, wherein: The etching solution used in the wet etching process includes H3PO4.
5. The method for forming a semiconductor structure according to claim 2, wherein: After forming the work function layer and before forming the dielectric wall, the method further comprises: forming a protective layer on the top surface of the substrate exposed by the channel structure layer, the top, sidewall and bottom of the channel structure layer, wherein the protective layer surrounds and covers the work function layer; In the step of forming the dielectric wall, the dielectric wall is located on the top of the protection layer at the junction of the first device region and the second device region; In the step of removing the dielectric material layer in the first device region and the second device region, an etching selectivity ratio of the dielectric material layer to the protective layer is greater than 50:
1.
6. The method for forming a semiconductor structure according to claim 5, wherein: The process of forming the protection layer includes an atomic layer deposition process.
7. The method for forming a semiconductor structure according to claim 5, wherein: After forming the dielectric wall and before forming the shielding layer, the method further includes: removing the protective layers of the first device region and the second device region.
8. The method for forming a semiconductor structure according to claim 7, wherein: The process of removing the protection layers of the first device region and the second device region includes a dry etching process.
9. The method for forming a semiconductor structure according to claim 8, wherein: The etching gas used in the dry etching process includes a mixed gas of HF and NH 3 .
10. The method for forming a semiconductor structure according to claim 7, wherein: In the step of removing the protective layers of the first device region and the second device region, an etching selectivity ratio between the protective layer and the work function layer is greater than 100:
1.
11. The method for forming a semiconductor structure according to claim 1, wherein: The step of removing the shielding layer and the work function layer in the first device area includes: removing the shielding layer in the first device area; and removing the work function layer in the first device area using the shielding layer in the second device area as a mask.
12. The method for forming a semiconductor structure according to claim 11, wherein: The step of removing the shielding layer in the first device area includes: forming a mask layer on the top of the shielding layer in the second device area, the mask layer exposing the first device area; and removing the shielding layer in the first device area using the mask layer as a mask.
13. The method for forming a semiconductor structure according to claim 1 or 11, characterized in that: The process of removing the shielding layer in the first device region includes an ashing process.
14. The method for forming a semiconductor structure according to claim 1 or 11, characterized in that: The process of removing the work function layer in the first device region includes a wet etching process.
15. The method for forming a semiconductor structure according to claim 1, wherein: The step of removing the dielectric wall and the shielding layer of the second device region includes: removing the dielectric wall; and after removing the dielectric wall, removing the shielding layer of the second device region.
16. The method for forming a semiconductor structure according to claim 1 or 15, characterized in that: The process of removing the dielectric wall includes an anisotropic dry etching process.
17. The method for forming a semiconductor structure according to claim 1, wherein: The material of the shielding layer includes one or both of BARC and SARC.
18. The method for forming a semiconductor structure according to claim 1, wherein: The material of the dielectric wall includes one or more of silicon nitride, amorphous silicon and polysilicon.
19. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming the gate dielectric layer and the work function layer, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; The material of the work function layer includes one or more of TiN, TaN, TiAl, TiSiN and TiAlC.
20. The method for forming a semiconductor structure according to claim 1, wherein: After removing the blocking layer in the second device area, the method for forming the semiconductor structure also includes: forming a gate electrode layer across the channel layer on the top of the substrate in the first device area and the second device area, wherein the gate electrode layer in the first device area surrounds and covers the gate dielectric layer, and the gate electrode layer in the second device area surrounds and covers the work function layer.