Display chip, display device and preparation method thereof

Abstract

The invention provides a display chip, a display device and a preparation method thereof, and the display chip comprises an epitaxial layer which comprises a first semiconductor layer, a quantum well light-emitting layer and a second semiconductor layer, the first reflecting layer is positioned on one side, deviating from the first semiconductor layer, of the second semiconductor layer; the first metal binding layer is located on the side, away from the epitaxial structure, of the first reflecting layer; the heat dissipation layer comprises a first heat dissipation layer and / or a second heat dissipation layer, the first heat dissipation layer is located between the epitaxial structure and the first reflection layer, the second heat dissipation layer is located on the side, away from the epitaxial structure, of the first reflection layer, and the second heat dissipation layer is provided with a first opening exposing the first reflection layer; the first metal binding layer is arranged on the side, away from the first reflecting layer, of the second heat dissipation layer and fills the first opening. The heat dissipation performance of the display chip can be improved.

Description

Technical Field

[0001] The present invention discloses a field of semiconductor light emitting device technology, and specifically relates to a display chip and a display device and a method for preparing the same. Background Art

[0002] At present, the heat dissipation performance of light emitting diodes (LEDs) needs to be further improved. In particular, with the development of technology, the size of LEDs has been miniaturized. For display devices such as micro-LEDs with miniaturized size, due to factors such as higher injection current density and high brightness, they face more serious heat dissipation problems. Summary of the invention

[0003] The present disclosure provides a display chip and a display device and a manufacturing method thereof, which can improve the heat dissipation performance of the display chip.

[0004] In a first aspect, an embodiment of the present disclosure provides a display chip, including:

[0005] An epitaxial layer, the epitaxial layer comprising a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer stacked in sequence, one of the first semiconductor layer and the second semiconductor layer being an n-type semiconductor layer and the other being a p-type semiconductor layer;

[0006] a first reflective layer, located on a side of the second semiconductor layer facing away from the first semiconductor layer;

[0007] A first metal binding layer, located on a side of the first reflective layer away from the epitaxial structure;

[0008] The heat dissipation layer includes a first heat dissipation layer and / or a second heat dissipation layer, the first heat dissipation layer is located between the epitaxial structure and the first reflective layer, the second heat dissipation layer is located on a side of the first reflective layer away from the epitaxial structure, the second heat dissipation layer is provided with a first opening exposing the first reflective layer, and the first metal binding layer is provided on a side of the second heat dissipation layer away from the first reflective layer and fills the first opening.

[0009] In a second aspect, an embodiment of the present disclosure provides a display device, including a chip structure and a second substrate, wherein the chip structure is formed by the aforementioned display chip, and the chip structure is bound to the second substrate through the first metal binding layer.

[0010] In a third aspect, an embodiment of the present disclosure provides a method for preparing the aforementioned display chip, comprising the following steps:

[0011] Providing an epitaxial wafer for forming the epitaxial layer;

[0012] forming the first reflective layer on a side of the second semiconductor layer of the epitaxial wafer away from the first semiconductor layer;

[0013] forming the first metal binding layer on the first reflective layer;

[0014] in,

[0015] Firstly, forming a first heat dissipation layer on a side of the second semiconductor layer of the epitaxial wafer away from the first semiconductor layer, and then forming the first reflective layer on a side of the first heat dissipation layer away from the second semiconductor layer;

[0016] and / or,

[0017] forming a dielectric layer on a side of the first reflective layer away from the epitaxial wafer;

[0018] Performing a patterning process on the dielectric layer to form a second opening exposing the first reflective layer;

[0019] Then forming the second heat dissipation layer filling the second opening;

[0020] Then etching and removing the dielectric layer to form a first opening exposing the first reflective layer;

[0021] Then, the first metal binding layer is formed on a side of the second heat dissipation layer away from the first reflective layer, and the first metal binding layer fills the first opening.

[0022] In a fourth aspect, an embodiment of the present disclosure provides a method for preparing the aforementioned display device, comprising the following steps:

[0023] According to the above-mentioned method for preparing a display chip, the display chip is prepared;

[0024] The display chip is bound to the second substrate via the first metal binding layer to obtain the display device.

[0025] The display chip and display device provided by the present disclosure and the method for manufacturing the same, by arranging a first heat dissipation layer between the epitaxial structure and the first reflective layer and / or arranging a second heat dissipation layer having a first opening on the side of the first reflective layer away from the epitaxial structure, when the second heat dissipation layer exists, the first metal binding layer is located on the side of the second heat dissipation layer away from the first reflective layer and fills the first opening. Thus, by arranging the first heat dissipation layer and / or the second heat dissipation layer of a specific structure, the heat dissipation performance of the display chip can be improved, and the chip's luminous brightness and other performance can be improved. The present disclosure is particularly applicable to improving the heat dissipation performance of micro-display devices such as Micro-LEDs, and improving their luminous brightness and other performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a schematic diagram of a chip structure in which a dielectric layer is formed on a first reflective layer according to an embodiment of the present disclosure;

[0027] Figure 2 For an embodiment of the present disclosure Figure 1 Schematic diagram of the chip structure after the dielectric layer is patterned;

[0028] Figure 3 For an embodiment of the present disclosure Figure 2 A schematic diagram of a chip structure in which a heat dissipation sub-layer (first heat dissipation layer) is formed on a first reflective layer;

[0029] Figure 4 For the removal of an embodiment of the present disclosure Figure 3 Schematic diagram of the chip structure after the dielectric layer in FIG.

[0030] Figure 5 For an embodiment of the present disclosure Figure 4 A schematic diagram of the structure of a display chip obtained after forming a first metal binding layer on the first reflective layer and the first heat dissipation layer;

[0031] Figure 6 For an embodiment of the present disclosure, Figure 4 A schematic diagram of the structure after the display chip is bound to the second substrate;

[0032] Figure 7 For the removal of an embodiment of the present disclosure Figure 6 A schematic diagram of the structure behind the substrate layer in the display chip;

[0033] Figure 8 For an embodiment of the present disclosure, Figure 7 A schematic diagram of a structure after the display chip in the embodiment is etched into a preset chip structure;

[0034] Fig. 9 For an embodiment of the present disclosure Figure 8 A schematic diagram of a display device structure obtained by sequentially forming various film layers on the surface of a chip structure;

[0035] Fig.10 Another embodiment of the present disclosure is Figure 7 A schematic diagram of a structure after the display chip in the embodiment is etched into a preset chip structure;

[0036] Fig.11 For an embodiment of the present disclosure Fig.10 A schematic diagram of a display device structure obtained by sequentially forming various film layers on the surface of a chip structure;

[0037] Fig.12 A schematic diagram of the structure of a display chip according to another embodiment of the present disclosure;

[0038] Fig.13For an embodiment of the present disclosure, Fig.12 A schematic diagram of the structure of a display device made of a display chip;

[0039] Fig.14 FIG. 4 is a schematic diagram of the structure of a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below. The specific implementation methods listed below are only for describing the principles and features of the present invention. The examples are only used to explain the present invention and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other implementation methods obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

[0041] The present disclosure provides a display chip. Figures 1 to 14 As shown, the display chip includes: an epitaxial layer, the epitaxial layer includes a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer which are stacked in sequence, one of the first semiconductor layer and the second semiconductor layer is an n-type semiconductor layer, and the other is a p-type semiconductor layer; a first reflective layer, located on a side of the second semiconductor layer away from the first semiconductor layer; a first metal binding layer, located on a side of the first reflective layer away from the epitaxial structure; a heat dissipation layer, the heat dissipation layer includes a first heat dissipation layer and / or a second heat dissipation layer, the first heat dissipation layer is located between the epitaxial structure and the first reflective layer, the second heat dissipation layer is located on a side of the first reflective layer away from the epitaxial structure, the second heat dissipation layer is provided with a first opening exposing the first reflective layer, and the first metal binding layer is provided on a side of the second heat dissipation layer away from the first reflective layer and fills the first opening.

[0042] For example, Figures 1 to 11 As shown, the display chip includes a first heat dissipation layer and a second heat dissipation layer; or Figure 12 to Figure 14 As shown, the above display chip includes a second heat dissipation layer.

[0043] Specifically, the heat dissipation layer can be formed of a material with high thermal conductivity (thermal conductivity coefficient), and its thermal conductivity can be greater than or equal to 2000W / (m·K). By introducing a heat dissipation layer with high thermal conductivity, the heat dissipation performance of the chip can be effectively alleviated, and the brightness and other performance of the display chip (such as Micro-LED) can be improved.

[0044] In some embodiments, the first heat dissipation layer may include a diamond material and / or a graphene material.

[0045] In some embodiments, the second heat dissipation layer may include diamond material and / or graphene material.

[0046] Specifically, the thermal conductivity of graphene material and diamond material may be approximately 5300 W / (m·K) and 2100 W / (m·K), respectively, which are higher than the silicon substrate and the metal film layer (for example, the thermal conductivity of the copper metal film layer and the silver metal film layer are approximately 400 W / (m·K) and 430 W / (m·K), respectively). By using diamond material and / or graphene material to form the above-mentioned heat dissipation layer, the heat dissipation performance of the chip can be further alleviated, and the brightness of the display chip and other performance can be improved.

[0047] In addition, the thickness of the first heat dissipation layer may be 100-300 nm, for example, 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm, 300 nm or a range consisting of any two thereof.

[0048] In addition, the thickness of the second heat dissipation layer may be 10-20 μm, for example, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm, 20 μm or a range consisting of any two thereof.

[0049] Specifically, the first opening penetrates the second heat dissipation layer to expose the surface of the first reflective layer, and the first metal binding layer fills the first opening and covers the second heat dissipation layer and the first opening (i.e., the projection of the first metal binding layer on the first reflective layer covers the projection of the second heat dissipation layer on the first reflective layer and the projection of the first opening on the first reflective layer).

[0050] Specifically, the second heat dissipation layer may include a plurality of heat dissipation sub-layers, and every two adjacent heat dissipation sub-layers are separated by a first opening.

[0051] The distance between the centers of two adjacent heat dissipation sub-layers may be 2-20 μm, for example, 2 μm, 5 μm, 8 μm, 10 μm, 13 μm, 15 μm, 18 μm, 20 μm or a range consisting of any two of them.

[0052] In addition, the size of each heat dissipation sublayer may be 1-10 μm, for example, 1 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm or a range consisting of any two thereof.

[0053] Specifically, the projection of the heat dissipation sublayer on the first reflective layer can be circular, the size of the heat dissipation sublayer is its diameter (that is, the diameter of the projection of the heat dissipation sublayer on the first reflective layer is 1 to 10 μm), and the center of the heat dissipation sublayer is its center of the circle (that is, the distance between the centers of each two adjacent heat dissipation sublayers is the distance between the centers of the projections of the two adjacent heat dissipation sublayers on the first reflective layer).

[0054] In addition, the first metal binding layer is used to bind the display chip to the second substrate (Bonding), that is, the display chip is bound to the second substrate through the first metal binding layer, and the second substrate includes, for example, a silicon substrate or a silicon-based complementary metal oxide semiconductor (CMOS) pixel driving circuit.

[0055] Specifically, the first metal binding layer includes metal, for example, one or more of chromium (Cr), platinum (Pt), nickel (Ni), titanium (Ti), silver (Ag), etc. Exemplarily, the first metal binding layer is a multilayer structure, that is, it includes multiple metal layers, for example, a chromium layer, a platinum layer, a nickel layer, a titanium layer, a nickel layer and a silver layer stacked in sequence on the side of the first reflective layer away from the first semiconductor layer.

[0056] In addition, the first reflective layer is used to enhance the light extraction efficiency of the display chip, and the first reflective layer may include silver (Ag), which may specifically be a silver reflective mirror.

[0057] In addition, the thickness of the first reflective layer may be 100-300 nm, for example, 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm, 300 nm or a range consisting of any two thereof.

[0058] The display chip of the embodiment of the present disclosure may be a vertical chip structure, such as a vertical Micro-LED chip structure. By adopting high thermal conductivity materials, the heat dissipation performance of the chip can be improved and the luminous brightness of the chip can be increased.

[0059] In one embodiment, if Figures 1 to 13 As shown, the above-mentioned epitaxial layer can be an InGaN-based epitaxial structure, the first semiconductor layer is an n-type semiconductor layer, the second semiconductor layer is a p-type semiconductor layer, and the above-mentioned quantum well light-emitting layer is an InGaN-based quantum well light-emitting layer, which can specifically be an InGaN-based quantum well light-emitting layer with 3 to 6 periods.

[0060] Specifically, the quantum well light-emitting layer includes one or more of a blue light quantum well light-emitting layer, a green light quantum well light-emitting layer or a red light quantum well light-emitting layer, and each of the blue light quantum well light-emitting layer, the green light quantum well light-emitting layer or the red light quantum well light-emitting layer is an InGaN-based quantum well light-emitting layer, specifically, it can be 3 to 6 periods of InGaN-based quantum well light-emitting layer.

[0061] Generally, the light emission band (wavelength range) of the blue light quantum well layer is 445-465 nm, the light emission band of the green light quantum well layer is 515-535 nm, and the light emission band of the red light quantum well layer is 615-630 nm.

[0062] In some embodiments, the blue light quantum well layer includes 3 to 6 first repeating units, each of which includes u-In stacked along a first direction. m Ga 1-m N-well layer and u-In q Ga 1-q N barrier layer (i.e. blue light quantum well layer is 3 to 6 periods of u-In m Ga 1-m N / u-In q Ga 1-q N quantum well structure), 0.18≤m≤0.21, 0.01≤q≤0.02, u-In m Ga 1- m The thickness of the N potential well layer can be 2.5 to 3 nm, and the u-In q Ga 1-q The thickness of the N barrier layer may be 10-15 nm, for example, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm or a range consisting of any two thereof.

[0063] In addition, the first repeating unit may further include a fourth u-GaN layer, a fourth u-GaN layer, a u-In m Ga 1-m N-well layer and u-In q Ga 1-q N barrier layers are stacked. m Ga 1-m N-well layer and u-In q Ga 1-q The fourth u-GaN layer is deposited before the N barrier layer is formed. This growth mode can effectively alleviate the wavelength shift problem under large current injection and further optimize the performance of the display chip. The thickness of the fourth u-GaN layer can be 2 to 3 nm.

[0064] In some embodiments, the green quantum well light-emitting layer may include 1 to 2 second repeating units and 2 to 3 third repeating units.

[0065] Each second repeating unit includes a stacked arrangement of u-In w Ga 1-w N potential well layer and the first n-GaN barrier layer (i.e., the second repeating unit is u-In w Ga 1-w N / n-GaN quantum well structure), 0.24≤w≤0.25, u-In w Ga 1-w The thickness of the N potential well layer is 2.5-3 nm, the thickness of the first n-GaN barrier layer is 10-15 nm, and the Hall electron concentration can be 5×1017 ~6×10 17 cm -3 .

[0066] In addition, the second repeating unit may further include a fifth u-GaN layer, a fifth u-GaN layer, a u-In w Ga 1-w The N potential well layer and the first n-GaN barrier layer are stacked. w Ga 1-w The fifth u-GaN layer is deposited before the N-well layer and the first n-GaN barrier layer are formed. This growth mode can effectively alleviate the wavelength shift problem under large current injection and further optimize the performance of the display chip. The thickness of the fifth u-GaN layer can be 2 to 3 nm.

[0067] Each third repeating unit includes a stacked arrangement of u-In z Ga 1-z N potential well layer and the second n-GaN barrier layer (ie, the third repeating unit is u-In z Ga 1-z N / n-GaN quantum well structure), 0.25≤z≤0.28, u-In z Ga 1-z The thickness of the N potential well layer is 2.5-3 nm, the thickness of the second n-GaN barrier layer is 10-15 nm, and the Hall electron concentration can be 5×10 17 ~6×10 17 cm -3 .

[0068] In addition, the third repeating unit may further include a sixth u-GaN layer, a sixth u-GaN layer, a u-In z Ga 1-z The N potential well layer and the second n-GaN barrier layer are stacked. z Ga 1-z The sixth u-GaN layer is deposited before the N potential well layer and the second n-GaN barrier layer are formed. This growth mode can effectively alleviate the wavelength shift problem under large current injection and further optimize the performance of the display chip. The thickness of the sixth u-GaN layer can be 2 to 3 nm.

[0069] In some embodiments, the red light quantum well light emitting layer may include 1 to 6 (e.g., 3 to 6) fourth repeating units, and each fourth repeating unit (i.e., the periodic structure of the red light quantum well light emitting layer) includes a seventh u-GaN layer, a u-In layer, and a seventh u-GaN layer stacked in sequence. g Ga 1-gN potential well layer (0.18≤g≤0.21, i.e., In component content is 18% to 21%), u-In h Ga 1-h N barrier layer (0.01≤h≤0.02, i.e., In component content is 1% to 2%), u-In i Ga 1-i N potential well layer (0.25≤i≤0.28, that is, the In component content is 25% to 28%), the third n-GaN barrier layer, u-In j Ga 1-j N potential well layer (0.35≤j≤0.38, that is, the In component content is 35% to 38%), the fourth n-GaN barrier layer, u-In k Ga 1-k N layer (0.1≤k≤0.25, that is, the In component content is 10% to 25%).

[0070] The thickness of the seventh u-GaN layer can be 2 to 3 nm, and the thickness of the u-In g Ga 1-g The thickness of the N potential well layer can be 2.5 to 3 nm, and the u-In h Ga 1-h The thickness of the N barrier layer can be 10-15 nm. i Ga 1-i The thickness of the N-well layer can be 2.5-3 nm, the thickness of the third n-GaN barrier layer can be 10-15 nm, and the thickness of the u-In j Ga 1-j The thickness of the N-well layer can be 2.5-3 nm, the thickness of the fourth n-GaN barrier layer can be 10-15 nm, and the thickness of the u-In k Ga 1-k The thickness of the N layer can be 1 to 2 nm.

[0071] Continue to refer Figures 1 to 13 The first semiconductor layer (ie, the n-type semiconductor layer) may include n-Al x Ga 1-x N / n-GaN superlattice layer, and n-Al x Ga 1-x n-Al between N / n-GaN superlattice layer and quantum well light emitting layer y Ga 1-y N / n-GaN superlattice layer (lightly doped superlattice structure), n-Al x Ga 1-x The Hall electron concentration of N / n-GaN superlattice is greater than that of n-Al y Ga 1- yHall electron concentration of N / n-GaN superlattice layer. By adopting the above superlattice structure, dislocation extension can be alleviated and the performance of display chips can be further optimized.

[0072] In the embodiments of the present disclosure, unless otherwise specified, the Hall electron concentration is the measured Hall electron concentration, and the Hall hole concentration is the measured Hall hole concentration.

[0073] Specifically, n-Al d Ga 1-d The N / n-GaN superlattice layer includes n-Al d Ga 1-d N layer and the fifth n-GaN layer, namely n-Al d Ga 1-d The N / n-GaN superlattice layer includes at least one fifth repeating unit, each of which includes n-Al stacked along the first direction. d Ga 1-d N layer and the fifth n-GaN layer, the number of the fifth repeating unit is n-Al d Ga 1-d The period number of N / n-GaN superlattice layers.

[0074] Among them, 0.05≤d≤0.1, that is, the Al component content is 5% to 10%, for example, 5%, 6%, 7%, 8%, 9%, 10% or the range of any two thereof.

[0075] In addition, n-Al d Ga 1-d The thickness of the N / N layer may be 2 to 2.5 nm, for example, 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm or any two thereof.

[0076] In addition, the thickness of the fifth n-GaN layer can be 7 to 8 nm, for example, 7 μm, 7.1 μm, 7.2 μm, 7.3 μm, 7.4 μm, 7.5 μm, 7.6 μm, 7.7 μm, 7.8 μm, 7.9 μm, 8 μm or a range consisting of any two thereof.

[0077] In addition, n-Al d Ga 1-d The thickness of the N / n-GaN superlattice layer may be 2 to 2.5 μm, for example, 2 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, 2.5 μm or a range consisting of any two thereof.

[0078] In addition, n-Al d Ga 1-dThe Hall electron concentration of the N / n-GaN superlattice layer can be 2×10 18 ~2×10 19 cm -3 , for example 2×10 18 cm -3 , 3×10 18 cm -3 , 4×10 18 cm -3 , 5×10 18 cm -3 , 6×10 18 cm -3 ,7×10 18 cm -3 , 8×10 18 cm -3 ,9×10 18 cm -3 , 1×10 19 cm -3 Or a range consisting of any two of them.

[0079] In addition, n-Al e Ga 1-e The Hall electron concentration of the N / n-GaN superlattice layer can be as high as 1×10 17 ~3×10 17 cm -3 , for example 1×10 17 cm -3 , 1.5×10 17 cm -3 , 2×10 17 cm -3 , 2.5×10 17 cm -3 , 3×10 17 cm -3 Or a range consisting of any two of them.

[0080] In addition, n-Al e Ga 1-e In the N / n-GaN superlattice layer, 0.01≤e≤0.03, n-Al e Ga 1-e The thickness of the N / n-GaN superlattice layer may be 0.2-0.5 μm, for example, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm or a range consisting of any two thereof.

[0081] Continue to refer Figures 1 to 13 The epitaxial layer may also include a second u-GaN layer, a u-In a Ga 1-aN / u-GaN superlattice layer (non-doped superlattice structure), u-In b Ga 1-b N / n-GaN superlattice layer (doped superlattice structure), first semiconductor layer, second u-GaN layer, u-In a Ga 1-a N / u-GaN superlattice layer, u-In b Ga 1-b The N / n-GaN superlattice layer and the quantum well light-emitting layer are stacked in sequence, and the second u-GaN layer is located between the n-Al y Ga 1-y N / n-GaN superlattice layer and u-In a Ga 1-a Between N / u-GaN superlattice layers.

[0082] The second u-GaN layer is mainly used as a non-doped GaN planarization layer, and its thickness can be 15 to 20 nm.

[0083] In addition, u-In a Ga 1-a N / u-GaN superlattice layer including u-In a Ga 1-a N layer and the seventh u-GaN layer, u-In a Ga 1-a The thickness of the N layer can be 2 to 2.5 nm, 0.01 ≤ a ≤ 0.03 (i.e. u-In a Ga 1-a The In component content in the N layer is 1% to 3%), and the thickness of the seventh u-GaN layer can be 5 to 15 nm, for example, 5 nm, 8 nm, 10 nm, 13 nm, 15 nm or a range consisting of any two of them.

[0084] In addition, u-In a Ga 1-a The number of periods of the N / u-GaN superlattice layer can be 3 to 5. a Ga 1-a The N / u-GaN superlattice layer includes at least one sixth repeating unit, each of which includes u-In stacked along the first direction. a Ga 1-a N layer and the seventh u-GaN layer, the number of the sixth repeating unit is u-In a Ga 1-a The period number of N / u-GaN superlattice layers.

[0085] In addition, u-In b Ga 1-bThe N / n-GaN superlattice layer includes u-In crystals arranged in a staggered manner along a first direction. b Ga 1-b N layer and the sixth n-GaN layer, u-In b Ga 1-b The thickness of the N layer can be 2 to 2.5 nm, 0.03 ≤ b ≤ 0.08 (i.e. u-In b Ga 1-b The In component content in N is 3% to 8%), the thickness of the sixth n-GaN layer can be 5 to 15 nm, for example, 5 nm, 8 nm, 10 nm, 13 nm, 15 nm or a range consisting of any two thereof, and the Hall electron concentration of the sixth n-GaN layer is 5×10 17 ~6×10 17 cm -3 .

[0086] In addition, u-In b Ga 1-b The number of periods of the N / n-GaN superlattice layer is 3 to 5. Specifically, the u-In b Ga 1-b The N / n-GaN superlattice layer includes at least one seventh repeating unit, each of which includes u-In stacked along the first direction. b Ga 1-b N layer and the sixth n-GaN layer, the number of the seventh repeating unit is u-In b Ga 1-b The period number of N / n-GaN superlattice layers.

[0087] Continue to refer Figures 1 to 13 The epitaxial layer also includes a third u-GaN layer disposed between the quantum well light-emitting layer and the second semiconductor layer (p-type semiconductor layer). In specific implementation, after the quantum well light-emitting layer is grown, the third u-GaN layer can be deposited first, and then the second semiconductor layer is grown. The third u-GaN layer is used as a protective layer, and its thickness can be 20 to 30 nm.

[0088] Continue to refer Figures 1 to 13 The second semiconductor layer may include an electron blocking layer, a hole supply layer and a p-type ohmic contact layer stacked in sequence on a side of the quantum well light-emitting layer away from the first semiconductor layer, and the third u-GaN layer is located between the electron blocking layer and the quantum well light-emitting layer.

[0089] Specifically, the electron blocking layer may include a p-AlGaN layer and / or a p-AlGaN polarization induction layer. The Al component content in the p-AlGaN layer may be 20-25% and the thickness may be 20-60 nm. The Al component content in the p-AlGaN polarization induction layer changes gradually in the thickness direction of the p-AlGaN polarization induction layer, specifically, it may change linearly from 30% to 0. The theoretically calculated hole concentration of the film layer is about 2.5×10 18 cm -3 about.

[0090] Specifically, the p-AlGaN layer is formed of p-AlGaN material, which is generally doped with Mg. In this material system, the activation energy of Mg doping is relatively high, and it is difficult to achieve high hole concentration and low resistivity. Therefore, relatively speaking, the use of the above-mentioned p-AlGaN polarization inducing layer can reduce the differential resistance of the device.

[0091] In addition, the hole supply layer may include a first p-GaN layer and / or a p-Al f Ga 1-f N / p-GaN superlattice layer.

[0092] The thickness of the first p-GaN layer may be 100-140 nm, for example, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm or a range consisting of any two thereof.

[0093] Among them, p-Al f Ga 1-f The N / p-GaN superlattice layer includes p-Al f Ga 1-f N layer and the second p-GaN layer, i.e., p-Al f Ga 1-f The N / p-GaN superlattice layer includes at least one eighth repeating unit, each of which includes p-Al stacked along the first direction. f Ga 1-f N layer and the second p-GaN layer. f Ga 1-f The Hall hole concentration of the N / p-GaN superlattice layer can be as high as 1.5×10 18 ~2.5×10 18 cm -3 , 0.15≤f≤0.25 (i.e. p-Al f Ga 1-f The Al content in the N layer is 15% to 25%), and the p-Al f Ga 1-f The thickness of the N layer may be 2 to 2.5 nm, and the thickness of the second p-GaN layer may be 7 to 8 nm.

[0094] In addition, the p-type ohmic contact layer includes 4 to 6 periods of p-In c Ga 1-c N / p-GaN ohmic contact layer, p-In c Ga 1- c The N / p-GaN ohmic contact layer includes p-In c Ga 1-c N layer and the third p-GaN layer, i.e. p-In c Ga 1-c The N / p-GaN ohmic contact layer includes at least one ninth repeating unit, each of which includes p-In stacked along the first direction. c Ga 1-c N layer and the third p-GaN layer, the number of the ninth repeating unit is p-In c Ga 1-c The period number of N / p-GaN ohmic contact layer.

[0095] Among them, 0.1≤c≤0.2 (i.e. p-In c Ga 1-c The In component content in the N layer is 10% to 20%), and the p-In c Ga 1-c The thickness of the N layer is 2 to 2.5 nm, and the thickness of the third p-GaN layer is 7 to 8 nm.

[0096] In addition, continue to refer to Figures 1 to 13 The display chip further includes a first transparent conductive layer disposed between the second semiconductor layer and the first reflective layer, and the first transparent conductive layer is located between the p-type ohmic contact layer and the first reflective layer.

[0097] The thickness of the first transparent conductive layer may be 20-100 nm, for example, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm or any two thereof. The first transparent conductive layer may include indium tin oxide (ITO), which may be an ITO film layer.

[0098] Continue to refer Figures 1 to 13 The display chip further comprises a base layer, the base layer comprises a first substrate and a buffer layer, the first substrate and the buffer layer are located on a side of the first semiconductor layer away from the second semiconductor layer, and the first substrate, the buffer layer and the first semiconductor layer are stacked in sequence.

[0099] Specifically, the first substrate may include a sapphire substrate, a silicon substrate, a SiC substrate or a GaN homogeneous substrate, wherein the sapphire substrate may include a c-plane sapphire substrate or a patterned sapphire substrate, etc.

[0100] In addition, the buffer layer may include one or more of an AlN buffer layer, a graded AlGaN buffer layer with a graded Al component content, and an n-AlGaN buffer layer, wherein the n-AlGaN buffer layer is formed of an n-type doped AlGaN material.

[0101] In addition, the thickness of the buffer layer may be in the range of 15 to 25 nm, for example, 15 nm, 18 nm, 20 nm, 23 nm, 25 nm, or any two thereof.

[0102] In addition, the matrix layer may further include a first u-GaN layer, the first u-GaN layer being located between the first semiconductor layer and the buffer layer, specifically between the buffer layer and the n-Al x Ga 1-x Between N / n-GaN superlattice layers.

[0103] In addition, the thickness of the first u-GaN layer can be 3 to 4 μm. In the X-ray diffraction test results of the first u-GaN layer, the half-peak width of the (0002) plane ω scan rocking curve of the first u-GaN layer is about 70 to 85 arcsec, and the half-peak width of the (10-12) plane ω scan rocking curve is 160 to 180 arcsec.

[0104] In some embodiments, Figures 1 to 6 and Fig.12 As shown, the first substrate is a sapphire substrate, the base layer includes a first substrate, an AlN buffer layer and a first u-GaN layer stacked in layers, and the first semiconductor layer (n-Al x Ga 1-x The N / n-GaN superlattice layer is disposed on the first u-GaN layer.

[0105] In some embodiments, the first substrate is a silicon substrate, the base layer includes a first substrate, an AlN buffer layer, a gradient AlGaN buffer layer and a first u-GaN layer stacked in layers, and the first semiconductor layer (n-Al x Ga 1-x The N / n-GaN superlattice layer is disposed on the first u-GaN layer.

[0106] Specifically, the Al component in the gradient AlGaN buffer layer may show a decreasing trend along the direction from the buffer layer to the first u-GaN layer, and the decreasing trend may be a gradient decrease or a linear gradient decrease (i.e., the gradient AlGaN buffer layer may be a linear gradient AlGaN layer, for example, linearly gradient from AlGaN to GaN (i.e., the Al component content therein linearly gradients to 0)).

[0107] In some embodiments, the first substrate is a SiC substrate, the base layer includes a first substrate and an n-AlGaN buffer layer stacked in layers, and the first semiconductor layer (n-Al x Ga 1-x The N / n-GaN superlattice layer is arranged on the n-AlGaN buffer layer. Generally, GaN and SiC substrates have a smaller lattice mismatch, and vertical structure display chips can be directly prepared.

[0108] In some embodiments, the first substrate is a GaN homogeneous substrate, and the first semiconductor layer (n-Al x Ga 1-x The N / n-GaN superlattice layer is disposed on a GaN homogeneous substrate.

[0109] In other embodiments, Fig.14 As shown, the epitaxial layer can be an AlGaInP-based epitaxial structure, specifically an AlGaInP red light epitaxial structure, such as an AlGaInP red light Micro-LED epitaxial structure, etc. Among them, the first semiconductor layer is a p-type semiconductor layer, specifically including a p-AlGaInP confinement layer; the second semiconductor layer is an n-type semiconductor layer, specifically including an n-AlGaInP confinement layer; the quantum well light-emitting layer can be an AlGaInP-based multi-quantum well light-emitting layer; the display chip also includes a GaAs substrate, and the GaAs substrate, the second semiconductor layer (n-type semiconductor layer), the quantum well light-emitting layer, and the first semiconductor layer (p-type semiconductor layer) are stacked in sequence.

[0110] The present disclosure also provides a display device, such as Figures 8 to 11 , Fig.13 and Fig.14 As shown, the display device includes a chip structure and a second substrate. The chip structure is formed by the above-mentioned display chip, and the chip structure is bound to the second substrate through a first metal binding layer.

[0111] Specifically, Figures 8 to 11 , Fig.13 and Fig.14 As shown, the chip structure includes a first semiconductor layer, a first metal binding layer, and other film layers located between the first semiconductor layer and the first metal binding layer (such as a second semiconductor layer, a quantum well light-emitting layer, etc., refer to the above for details and will not be repeated here).

[0112] Continue to participate Fig. 9 , Fig.11 , Fig.13 and Fig.14The display device may further include a third heat dissipation layer disposed on the surface of the chip structure, the third heat dissipation layer including a first layer portion located on a side of the first semiconductor layer away from the second semiconductor layer, and a second layer portion connected to the first layer portion, the second layer portion extending along the side wall of the chip structure until covering the side wall of the first metal binding layer. By providing the third heat dissipation layer, the heat dissipation characteristics of the display device can be further improved, and its luminous brightness and other performance can be enhanced.

[0113] Specifically, the third heat dissipation layer may include a high thermal conductivity material, and the thermal conductivity of the material may be greater than or equal to 2000 W / (m·K). In some preferred embodiments, the third heat dissipation layer includes a diamond material and / or a graphene material.

[0114] In addition, the thickness of the third heat dissipation layer may be 50-200 nm, for example, 50 nm, 80 nm, 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, or a range consisting of any two thereof.

[0115] Continue to refer Fig. 9 , Fig.11 , Fig.13 and Fig.14 The above-mentioned display device may also include a second reflective layer, a passivation layer, and a second transparent conductive layer sequentially arranged on the surface of the chip structure, and the third heat dissipation layer is located on the surface of the second transparent conductive layer (the passivation layer and the second transparent conductive layer are located between the second reflective layer and the third heat dissipation layer).

[0116] The second transparent conductive layer penetrates the passivation layer and the second reflective layer and is connected to the first semiconductor layer (specifically, to the n-Al x Ga 1-x N / n-GaN superlattice layer is connected), that is, the second reflective layer is provided with a third opening for the second transparent conductive layer to pass through, and the passivation layer is provided with a fourth opening for the second transparent conductive layer to pass through, and the second transparent conductive layer passes through the fourth opening of the passivation layer and the third opening of the second reflective layer respectively to be connected to the first semiconductor layer, and accordingly, the second transparent conductive layer forms a first recessed portion recessed toward the first semiconductor layer at the fourth opening and the third opening (the first recessed portion is connected to the first semiconductor layer after passing through the fourth opening and the third opening), and the third heat dissipation layer also forms a second recessed portion recessed toward the first semiconductor layer at the fourth opening and the third opening.

[0117] Continue to refer Fig. 9 , Fig.11 , Fig.13 and Fig.14 The display device further includes a first ohmic contact layer, the first ohmic contact layer is connected to the third heat dissipation layer, and the polarity of the first ohmic contact layer is consistent with that of the first semiconductor layer, that is, when the first semiconductor layer is an n-type semiconductor layer (such as Figures 8 to 11 and Fig.13 As shown), the first ohmic contact layer is an n-type ohmic contact layer (n-type ohmic contact electrode), and when the first semiconductor layer is a p-type semiconductor layer, the first ohmic contact layer is a p-type ohmic contact layer (as shown Fig.14 shown).

[0118] Exemplarily, when the first ohmic contact layer is an n-type ohmic contact layer, it may include one or more of titanium (Ti), aluminum (Al), gold (Au), etc. For example, the first ohmic contact layer includes a titanium layer, an aluminum layer, a titanium layer and a gold layer stacked in sequence.

[0119] Continue to refer Fig. 9 , Fig.11 , Fig.13 and Fig.14 The display device also includes an isolation layer, which covers the third heat dissipation layer. One end of the first ohmic contact layer is connected to the third heat dissipation layer, and the other end extends from the second semiconductor layer to the first semiconductor layer until it penetrates the isolation layer, that is, a side of the first ohmic contact layer facing away from the second substrate is substantially flush with a side of the isolation layer facing away from the first substrate.

[0120] Specifically, the projection of the isolation layer on the second substrate covers the projections of the chip structure, the second reflective layer, the passivation layer, the second transparent conductive layer and the third heat dissipation layer on the second substrate.

[0121] Specifically, Fig. 9 , Fig.11 , Fig.13 and Fig.14 As shown, the second reflective layer includes a first reflective portion located on a side of the chip structure facing away from the second substrate, and a second reflective portion connected to the first reflective portion and extending along the side wall of the chip structure, that is, the second reflective portion is arranged around the peripheral side (side wall) of the chip structure and covers the entire side wall of the chip structure, that is, one end of the second extension portion in the first direction is connected to the first reflective portion, and the other end is connected to the second substrate.

[0122] In addition, the passivation layer includes a first passivation portion located on a side of the chip structure facing away from the second substrate, and a second passivation portion connected to the first passivation portion and extending along the surface of the second reflection portion, that is, the second passivation portion is also arranged on the peripheral side of the chip structure and covers the entire side wall of the chip structure, that is, one end of the second passivation portion in the first direction is connected to the first passivation portion, and the other end is connected to the second substrate.

[0123] In addition, the second transparent conductive layer includes a first transparent conductive portion located on a side of the chip structure away from the second substrate, and a second transparent conductive portion connected to the first transparent conductive portion and extending along the surface of the second passivation portion, that is, the second transparent conductive portion is also arranged on the peripheral side of the chip structure and covers the entire side wall of the chip structure, that is, one end of the second transparent conductive portion in the first direction is connected to the first transparent conductive portion, and the other end is connected to the second substrate.

[0124] In addition, the third heat dissipation layer includes a first heat dissipation portion located on a side of the chip structure away from the second substrate, and a second heat dissipation portion connected to the first heat dissipation portion and extending along the surface of the second transparent conductive portion, that is, the second heat dissipation portion is also arranged around the chip structure and covers the entire side wall of the chip structure, that is, one end of the second heat dissipation portion in the first direction is connected to the first heat dissipation portion, and the other end is connected to the second substrate.

[0125] Specifically, the first transparent conductive part penetrates the first reflective part and the first passivation part and is connected to the first semiconductor layer, that is, the third opening is provided in the first reflective part, the fourth opening is provided in the first passivation part, the first recessed part is provided in the first transparent conductive part, and the second recessed part is provided in the first heat dissipation part.

[0126] For example, Figure 8 , Fig. 9 , Fig.13 and Fig.14 As shown, in the display device, the projection of the composite film layer composed of the first transparent conductive layer, the first reflective layer, the heat dissipation layer (the first heat dissipation layer and / or the second heat dissipation layer) and the first metal binding layer on the second substrate can cover the projection of the epitaxial layer (from the first semiconductor layer to the second semiconductor layer) on the second substrate, the width of the composite film layer can be greater than the width of the epitaxial layer, the projections of each film layer in the composite film layer on the second substrate can basically overlap, and the projections of each film layer in the epitaxial layer on the second substrate can basically overlap.

[0127] For example, Fig.10 and Fig.11 As shown, in the display device, the chip structure can be a trapezoidal structure, that is, the first semiconductor layer, the first metal binding layer, and the film layers between the first semiconductor layer and the first metal binding layer can be trapezoidal structures respectively, and the width of the side away from the second substrate is smaller than the width of the side close to the second substrate.

[0128] Specifically, the second reflective layer may include Ta2O5 and / or SiO2, for example, a Ta2O5 / SiO2 reflective film. By providing the second reflective layer, light extraction efficiency may be enhanced.

[0129] Specifically, the passivation layer may include silicon oxide compounds and / or silicon nitride compounds (SiN x), the silicon oxide compound may specifically include silicon dioxide (SiO2), for example, the passivation layer may include SiN x film layer and / or SiO2 film layer.

[0130] Specifically, the second transparent conductive layer may include ITO, which may specifically be an ITO film layer.

[0131] In some embodiments, the thickness of the second transparent conductive layer may be 20-100 nm, for example, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or a range consisting of any two thereof.

[0132] In a specific implementation, the aforementioned display chip can be used and bound to a second substrate, the base layer in the display chip is removed, and the sidewalls thereof are etched and repaired to form a chip structure of a preset shape and size, and then a second reflective layer, a passivation layer, a second transparent conductive layer and a third heat dissipation layer are sequentially formed on the surface of the chip structure, and then an isolation layer covering these film layers and a first ohmic contact layer connected to the third heat dissipation layer are formed to obtain a display device.

[0133] The present disclosure also provides a method for preparing the above-mentioned display chip, comprising the following steps: providing an epitaxial wafer for forming an epitaxial layer; forming a first reflective layer on a side of the second semiconductor layer of the epitaxial wafer away from the first semiconductor layer; forming a first metal binding layer on the first reflective layer; wherein, after first forming a first heat dissipation layer on a side of the second semiconductor layer of the epitaxial wafer away from the first semiconductor layer, a first reflective layer (such as a first metal binding layer) is formed on a side of the first heat dissipation layer away from the second semiconductor layer. Fig.12 and Fig.13 and / or, forming a dielectric layer (such as Figure 1 ); performing patterning on the dielectric layer to form a second opening (as shown) exposing the first reflective layer Figure 2 Then, a second heat dissipation layer (as shown in Figure 3 ); and then etching to remove the dielectric layer to form a first opening (as shown) exposing the first reflective layer. Figure 4 Then, a first metal binding layer is formed on the side of the second heat dissipation layer away from the first reflective layer, and the first metal binding layer fills the first opening (as shown in Figure 5 As shown), a display chip is obtained.

[0134] The dielectric layer may specifically include silicon dioxide (SiO2), and its thickness may be 500 nm to 1 μm.

[0135] Specifically, the number of the second openings may be multiple (consistent with the number of the heat dissipation sub-layers mentioned above), and each second opening penetrates the dielectric layer to expose the surface of the first reflective layer.

[0136] When there are multiple second openings, the distance (pitch) between the centers of each two adjacent second openings can be 2 to 20 μm, for example, 2 μm, 5 μm, 8 μm, 10 μm, 13 μm, 15 μm, 18 μm, 20 μm or a range consisting of any two of them.

[0137] In addition, the size R of the second opening may be 1 to 10 μm, for example, 1 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm or a range consisting of any two thereof.

[0138] Specifically, the second opening can be a hole that penetrates the dielectric layer, for example, a circular hole (i.e., the projection of the second opening on the first reflective layer is substantially circular), the size of the second opening is its diameter (i.e., the diameter of the second opening is 1 to 10 μm), and the center of the second opening is its center of circle (i.e., as described above, the distance between the centers of each two adjacent second openings is the distance between the centers of the projections of the two adjacent second openings on the first reflective layer).

[0139] In addition, the epitaxial wafer may include an InGaN-based epitaxial wafer, and the formed epitaxial layer is an InGaN-based epitaxial structure, or the epitaxial wafer may include an AlGaInP-based epitaxial wafer, and the formed epitaxial layer is an AlGaInP-based epitaxial structure.

[0140] In the embodiments of the present disclosure, unless otherwise specified, each film layer may be formed by conventional methods of forming these film layers in the art, such as deposition or growth by magnetron sputtering (Sputter), chemical vapor deposition (CVD) (such as metal organic chemical vapor deposition (MOCVD), microwave plasma chemical vapor deposition (MPCVD)), 3D inkjet printing, etc.

[0141] The following takes InGaN-based epitaxial wafer as an example to further introduce its preparation process.

[0142] As mentioned above, the display chip further includes a base layer, and the preparation process further includes a process of sequentially forming a buffer layer, a first u-GaN layer and other film layers on the first substrate to obtain the base layer.

[0143] Specifically, when the first substrate is a sapphire substrate, a Sputter device is used to epitaxially grow an AlN buffer layer on the first substrate, and then a first u-GaN layer is grown by a MOCVD device to obtain a base layer.

[0144] When the first substrate is a silicon substrate, an AlN buffer layer, a gradient AlN buffer layer, etc. can be epitaxially grown using MOCVD equipment, and then a first u-GaN layer is epitaxially grown to obtain a base layer.

[0145] When the first substrate is a SiC substrate, an n-AlGaN buffer layer may be formed on the first substrate using an n-type doped AlGaN material to obtain a base layer.

[0146] In the preparation process of the InGaN-based epitaxial wafer, after the base layer is prepared, MOCVD or the like can be used to sequentially epitaxially grow n-AlGaN layers on the surface of the base layer (i.e., the side of the first u-GaN layer (or n-AlGaN buffer layer) facing away from the first substrate). x Ga 1- x N / n-GaN superlattice layer and n-Al y Ga 1-y A N / n-GaN superlattice layer is formed to form a first semiconductor layer.

[0147] When the first substrate is a GaN homogeneous substrate, n-Al can be directly epitaxially grown on the first substrate. x Ga 1- x N / n-GaN superlattice layer and n-Al y Ga 1-y A N / n-GaN superlattice layer is formed to form a first semiconductor layer.

[0148] Subsequently, in n-Al y Ga 1-y A second u-GaN layer (non-doped GaN planarization layer) is epitaxially grown on the N / n-GaN superlattice layer; then u-In is deposited on the second u-GaN layer. a Ga 1-a N / u-GaN superlattice layer, and then u-In a Ga 1-a u-In grown on N / u-GaN superlattice layer b Ga 1-b N / n-GaN superlattice layer.

[0149] Later, at u-In b Ga 1-b An InGaN-based quantum well light-emitting layer is epitaxially grown on the N / n-GaN superlattice layer.

[0150] Subsequently, a third u-GaN layer is deposited on the quantum well light emitting layer.

[0151] Subsequently, an electron blocking layer, a hole supply layer (such as depositing a first p-GaN layer), a p-type ohmic contact layer (such as depositing a p-In layer) and a second p-type ohmic contact layer (such as depositing a p-In layer) are sequentially grown on the third u-GaN layer. c Ga 1-c N / p-GaN ohmic contact layer, etc.).

[0152] Subsequently, a first transparent conductive layer is formed on the p-type ohmic contact layer to obtain an InGaN-based epitaxial wafer. Specifically, an ITO film layer can be deposited on the p-type ohmic contact layer and annealed to form the first transparent conductive layer. By combining the annealing process, the transmittance of the ITO film layer (first transparent conductive layer) can be improved and the material resistance can be reduced.

[0153] Subsequently, a first reflective layer is formed on the first transparent conductive layer (eg, a Ag reflective mirror is deposited).

[0154] Then, if Figure 1 and Figure 2 As shown, a dielectric layer (such as depositing SiO2 material) is formed on the first reflective layer and patterned to form a second opening exposing the first reflective layer (ie, the second opening penetrates the dielectric layer).

[0155] Then, if Figure 3 As shown, a second heat dissipation layer is formed on the patterned dielectric layer. For example, diamond material can be deposited by MPCVD or 3D inkjet printing to form the second heat dissipation layer.

[0156] Then, if Figure 4 As shown, the dielectric layer is etched away to expose the first reflective layer covered by the patterned dielectric layer. When the dielectric layer is made of SiO2 material, a BOE solution can be used to etch the dielectric layer until the first reflective layer is exposed.

[0157] Then, if Figure 5 As shown, a metal material for forming a first metal binding layer is deposited on the second heat dissipation layer and the first reflective layer not covered by the second heat dissipation layer (ie, the first reflective layer exposed after removing the dielectric layer) to form a first metal binding layer, thereby manufacturing a display chip.

[0158] In other embodiments, Fig.12As shown, after forming the first transparent conductive layer, a first heat dissipation layer can be first formed on the first transparent conductive layer, for example, by depositing graphene material by CVD, 3D inkjet printing, etc., and annealing it by vacuum annealing and / or laser annealing to form the first heat dissipation layer. In which, in combination with vacuum annealing or laser annealing process, the material density and conductivity of the first heat dissipation layer can be improved. Subsequently, a first reflective layer, a second heat dissipation layer, a first metal binding layer and other film layers can be sequentially formed on the first heat dissipation layer (the formation method is referred to above and will not be repeated here) to obtain a display chip having a first heat dissipation layer and a second heat dissipation layer.

[0159] The embodiment of the present disclosure also provides a method for preparing the aforementioned display device, comprising the following steps: preparing a display chip according to the aforementioned method for preparing a display chip; and binding the display chip to a second substrate via a first metal binding layer to prepare a display device.

[0160] Specifically, the process of binding the display chip to the second substrate through the first metal binding layer may include: depositing the second metal binding layer on the second substrate, and then binding (connecting) the first metal binding layer of the display chip and the second metal binding layer of the second substrate.

[0161] Specifically, the second metal binding layer includes metal, for example, one or more of chromium (Cr), platinum (Pt), silver (Ag), indium (In), etc. Exemplarily, the second metal binding layer is a multilayer structure, that is, it includes multiple metal layers, for example, a chromium layer, a platinum layer, a silver layer, an indium layer, etc., which are sequentially stacked on the second substrate.

[0162] Specifically, as mentioned above, the second substrate may include a silicon substrate or a silicon-based complementary metal oxide semiconductor (CMOS) pixel driving circuit.

[0163] In some embodiments, the epitaxial wafer is an InGaN-based epitaxial wafer. As mentioned above, the InGaN-based epitaxial wafer also includes a substrate layer located on the side of the first semiconductor layer away from the second semiconductor layer. The method for preparing the display device also includes the following steps S101 to S105.

[0164] S101, the display chip is bonded to the second substrate via a first metal bonding layer (eg Figure 6 shown).

[0165] S102, removing the base layer to expose the first semiconductor layer (such as Figure 7 shown).

[0166] In specific implementation, the substrate and the first u-GaN layer and other film layers in the above-mentioned base layer can be removed by conventional methods in the art. For example, when the first substrate in the base layer is a sapphire substrate, the sapphire substrate can be removed by a laser lift-off (LLO) process; when the first substrate in the base layer is a silicon substrate, the silicon substrate can be removed by wet etching; when the first substrate in the base layer is a SiC substrate, it can be removed by laser lift-off or grinding.

[0167] Exemplarily, when the first substrate in the base layer is a sapphire substrate, after the display chip is bonded to the second substrate, the sapphire substrate can be removed by a laser lift-off (LLO) process, and the first u-GaN layer can be etched by an inductively coupled plasma etching (ICP-RIE) process until the first semiconductor layer is etched (i.e., the first semiconductor layer is exposed), and the first semiconductor layer is planarized and polished before performing subsequent steps.

[0168] S103, then, according to the preset parameters of the chip structure, the display chip is etched to form a chip structure (such as Figure 8 and Fig.10 shown).

[0169] In specific implementation, the display chip can be etched (mainly the sidewall thereof) according to the preset pixel size and pixel pitch of the display device, and the ICP-RIE process can be used for etching to form a chip structure that meets the preset size and other parameters. For example, according to the aforementioned display chip preparation method, a blue light chip (the quantum well light emitting layer of the display chip is a blue light quantum well light emitting layer), a green light chip (the quantum well light emitting layer of the display chip is a green light quantum well light emitting layer) and a red light chip (the quantum well light emitting layer of the display chip is a red light quantum well light emitting layer) can be prepared respectively, and then according to different pixel sizes and pixel pitches and other parameters, the blue light chip, the green light chip and the red light chip are etched respectively to form a blue light chip structure (B), a green light chip structure (G) and a red light chip structure (R), and then according to the preparation method of the display device of the embodiment of the present disclosure, the blue light chip structure (B), the green light chip structure (G) and the red light chip structure (R) are respectively bound to the second substrate to prepare an RGB Micro-LED chip.

[0170] Among them, after the display chip is etched, a sidewall repair process (such as wet etching, etc.) can be used to repair the etched interface (such as the sidewall surface) of the formed chip structure to reduce the defect density, and then proceed to the subsequent step (forming a second reflective layer on the surface of the chip structure).

[0171] S104, forming a second reflective layer, a passivation layer, a second transparent conductive layer and a third heat dissipation layer in sequence on the surface of the chip structure, wherein the second transparent conductive layer penetrates the passivation layer and the second reflective layer and is connected to the first semiconductor layer (such as Fig. 9 , Fig.11 and Fig.13 shown).

[0172] For example, a Ta2O5 / SiO2 reflective film can be deposited on the surface of the chip structure to form a second reflective layer, and SiO2 / SiN2 can be deposited by plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). x , to form a passivation layer.

[0173] Exemplarily, an ITO film layer can be deposited on the surface of the passivation layer and annealed to form a second transparent conductive layer. By combining the annealing process, the transmittance of the ITO film layer (second transparent conductive layer) can be improved and the material resistance can be reduced.

[0174] For example, graphene material can be deposited on the surface of the second transparent conductive layer by CVD, inkjet printing, etc., and annealed by vacuum annealing and / or laser annealing to form the third heat dissipation layer. The vacuum annealing or laser annealing process can improve the material density and conductivity of the third heat dissipation layer.

[0175] S105, forming a first ohmic contact layer connected to the third heat dissipation layer, and manufacturing a display device (such as Fig. 9 , Fig.11 and Fig.13 )).

[0176] In some other embodiments, the epitaxial wafer is an AlGaInP-based epitaxial wafer, the AlGaInP-based epitaxial wafer includes a GaAs substrate, and the method for preparing the display device further includes the following steps S201 to S208.

[0177] S201, etching the AlGaInP-based epitaxial wafer according to preset parameters of the chip structure.

[0178] As mentioned above, the display chip can be etched (mainly the sidewalls thereof, specifically by ICP-RIE etching) according to the preset pixel size and pixel pitch parameters of the display device, so as to form a chip structure meeting the preset size and other parameters after subsequent steps S202 to S206.

[0179] S202 , then binding the first semiconductor layer (p-type semiconductor layer) of the etched AlGaInP-based epitaxial wafer to a transfer substrate.

[0180] The transfer substrate may include a sapphire substrate or a silicon substrate.

[0181] A protective film layer may be provided between the transfer substrate and the first semiconductor layer, and a colloid may be provided between the protective film layer and the transfer substrate.

[0182] S203 , then remove the GaAs substrate (ie, peel off the GaAs substrate) to expose the second semiconductor layer (n-type semiconductor layer).

[0183] S204, forming a first reflective layer, a first metal binding layer and a heat dissipation layer on the side of the second semiconductor layer of the epitaxial wafer away from the first semiconductor layer, wherein the heat dissipation layer includes a first heat dissipation layer and / or a second heat dissipation layer, to obtain a display chip. The formation process of these film layers may be specifically referred to above, and will not be described in detail here.

[0184] S205 , bonding the display chip to the second substrate via the first metal bonding layer.

[0185] S206, removing the transfer substrate and exposing the first semiconductor layer to form a chip structure.

[0186] In the specific implementation, the transfer substrate is peeled off, and the colloid and protective film layer are removed to expose the first semiconductor layer. Then, a sidewall repair process (such as wet etching) can be used to repair the etched interface (such as the sidewall surface) of the formed chip structure to reduce the defect density, and then the subsequent step (forming a second reflective layer on the surface of the chip structure) can be carried out.

[0187] S207, forming a second reflective layer, a passivation layer, a second transparent conductive layer and a third heat dissipation layer on the surface of the chip structure in sequence, wherein the second transparent conductive layer penetrates the passivation layer and the second reflective layer and is connected to the first semiconductor layer. The formation process of these film layers is referred to above and will not be repeated here.

[0188] S208, forming a first ohmic contact layer connected to the third heat dissipation layer, and manufacturing a display device (such as Fig.14 shown).

[0189] In addition, as mentioned above, the display device may further include an isolation layer, and its preparation process may further include a process of forming the isolation layer. The isolation layer may include SiO2, and may specifically be a SiO2 film layer formed of SiO2.

[0190] In the description of the present disclosure, "n-" means n-type doping, such as the aforementioned n-GaN layer, n-Al x Ga 1-xN / n-GaN superlattice layer and the like all represent n-type doped layers, which may use conventional dopants in the art, such as SiH4; "p-" represents p-type doping, such as the aforementioned p-GaN layer, p-AlGaN layer, p-Al f Ga 1-f N / p-GaN superlattice layer and the like all represent p-type doped layers, which may also use conventional dopants in the art; "u-" represents non-doping, such as the aforementioned u-GaN layer represents a non-doped gallium nitride film layer, etc. In addition, unless otherwise specified, the "content" mentioned above refers to the molar content, and the thickness direction of the "thickness" mentioned above is parallel to the first direction, and the first direction is parallel to the direction from the first semiconductor layer to the second semiconductor layer.

[0191] In addition, terms such as "first" and "second" are used only for descriptive purposes, such as distinguishing between components to more clearly illustrate / explain the technical solution, and cannot be understood as indicating or implying the number of technical features indicated or an order with substantive significance.

[0192] In addition, unless otherwise clearly specified and limited, the terms "disposed", "located at", "connected", "connected" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication connection (network connection); it can be a direct connection, an indirect connection through an intermediate medium, or the two elements can be internally connected. For ordinary technicians in this field, the specific meanings of the above-mentioned belonging to the present invention can be understood according to specific circumstances.

[0193] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display chip, characterized in that: include: An epitaxial layer, the epitaxial layer comprising a first semiconductor layer, a quantum well light-emitting layer, and a second semiconductor layer stacked in sequence, one of the first semiconductor layer and the second semiconductor layer being an n-type semiconductor layer and the other being a p-type semiconductor layer; a first reflective layer, located on a side of the second semiconductor layer facing away from the first semiconductor layer; A first metal binding layer, located on a side of the first reflective layer away from the epitaxial structure; The heat dissipation layer includes a first heat dissipation layer and / or a second heat dissipation layer, the first heat dissipation layer is located between the epitaxial structure and the first reflective layer, the second heat dissipation layer is located on a side of the first reflective layer away from the epitaxial structure, the second heat dissipation layer is provided with a first opening exposing the first reflective layer, and the first metal binding layer is provided on a side of the second heat dissipation layer away from the first reflective layer and fills the first opening.

2. The display chip according to claim 1, characterized in that: The first heat dissipation layer includes diamond material and / or graphene material; And / or, the thickness of the first heat dissipation layer is 100-300 nm; And / or, the second heat dissipation layer includes diamond material and / or graphene material; And / or, the thickness of the second heat dissipation layer is 10-20 μm; And / or, the second heat dissipation layer includes multiple heat dissipation sub-layers, each two adjacent heat dissipation sub-layers are separated by the first opening, the size of the heat dissipation sub-layers is 1-10 μm, and / or, the distance between the centers of each two adjacent heat dissipation sub-layers is 2-20 μm.

3. The display chip according to claim 1, characterized in that: The epitaxial layer is an InGaN-based epitaxial structure, the first semiconductor layer is an n-type semiconductor layer, and the second semiconductor layer is a p-type semiconductor layer.

4. The display chip according to claim 3, characterized in that: The first semiconductor layer includes n-Al x Ga 1-x N / n-GaN superlattice layer, and located in the n-Al x Ga 1-x The n-Al between the N / n-GaN superlattice layer and the quantum well light emitting layer y Ga 1-y N / n-GaN superlattice layer, the n-Al x Ga 1-x The Hall electron concentration of the N / n-GaN superlattice layer is greater than that of the n-Al y Ga 1-y Hall electron concentration in N / n-GaN superlattice layer.

5. The display chip according to claim 4, characterized in that: The n-Al d Ga 1-d The Hall electron concentration of the N / n-GaN superlattice layer is 2×10 18 ~2×10 19 cm -3 ; And / or, the n-Al d Ga 1-d The N / n-GaN superlattice layer includes n-Al d Ga 1-d N layer and the fifth n-GaN layer, 0.05≤d≤0.1, the n-Al d Ga 1-d The thickness of the N layer is 2 to 2.5 nm, and the thickness of the fifth n-GaN layer is 7 to 8 nm; And / or, the n-Al d Ga 1-d The thickness of the N / n-GaN superlattice layer is 2 to 2.5 μm; And / or, the n-Al e Ga 1-e The Hall electron concentration of the N / n-GaN superlattice layer is 1×10 17 ~3×10 17 cm -3 ; And / or, the n-Al e Ga 1-e In the N / n-GaN superlattice layer, 0.01≤e≤0.03; And / or, the n-Al e Ga 1-e The thickness of the N / n-GaN superlattice layer is 0.2 to 0.5 μm.

6. The display chip according to claim 3, characterized in that: The epitaxial layer also includes a second u-GaN layer, a u-In a Ga 1-a N / u-GaN superlattice layer, u-In b Ga 1-b N / n-GaN superlattice layer, the n-type semiconductor layer, the second u-GaN layer, the u-In a Ga 1-a N / u-GaN superlattice layer, the u-In b Ga 1-b The N / n-GaN superlattice layer and the quantum well light-emitting layer are stacked in sequence; wherein, and / or, the u-In a Ga 1-a N / u-GaN superlattice layer including u-In a Ga 1-a N layer and the seventh u-GaN layer, the u-In a Ga 1-a The thickness of the N layer is 2 to 2.5 nm, 0.01≤a≤0.03, and the thickness of the seventh u-GaN layer is 5 to 15 nm; and / or, the u-In a Ga 1-a The period number of N / u-GaN superlattice layers is 3 to 5; and / or, the u-In b Ga 1-b N / n-GaN superlattice layer including u-In b Ga 1-b N layer and the sixth n-GaN layer, the u-In b Ga 1-b The thickness of the N layer is 2-2.5 nm, 0.03≤b≤0.08, the thickness of the sixth n-GaN layer is 5-15 nm, and the Hall electron concentration of the sixth n-GaN layer is 5×10 17 ~6×10 17 cm -3 ; and / or, the u-In b Ga 1-b The period number of the N / n-GaN superlattice layer is 3 to 5.

7. The display chip according to claim 3, characterized in that: The epitaxial layer further includes a third u-GaN layer disposed between the quantum well light-emitting layer and the second semiconductor layer and / or a first transparent conductive layer disposed between the second semiconductor layer and the first reflective layer.

8. The display chip according to claim 3, characterized in that: The second semiconductor layer includes an electron blocking layer, a hole supply layer and a p-type ohmic contact layer which are sequentially stacked on a side of the quantum well light-emitting layer away from the first semiconductor layer, wherein: The electron blocking layer comprises a p-AlGaN polarization induction layer, and the Al component content in the p-AlGaN polarization induction layer linearly changes from 30% to 0 in the thickness direction of the p-AlGaN polarization induction layer; And / or, the hole supply layer includes a first p-GaN layer and / or a p-Al f Ga 1-f N / p-GaN superlattice layer, the thickness of the first p-GaN layer is 100-140nm; the p-Al f Ga 1-f N / p-GaN superlattice layer includes p-Al f Ga 1-f N layer and a second p-GaN layer, the p-Al f Ga 1-f The thickness of the N layer is 2 to 2.5 nm, 0.15 ≤ f ≤ 0.25, and the Hall hole concentration is 1.5 × 10 18 ~2.5×10 18 cm -3 , the thickness of the second p-GaN layer is 7 to 8 nm; And / or, the p-type ohmic contact layer includes 4 to 6 periods of p-In c Ga 1-c N / p-GaN ohmic contact layer, the p-In c Ga 1-c N / p-GaN superlattice layer includes p-In c Ga 1-c N layer and the third p-GaN layer, the p-In c Ga 1-c The thickness of the N layer is 2-2.5 nm, 0.1≤c≤0.2, and the thickness of the third p-GaN layer is 7-8 nm.

9. The display chip according to claim 3, characterized in that: It also includes a base layer, wherein the base layer includes a first substrate located on a side of the first semiconductor layer away from the second semiconductor layer; wherein, The first substrate is a sapphire substrate, the base layer further comprises an AlN buffer layer and a first u-GaN layer located between the first substrate and the first semiconductor layer, and the first semiconductor layer is disposed on the first u-GaN layer; Alternatively, the first substrate is a silicon substrate, the base layer further comprises an AlN buffer layer, a gradient AlGaN buffer layer with a gradient Al component content, and a first u-GaN layer, the first substrate, the AlN buffer layer, the gradient AlGaN buffer layer, and the first u-GaN layer are stacked in sequence, and the first semiconductor layer is arranged on the first u-GaN layer; Alternatively, the first substrate is a SiC substrate, the base layer further includes an n-AlGaN buffer layer, and the first semiconductor layer is disposed on the n-AlGaN buffer layer; Alternatively, the first substrate is a GaN homogeneous substrate, and the first semiconductor layer is disposed on the GaN homogeneous substrate.

10. The display chip according to claim 1 or 3, characterized in that: The quantum well light-emitting layer includes one or more of a blue light quantum well light-emitting layer, a green light quantum well light-emitting layer or a red light quantum well light-emitting layer.

11. The display chip according to claim 10, characterized in that: The blue light quantum well layer includes 3 to 6 first repeating units, each of which includes stacked u-In m Ga 1-m N-well layer and u-In q Ga 1-q N barrier layer, 0.18≤m≤0.21, 0.01≤q≤0.02, the u-In m Ga 1-m The thickness of the N potential well layer is 2.5 to 3 nm. q Ga 1-q The thickness of the N barrier layer is 10 to 15 nm; And / or, the green light quantum well light emitting layer comprises 1 to 2 second repeating units and 2 to 3 third repeating units, wherein the second repeating unit comprises a stacked arrangement of u-In w Ga 1-w N potential well layer and the first n-GaN barrier layer, 0.24≤w≤0.25, the u-In w Ga 1-w The thickness of the N potential well layer is 2.5-3 nm, the thickness of the first n-GaN barrier layer is 10-15 nm; the third repeating unit includes a stacked u-In z Ga 1-z N potential well layer and the second n-GaN barrier layer, 0.25≤z≤0.28, the u-In z Ga 1-z The thickness of the N potential well layer is 2.5 to 3 nm, and the thickness of the second n-GaN barrier layer is 10 to 15 nm; And / or, the red light quantum well light-emitting layer includes 1 to 6 fourth repeating units, each of which includes a seventh u-GaN layer stacked in sequence, a u-In layer with a thickness of 2.5 to 3 nm, g Ga 1-g N potential well layer, u-In with a thickness of 10 to 15 nm h Ga 1-h N barrier layer, u-In with a thickness of 2.5 to 3 nm i Ga 1-i N potential well layer, a third n-GaN barrier layer with a thickness of 10 to 15 nm, and a u-In layer with a thickness of 2.5 to 3 nm j Ga 1-j N potential well layer, a fourth n-GaN barrier layer with a thickness of 10 to 15 nm, and a u-In layer with a thickness of 1 to 2 nm k Ga 1-k N layer, 0.18≤g≤0.21, 0.01≤h≤0.02, 0.25≤i≤0.28, 0.35≤j≤0.38, 0.1≤k≤0.

25.

12. The display chip according to claim 1 or 2, characterized in that: The epitaxial layer is an AlGaInP-based epitaxial structure, the first semiconductor layer is a p-type semiconductor layer, and the second semiconductor layer is an n-type semiconductor layer.

13. A display device, characterized in that: The device comprises a chip structure and a second substrate, wherein the chip structure is formed by the display chip according to any one of claims 1 to 12, and the chip structure is bound to the second substrate through the first metal binding layer.

14. The display device according to claim 13, characterized in that: It also includes a third heat dissipation layer arranged on the surface of the chip structure, the third heat dissipation layer includes a first layer portion located on a side of the first semiconductor layer away from the second semiconductor layer, and a second layer portion connected to the first layer portion, the second layer portion extends along the side wall of the chip structure until it covers the side wall of the first metal binding layer.

15. The display device according to claim 14, characterized in that: The third heat dissipation layer includes diamond material and / or graphene material; And / or, the thickness of the third heat dissipation layer is 50-200 nm.

16. The display device according to claim 14, characterized in that: It also includes a second reflective layer, a passivation layer, and a second transparent conductive layer which are sequentially arranged on the surface of the chip structure, and the third heat dissipation layer is located on the surface of the second transparent conductive layer; The second transparent conductive layer penetrates the passivation layer and the second reflective layer and is connected to the first semiconductor layer; The display device further includes a first ohmic contact layer, wherein the first ohmic contact layer is connected to the third heat dissipation layer; The display device further includes an isolation layer, which covers the third heat dissipation layer. One end of the first ohmic contact layer is connected to the third heat dissipation layer, and the other end extends from the second semiconductor layer to the first semiconductor layer until penetrating the isolation layer.

17. A method for preparing a display chip according to any one of claims 1 to 12, characterized in that: The following steps are involved: Providing an epitaxial wafer for forming the epitaxial layer; forming the first reflective layer on a side of the second semiconductor layer of the epitaxial wafer away from the first semiconductor layer; forming the first metal binding layer on the first reflective layer; in, Firstly, forming a first heat dissipation layer on a side of the second semiconductor layer of the epitaxial wafer away from the first semiconductor layer, and then forming the first reflective layer on a side of the first heat dissipation layer away from the second semiconductor layer; and / or, forming a dielectric layer on a side of the first reflective layer away from the epitaxial wafer; Performing a patterning process on the dielectric layer to form a second opening exposing the first reflective layer; Then forming the second heat dissipation layer filling the second opening; Then etching and removing the dielectric layer to form a first opening exposing the first reflective layer; Then, the first metal binding layer is formed on a side of the second heat dissipation layer away from the first reflective layer, and the first metal binding layer fills the first opening.

18. The method for preparing a display chip according to claim 17, characterized in that: The dielectric layer includes silicon dioxide.

19. A method for preparing a display device according to any one of claims 13 to 16, characterized in that: The following steps are involved: The display chip is obtained according to the method for preparing the display chip according to claim 17 or 18; The display chip is bound to the second substrate via the first metal binding layer to obtain the display device.

20. The method for manufacturing a display device according to claim 19, characterized in that: The epitaxial wafer is an InGaN-based epitaxial wafer, and the InGaN-based epitaxial wafer further includes a substrate layer located on a side of the first semiconductor layer away from the second semiconductor layer. The method for preparing the display device further includes: Binding the display chip to the second substrate through the first metal binding layer; removing the base layer to expose the first semiconductor layer; Then, etching the display chip according to preset parameters of the chip structure to form the chip structure; Then, forming a second reflective layer, a passivation layer, a second transparent conductive layer and a third heat dissipation layer in sequence on the surface of the chip structure, wherein the second transparent conductive layer penetrates the passivation layer and the second reflective layer and is connected to the first semiconductor layer; Then forming a first ohmic contact layer connected to the third heat dissipation layer; or, The epitaxial wafer is an AlGaInP-based epitaxial wafer, and the AlGaInP-based epitaxial wafer includes a GaAs substrate. The method for preparing the display device further includes: Etching the AlGaInP-based epitaxial wafer according to preset parameters of the chip structure; Then, the first semiconductor layer of the etched AlGaInP-based epitaxial wafer is bound to a transfer substrate; Then, removing the GaAs substrate to expose the second semiconductor layer; Then, forming the first reflective layer, the first metal binding layer and a heat dissipation layer on the side of the second semiconductor layer of the epitaxial wafer away from the first semiconductor layer, wherein the heat dissipation layer includes the first heat dissipation layer and / or the second heat dissipation layer, to obtain the display chip; Binding the display chip to the second substrate through the first metal binding layer; Then removing the transfer substrate and exposing the first semiconductor layer to form the chip structure; Then, forming a second reflective layer, a passivation layer, a second transparent conductive layer and a third heat dissipation layer in sequence on the surface of the chip structure, wherein the second transparent conductive layer penetrates the passivation layer and the second reflective layer and is connected to the first semiconductor layer; A first ohmic contact layer connected to the third heat dissipation layer is then formed.

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