Adjustable wide-adaptation MOSFET turn-off gate driving circuit and driving method

Abstract

The invention discloses an adjustable wide-adaptation MOSFET turn-off gate drive circuit and a drive method, and relates to the field of power electronics, and the drive circuit matches parasitic parameters of a to-be-controlled power MOSFET through parameter configuration so as to improve the applicability. In the turn-off process of the to-be-controlled power MOSFET, the circuit controls the grid voltage to be rapidly decreased at the stage higher than the Miller platform, to be kept at the Miller platform voltage during the Miller platform, to be linearly decreased at the stage from the Miller platform to the threshold voltage, and to be rapidly decreased below the threshold voltage. Through continuous fine control of grid voltage, drain-source side voltage and current track regulation and control are realized. The problems that according to an existing turn-off driving circuit, grid voltage is difficult to finely regulate and control in the turn-off process of a power MOSFET device, voltage and current tracks on the drain side and the source side of the power MOSFET cannot be finely regulated and controlled independently, the targets of low voltage overshoot and low turn-off loss are difficult to meet in the turn-off process at the same time, limited application of the power MOSFET device is difficult to achieve, and the turn-off efficiency of the power MOSFET device is low are solved. And the high power density requirement of the power electronic device is difficult to meet.

Description

Technical Field

[0001] The invention relates to the field of power electronics, and in particular to an adjustable wide-adaptability MOSFET turn-off gate drive circuit and a drive method. Background Art

[0002] During the shutdown process of the power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the shutdown digital signal needs to be converted into a shutdown analog signal suitable for the power device through the gate drive, and applied to the gate-source (hereinafter referred to as "gate-source") of the power MOSFET to complete the shutdown action. During the shutdown process of the power MOSFET, the voltage overshoot caused by the rise of the drain-source (hereinafter referred to as "drain-source") voltage and the shutdown loss are contradictory. It is necessary to change the drain-source side voltage and current trajectory by adjusting the gate signal trajectory, so that the power MOSFET can be used as much as possible to meet the needs of power electronic devices.

[0003] At present, existing drive circuits mostly use a two-level turn-off method in conjunction with a gate resistor to adjust the voltage and current trajectory of a power MOSFET device during the turn-off process. It is impossible to finely and continuously regulate the gate voltage during the turn-off process, and it is impossible to separately regulate the voltage and current trajectory on the drain-source side of the power MOSFET. It is difficult to simultaneously meet the goals of low voltage overshoot and low turn-off loss during the turn-off process, and it is difficult to meet the high power density requirements of power electronic devices. Summary of the invention

[0004] The present invention aims to solve the problem that the existing shutdown drive circuit cannot finely and continuously regulate the gate voltage during the shutdown process of the power MOSFET device, resulting in the inability to separately regulate the voltage and current trajectory on the drain-source side of the power MOSFET, making it difficult to simultaneously meet the goals of low voltage overshoot and low shutdown loss during the shutdown process, making it difficult to fully apply the power MOSFET, and making it difficult to meet the high power density requirements of power electronic devices. The present invention provides an adjustable wide-adaptability MOSFET shutdown gate drive circuit and a drive method.

[0005] The technical solution adopted by the present invention is:

[0006] A controllable wide-adaptability MOSFET turn-off gate drive circuit, the drive circuit is suitable for a power electronic device using a power MOSFET transistor, the power electronic device comprises an electric energy converter and an inverter, the drive circuit drives a power MOSFET to be controlled (09) through a port Vgate, the drive circuit comprises:

[0007] A current mirror module (01), a parameter configuration module (02), a maintenance module (03), a conduction module (04), a control module (05), a first leakage module (06), a second leakage module (07), an external gate resistor (08), nodes net1 to net6, a power supply VDD, a first shutdown enable signal (Vctrl1), a second shutdown enable (Vctrl2), a third shutdown enable signal (Vctrl3), a fourth shutdown enable signal (Vctrl4), a fifth shutdown enable (Vctrl5), a sixth shutdown enable (Vctrl6), and a ground (GND);

[0008] The current mirror module (01) comprises a first PMOS tube (MP1), a second PMOS tube (MP2), a third PMOS tube (MP3) and a fourth PMOS tube (MP4); the drain and gate of the third PMOS tube (MP3) and the gate of the fourth PMOS tube (MP4) are all connected to a node net1, the source of the third PMOS tube (MP3) is connected to the drain of the first PMOS tube (MP1), the drain of the fourth PMOS tube (MP4) is connected to a node net2, the source of the fourth PMOS tube (MP4) is connected to the gate of the first PMOS tube (MP1), the gate of the second PMOS tube (MP2) and the drain of the second PMOS tube (MP2), and the source of the first PMOS tube (MP1) and the source of the second PMOS tube (MP2) are all connected to a power supply VDD;

[0009] The parameter configuration module (02) comprises a first NMOS transistor (MN1), a first resistor (R1), a second resistor (R2) and a first capacitor (C1); the gate of the first NMOS transistor (MN1) is connected to the first shutdown enable signal (Vctrl1), the drain of the first NMOS transistor (MN1) is connected to the node net1, the source is connected to the second resistor (R2) and the first capacitor (C1) through the first resistor (R1), one end of the second resistor (R2) and the first capacitor (C1) is connected to the source of the first NMOS transistor (MN1) through the first resistor (R1), and the other end is connected to the ground (GND);

[0010] The maintenance module (03) comprises a second NMOS transistor (MN2), a third NMOS transistor (MN3), a fourth NMOS transistor (MN4), a first diode (D1) and a third resistor (R3); the anode of the first diode (D1) is connected to a node net2, the cathode is connected to a node net3, the node net3 is connected to the drain of the second NMOS transistor (MN2) and the gate of the third NMOS transistor (MN3), the source of the second NMOS transistor (MN2) is connected to the ground (GND), the gate thereof and the source of the third NMOS transistor (MN3) are connected to a node net4, the drain of the third NMOS transistor (MN3) is connected to a power supply VDD, the source of the fourth NMOS transistor (MN4) is connected to the node net4, the gate is connected to a second shutdown enable (Vctrl2), the drain is connected to the gate of the eleventh NMOS transistor (MN11) in the second leakage module (07), and the node net4 is connected to the ground (GND) through the third resistor (R3);

[0011] The conduction module (04) comprises a fifth NMOS transistor (MN5), a second diode (D2), a fourth resistor (R4) and a fifth resistor (R5), wherein the drain of the fifth NMOS transistor (MN5) is connected to a power supply VDD, the gate is connected to a node net2, and the source is connected to a node net5, the anode of the second diode (D2) is connected to the node net2, and the cathode is connected to the node net5, the node net5 is connected to the node net6 through the fourth resistor (R4), and the node net6 is connected to the ground (GND) through the fifth resistor (R5);

[0012] The control module (05) comprises a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7) and a sixth resistor (R6), wherein the drain of the sixth NMOS transistor (MN6) is connected to a control power supply VCC, the gate is connected to a third shutdown enable signal (Vctrl3), the source of the sixth NMOS transistor (MN6) is connected to a node net6, the drain of the seventh NMOS transistor (MN7) is connected to the node net6 via the sixth resistor (R6), the gate is connected to a fourth shutdown enable signal (Vctrl4), and the source is connected to a ground (GND);

[0013] The first leakage module (06) comprises an eighth NMOS tube (MN8) and a ninth NMOS tube (MN9), wherein the drain of the eighth NMOS tube (MN8) is connected to the gate of the to-be-controlled power MOSFET (09) through a port Vgate, the gate thereof is connected to a fifth shutdown enable (Vctrl5), and the source thereof is connected to the drain of a ninth NMOS tube (MN9), the drain of the ninth NMOS tube (MN9) is connected to the source of the eighth NMOS tube (MN8), the gate thereof is connected to a sixth shutdown enable (Vctrl6), and the source thereof is connected to ground (GND);

[0014] The second leakage module (07) comprises a tenth NMOS tube (MN10) and an eleventh NMOS tube (MN11), the drain of the tenth NMOS tube (MN10) being connected to the gate of the to-be-controlled power MOSFET (09) through a port Vgate, the gate thereof being connected to a node net6, the source thereof being connected to the drain of the eleventh NMOS tube (MN11), the drain of the eleventh NMOS tube (MN11) being connected to the source of the tenth NMOS tube (MN10), the gate thereof being connected to the drain of the fourth NMOS tube (MN4) in the maintaining module (03), and the source thereof being connected to a ground (GND);

[0015] The external gate resistor (08) is connected between the port Vgate and the gate of the power MOSFET (09) to be controlled.

[0016] Furthermore, the current mirror module (01) is connected to the parameter configuration module (02) at the node net1, and is connected to the maintenance module (03) and the conduction module (04) at the node net2;

[0017] The parameter configuration module (02) is connected to the current mirror module (01) at a node net1, and the input is a first shutdown enable signal (Vctrl1);

[0018] The maintenance module (03) is connected to the current mirror module (01) at the node net2, and the input is the second shutdown enable signal (Vctrl2), and is connected to the gate of the eleventh NMOS tube (MN11) in the second leakage module (07) through the fourth NMOS (MN4);

[0019] The conduction module (04) is connected to the current mirror module (01) at a node net2, and is connected to the control module (05) at a node net6;

[0020] The control module (05) is connected to the conduction module (04) at a node net6, and its input end is a third shutdown enable signal (Vctrl3) and a fourth shutdown enable signal (Vctrl4), and is connected to the gate of the tenth NMOS tube (MN10) in the second leakage module (07);

[0021] The first leakage module (06) is inputted with a fifth shutdown enable signal (Vctrl5) and a sixth shutdown enable signal (Vctrl6), and is connected to the second leakage module (07) at a port Vgate;

[0022] The second leakage module (07) is connected to the drain of the fourth NMOS tube (MN4) in the maintaining module (03).

[0023] Furthermore, the current mirror module (01) is used to copy the current i1 of the path connected to the parameter configuration module (02) to the line connected to the maintenance module (03) in the pre-shutdown stage to form a current i2, and to increase the voltage at the node net2 during the shutdown process of the power MOSFET to be controlled (09), so that the fifth NMOS transistor (MN5) in the conduction module (04) establishes a channel in the pre-shutdown stage, thereby enabling the conduction module (04) to operate;

[0024] The parameter configuration module (O2) is used to generate a current i1 in the circuit where the first NMOS tube (MN1) is located in the pre-turnoff stage of the power MOSFET (09) to be controlled according to the first turnoff enable signal (Vctrl1);

[0025] The maintaining module (O3) is used to firstly increase the voltage of the node net3 and then increase the voltage of the node net4 in the pre-turnoff stage of the controlled power MOSFET (09) according to the current i2 copied by the current mirror module (01) in the pre-turnoff stage, and then transmit the voltage of the node net4 to the gate of the eleventh NMOS tube (MN11) in the second leakage module (07) through the channel of the fourth NMOS tube (MN4) through the second turnoff enable signal (Vctrl2), so that the eleventh NMOS tube (MN11) establishes a channel;

[0026] The conduction module (04) is used to, in the pre-turnoff stage of the power MOSFET (09) to be controlled, be affected by the voltage of the node net2 to enable the fifth NMOS tube (MN5) to establish a channel, and at the same time, transmit the voltage of the node net2 to the node net5 through the second diode (D2), and pull the voltage of the node net5 down to the node net6 through the voltage division of the fourth resistor (R4) and the fifth resistor (R5), and transmit it to the gate of the tenth NMOS tube (MN10) in the second leakage module (07), so that the tenth NMOS tube (MN10) establishes a channel;

[0027] The control module (05) is used to change the node net6 and the gate voltage of the tenth NMOS tube (MN10) in the second leakage module (07) under the control of the third shutdown enable signal (Vctrl3) and the fourth shutdown enable signal (Vctrl4) during the shutdown phase of the controlled power MOSFET (09);

[0028] The first current discharge module (06) is used for, during the shutdown process of the controlled power MOSFET (09), being controlled by a fifth shutdown enable signal (Vctrl5) and a sixth shutdown enable signal (Vctrl6), to enable the eighth NMOS transistor (MN8) and the ninth NMOS transistor (MN9) to establish a channel, thereby discharging current through the port Vgate;

[0029] The second leakage module (07) is used for, in the pre-turn-off phase of the power MOSFET (09) to be controlled, the eleventh NMOS tube (MN11) obtains a channel establishment voltage from the node net4 through the fourth NMOS tube (MN4), and in the turn-off phase of the power MOSFET (09) to be controlled, controls the channel opening degree of the tenth NMOS tube (MN10) through the node net6, changes the flow capacity of the tenth NMOS tube (MN10) and the eleventh NMOS tube (MN11) in the second leakage module (07), and enables the second leakage module (07) to discharge current from the port Vgate.

[0030] Based on a driving method for a controllable wide-adaptability MOSFET turn-off gate drive circuit, the method comprises:

[0031] A method for duplicating a current i1 in a path connected to a parameter configuration module (02) in equal proportion to a line connected to a maintenance module (03) in a pre-shutdown phase to form a current i2, and raising a voltage at a node net2 during a shutdown process of a power MOSFET to be controlled (09), so that a fifth NMOS transistor (MN5) in the conduction module (04) establishes a channel in the pre-shutdown phase, thereby enabling the conduction module (04) to operate;

[0032] A method for generating a current i1 in a circuit where the first NMOS tube (MN1) is located in a pre-turnoff phase of a power MOSFET (09) to be controlled according to a first turnoff enable signal (Vctrl1);

[0033] A method for first raising the voltage of node net3 and then raising the voltage of node net4 in the pre-shutdown stage of a power MOSFET (09) to be controlled according to the current i2 copied by the current mirror module (01) in the pre-shutdown stage, and then transmitting the voltage of node net4 to the gate of an eleventh NMOS tube (MN11) in a second leakage module (07) through the channel of a fourth NMOS tube (MN4) by means of a second shutdown enable signal (Vctrl2), so that the eleventh NMOS tube (MN11) establishes a channel;

[0034] A method for causing the fifth NMOS tube (MN5) to establish a channel under the influence of the node net2 voltage in the pre-turnoff stage of the power MOSFET (09) to be controlled, and at the same time, transferring the node net2 voltage to the node net5 through the second diode (D2), and pulling the node net5 voltage down to the node net6 through the fourth resistor (R4) and the fifth resistor (R5) voltage division, and transmitting the voltage to the gate of the tenth NMOS tube (MN10) in the second leakage module (07), so that the tenth NMOS tube (MN10) establishes a channel;

[0035] A method for changing the gate voltage of a tenth NMOS tube (MN10) in a node net6 and a second leakage module (07) under the control of a third shutdown enable signal (Vctrl3) and a fourth shutdown enable signal (Vctrl4) during the shutdown phase of a power MOSFET (09) to be controlled;

[0036] A method for causing an eighth NMOS transistor (MN8) and a ninth NMOS transistor (MN9) to establish a channel under the control of a fifth turn-off enable signal (Vctrl5) and a sixth turn-off enable signal (Vctrl6) during a turn-off process of a power MOSFET to be controlled, thereby discharging current through a port Vgate;

[0037] A method for enabling an eleventh NMOS tube (MN11) to obtain a channel establishment voltage from a node net4 via a fourth NMOS tube (MN4) during a pre-turnoff phase of a power MOSFET (09) to be controlled, controlling the channel opening degree of a tenth NMOS tube (MN10) via a node net6 during a turnoff phase of the power MOSFET (09) to be controlled, changing the flow capacity of the tenth NMOS tube (MN10) and the eleventh NMOS tube (MN11) in a second discharge module (07), and enabling the second discharge module (07) to discharge current from a port Vgate.

[0038] Furthermore, the first resistor (R1), the second resistor (R2), and the first capacitor (C1) in the parameter configuration module (02) are configured according to the parasitic parameters of the power MOSFET (09) to be controlled, and the voltage waveforms of the nodes net2 and net6 in the current mirror module (01) are specifically expressed as follows:

[0039] During the turn-off process of the power MOSFET (09) to be controlled, when the gate voltage of the power MOSFET (09) to be controlled is higher than the Miller platform (Vmiller), a voltage peak value appears at the node net2;

[0040] During the shutdown process of the power MOSFET (09) to be controlled, the voltage of the node net6 is synchronized with the voltage of the node net2. When the gate voltage of the power MOSFET (09) to be controlled is higher than the Miller platform (Vmiller), the voltage of the node net6 has a voltage peak.

[0041] Furthermore, the voltage waveform of the node net6 is specifically expressed as follows: during the shutdown process of the power MOSFET to be controlled (09), when the gate voltage of the power MOSFET to be controlled (09) drops to the threshold voltage (Vth), the third shutdown enable signal (Vctrl3) and the fourth shutdown enable signal (Vctrl4) in the control module (05) synchronously control the sixth NMOS tube (MN6) and the seventh NMOS tube (MN7) to be turned on, thereby raising the voltage of the node net6. At this time, the voltage of the node net6 is raised and remains unchanged.

[0042] Furthermore, the voltage waveform at the output end (Vgate) during the shutdown process of the power MOSFET (09) to be controlled is specifically expressed as follows:

[0043] Phase 1: When the gate voltage of the power MOSFET (09) to be controlled is higher than the Miller platform (Vmiller) voltage, the gate voltage rapidly drops to the Miller platform (Vmiller) voltage;

[0044] The second stage: when the gate voltage of the power MOSFET (09) to be controlled is at the Miller platform (Vmiller) voltage, the gate voltage is maintained at the Miller platform (Vmiller) voltage;

[0045] The third stage: when the gate voltage of the power MOSFET (09) to be controlled is lower than the Miller platform (Vmiller) voltage but higher than the threshold voltage (Vth), the gate voltage decreases slowly and linearly;

[0046] The fourth stage: when the gate voltage of the power MOSFET (09) to be controlled is lower than the threshold voltage (Vth), the gate voltage drops rapidly to zero.

[0047] Furthermore, during the shutdown process of the power MOSFET to be controlled (09), the gate voltage waveform of the power MOSFET to be controlled (09) is affected by the resistance and capacitance values ​​of the first resistor (R1), the second resistor (R2) and the first capacitor (C1) in the parameter configuration module (02), and the specific expression method is as follows:

[0048] When the resistance and capacitance values ​​of the second resistor (R2) and the first capacitor (C1) remain unchanged, the greater the resistance value of the first resistor (R1), the slower the gate voltage of the controlled power MOSFET (09) decreases in the stage above the Miller platform (Vmiller), that is, the smaller the absolute value of the gate voltage drop slope in this stage, the longer the gate voltage is at the Miller platform (Vmiller) voltage;

[0049] When the resistance and capacitance values ​​of the first resistor (R1) and the first capacitor (C1) remain unchanged, the greater the resistance value of the second resistor (R2), the shorter the time that the gate voltage of the power MOSFET (09) to be controlled is lower than the Miller platform (Vmiller) voltage, thereby shortening the turn-off time of the power MOSFET (09) to be controlled;

[0050] When the resistance values ​​of the first capacitor (R1) and the second resistor (R2) remain unchanged, the smaller the capacitance value of the first capacitor (C1), the slower the gate voltage of the controlled power MOSFET (09) decreases in the stage above the Miller platform (Vmiller), that is, the smaller the absolute value of the gate voltage decrease slope in this stage.

[0051] Furthermore, during the shutdown process of the power MOSFET to be controlled (09), the drain-source current and drain-source voltage waveforms of the power MOSFET to be controlled (09) are specifically expressed as follows:

[0052] When the resistance and capacitance values ​​of the second resistor (R2) and the first capacitor (C1) remain unchanged, the greater the resistance value of the first resistor (R1), the greater the slope of the drain-source voltage of the power MOSFET (09) to be controlled, and the greater the absolute value of the slope of the drain-source current of the power MOSFET (09) to be controlled;

[0053] When the resistance and capacitance values ​​of the first resistor (R1) and the first capacitor (C1) remain unchanged, the greater the resistance value of the second resistor (R2), the smaller the slope of the drain-source voltage of the power MOSFET (09) to be controlled, and the smaller the absolute value of the slope of the drain-source current of the power MOSFET (09) to be controlled;

[0054] When the resistance values ​​of the first capacitor (R1) and the second resistor (R2) remain unchanged, the smaller the capacitance value of the first capacitor (C1), the smaller the slope of the drain-source voltage of the power MOSFET (09) to be controlled, and the smaller the absolute value of the slope of the drain-source current of the power MOSFET (09) to be controlled.

[0055] Furthermore, during the shutdown process of the power MOSFET (09) to be controlled, the drive circuit does not need to introduce the drain-source side information of the power MOSFET (09) to be controlled, and only utilizes the change characteristics of the transconductance capacitance of the power MOSFET (09) to control the gate voltage of the power MOSFET (09) to be controlled, and finally completes the control of the drain-source voltage and current trajectory of the power MOSFET (09) to be controlled; the drive circuit separately controls the slope of the drain-source voltage and drain-source current of the power MOSFET (09) to be controlled through the resistance and capacitance parameters in the parameter configuration module.

[0056] Beneficial effects: Starting from the perspective of the power MOSFET shutdown mechanism, the present invention proposes an adjustable wide-adaptability MOSFET shutdown gate drive circuit and driving method, which continuously and finely controls the gate voltage during the power MOSFET shutdown process, and realizes separate and fine control of the drain-source side voltage and current trajectory during the shutdown process, so as to achieve the purpose of low voltage overshoot and low shutdown loss of the power MOSFET during the shutdown process, and realize the maximum application of the power MOSFET. At the same time, the adjustable wide-adaptability MOSFET shutdown gate drive circuit and driving method proposed by the present invention can adjust and configure parameters according to the parasitic parameters of the power MOSFET to adapt to power MOSFETs with different parasitic parameters, thereby improving applicability. In addition, the adjustable wide-adaptability MOSFET shutdown gate drive circuit and driving method proposed by the present invention can realize separate control of the drain-source voltage and drain-source current trajectory only by controlling the gate of the power MOSFET, without introducing high-voltage information on the drain-source side, reducing insulation requirements, and improving power density.

[0057] Compared with the prior art, the present invention has the following advantages:

[0058] 1. During the shutdown process of the power MOSFET to be controlled, the gate voltage of the power MOSFET to be controlled is continuously and finely controlled to achieve separate and fine regulation of the drain-source voltage and current trajectory of the power MOSFET to be controlled, so that the power MOSFET has the characteristics of low voltage overshoot and low shutdown loss during the shutdown process, and the power MOSFET is applied to the maximum extent;

[0059] 2. Match the parasitic parameters of the power MOSFET to be controlled through the parameter configuration module to improve the applicability of the circuit;

[0060] 3. Avoid the introduction of high voltage information on the drain-source side of the power MOSFET to be controlled, reduce insulation requirements, and improve power density.

[0061] The present invention solves the problems that the existing drive circuit cannot continuously and finely control the gate voltage during the shutdown process of the power MOSFET device, cannot individually and finely control the voltage and current trajectory on the drain-source side of the power MOSFET, is difficult to simultaneously meet the goals of low voltage overshoot and low shutdown loss during the shutdown process, is difficult to achieve the maximum application of the power MOSFET, and is difficult to meet the high power density requirements of power electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 A schematic diagram of a topology of a MOSFET turn-off gate drive circuit with adjustable wide adaptability;

[0063] Figure 2 A circuit diagram of a MOSFET turn-off gate drive circuit that can be adjusted with wide adaptability;

[0064] Figure 3 A waveform diagram of a gate voltage of a controllable wide-adaptability MOSFET turn-off gate drive circuit node net2, node net6 and a power MOSFET to be controlled;

[0065] Figure 4 A waveform diagram of the current of the first leakage module of a controllable wide-adaptability MOSFET turn-off gate drive circuit and the gate voltage of the power MOSFET to be controlled;

[0066] Figure 5 This is the gate voltage waveform diagram of the power MOSFET to be controlled during the turn-off process;

[0067] Figure 6 It is a gate voltage waveform diagram of the turn-off process of the power MOSFET to be controlled when the first resistance in the parameter configuration module changes;

[0068] Figure 7 It is a schematic diagram of a gate voltage waveform during the turn-off process of the power MOSFET to be controlled when the second resistance in the parameter configuration module changes;

[0069] Figure 8 It is a gate voltage waveform diagram of the turn-off process of the power MOSFET to be controlled when the first capacitance in the parameter configuration module changes;

[0070] Fig. 9 The waveform diagram of drain-source voltage and drain-source current during the turn-off process of the power MOSFET to be controlled when the first resistance changes in the parameter configuration module;

[0071] Fig.10 The waveform diagram of drain-source voltage and drain-source current during the turn-off process of the power MOSFET to be controlled when the second resistance changes in the parameter configuration module;

[0072] Fig.11 Drain-source voltage and drain-source current waveforms during the turn-off process of the power MOSFET to be controlled when the first capacitance in the parameter configuration module changes. DETAILED DESCRIPTION

[0073] The technical solution of the present invention is further described below in conjunction with the accompanying drawings, but is not limited thereto. Any modification or equivalent replacement of the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention should be included in the protection scope of the present invention.

[0074] The present invention provides a MOSFET turn-off gate drive circuit that can be adjusted and adapted to a wide range. Figure 1As shown, it is suitable for power electronic devices using power MOSFET, and the power electronic devices include power converters and inverters. The adjustable wide-adaptability MOSFET turn-off gate drive circuit includes a current mirror module, a parameter configuration module, a maintenance module, a conduction module, a control module, a first leakage module, a second leakage module, an external power MOSFET to be controlled, and an external gate resistor. Figure 2 As shown, where:

[0075] The current mirror module includes a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3 and a fourth PMOS tube MP4, wherein the source electrodes of the first PMOS tube and the second PMOS tube are connected to a power supply VDD, the first PMOS tube is connected to a gate electrode of the second PMOS tube, the third PMOS tube is connected to a gate electrode of the fourth PMOS tube, the drain electrode of the second PMOS tube and the source electrode of the fourth PMOS tube are connected to the gate electrode of the second PMOS tube, the source electrode of the first PMOS tube is connected to the drain electrode of the third PMOS tube, the gate electrode and the drain electrode of the third PMOS tube are connected to a node net1, and the drain electrode of the fourth PMOS tube is connected to a node net2;

[0076] The parameter configuration module includes a first NMOS tube MN1, a first resistor R1, a second resistor R2 and a first capacitor C1, wherein the gate of the first NMOS tube is connected to the first shutdown enable signal Vctrl1, the drain of the first NMOS tube is connected to the node net1, the source is connected to the second resistor and the first capacitor through the first resistor, one end of the second resistor and the first capacitor is connected to the source of the first NMOS tube through the first resistor, and the other end is connected to the ground GND;

[0077] The maintenance module includes a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a first diode D1 and a third resistor R3, wherein the anode of the first diode is connected to the node net2, the cathode is connected to the node net3, the node net3 is connected to the drain of the second NMOS tube and the gate of the third NMOS tube, the source of the second NMOS tube is connected to the ground GND, its gate and the source of the third NMOS tube are connected to the node net4, the drain of the third NMOS tube is connected to the power supply VDD, the source of the fourth NMOS tube is connected to the node net4, the gate is connected to the second shutdown enable Vctrl2, the drain is connected to the gate of the eleventh NMOS tube MN11 in the second leakage module, and the node net4 is connected to the ground through the third resistor;

[0078] The conduction module includes a fifth NMOS transistor MN5, a second diode D2, a fourth resistor R4 and a fifth resistor R5, wherein the drain of the fifth NMOS transistor is connected to the power supply VDD, the gate is connected to the node net2, and the source is connected to the node net5, the anode of the second diode is connected to the node net2, the cathode is connected to the node net5, the node net5 is connected to the node net6 through the fourth resistor, and the node net6 is connected to the ground through the fifth resistor;

[0079] The control module includes a sixth NMOS tube MN6, a seventh NMOS tube MN7 and a sixth resistor R6, wherein the drain of the sixth NMOS tube is connected to the control power supply VCC, the gate is connected to the third shutdown enable signal Vctrl3, and the source is connected to the node net6, the drain of the seventh NMOS tube is connected to the node net6 through the sixth resistor, the gate is connected to the fourth shutdown enable signal Vctrl4, and the source is connected to the ground;

[0080] The first leakage module includes an eighth NMOS tube MN8 and a ninth NMOS tube MN9, wherein the drain of the eighth NMOS tube is connected to the gate of the power MOSFET to be controlled through the port Vgate via an external gate resistor, the gate is connected to the fifth shutdown enable signal Vctrl5, the source is connected to the drain of the ninth NMOS tube, the drain of the ninth NMOS tube is connected to the source of the eighth NMOS tube, the gate is connected to the sixth shutdown enable signal Vctrl6, and the source is connected to the ground GND;

[0081] The second leakage module includes a tenth NMOS tube MN10 and an eleventh NMOS tube MN11, wherein the drain of the tenth NMOS tube is connected to the gate of the power MOSFET to be controlled through the port Vgate via an external gate resistor, the gate is connected to the node net6, the source is connected to the drain of the eleventh NMOS tube, the drain of the eleventh NMOS tube is connected to the source of the tenth NMOS tube, the gate is connected to the drain of the fourth NMOS tube in the maintenance module, and the source is connected to the ground GND;

[0082] The above-mentioned current mirror module is respectively connected to the parameter configuration module, the position module, and the conduction module at the node net1 and the node net2; the input of the parameter configuration module is the first shutdown enable signal Vctrl1; the input of the maintenance module is the second shutdown enable signal Vctrl2; the maintenance module is connected to the node net2 with the current mirror module, and is connected to the drain of the fourth NMOS tube MN4 with the second leakage module; the conduction module is connected to the node net2 with the current mirror module, and is connected to the node net6 with the control module and the first leakage module; the input of the control module is the third shutdown enable signal Vctrl3 and the fourth shutdown enable signal Vctrl4, and is connected to the node net6 with the conduction module and the second leakage module; the input of the first leakage module is the fifth shutdown enable signal Vctrl5 and the sixth shutdown enable signal Vctrl6, and is connected to the output port Vgate with the second leakage module; the second leakage module is connected to the node net6 with the conduction module and the first leakage module, and is connected to the drain of the fourth NMOS tube with the maintenance module, and is connected to the output end Vgate with the first leakage module.

[0083] During the shutdown process of the power MOSFET to be controlled, the functions of the above modules are specifically manifested as follows:

[0084] The current mirror module is used to copy the current of the path formed by it and the parameter configuration module to the path formed by the maintenance module. When the first shutdown enable signal Vctrl1 in the parameter configuration module is set high, the potential of the node net1 and the node net2 in the current mirror module is pulled high;

[0085] The parameter configuration module is used to control the branch where the first NMOS tube is located to establish a current-carrying capacity according to the first shutdown enable signal Vctrl1 during the shutdown process of the power MOSFET to be controlled; in the pre-shutdown stage, the first shutdown enable signal Vctrl1 is set high, and the first NMOS tube establishes a channel. At this time, the potential of the node net1 in the current mirror module is pulled up, and the potential of the node net2 is synchronously affected. At this time, the voltage waveform of the node net2 is: during the shutdown process of the power MOSFET to be controlled, when the gate voltage of the power MOSFET to be controlled is higher than the Miller platform Vmiller stage, the node net2 voltage presents a voltage peak.

[0086] The conduction module is used to conduct the voltage of node net2 in the node current mirror module to node net5, and use the fourth resistor and the fifth resistor to divide the voltage to pull down the potential of node net5, and the lowered potential is output from node net6 to the gate of the tenth NMOS tube in the second leakage module. Among them, the voltage waveform of node net6 is: during the shutdown process of the power MOSFET to be controlled, when the gate voltage of the power MOSFET to be controlled is higher than the Miller platform Vmiller stage, the voltage of node net6 presents a voltage peak, following the voltage waveform of node net2 in the current mirror module, such as Figure 3 shown.

[0087] The control module is used to control the sixth NMOS tube and the seventh NMOS tube to establish a channel according to the third shutdown enable signal Vctrl3 and the fourth shutdown enable signal Vctrl4. The control module is internally connected to the conduction module at the node net6, and the potential of the node net6 is changed according to the input third shutdown enable signal and the fourth shutdown enable signal. The voltage waveform of the node net6 connected to it is: during the shutdown process of the power MOSFET to be controlled, when the gate voltage of the power MOSFET to be controlled drops to the threshold voltage Vth, the third shutdown enable and the fourth shutdown enable are set high at the same time. At this time, the sixth NMOS tube and the seventh NMOS tube establish a channel, so that the potential of the node net6 is pulled up again and remains unchanged, and the tenth NMOS tube in the second leakage module is driven to establish a channel so that it obtains the flow capacity, such as Figure 3 shown.

[0088] The maintenance module is used for, during the shutdown process of the power MOSFET to be controlled, when the potential of the node net2 in the current mirror module is pulled high, the potential of the node net3 is also pulled high, so that the third NMOS tube establishes a channel, and then the potential of the node net4 is pulled high by using the third NMOS tube and the third resistor R3 path, so that the second NMOS tube establishes a channel. Thus, during the shutdown process of the power MOSFET to be controlled, the maintenance module always has a voltage value at the node net4, and transmits the voltage of the node net4 to the gate of the eleventh NMOS tube in the second leakage module according to the second shutdown enable signal, so that the eleventh NMOS tube always maintains the channel establishment state during the shutdown process of the power MOSFET to be controlled.

[0089] The first leakage module is used to control the eighth NMOS tube and the ninth NMOS tube to establish a channel according to the fifth shutdown enable signal Vctrl5 and the sixth shutdown enable signal Vctrl6, so that the circuit where the eighth NMOS tube and the ninth NMOS tube are located obtains flow capacity; the first leakage module and the second leakage module are connected to the output end Vgate, and the module discharges current from the output end Vgate, which is specifically manifested as follows: during the shutdown process of the power MOSFET to be controlled, at the beginning of the shutdown process, the gate voltage of the power MOSFET to be controlled has not yet dropped, the fifth shutdown enable signal and the sixth shutdown enable signal are set high at the same time, at this time, the first leakage module obtains flow capacity, and discharges current from the gate of the power MOSFET to be controlled through the output end Vgate; after the shutdown process is completed, the gate voltage of the power MOSFET to be controlled will be zero, the fifth shutdown enable signal and the sixth shutdown enable signal are set low at the same time, at this time, the first leakage module loses flow capacity and stops discharging current through the output end Vgate.

[0090] like Figure 5 As shown in the figure, during the shutdown process of the power MOSFET to be controlled, its gate voltage waveform is specifically expressed as follows:

[0091] Phase 1: When the gate voltage of the power MOSFET to be controlled is higher than the Miller platform Vmiller voltage, the gate voltage drops rapidly to the Miller platform voltage;

[0092] The second stage: when the gate voltage of the power MOSFET to be controlled is at the Miller platform voltage Vmiller, the gate voltage is maintained at the Miller platform voltage;

[0093] The third stage: when the gate voltage of the power MOSFET to be controlled is lower than the Miller platform Vmiller voltage but higher than the threshold voltage Vth, the gate voltage slowly decreases linearly;

[0094] Stage 4: When the gate voltage of the power MOSFET to be controlled is lower than the threshold voltage Vth, the gate voltage drops rapidly to zero.

[0095] Furthermore, the first resistor, the second resistor and the first capacitor values ​​inside the parameter configuration module can be configured according to the parasitic parameters of the power MOSFET to be controlled; during the shutdown process of the power MOSFET to be controlled, the internal resistor and capacitor values ​​of the parameter configuration module have an influence on the gate voltage of the power MOSFET to be controlled, which is specifically manifested as follows:

[0096] When the resistance and capacitance values ​​of the second resistor R2 and the first capacitor C1 remain unchanged, the larger the resistance value of the first resistor R1, the slower the gate voltage of the controlled power MOSFET decreases in the stage above the Miller platform Vmiller, that is, the smaller the absolute value of the gate voltage drop slope in this stage, the longer the gate voltage is at the Miller platform Vmiller voltage. Figure 6 As shown;

[0097] When the resistance and capacitance values ​​of the first resistor R1 and the first capacitor C1 remain unchanged, the larger the resistance value of the second resistor R2 is, the shorter the time that the gate voltage of the power MOSFET to be controlled is below the Miller platform (Vmiller) voltage is, and thus the shorter the turn-off time of the power MOSFET to be controlled is. Figure 7 As shown;

[0098] When the resistance values ​​of the first capacitor R1 and the second resistor R2 remain unchanged, the smaller the capacitance value of the first capacitor C1 is, the slower the gate voltage of the power MOSFET to be controlled decreases in the stage above the Miller platform (Vmiller), that is, the smaller the absolute value of the gate voltage drop slope in this stage is, such as Figure 8 shown.

[0099] In the process of turning off the power MOSFET to be controlled, the drain-source current and drain-source voltage waveforms of the controllable wide-adaptability MOSFET turn-off gate drive circuit are affected by the internal parameter values ​​of the parameter configuration module, which are specifically manifested as follows:

[0100] When the resistance and capacitance values ​​of the second resistor R2 and the first capacitor C1 remain unchanged, the larger the resistance value of the first resistor R1, the same the slope of the drain-source voltage of the power MOSFET to be controlled, and the larger the absolute value of the slope of the drain-source current of the power MOSFET to be controlled. Fig. 9 As shown;

[0101] When the resistance and capacitance values ​​of the first resistor R1 and the first capacitor C1 remain unchanged, the larger the resistance value of the second resistor R2, the smaller the slope of the drain-source voltage of the power MOSFET to be controlled, and the smaller the absolute value of the slope of the drain-source current of the power MOSFET to be controlled. Fig.10 As shown;

[0102] When the resistance values ​​of the first capacitor R1 and the second resistor R2 remain unchanged, the smaller the capacitance value of the first capacitor C1 is, the smaller the slope of the drain-source voltage of the power MOSFET to be controlled is, and the smaller the absolute value of the slope of the drain-source current of the power MOSFET to be controlled is. Fig.11 shown.

[0103] The present invention states that “during the shutdown process of the power MOSFET to be controlled (09), the driving circuit does not need to introduce the drain-source side information of the power MOSFET to be controlled (09)”. The power MOSFET is divided into a gate, a drain, and a source, wherein the gate-source side carries a control voltage, and the drain-source side carries a power voltage, that is, the gate-source side is a low voltage, and the drain-source side is a high voltage. The circuits are all connected to the gate, that is, regulation is performed on the low voltage side;

[0104] The present invention proposes a MOSFET turn-off gate drive circuit with adjustable wide adaptability, which is mainly used for the turn-off drive of power MOSFET devices in power electronic devices. The circuit does not introduce the drain-source side information of the power MOSFET to be controlled in design, but only utilizes the transconductance capacitance change characteristics of the power MOSFET during the turn-off process, and realizes the separate fine control of the drain-source side voltage and current trajectory through continuous fine control of the gate voltage of the power MOSFET to be controlled, and optimizes between the turn-off loss and the voltage overshoot, so as to achieve the low voltage overshoot and low turn-off loss goals of the power MOSFET during the turn-off process, and realize the maximum application of the power MOSFET; at the same time, since the drain-source side information of the power MOSFET to be controlled is not introduced, the insulation requirements and circuit complexity are reduced, the power density is improved, and the high power density requirements of the power electronic device are met.

[0105] The present invention is described by several specific embodiments, and it should be understood by those skilled in the art that various changes and equivalent substitutions may be made to the present invention without departing from the scope of the present invention. In addition, various modifications may be made to the present invention for specific situations or specific circumstances without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed, but should include all implementation methods falling within the scope of the claims of the present invention.

Claims

1. A controllable wide-adaptability MOSFET turn-off gate drive circuit, the drive circuit is suitable for a power electronic device using a power MOSFET transistor, the power electronic device includes an electric energy converter and an inverter, the drive circuit drives a power MOSFET to be controlled (09) through a port Vgate, characterized in that: The adjustable wide adaptability MOSFET turn-off gate drive circuit comprises: A current mirror module (01), a parameter configuration module (02), a maintenance module (03), a conduction module (04), a control module (05), a first leakage module (06), a second leakage module (07), an external gate resistor (08), nodes net1 to net6, a power supply VDD, a first shutdown enable signal (Vctrl1), a second shutdown enable (Vctrl2), a third shutdown enable signal (Vctrl3), a fourth shutdown enable signal (Vctrl4), a fifth shutdown enable (Vctrl5), a sixth shutdown enable (Vctrl6), and a ground (GND); The current mirror module (01) comprises a first PMOS tube (MP1), a second PMOS tube (MP2), a third PMOS tube (MP3) and a fourth PMOS tube (MP4); the drain and gate of the third PMOS tube (MP3) and the gate of the fourth PMOS tube (MP4) are all connected to a node net1, the source of the third PMOS tube (MP3) is connected to the drain of the first PMOS tube (MP1), the drain of the fourth PMOS tube (MP4) is connected to a node net2, the source of the fourth PMOS tube (MP4) is connected to the gate of the first PMOS tube (MP1), the gate of the second PMOS tube (MP2) and the drain of the second PMOS tube (MP2), and the source of the first PMOS tube (MP1) and the source of the second PMOS tube (MP2) are all connected to a power supply VDD; The parameter configuration module (02) comprises a first NMOS transistor (MN1), a first resistor (R1), a second resistor (R2) and a first capacitor (C1); the gate of the first NMOS transistor (MN1) is connected to the first shutdown enable signal (Vctrl1), the drain of the first NMOS transistor (MN1) is connected to the node net1, the source is connected to the second resistor (R2) and the first capacitor (C1) through the first resistor (R1), one end of the second resistor (R2) and the first capacitor (C1) is connected to the source of the first NMOS transistor (MN1) through the first resistor (R1), and the other end is connected to the ground (GND); The maintenance module (03) comprises a second NMOS transistor (MN2), a third NMOS transistor (MN3), a fourth NMOS transistor (MN4), a first diode (D1) and a third resistor (R3); the anode of the first diode (D1) is connected to a node net2, the cathode is connected to a node net3, the node net3 is connected to the drain of the second NMOS transistor (MN2) and the gate of the third NMOS transistor (MN3), the source of the second NMOS transistor (MN2) is connected to the ground (GND), the gate thereof and the source of the third NMOS transistor (MN3) are connected to a node net4, the drain of the third NMOS transistor (MN3) is connected to a power supply VDD, the source of the fourth NMOS transistor (MN4) is connected to the node net4, the gate is connected to a second shutdown enable (Vctrl2), the drain is connected to the gate of the eleventh NMOS transistor (MN11) in the second leakage module (07), and the node net4 is connected to the ground (GND) through the third resistor (R3); The conduction module (04) comprises a fifth NMOS transistor (MN5), a second diode (D2), a fourth resistor (R4) and a fifth resistor (R5), wherein the drain of the fifth NMOS transistor (MN5) is connected to a power supply VDD, the gate is connected to a node net2, and the source is connected to a node net5, the anode of the second diode (D2) is connected to the node net2, and the cathode is connected to the node net5, the node net5 is connected to the node net6 through the fourth resistor (R4), and the node net6 is connected to the ground (GND) through the fifth resistor (R5); The control module (05) comprises a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7) and a sixth resistor (R6), wherein the drain of the sixth NMOS transistor (MN6) is connected to a control power supply VCC, the gate is connected to a third shutdown enable signal (Vctrl3), the source of the sixth NMOS transistor (MN6) is connected to a node net6, the drain of the seventh NMOS transistor (MN7) is connected to the node net6 via the sixth resistor (R6), the gate is connected to a fourth shutdown enable signal (Vctrl4), and the source is connected to a ground (GND); The first leakage module (06) comprises an eighth NMOS tube (MN8) and a ninth NMOS tube (MN9), wherein the drain of the eighth NMOS tube (MN8) is connected to the gate of the to-be-controlled power MOSFET (09) through a port Vgate, the gate thereof is connected to a fifth shutdown enable (Vctrl5), and the source thereof is connected to the drain of a ninth NMOS tube (MN9), the drain of the ninth NMOS tube (MN9) is connected to the source of the eighth NMOS tube (MN8), the gate thereof is connected to a sixth shutdown enable (Vctrl6), and the source thereof is connected to ground (GND); The second leakage module (07) comprises a tenth NMOS tube (MN10) and an eleventh NMOS tube (MN11), the drain of the tenth NMOS tube (MN10) being connected to the gate of the to-be-controlled power MOSFET (09) through a port Vgate, the gate thereof being connected to a node net6, the source thereof being connected to the drain of the eleventh NMOS tube (MN11), the drain of the eleventh NMOS tube (MN11) being connected to the source of the tenth NMOS tube (MN10), the gate thereof being connected to the drain of the fourth NMOS tube (MN4) in the maintaining module (03), and the source thereof being connected to a ground (GND); The external gate resistor (08) is connected between the port Vgate and the gate of the power MOSFET (09) to be controlled.

2. The adjustable wide adaptability MOSFET turn-off gate drive circuit according to claim 1, characterized in that: The current mirror module (01) is connected to the parameter configuration module (02) at a node net1, and is connected to the maintenance module (03) and the conduction module (04) at a node net2; The parameter configuration module (02) is connected to the current mirror module (01) at a node net1, and the input is a first shutdown enable signal (Vctrl1); The maintenance module (03) is connected to the current mirror module (01) at the node net2, and the input is the second shutdown enable signal (Vctrl2), and is connected to the gate of the eleventh NMOS tube (MN11) in the second leakage module (07) through the fourth NMOS (MN4); The conduction module (04) is connected to the current mirror module (01) at a node net2, and is connected to the control module (05) at a node net6; The control module (05) is connected to the conduction module (04) at a node net6, and its input end is a third shutdown enable signal (Vctrl3) and a fourth shutdown enable signal (Vctrl4), and is connected to the gate of the tenth NMOS tube (MN10) in the second leakage module (07); The first leakage module (06) is inputted with a fifth shutdown enable signal (Vctrl5) and a sixth shutdown enable signal (Vctrl6), and is connected to the second leakage module (07) at a port Vgate; The second leakage module (07) is connected to the drain of the fourth NMOS tube (MN4) in the maintaining module (03).

3. The adjustable wide adaptability MOSFET turn-off gate drive circuit according to claim 2, characterized in that: The current mirror module (01) is used to copy the current i1 of the path connected to the parameter configuration module (02) to the line connected to the maintenance module (03) in the pre-shutdown stage to form a current i2, and to increase the voltage at the node net2 during the shutdown process of the power MOSFET (09) to be controlled, so that the fifth NMOS transistor (MN5) in the conduction module (04) establishes a channel in the pre-shutdown stage, thereby enabling the conduction module (04) to work; The parameter configuration module (O2) is used to generate a current i1 in the circuit where the first NMOS tube (MN1) is located in the pre-turnoff stage of the power MOSFET (09) to be controlled according to the first turnoff enable signal (Vctrl1); The maintaining module (O3) is used to firstly increase the voltage of the node net3 and then increase the voltage of the node net4 in the pre-turnoff stage of the controlled power MOSFET (09) according to the current i2 copied by the current mirror module (01) in the pre-turnoff stage, and then transmit the voltage of the node net4 to the gate of the eleventh NMOS tube (MN11) in the second leakage module (07) through the channel of the fourth NMOS tube (MN4) through the second turnoff enable signal (Vctrl2), so that the eleventh NMOS tube (MN11) establishes a channel; The conduction module (04) is used to, in the pre-turnoff stage of the power MOSFET (09) to be controlled, be affected by the voltage of the node net2 to enable the fifth NMOS tube (MN5) to establish a channel, and at the same time, transmit the voltage of the node net2 to the node net5 through the second diode (D2), and pull the voltage of the node net5 down to the node net6 through the voltage division of the fourth resistor (R4) and the fifth resistor (R5), and transmit it to the gate of the tenth NMOS tube (MN10) in the second leakage module (07), so that the tenth NMOS tube (MN10) establishes a channel; The control module (05) is used to change the node net6 and the gate voltage of the tenth NMOS tube (MN10) in the second leakage module (07) under the control of the third shutdown enable signal (Vctrl3) and the fourth shutdown enable signal (Vctrl4) during the shutdown phase of the controlled power MOSFET (09); The first current discharge module (06) is used for, during the shutdown process of the controlled power MOSFET (09), being controlled by a fifth shutdown enable signal (Vctrl5) and a sixth shutdown enable signal (Vctrl6), to enable the eighth NMOS transistor (MN8) and the ninth NMOS transistor (MN9) to establish a channel, thereby discharging current through the port Vgate; The second leakage module (07) is used for, in the pre-turn-off phase of the power MOSFET (09) to be controlled, the eleventh NMOS tube (MN11) obtains a channel establishment voltage from the node net4 through the fourth NMOS tube (MN4), and in the turn-off phase of the power MOSFET (09) to be controlled, controls the channel opening degree of the tenth NMOS tube (MN10) through the node net6, changes the flow capacity of the tenth NMOS tube (MN10) and the eleventh NMOS tube (MN11) in the second leakage module (07), and enables the second leakage module (07) to discharge current from the port Vgate.

4. A driving method for a controllable wide-adaptability MOSFET turn-off gate drive circuit according to claim 3, characterized in that: The method includes: A method for duplicating a current i1 in a path connected to a parameter configuration module (02) in equal proportion to a line connected to a maintenance module (03) in a pre-shutdown phase to form a current i2, and raising a voltage at a node net2 during a shutdown process of a power MOSFET to be controlled (09), so that a fifth NMOS transistor (MN5) in the conduction module (04) establishes a channel in the pre-shutdown phase, thereby enabling the conduction module (04) to operate; A method for generating a current i1 in a circuit where the first NMOS tube (MN1) is located in a pre-turnoff phase of a power MOSFET (09) to be controlled according to a first turnoff enable signal (Vctrl1); A method for first raising the voltage of node net3 and then raising the voltage of node net4 in the pre-shutdown stage of a power MOSFET (09) to be controlled according to the current i2 copied by the current mirror module (01) in the pre-shutdown stage, and then transmitting the voltage of node net4 to the gate of an eleventh NMOS tube (MN11) in a second leakage module (07) through the channel of a fourth NMOS tube (MN4) by means of a second shutdown enable signal (Vctrl2), so that the eleventh NMOS tube (MN11) establishes a channel; A method for causing the fifth NMOS tube (MN5) to establish a channel under the influence of the node net2 voltage in the pre-turnoff stage of the power MOSFET (09) to be controlled, and at the same time, transferring the node net2 voltage to the node net5 through the second diode (D2), and pulling the node net5 voltage down to the node net6 through the fourth resistor (R4) and the fifth resistor (R5) voltage division, and transmitting the voltage to the gate of the tenth NMOS tube (MN10) in the second leakage module (07), so that the tenth NMOS tube (MN10) establishes a channel; A method for changing the gate voltage of a tenth NMOS tube (MN10) in a node net6 and a second leakage module (07) under the control of a third shutdown enable signal (Vctrl3) and a fourth shutdown enable signal (Vctrl4) during the shutdown phase of a power MOSFET (09) to be controlled; A method for causing an eighth NMOS transistor (MN8) and a ninth NMOS transistor (MN9) to establish a channel under the control of a fifth turn-off enable signal (Vctrl5) and a sixth turn-off enable signal (Vctrl6) during a turn-off process of a power MOSFET to be controlled, thereby discharging current through a port Vgate; A method for enabling an eleventh NMOS tube (MN11) to obtain a channel establishment voltage from a node net4 via a fourth NMOS tube (MN4) during a pre-turnoff phase of a power MOSFET (09) to be controlled, controlling the channel opening degree of a tenth NMOS tube (MN10) via a node net6 during a turnoff phase of the power MOSFET (09) to be controlled, changing the flow capacity of the tenth NMOS tube (MN10) and the eleventh NMOS tube (MN11) in a second discharge module (07), and enabling the second discharge module (07) to discharge current from a port Vgate.

5. The driving method of the adjustable wide adaptability MOSFET turn-off gate driving circuit according to claim 4, characterized in that: The first resistor (R1), the second resistor (R2), and the first capacitor (C1) in the parameter configuration module (02) are configured according to the parasitic parameters of the power MOSFET (09) to be controlled, and the voltage waveforms of the nodes net2 and net6 in the current mirror module (01) are specifically expressed as follows: During the shutdown process of the power MOSFET (09) to be controlled, when the gate voltage of the power MOSFET (09) to be controlled is higher than the Miller platform (Vmiller), a voltage peak value appears at the node net2; During the shutdown process of the power MOSFET (09) to be controlled, the voltage of the node net6 is synchronized with the voltage of the node net2. When the gate voltage of the power MOSFET (09) to be controlled is higher than the Miller platform (Vmiller), the voltage of the node net6 has a voltage peak.

6. The driving method of the adjustable wide adaptability MOSFET turn-off gate driving circuit according to claim 4, characterized in that: The voltage waveform of the node net6 is specifically expressed as follows: during the shutdown process of the power MOSFET to be controlled (09), when the gate voltage of the power MOSFET to be controlled (09) drops to the threshold voltage (Vth), the third shutdown enable signal (Vctrl3) and the fourth shutdown enable signal (Vctrl4) in the control module (05) synchronously control the sixth NMOS tube (MN6) and the seventh NMOS tube (MN7) to be turned on, thereby raising the voltage of the node net6. At this time, the voltage of the node net6 is raised and remains unchanged.

7. The driving method of a controllable wide-adaptability MOSFET turn-off gate drive circuit according to claim 4, characterized in that: The gate voltage waveform during the turn-off process of the power MOSFET (09) to be controlled is specifically expressed as follows: The first stage: when the gate voltage of the power MOSFET (09) to be controlled is higher than the Miller platform (Vmiller) voltage, the gate voltage drops rapidly to the Miller platform (Vmiller) voltage; The second stage: when the gate voltage of the power MOSFET to be controlled (09) is at the Miller platform (Vmiller) voltage, the gate voltage is maintained at the Miller platform (Vmiller) voltage; The third stage: when the gate voltage of the power MOSFET (09) to be controlled is lower than the Miller platform (Vmiller) voltage but higher than the threshold voltage (Vth), the gate voltage decreases slowly and linearly; The fourth stage: when the gate voltage of the power MOSFET (09) to be controlled is lower than the threshold voltage (Vth), the gate voltage drops rapidly to zero.

8. The driving method of a controllable wide-adaptability MOSFET turn-off gate drive circuit according to claim 4, characterized in that: During the shutdown process of the power MOSFET to be controlled (09), the gate voltage waveform of the power MOSFET to be controlled (09) is affected by the resistance and capacitance values ​​of the first resistor (R1), the second resistor (R2) and the first capacitor (C1) in the parameter configuration module (02), and the specific expression method is as follows: When the resistance and capacitance values ​​of the second resistor (R2) and the first capacitor (C1) remain unchanged, the greater the resistance value of the first resistor (R1), the slower the gate voltage of the controlled power MOSFET (09) decreases in the stage above the Miller platform (Vmiller), that is, the smaller the absolute value of the gate voltage drop slope in this stage, the longer the gate voltage is at the Miller platform (Vmiller) voltage; When the resistance and capacitance values ​​of the first resistor (R1) and the first capacitor (C1) remain unchanged, the greater the resistance value of the second resistor (R2), the shorter the time that the gate voltage of the power MOSFET (09) to be controlled is lower than the Miller platform (Vmiller) voltage, thereby shortening the turn-off time of the power MOSFET (09) to be controlled; When the resistance values ​​of the first capacitor (R1) and the second resistor (R2) remain unchanged, the smaller the capacitance value of the first capacitor (C1), the slower the gate voltage of the controlled power MOSFET (09) decreases in the stage above the Miller platform (Vmiller), that is, the smaller the absolute value of the gate voltage decrease slope in this stage.

9. The driving method of a controllable wide-adaptability MOSFET turn-off gate driving circuit according to claim 4, characterized in that: During the shutdown process of the power MOSFET to be controlled (09), the drain-source current and drain-source voltage waveforms of the power MOSFET to be controlled (09) are specifically expressed as follows: When the resistance and capacitance values ​​of the second resistor (R2) and the first capacitor (C1) remain unchanged, the greater the resistance value of the first resistor (R1), the greater the slope of the drain-source voltage of the power MOSFET (09) to be controlled, and the greater the absolute value of the slope of the drain-source current of the power MOSFET (09) to be controlled; When the resistance and capacitance values ​​of the first resistor (R1) and the first capacitor (C1) remain unchanged, the greater the resistance value of the second resistor (R2), the smaller the slope of the drain-source voltage of the power MOSFET (09) to be controlled, and the smaller the absolute value of the slope of the drain-source current of the power MOSFET (09) to be controlled; When the resistance values ​​of the first capacitor (R1) and the second resistor (R2) remain unchanged, the smaller the capacitance value of the first capacitor (C1), the smaller the slope of the drain-source voltage of the power MOSFET (09) to be controlled, and the smaller the absolute value of the slope of the drain-source current of the power MOSFET (09) to be controlled.

10. The driving method of the adjustable wide adaptability MOSFET turn-off gate driving circuit according to claim 4, characterized in that: During the shutdown process of the power MOSFET (09) to be controlled, the drive circuit does not need to introduce drain-source side information of the power MOSFET (09) to be controlled, and only utilizes the change characteristics of the transconductance capacitance of the power MOSFET (09) to control the gate voltage of the power MOSFET (09) to be controlled, and finally completes the control of the drain-source voltage and current trajectory of the power MOSFET (09) to be controlled; the drive circuit independently controls the slope of the drain-source voltage and drain-source current of the power MOSFET (09) to be controlled through the resistance and capacitance parameters in the parameter configuration module.

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