Verification method and device of large model reasoning chip, and storage medium

Abstract

The invention provides a verification method and device for a large model reasoning chip and a storage medium, and the method comprises the steps: building a simulator core state machine according to a design document of the large model reasoning chip, and building a simulator of the large model reasoning chip based on the state machine; capturing a data flow trace of each step of a model reasoning algorithm of the large model reasoning chip, and obtaining a trace file; simulating a reasoning process by using a simulator, providing model parameters by using a weight type file, comparing activation data obtained by operation under the same input in a model reasoning algorithm execution process by using an activation type file, and verifying the correctness of a data flow trace; if the data flow trace comparison succeeds, capturing trace files meeting hardware behavior simulation verification format requirements, and obtaining screened tracking files; and verifying the large model reasoning chip by using the screened tracking file as a gold standard. According to the method, the simulation effect of the large model reasoning chip behavior is improved, and the verification efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of large model reasoning chips, and specifically relates to a verification method, device, and storage medium for a large model reasoning chip. Background Art

[0002] In the design process of large model reasoning chips, verifying the correctness of chip behavior and performance analysis is an important step. However, as the complexity of large model reasoning chips increases, traditional verification methods lack efficient simulator systems to quickly verify the correctness of chip designs, and are often inefficient and unable to meet the needs of rapid iteration and optimization. Summary of the invention

[0003] In view of the deficiencies in the prior art, the present invention proposes a verification method, device, and storage medium for a large model reasoning chip. The method improves the simulation effect of the large model reasoning chip behavior and improves the efficiency of large model chip design verification.

[0004] In order to achieve the above object, the present invention provides a verification method for a large model inference chip, the method comprising:

[0005] Build the simulator core state machine based on the design documentation of the large model inference chip;

[0006] Based on the simulator core state machine, a corresponding sub-simulator is configured for each component of the large model reasoning chip, and all sub-simulators are integrated to form a simulator of the large model reasoning chip;

[0007] Capturing the data flow trace of each step of the model inference algorithm of the large model inference chip to obtain a trace file, wherein the trace file includes a weight type file and an activation type file;

[0008] Using the simulator to simulate the reasoning process of the large model reasoning chip, using the weight type file to provide model parameters, and using the activation type file to compare the activation data obtained by calculation under the same input during the execution of the model reasoning algorithm, so as to verify the correctness of the data flow trace;

[0009] If the data flow trace comparison is successful, the trace file that meets the given hardware behavior simulation verification format requirements is captured to obtain a filtered trace file;

[0010] The large model inference chip was validated using the screened trace files as the gold standard.

[0011] In one embodiment of the present invention, the step of verifying the correctness of the data flow trace includes:

[0012] Calculating the error between the activation data and the trace file array data;

[0013] The error is compared with a given threshold, and if the error does not exceed the threshold, it is determined that the data flow trace comparison is correct.

[0014] In one embodiment of the present invention, the trace file format is defined based on the .npz file format of a compressed file storing multiple arrays in NumPy;

[0015] The weight type file is configured as a separate .npz format file, and the weight type file is divided into three categories: Embedding, Weight and NormAffine according to the dimension and data type, and different key-value pairs are defined for each type of weight type file;

[0016] The activation type files are configured as a plurality of .npz format files, and the activation type files are divided into three categories, namely, Prompt, Activation and SampleResult, according to the dimension and data type, and different key-value pairs are defined for each type of activation type files.

[0017] In one embodiment of the present invention, a multi-level directory organization method is used to store the filtered tracking files, wherein the first-level directory indexes the tracking files of different groups of conversations, the second-level directory indexes the tracking files of different rounds of conversations within the same group of conversations, and the third-level directory indexes the tracking files of different words in the same round of conversations within the same group of conversations.

[0018] In one embodiment of the present invention, the Activation file of the activation type file is stored in the third-level directory, and the SampleResult file of the activation type file is stored in the third-level directory.

[0019] In one embodiment of the present invention, for the Activation file or the SampleResult file, each data of the tensor is stored in the same row and arranged in the array index from 0 to n; and a 16-bit half-precision floating point number that meets the IEEE754 standard is used to represent each array element, and 0-1 binary text is used for storage.

[0020] In one embodiment of the present invention, the large model inference chip is verified using the screened tracking file as a gold standard, which specifically includes:

[0021] According to the algorithm step of the chip during the large model inference chip simulation, the filtered tracking files are indexed in multiple directories and the file names are indexed under the directory. The 0-1 binary text string in the file is read and compared with the activation output signal of the corresponding component of the chip during the simulation process.

[0022] In one embodiment of the present invention, the method for constructing the simulator core state machine is:

[0023] Decomposing chip functions and behavioral characteristics that the simulator needs to simulate based on the design document of the large model inference chip;

[0024] Analyze the algorithm steps of the large model inference chip in detail to determine the input, output and internal processing logic of each algorithm step;

[0025] According to the input, output and internal processing logic of each algorithm step, the simulator behavior is segmented to decompose the complex simulation task into multiple subtasks;

[0026] Design the corresponding state for each subtask, and define clear entry conditions, exit conditions and state transition logic for each state;

[0027] All designed states are organized in the order of the algorithm steps to form a complete simulator core state machine.

[0028] Another aspect of the present invention further provides a verification device for a large model inference chip, the device adopts the above method, and the device comprises:

[0029] The state machine configuration module is used to build the simulator core state machine according to the design documents of the large model inference chip;

[0030] A simulator configuration module, configured to configure a corresponding sub-simulator for each component of the large model reasoning chip based on the simulator core state machine, and integrate all sub-simulators to form a simulator of the large model reasoning chip;

[0031] A trace comparison module is used to capture the data flow trace of each step of the model reasoning algorithm of the large model reasoning chip, obtain a trace file, and the trace file includes a weight type file and an activation type file; and use the simulator to simulate the reasoning process of the large model reasoning chip, use the weight type file to provide model parameters, and use the activation type file to compare the activation data obtained by calculation under the same input during the execution of the model reasoning algorithm to verify the correctness of the data flow trace;

[0032] A trace capture module, for capturing the trace file that meets the given hardware behavior simulation verification format requirements if the data stream trace comparison is successful, to obtain a filtered trace file;

[0033] The verification module is used to verify the large model inference chip by using the screened tracking file as a gold standard.

[0034] Another aspect of the present invention provides a computer-readable storage medium, characterized in that a computer program is stored therein, and when the computer program is executed by a processor, the steps of the verification method of the large model inference chip are implemented.

[0035] It can be seen from the above scheme that the advantages of the present invention are:

[0036] The verification method of the large model inference chip disclosed by the present invention is based on the data flow trace comparison technology of the large model inference chip, captures the data flow trace of each step of the model inference algorithm of the large model inference chip, obtains the trace file, and uses the weight type file to provide the model parameters in the simulator simulating the inference process of the large model inference chip, and uses the activation type file to compare the activation data obtained by calculation under the same input during the execution of the model inference algorithm to verify the correctness of the data flow trace; and based on the data flow trace capture technology of the large model inference chip, when the data flow trace comparison is successful, the trace file that meets the given hardware behavior simulation verification format requirements is captured to obtain the screened tracking file, and then the screened tracking file is used as the gold standard to verify the large model inference chip. This method realizes the simulation effect of the behavior of the large model inference chip at the cycle level accuracy. Based on the data flow trace comparison technology, the behavioral correctness verification of the large model reasoning chip architecture design is accelerated in the large model reasoning chip software simulator, thereby improving the efficiency of aligning the large model reasoning chip simulator behavior with the existing large model reasoning behavior; at the same time, the invention provides fine-grained gold standard data flow traces at each step level of the reasoning algorithm for the large model reasoning chip behavior simulation verification based on the data flow trace capture technology, thereby improving the efficiency of large model chip design verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 The overall flow chart of the verification method of the large model inference chip provided by one embodiment of the present invention is shown;

[0038] Figure 2 A schematic structural diagram of a verification device for a large model inference chip provided in one embodiment of the present invention is shown.

[0039] in:

[0040] 200: verification device of large model reasoning chip;

[0041] 201: state machine configuration module;

[0042] 202: simulator configuration module;

[0043] 203: trace comparison module;

[0044] 204: trace capture module;

[0045] 205: Verification module. DETAILED DESCRIPTION

[0046] In order to make the above features and effects of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

[0047] See also Figure 1 , Figure 1 The overall flow chart of the verification method of the large model reasoning chip provided by one embodiment of the present invention is shown. The verification method of the large model reasoning chip comprises the following steps:

[0048] Step S1, build a simulator core state machine according to the design document of the large model inference chip.

[0049] In one embodiment, specifically, according to the design document of the large model reasoning chip, the chip functions and behavioral characteristics that the simulator needs to simulate are decomposed. The algorithm steps of the large model reasoning chip are analyzed in detail to determine the input, output and internal processing logic of each algorithm step; then, according to the input, output and internal processing logic of each algorithm step, the simulator behavior is segmented to decompose the complex simulation task into multiple simple subtasks. For example, in one embodiment, the simulator behavior is segmented in chronological order to form multiple time slices, each of which corresponds to the execution of one or more algorithm steps. For each subtask, a corresponding state is designed, and clear entry conditions, exit conditions and state transition logic are defined for each state; and all designed states are organized in the order of the algorithm steps to form a complete simulator core state machine. In addition, when designing the state machine, it is also necessary to consider and handle possible abnormal situations, such as data errors, invalid instructions, etc., to ensure that the simulator can respond and recover correctly under abnormal circumstances. The designed simulator core state machine is verified and tested to ensure that it can correctly simulate the behavior of the large model reasoning chip under various circumstances.

[0050] Step S2: Based on the simulator core state machine, a corresponding sub-simulator is configured for each component of the large model reasoning chip, and all sub-simulators are integrated to form a simulator of the large model reasoning chip.

[0051] In one embodiment, the design document of the large model reasoning chip contains the specifications, connection methods, clock frequencies, delay parameters, etc. of each component of the large model reasoning chip, as well as the direct interface protocols and communication methods of each component. Based on the design of the core state machine of the simulator, the simulator is designed as a modular structure, and each module corresponds to a component in the chip. That is, a corresponding sub-simulator is configured for each component of the large model reasoning chip to simulate the behavior of the component. The sub-simulator corresponding to each component should be able to respond to the control signal of the state machine, and implement clock cycle-level simulation in the simulator to accurately calculate the delay of each operation, ensuring that the cycle-level delay is consistent with the design document. At the same time, an event-driven mechanism is used to simulate the interaction between components. When an event occurs, the simulation operation of the corresponding component is triggered. Finally, all sub-simulators are integrated to form a simulator of the large model reasoning chip.

[0052] In this embodiment, the behavioral simulation of the large model reasoning chip is implemented at cycle-level accuracy, which can be used for correctness verification and performance analysis of the large model reasoning chip design.

[0053] Step S3, capture the data flow trace of each step of the model inference algorithm of the large model inference chip, and obtain the trace file, wherein the trace file includes a weight type file and an activation type file.

[0054] In this embodiment, the existing large model is inferred using an existing framework, and the data flow traces of each step of the model inference algorithm of the large model inference chip are captured to obtain a trace file. In this process, the data flow trace is captured according to the data flow of the existing large model neural network inference process, so that the simulator can complete the preliminary verification of the correctness of the behavior of the large model inference chip at the data flow level. Specifically, in this process, the trace file format designed using the data flow trace comparison technology is defined to obtain the trace file. Specifically, trace files are mainly divided into two categories: weight type files and activation type files. Among them, the weight type file is used to store the specific parameters of the model after training, and the activation type file is used to store the activation data generated by each step of the model inference operation when the input is given during the inference process; the trace file generated by this step will be stored in the form of a compressed file based on NumPy to store multiple arrays.

[0055] For the comparison of data flow traces based on large model inference chips, in one embodiment, the format of the inference data flow trace file captured by the inference process implemented on the Python side based on the existing model inference framework is defined. Specifically, based on the .npz file format of the compressed file that stores multiple arrays in NumPy, the format of the trace file obtained by this process is defined. During the model inference process, each data flow trace will be searched for a compressed file with the suffix .npz in the form of a key-value pair through a string key named npz_key.

[0056] For the weight type file, it is configured as a separate .npz format file, and the weight type file is divided into three categories according to the dimension and data type: Embedding, Weight and NormAffine, and different key-value pairs are defined for each type of weight type file. As shown in the following Table 1, Table 1 shows the naming rules of the weight type file.

[0057] Table 1 Naming rules for weight type files

[0058]

[0059] For activation type files, the activation type files are configured as multiple .npz format files, each file represents a group of conversations, and different types of activation data are distinguished using different npz_keys within each group of conversations. Similarly, the activation type files are divided into three categories according to the dimension and data type: Prompt, Activation, and SampleResult, and different key-value pairs are defined for each type of activation type file. Specifically, as shown in the following Table 2, Table 2 shows the naming rules of the activation type files.

[0060] Table 2 Naming rules for activation type files

[0061]

[0062]

[0063] Step S4, using the simulator to simulate the reasoning process of the large model reasoning chip, using the weight type file to provide model parameters, and using the activation type file to compare the activation data obtained under the same input during the execution of the model reasoning algorithm to verify the correctness of the data flow trace.

[0064] In this process, in one embodiment, the error between the activation data and the trace file array data is calculated; the error is compared with a given threshold, and if the error does not exceed the threshold, it is determined that the data flow trace comparison is correct.

[0065] Step S5: If the data flow trace comparison is successful, the trace file that meets the given hardware behavior simulation verification format requirements is captured to obtain a filtered trace file, otherwise step S3 is re-executed to iteratively modify the simulator.

[0066] In this embodiment, if the data flow trace comparison is successful, the trace file that meets the given hardware behavior simulation verification format requirements is captured to obtain a filtered trace file. In this process, according to the existing large model neural network reasoning process data flow trace, the calculation results of the reasoning chip at each stage of the reasoning algorithm are captured, and the large model reasoning chip verification provides a data flow trace that can be read by the verification end, that is, the filtered trace file. Specifically, the trace file format used by the data flow trace capture technology is used to define the filtered trace file during the capture process. This step will adopt a multi-level directory storage design for the filtered trace file according to different groups of conversations, different rounds of conversations in the same group, and different words in the same round. The first-level directory indexes the trace files (Conversation ID) of different groups of conversations, the second-level directory indexes the trace files (Turn ID) of different rounds of conversations in the same group of conversations, and the third-level directory indexes the trace files (Token ID) of different words in the same round of conversations in the same group of conversations. The third-level directory contains two types of trace files, the first type of file is the Activation file of the activation type file (for example, activation_x_x_xxx.txt), and the second type is the SampleResult file (sample_result.txt). In this embodiment, for the naming of the activation type trace file Activation file and SampleResult file, the word element index and the algorithm step information in the inference algorithm such as the number of layers, calculation type, etc. are added to enhance the recognition of the activation type data flow trace file name. All trace files captured in this step use 0-1 binary text strings to densely store the data in the array.

[0067] Specifically, each activation file stores only one tensor's data. For the nth round of dialogue, all activation data in this round of dialogue are stored in the same directory. The details are shown in Table 3, which shows the naming rules of the activation file.

[0068] Table 3 Naming rules for activation files

[0069]

[0070]

[0071] For the case where trace_log_level is 0 (i.e., the format for verilog reading), each data of the Activation file tensor is stored in the same row and arranged tightly. For the data in a row, the array index is arranged from 0 to n. And each array element is represented by a 16-bit half-precision floating point number that meets the IEEE 754 standard, and stored using 0-1 binary text. It should be noted that the direction of the beginning of each row is MSB (MostSignificant Bit), and the direction of the end of the row is LSB (Last Significant Bit).

[0072] For the SampleResult file of the activation type file, for each round of dialogue, the sample data corresponding to each token of the round of dialogue is stored in the third-level directory of the corresponding token. For the nth token of each round of dialogue, the file name is fixed as sample_n.txt, where n is an Arabic numeral of 1, 2, ..., k. Each line in the file represents a 64-bit data, and each data is stored using 64 0-1 character texts. The specific storage arrangement rules are the same as those defined in the above Activation file.

[0073] Step S6: Use the screened tracking file as the gold standard to verify the large model inference chip.

[0074] In this embodiment, the filtered tracking file is finally used as the gold standard to verify the large model reasoning chip. Specifically, the filtered tracking file is indexed in multiple directories according to the algorithm step of the chip during the simulation of the large model reasoning chip, and the file name is indexed in the directory, and the 0-1 binary text string in the file is read and compared with the activation output signal of the corresponding component of the chip during the simulation process.

[0075] In summary, the verification method of the large model inference chip disclosed by the present invention is based on the data flow trace comparison technology of the large model inference chip, captures the data flow trace of each step of the model inference algorithm of the large model inference chip, obtains the trace file, and uses the weight type file to provide the model parameters in the simulator to simulate the inference process of the large model inference chip, and uses the activation type file to compare the activation data obtained by calculation under the same input during the execution of the model inference algorithm to verify the correctness of the data flow trace; and based on the data flow trace capture technology of the large model inference chip, when the data flow trace comparison is successful, the trace file that meets the given hardware behavior simulation verification format requirements is captured to obtain the screened trace file, and then the screened trace file is used as the gold standard to verify the large model inference chip. This method realizes the simulation effect of the behavior of the large model inference chip at the cycle level accuracy. Based on the data flow trace comparison technology, the behavioral correctness verification of the large model reasoning chip architecture design is accelerated in the large model reasoning chip software simulator, thereby improving the efficiency of aligning the large model reasoning chip simulator behavior with the existing large model reasoning behavior; at the same time, the invention provides fine-grained gold standard data flow traces at each step level of the reasoning algorithm for the large model reasoning chip behavior simulation verification based on the data flow trace capture technology, thereby improving the efficiency of large model chip design verification.

[0076] In addition, it should be noted that the verification method of the large model inference chip disclosed in the present invention is not limited to being executed in the order of the above steps S1-S6, and the steps can be reordered, added or deleted. For example, the steps recorded in the present invention can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solution of the present invention can be achieved, the present invention is not limited here.

[0077] In addition, corresponding to the embodiment of the verification method of the aforementioned large model reasoning chip, the present invention also provides an embodiment of the verification device of the large model reasoning chip.

[0078] See also Figure 2 , a verification device 200 of a large model inference chip provided by an embodiment of the present invention, the device at least comprises:

[0079] The state machine configuration module 201 is used to build the simulator core state machine according to the design document of the large model inference chip.

[0080] The simulator configuration module 202 is used to configure a corresponding sub-simulator for each component of the large model reasoning chip based on the simulator core state machine, and integrate all sub-simulators to form a simulator of the large model reasoning chip.

[0081] The trace comparison module 203 is used to capture the data flow trace of each step of the model reasoning algorithm of the large model reasoning chip, obtain the trace file, and the trace file includes a weight type file and an activation type file. And, the simulator is used to simulate the reasoning process of the large model reasoning chip, the weight type file is used to provide model parameters, and the activation type file is used to compare the activation data obtained by calculation under the same input during the execution of the model reasoning algorithm to verify the correctness of the data flow trace.

[0082] The trace capture module 204 is used to capture the trace file that meets the given hardware behavior simulation verification format requirements if the data flow trace comparison is successful, and obtain a filtered trace file.

[0083] The verification module 205 is used to verify the large model inference chip using the screened tracking file as a gold standard.

[0084] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of each module of the described device can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0085] According to an embodiment of the present invention, the present invention also provides a machine-readable medium, which may be a tangible medium, which may contain or store a program for use by an instruction execution system, apparatus or device or used in conjunction with an instruction execution system, apparatus or device, and the computer program, when executed by a processor, implements the steps of the above-mentioned large model reasoning chip verification method.

[0086] In addition, the machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the above. More specific examples of machine-readable storage media may include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above.

[0087] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A verification method for a large model inference chip, characterized in that: The method includes: Build the simulator core state machine based on the design documentation of the large model inference chip; Based on the simulator core state machine, a corresponding sub-simulator is configured for each component of the large model reasoning chip, and all sub-simulators are integrated to form a simulator of the large model reasoning chip; Capturing the data flow trace of each step of the model inference algorithm of the large model inference chip to obtain a trace file, wherein the trace file includes a weight type file and an activation type file; Using the simulator to simulate the reasoning process of the large model reasoning chip, using the weight type file to provide model parameters, and using the activation type file to compare the activation data obtained by calculation under the same input during the execution of the model reasoning algorithm, so as to verify the correctness of the data flow trace; If the data flow trace comparison is successful, the trace file that meets the given hardware behavior simulation verification format requirements is captured to obtain a filtered trace file; The large model inference chip was validated using the screened trace files as the gold standard.

2. The method according to claim 1, characterized in that The steps of verifying the correctness of the data flow trace include: Calculating the error between the activation data and the trace file array data; The error is compared with a given threshold, and if the error does not exceed the threshold, it is determined that the data flow trace comparison is correct.

3. The method according to claim 1, characterized in that Based on the compressed file .npz file format of NumPy storing multiple arrays, the trace file format is defined; The weight type file is configured as a separate .npz format file, and the weight type file is divided into three categories: Embedding, Weight and NormAffine according to the dimension and data type, and different key-value pairs are defined for each type of weight type file; The activation type files are configured as a plurality of .npz format files, and the activation type files are divided into three categories, namely, Prompt, Activation and SampleResult, according to the dimension and data type, and different key-value pairs are defined for each type of activation type files.

4. The method according to claim 3, characterized in that The filtered trace files are stored in a multi-level directory organization method, where the first-level directory indexes the trace files of different groups of dialogues, the second-level directory indexes the trace files of different rounds of dialogues in the same group of dialogues, and the third-level directory indexes the trace files of different words in the same round of dialogues in the same group of dialogues.

5. The method according to claim 4, characterized in that The Activation file of the activation type file is stored in the third-level directory, and the SampleResult file of the activation type file is stored in the third-level directory.

6. The method according to claim 5, characterized in that For the Activation file or the SampleResult file, each data of the tensor is stored in the same row and arranged in the array index from 0 to n; and each array element is represented by a 16-bit half-precision floating point number that meets the IEEE 754 standard and stored using 0-1 binary text.

7. The method according to claim 5, characterized in that Using the screened tracking files as the gold standard, the large model inference chip is verified, specifically including: According to the algorithm step of the chip during the large model inference chip simulation, the filtered tracking files are indexed in multiple directories and the file names are indexed under the directory. The 0-1 binary text string in the file is read and compared with the activation output signal of the corresponding component of the chip during the simulation process.

8. The method according to claim 1, characterized in that The method for constructing the simulator core state machine is: Decomposing chip functions and behavioral characteristics that the simulator needs to simulate based on the design document of the large model inference chip; Analyze the algorithm steps of the large model inference chip in detail to determine the input, output and internal processing logic of each algorithm step; According to the input, output and internal processing logic of each algorithm step, the simulator behavior is segmented to decompose the complex simulation task into multiple subtasks; Design the corresponding state for each subtask, and define clear entry conditions, exit conditions and state transition logic for each state; All designed states are organized in the order of the algorithm steps to form a complete simulator core state machine.

9. A verification device for a large model inference chip, characterized in that: The device includes: The state machine configuration module is used to build the simulator core state machine according to the design documents of the large model inference chip; A simulator configuration module, configured to configure a corresponding sub-simulator for each component of the large model reasoning chip based on the simulator core state machine, and integrate all sub-simulators to form a simulator of the large model reasoning chip; A trace comparison module is used to capture the data flow trace of each step of the model reasoning algorithm of the large model reasoning chip, obtain a trace file, and the trace file includes a weight type file and an activation type file; and use the simulator to simulate the reasoning process of the large model reasoning chip, use the weight type file to provide model parameters, and use the activation type file to compare the activation data obtained by calculation under the same input during the execution of the model reasoning algorithm to verify the correctness of the data flow trace; A trace capture module, for capturing the trace file that meets the given hardware behavior simulation verification format requirements if the data stream trace comparison is successful, to obtain a filtered trace file; The verification module is used to verify the large model inference chip by using the screened tracking file as a gold standard.

10. A computer-readable storage medium, characterized in that: A computer program is stored, which, when executed by a processor, implements the steps of the verification method for the large model reasoning chip described in any one of claims 1-8.

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