Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing two wafers to be mixed and bonded; forming a bonding layer; etching the metal layer of the first wafer to enable the surface of the metal layer to be lower than the surface of the dielectric layer; forming a nano bridge metal layer on the surface of the metal layer of the first wafer; forming a nano bridge dielectric layer; bonding the first wafer and the second wafer; leading out a metal connecting piece; and applying voltage by using the metal connecting pieces so as to conduct the nano-bridge dielectric layer between the metal layers. According to the invention, the nanometer bridge structure is formed in the metal bonding area of the first wafer and the second wafer, so that metal bonding is realized by using the nanometer bridge structure under a power-on condition, metal layers do not need to be bonded by using annealing thermal expansion, and the height of the metal layers relative to a dielectric layer and the surface pattern of the metal layers do not need to be strictly controlled; and high-temperature annealing is not needed, so that the process difficulty is reduced, the performance of the device is ensured, and the problems of high difficulty and influence on the performance of the device in the existing mixed bonding process method are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor ultra-large-scale integrated circuits, existing technical processes have reached their physical limits. Driven by the goal of further miniaturization and multifunctionality of electronic products, other new technologies, new materials, and new technologies have been explored, including three-dimensional stacking packaging technology. Three-dimensional stacking packaging technology uses wafer bonding technology to stack silicon wafers to achieve metal interconnection on a three-dimensional level, thereby reducing the interconnection distance. It can effectively increase transmission speed, reduce device size, and provide the possibility of heterogeneous structure integration. Currently commonly used wafer bonding technologies include silicon-silicon bonding, copper-copper bonding, hybrid bonding, etc. Among them, hybrid bonding can not only provide metal interconnection structure, but also provide mechanical support. It is one of the key technologies of three-dimensional stacking packaging technology.

[0003] At present, the commonly used hybrid bonding process is roughly as follows: first, a hybrid bonding surface with both a dielectric layer and a metal layer is formed on the wafer using a bonding layer deposition and patterning process, wherein the surface height of the metal layer is lower than the surface of the dielectric layer; then, a pre-bonding process is used to temporarily bond the dielectric layers of the two wafers to be bonded through van der Waals forces and hydrogen bonds; finally, an annealing process is used to form chemical bonds between the dielectric layers; at the same time, the metal layer is lifted up due to thermal expansion, causing the metal layers of the two wafers to be bonded to contact and fuse with each other, forming an electrical connection.

[0004] However, existing hybrid bonding processes have strict requirements on the height of the metal layer's recess relative to the dielectric layer. If the metal layer's surface is too low, thermal expansion prevents the metal layers of the two wafers from contacting and fusing, resulting in a short circuit. If the metal layer's surface is flush with the dielectric layer, or even higher than the dielectric layer, thermal expansion can cause significant stress where the metal layers of the two wafers fuse, potentially lifting the surrounding dielectric layer and affecting interconnect reliability. Furthermore, given that the thermal expansion of the metal layer is related to its size, the metal pad pattern parameters used for bonding must remain consistent to facilitate process control of bonding quality, resulting in limited design flexibility. Furthermore, to ensure reliable bonding between the metal layers of the two wafers, the currently used annealing process typically requires temperatures exceeding 400°C. This temperature degrades device performance for most semiconductor devices, particularly those at advanced process nodes, such as SRAM (static random access memory), impacting product performance. Summary of the Invention

[0005] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to solve the problem that the existing hybrid bonding process is difficult and affects the performance of the device.

[0006] To solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising: Providing two wafers to be hybrid-bonded, respectively denoted as a first wafer and a second wafer, wherein the first wafer and the second wafer both include a substrate and a device functional layer formed from bottom to top; forming a bonding layer on the surfaces of the device functional layers of the first wafer and the second wafer, wherein the dielectric layer and the metal layer are exposed on the surface of the bonding layer; Etching the metal layer of the first wafer so that the surface of the metal layer is lower than the surface of the dielectric layer; forming a nanobridge metal layer on the surface of the metal layer of the first wafer; forming a nanobridge dielectric layer on a surface of the first wafer; Place the nanobridge dielectric layer of the first wafer toward the bonding layer of the second wafer and perform bonding; Leading out metal connectors on the substrate surface of the first wafer; A voltage is applied to the metal layers using metal connectors to make the nanobridge dielectric layers between the metal layers conductive.

[0007] Optionally, in the method for manufacturing a semiconductor device, the method for forming bonding layers on the surfaces of the device functional layers of the first wafer and the second wafer includes: forming a dielectric layer on a surface of the device functional layer; forming a first through hole in the dielectric layer, wherein the first through hole exposes the metal structure in the device functional layer; The first through hole is filled to form a metal layer.

[0008] Optionally, in the method for manufacturing a semiconductor device, the method for forming a nanobridge metal layer on the surface of the metal layer of the first wafer includes: forming a nanobridge metal layer on the bonding layer surface of the first wafer using a physical vapor deposition process, wherein the nanobridge metal layer is made of ruthenium; Chemical mechanical polishing is used to remove the nanobridge metal layer on the surface of the dielectric layer of the first wafer, and the surface of the dielectric layer is made flush with the surface of the nanobridge metal layer.

[0009] Optionally, in the method for manufacturing a semiconductor device, the method for forming a nanobridge dielectric layer on the surface of the first wafer includes: A nanobridge dielectric layer is formed on the surface of the first wafer by using an atomic layer deposition process, wherein the material of the nanobridge dielectric layer is hafnium oxide.

[0010] Optionally, in the method for manufacturing a semiconductor device, the method of placing the nanobridge dielectric layer of the first wafer toward the bonding layer of the second wafer and performing bonding includes: Pre-treating the surface of the nanobridge dielectric layer of the first wafer and the surface of the bonding layer of the second wafer; Flipping the first wafer and aligning and pre-bonding it with the second wafer; The pre-bonded first wafer and the second wafer are subjected to low temperature annealing.

[0011] Optionally, in the method for manufacturing a semiconductor device, the pretreatment method includes plasma bombardment treatment or wet treatment.

[0012] Optionally, in the method for manufacturing a semiconductor device, the temperature of the low-temperature annealing does not exceed 250°C.

[0013] Optionally, in the method for manufacturing a semiconductor device, the method for leading out a metal connector on the substrate surface of the first wafer includes: reducing the thickness of the substrate of the first wafer; forming a second through hole on the substrate of the first wafer, wherein the second through hole exposes the metal structure in the device functional layer; The second through hole is filled to form a metal connector.

[0014] In order to solve the above technical problems, the present invention also provides a semiconductor device, which is manufactured using the manufacturing method of a semiconductor device as described in any of the above items, and the semiconductor device includes a second substrate, a second device functional layer, a second bonding layer, a nanobridge dielectric layer, a first bonding layer, a first device functional layer and a first substrate formed in sequence from bottom to top; a metal connector is formed in the first substrate, and the metal connector is connected to the metal structure of the first device functional layer; the first bonding layer includes a stacked first metal layer and a nanobridge metal layer, and the nanobridge metal layer is connected to the nanobridge dielectric layer; the second bonding layer includes a second metal layer, and the nanobridge dielectric layer between the nanobridge metal layer and the second metal layer is turned on when voltage is applied.

[0015] Optionally, in the semiconductor device, the first metal layer and the second metal layer are made of copper; the nanobridge dielectric layer is made of hafnium oxide; and the nanobridge metal layer is made of ruthenium.

[0016] The semiconductor device and manufacturing method provided by the present invention include: providing two wafers to be mixed and bonded, respectively denoted as a first wafer and a second wafer, wherein the first wafer and the second wafer both include a substrate and a device functional layer formed from bottom to top; forming a bonding layer on the surface of the device functional layer of the first wafer and the second wafer, wherein a dielectric layer and a metal layer are exposed on the surface of the bonding layer; etching the metal layer of the first wafer so that the surface of the metal layer is lower than the surface of the dielectric layer; forming a nanobridge metal layer on the surface of the metal layer of the first wafer; forming a nanobridge dielectric layer on the surface of the first wafer; aligning the nanobridge dielectric layer of the first wafer toward the bonding layer of the second wafer and bonding them; leading out a metal connector on the substrate surface of the first wafer; and applying a voltage to the metal layer using the metal connector to make the nanobridge dielectric layer between the metal layers conductive. By forming a nanobridge structure in the metal bonding area of ​​the first wafer and the second wafer, metal bonding is achieved by utilizing the nanobridge structure when power is applied. There is no need to utilize annealing thermal expansion to bond the metal layers, and therefore there is no need to strictly control the height of the metal layer relative to the dielectric layer and the surface pattern of the metal layer, nor is there any need to use high-temperature annealing. This not only reduces the process difficulty but also ensures device performance, solving the problem that the existing hybrid bonding process method is difficult and affects device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A flow chart of a method for manufacturing a semiconductor device provided in this embodiment; 2(A) to 2(J) are schematic structural diagrams of the semiconductor device provided by this embodiment at various steps; The descriptions of the reference numerals are as follows: 100 - first substrate; 110 - first device functional layer; 111 - first metal structure; 120 - first dielectric layer; 121 - first through hole in the first dielectric layer; 130 - first metal layer; 140 - nanobridge metal layer; 150 - nanobridge dielectric layer; 151 - nanobridge dielectric layer when voltage is applied; 160 - third dielectric layer; 161 - metal pattern; 170 - metal connector; 200 - second substrate; 210 - second device functional layer; 211 - second metal structure; 220 - second dielectric layer; 221 - first through hole in the second dielectric layer; 230 - second metal layer. DETAILED DESCRIPTION

[0018] The semiconductor device and its manufacturing method proposed in the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not in precise proportions. They are only used to conveniently and clearly assist in illustrating the purpose of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to show different focuses and sometimes use different proportions.

[0019] It should be noted that the terms "first", "second", etc. in the specification, claims, and accompanying drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, and are not used to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or are inherent to these processes, methods, products, or apparatuses.

[0020] The metal nanobridge structure is a new type of programmable structure whose on and off states can be changed by applying voltage. The basic structure of a metal nanobridge is a sandwich structure: the middle layer is a special dielectric material, such as hafnium oxide (HfO2); the upper and lower metal electrodes are made of different metals, such as copper (Cu) and ruthenium (Ru), respectively. When a positive voltage is applied to the Cu end, a nanoscale path is formed in the middle dielectric layer, resulting in a conductive state. When no voltage is applied to the Cu end, the initial insulating state is restored.

[0021] Based on this, this embodiment provides a method for manufacturing a semiconductor device, such as Figure 1 Shown, including: S1, providing two wafers to be hybrid-bonded, respectively denoted as a first wafer and a second wafer, wherein the first wafer and the second wafer both include a substrate and a device functional layer formed from bottom to top; S2, forming a bonding layer on the surfaces of the device functional layers of the first wafer and the second wafer, wherein the dielectric layer and the metal layer are exposed on the surface of the bonding layer; S3, etching the metal layer of the first wafer so that the surface of the metal layer is lower than the surface of the dielectric layer; S4, forming a nanobridge metal layer on the surface of the metal layer of the first wafer; S5, forming a nanobridge dielectric layer on the surface of the first wafer; S6, aligning the nanobridge dielectric layer of the first wafer toward the bonding layer of the second wafer and performing bonding; S7, leading out metal connectors on the substrate surface of the first wafer; S8, using metal connectors to apply voltage to the metal layers to make the nanobridge dielectric layer between the metal layers conductive.

[0022] The manufacturing method of the semiconductor device provided in this embodiment forms a nanobridge metal layer on the surface of the metal layer of the first wafer and forms a nanobridge dielectric layer on the surface of the first wafer, so that the nanobridge metal layer, the nanobridge dielectric layer and the metal layer of the second wafer form a nanobridge structure, thereby utilizing the nanobridge structure to achieve metal bonding when power is applied, eliminating the need to utilize annealing thermal expansion to bond the metal layers, and further eliminating the need to strictly control the height of the metal layer relative to the dielectric layer and the surface pattern of the metal layer, and eliminating the need to use high-temperature annealing. This not only reduces the process difficulty but also ensures device performance, thereby solving the problem that the existing hybrid bonding process method is difficult and affects device performance.

[0023] Specifically, in this embodiment, in step S1, two wafers to be hybrid-bonded are provided, which are respectively denoted as a first wafer and a second wafer. The first wafer and the second wafer both include a substrate and a device functional layer formed from bottom to top.

[0024] In actual applications, the wafer to be hybrid bonded is formed with a device functional layer on the substrate through conventional front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. The device functional layer may include structures such as transistors, capacitors, resistors, and metal interconnects.

[0025] In this embodiment, the specific structure and process of the device functional layer in the wafer to be hybrid-bonded are not limited, and only the parts related to the present application solution are illustrated and described.

[0026] As shown in Figure 2 (A), the first wafer includes a substrate (first substrate) 100 and a device functional layer (first device functional layer) 110, wherein the first device functional layer 110 includes a metal structure (first metal structure) 111; similarly, the second wafer includes a substrate (second substrate) 200 and a device functional layer (second device functional layer) 210, wherein the second device functional layer 210 includes a metal structure (second metal structure) 211.

[0027] Furthermore, in this embodiment, step S2, the method of forming a bonding layer on the surfaces of the device functional layers of the first wafer and the second wafer includes: S21, forming a dielectric layer on the surface of the device functional layer.

[0028] Specifically, as shown in FIG2(B), dielectric layers are deposited on the first wafer and the second wafer, respectively, to form a first dielectric layer 120 on the surface of the first device functional layer 110, and a second dielectric layer 220 on the surface of the second device functional layer 210. The dielectric layer can be made of silicon oxide, or a stacked structure of silicon oxide and nitrogen oxide.

[0029] S22 , forming a first through hole in the dielectric layer, wherein the first through hole exposes the metal structure in the device functional layer.

[0030] Specifically, as shown in FIG2 (C), the areas to be through-holes are planned on the surfaces of the dielectric layers of the first wafer and the second wafer respectively using photoresist, and then the first through-holes are formed on the areas to be through-holes using an etching process, thereby forming the first through-holes 121 on the first dielectric layer 120 and the first through-holes 211 on the second dielectric layer 210, wherein the bottom of the first through-holes 121 on the first dielectric layer 120 exposes the first metal structure 111, and the bottom of the first through-holes 221 on the second dielectric layer 220 exposes the second metal structure 211.

[0031] S23 , filling the first through hole to form a metal layer.

[0032] Specifically, as shown in Figure 2(D), a copper diffusion barrier layer physical vapor deposition (PVD) process can be performed in the first through-hole to form a barrier layer on the surface of the first through-hole. The barrier layer can be made of tantalum nitride (TaN) or tantalum (Ta). Then, the first through-hole is filled with metal using an electroplating process. The metal can be made of copper (Cu). Finally, a chemical mechanical polishing (CMP) process is used to polish the metal surface formed in the first through-hole until it is flush with the dielectric layer. At this point, the bonding layer of the first wafer includes a first dielectric layer 120 and a first metal layer 130, and the bonding layer of the second wafer includes a second dielectric layer 220 and a second metal layer 230.

[0033] In this way, the bonding layer is formed with a metal layer in the area to be bonded and a dielectric layer in other areas, and the metal layer and the dielectric layer are flush. Since the method for manufacturing a semiconductor device provided in this embodiment does not need to strictly control the height difference between the metal layer and the dielectric layer in the bonding layer, the process difficulty is effectively reduced.

[0034] In practical applications, the specific implementation method of step S2 can adopt the existing process method for forming a bonding layer, such as a conventional dual damascene process, which will not be described in detail in this application.

[0035] Furthermore, in this embodiment, in step S3 , the metal layer of the first wafer is etched so that the surface of the metal layer is lower than the surface of the dielectric layer.

[0036] Specifically, as shown in FIG2(E), a chemical mechanical polishing (CMP) process is used to make the surface of the first metal layer 130 lower than the surface of the first dielectric layer 120. Thus, by controlling the CMP process, the polishing speed of the first metal layer 130 can be increased while the polishing speed of the first dielectric layer 120 can be decreased. As a result, the surface of the first metal layer 130 is lower than the surface of the first dielectric layer 120, forming a concave topography.

[0037] In actual application, it is not necessary to strictly control the height difference between the surface of the first metal layer 130 and the surface of the first dielectric layer 120, thereby reducing the difficulty of the process. Generally, the height difference between the two can be around 20 nm.

[0038] Furthermore, in this embodiment, in step S4 , a nanobridge metal layer is formed on the surface of the metal layer of the first wafer.

[0039] Specifically, in this embodiment, a physical vapor deposition (PVD) process may be used to form the nanobridge metal layer 140 on the surface of the first metal layer 130 , wherein the material of the nanobridge metal layer 140 is ruthenium.

[0040] Typically, the nanobridge metal layer 140 only needs to fill the recess in the first metal layer 130. However, considering that the thickness of the formed nanobridge metal layer 140 after physical vapor deposition may be higher than the first dielectric layer 120, or even cover part of the first dielectric layer 120, chemical mechanical polishing (CMP) can be used after physical vapor deposition to remove the nanobridge metal layer 140 on the surface of the first dielectric layer 120 and make the surface of the first dielectric layer 120 flush with the surface of the nanobridge metal layer 140. The structure of the semiconductor device thus formed is shown in Figure 2(F).

[0041] In practical applications, the material of the nanobridge metal layer 140 can also be other metals, and usually needs to be different from the material of the second metal layer 230 to be bonded to the second wafer to form a stable metal nanobridge structure. The material selection of the nanobridge metal layer 140 is not limited in this application.

[0042] Furthermore, in this embodiment, in step S5 , a nanobridge dielectric layer is formed on the surface of the first wafer.

[0043] Specifically, in this embodiment, an atomic layer deposition process is used to form a nanobridge dielectric layer 150 on the surface of the first wafer. The material of the nanobridge dielectric layer 150 is hafnium oxide (HfO2). The resulting semiconductor device structure is shown in Figure 2(G). In this way, the atomic layer deposition process can form a nanobridge dielectric layer 150 with high thickness uniformity and surface flatness on the surfaces of the first dielectric layer 120 and the nanobridge metal layer 140.

[0044] In other embodiments, other deposition processes may be used to form the nanobridge dielectric layer 150, and surface planarization may be performed to increase the surface thickness and flatness of the nanobridge metal layer 140. The present application does not limit the specific process for forming the nanobridge metal layer 140.

[0045] In practical applications, the material of nanobridge dielectric layer 150 can also be other semiconductor materials. Generally, it is required to be able to form a path when conducting electricity after bonding with the metal at both ends, and to restore insulation after power is disconnected, so as to form a stable metal nanobridge structure. The material selection of nanobridge dielectric layer 150 is not limited in this application.

[0046] Furthermore, in this embodiment, in step S6, the method of aligning the nanobridge dielectric layer of the first wafer toward the bonding layer of the second wafer and performing bonding includes: S61 , pre-treating the surface of the nanobridge dielectric layer of the first wafer and the surface of the bonding layer of the second wafer.

[0047] Specifically, the surface of the nanobridge dielectric layer of the first wafer and the surface of the bonding layer of the second wafer can be plasma bombarded or wet treated to increase the activity of the surfaces to be bonded. The specific implementation process of the pretreatment is well known to those skilled in the art and will not be described in detail in this application.

[0048] S62 , flipping the first wafer and aligning and pre-bonding the first wafer with the second wafer.

[0049] Specifically, a bonding machine can be used to flip the first wafer so that the amorphous silicon layer of the first wafer faces the bonding layer of the second wafer. The first and second wafers are then aligned and pre-bonded. The alignment and pre-bonding processes are well known to those skilled in the art and will not be described in detail herein.

[0050] After pre-bonding, the nanobridge dielectric layer of the first wafer and the bonding layer of the second wafer are bonded together by van der Waals forces and hydrogen bonds. The metal layers to be bonded on the first and second wafers are aligned one-to-one.

[0051] S63, performing low-temperature annealing on the pre-bonded first wafer and the second wafer.

[0052] Specifically, in this embodiment, the low-temperature annealing temperature does not exceed 250°C. Thus, after annealing, stable chemical bonds are formed between the nanobridge dielectric layer 150 and the first dielectric layer 120 and the second dielectric layer 220, and preliminary mutual melting is achieved between the nanobridge dielectric layer 150 and the first metal layer 130 and the second metal layer 230. Furthermore, the performance of the functional layers of the semiconductor device is prevented from being degraded by high temperatures. Furthermore, the low-temperature annealing ensures that the thermal expansion of the first metal layer 130 and the second metal layer 230 is low. Furthermore, the nanobridge dielectric layer 150 can also serve as a buffer layer, preventing the first metal layer 130 and the second metal layer 230 from direct contact after thermal expansion, which could lead to excessive stress concentration, thereby ensuring the stability of the device structure.

[0053] At this time, the structure of the semiconductor device is as shown in FIG2(H).

[0054] Furthermore, in this embodiment, in step S7, the method of leading out the metal connector on the substrate surface of the first wafer includes: First, the thickness of the substrate of the first wafer is reduced. Then, a second through-hole is formed in the substrate of the first wafer, wherein the second through-hole exposes the metal structure in the device functional layer. Finally, the second through-hole is filled to form a metal connector.

[0055] In a specific embodiment, after the thickness of the first substrate 100 is thinned, a third dielectric layer 160 can be first formed on the surface of the first substrate 100; then, similar to the process of step S22, a second through hole is formed, and the second through hole passes through the third dielectric layer 160, the first substrate 100 and a portion of the device functional layer 110 until the first metal structure 111 is exposed at the bottom; finally, similar to the process of step S23, the second through hole is filled to form a metal connector 170, wherein, to facilitate subsequent voltage application, a metal pattern 161 can be formed on the surface of the third dielectric layer 160 using a wiring process, and the metal pattern 161 is connected to the metal connector 170.

[0056] At this time, the structure of the semiconductor device is as shown in FIG2(I).

[0057] Furthermore, in this embodiment, in step S8, a voltage is applied to the metal layers using metal connectors to make the nanobridge dielectric layer between the metal layers conductive.

[0058] Specifically, a voltage can be applied to the metal pattern 161 formed on the surface of the third dielectric layer 160, so that the voltage reaches the nanobridge dielectric layer 150 through the metal connector 170, the first metal structure 111, the first metal layer 130, and the nanobridge metal layer 140 in sequence; when the voltage difference reaches a threshold value (such as 3V), the metal ions in the second metal layer 230 will diffuse into the nanobridge dielectric layer 150 between the first metal layer 130 and the second metal layer 230, and continue to accumulate under the action of the voltage, so that the nanobridge dielectric layer 151 here is converted into a conductive area, so that the first metal layer 130 and the second metal layer 230 are conductive; while the nanobridge dielectric layer 150 between the first dielectric layer 120 and the second dielectric layer 220 still maintains its insulating properties.

[0059] Finally, the structure of the obtained semiconductor device is shown in FIG2(J).

[0060] The semiconductor device manufacturing method provided by this embodiment does not require strict control of the height difference between the metal layer and the dielectric layer in the bonding layer, thereby effectively reducing the process difficulty. The semiconductor device manufacturing method provided by this embodiment uses low-temperature annealing, which not only ensures that the device functional layer will not degrade due to high temperature, but also controls the thermal expansion of the metal layer, thereby reducing the stress in the metal layer within the semiconductor device and ensuring the stability of the device structure. The semiconductor device manufacturing method provided by this embodiment, by adding a metal nanobridge structure between the two bonding layers to be bonded, not only can the nanobridge dielectric layer of the metal nanobridge structure be used to achieve pre-bonding of the dielectric layer, reduce the stress between the metal layers, and enhance the stability of the device structure, but also can apply a voltage to the nanobridge dielectric layer through the metal layer, thereby connecting the nanobridge dielectric layer between the metal layers and achieving conductive connection of the metal layers. Compared with the existing technology, the semiconductor device manufacturing method provided by this embodiment not only has a low process difficulty, but also can improve the performance stability of the semiconductor device while ensuring the effectiveness of hybrid bonding.

[0061] Based on the above-mentioned method for manufacturing a semiconductor device, this embodiment further provides a semiconductor device, as shown in Figure 2 (J), wherein the semiconductor device includes a second substrate 200, a second device functional layer 210, a second bonding layer, a nanobridge dielectric layer 150, a first bonding layer, a first device functional layer 110 and a first substrate 100 formed in sequence from bottom to top; a metal connector 170 is formed in the first substrate 100, and the metal connector 170 is connected to the metal structure 111 of the first device functional layer 110; the first bonding layer includes a stacked first metal layer 130 and a nanobridge metal layer 140, and the nanobridge metal layer 140 is connected to the nanobridge dielectric layer 150; the second bonding layer includes a second metal layer 230, and the nanobridge dielectric layer 150 between the nanobridge metal layer 140 and the second metal layer 230 is turned on when voltage is applied.

[0062] Specifically, the first metal layer 130 and the second metal layer 230 may be made of copper; the nanobridge metal layer 140 may be made of ruthenium; and the nanobridge dielectric layer 150 may be made of hafnium oxide.

[0063] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0064] The semiconductor device and manufacturing method provided by this embodiment include: providing two wafers to be mixed and bonded, respectively denoted as a first wafer and a second wafer, wherein the first wafer and the second wafer both include a substrate and a device functional layer formed from bottom to top; forming a bonding layer on the surface of the device functional layer of the first wafer and the second wafer, wherein the dielectric layer and the metal layer are exposed on the surface of the bonding layer; etching the metal layer of the first wafer so that the surface of the metal layer is lower than the surface of the dielectric layer; forming a nanobridge metal layer on the surface of the metal layer of the first wafer; forming a nanobridge dielectric layer on the surface of the first wafer; aligning the nanobridge dielectric layer of the first wafer toward the bonding layer of the second wafer and bonding them; leading out a metal connector on the substrate surface of the first wafer; and applying a voltage to the metal layer using the metal connector to make the nanobridge dielectric layer between the metal layers conductive. By forming a nanobridge structure in the metal bonding area of ​​the first wafer and the second wafer, metal bonding is achieved by utilizing the nanobridge structure when power is applied. There is no need to utilize annealing thermal expansion to bond the metal layers, and therefore there is no need to strictly control the height of the metal layer relative to the dielectric layer and the surface pattern of the metal layer, nor is there any need to use high-temperature annealing. This not only reduces the process difficulty but also ensures device performance, solving the problem that the existing hybrid bonding process method is difficult and affects device performance.

[0065] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing two wafers to be hybrid-bonded, respectively denoted as a first wafer and a second wafer, wherein the first wafer and the second wafer both include a substrate and a device functional layer formed from bottom to top; forming a bonding layer on the surfaces of the device functional layers of the first wafer and the second wafer, wherein the dielectric layer and the metal layer are exposed on the surface of the bonding layer; Etching the metal layer of the first wafer so that the surface of the metal layer is lower than the surface of the dielectric layer; forming a nanobridge metal layer on a surface of the metal layer of the first wafer; forming a nanobridge dielectric layer on a surface of the first wafer; Direct the nanobridge dielectric layer of the first wafer toward the bonding layer of the second wafer and perform bonding; Leading out metal connectors on the substrate surface of the first wafer; A voltage is applied to the metal layers by using metal connectors to make the nanobridge dielectric layers between the metal layers conductive.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for forming a bonding layer on the surface of the device functional layer of the first wafer and the second wafer comprises: forming a dielectric layer on the surface of the device functional layer; Forming a first through hole on the dielectric layer, wherein the first through hole exposes the metal structure in the device functional layer; The first through hole is filled to form a metal layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for forming a nanobridge metal layer on the metal layer surface of the first wafer comprises: Using a physical vapor deposition process, a nanobridge metal layer is formed on the bonding layer surface of the first wafer, wherein the material of the nanobridge metal layer is ruthenium; The nanobridge metal layer on the surface of the dielectric layer of the first wafer is removed by chemical mechanical polishing, and the surface of the dielectric layer is made flush with the surface of the nanobridge metal layer.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for forming a nanobridge dielectric layer on the surface of the first wafer comprises: A nanobridge dielectric layer is formed on the surface of the first wafer by using an atomic layer deposition process, wherein the material of the nanobridge dielectric layer is hafnium oxide.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The method of placing the nanobridge dielectric layer of the first wafer toward the bonding layer of the second wafer and performing bonding includes: Pre-treating the surface of the nanobridge dielectric layer of the first wafer and the surface of the bonding layer of the second wafer; flipping the first wafer, and aligning and pre-bonding the first wafer with the second wafer; The pre-bonded first wafer and the second wafer are subjected to low temperature annealing.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The pretreatment method includes plasma bombardment treatment or wet treatment.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: The temperature of the low temperature annealing does not exceed 250°C.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for leading out a metal connector on the substrate surface of the first wafer comprises: reducing the thickness of the substrate of the first wafer; forming a second through hole on the substrate of the first wafer, wherein the second through hole exposes the metal structure in the device functional layer; The second through hole is filled to form a metal connector.

9. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 8, characterized in that: The semiconductor device includes a second substrate, a second device functional layer, a second bonding layer, a nanobridge dielectric layer, a first bonding layer, a first device functional layer and a first substrate which are formed in sequence from bottom to top; a metal connector is formed in the first substrate, and the metal connector is connected to the metal structure of the first device functional layer; the first bonding layer includes a stacked first metal layer and a nanobridge metal layer, and the nanobridge metal layer is connected to the nanobridge dielectric layer; the second bonding layer includes a second metal layer, and the nanobridge dielectric layer between the nanobridge metal layer and the second metal layer is turned on when voltage is applied.

10. The semiconductor device according to claim 9, characterized in that The material of the first metal layer and the second metal layer is copper; the material of the nanobridge dielectric layer is hafnium oxide; and the material of the nanobridge metal layer is ruthenium.

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