Non-volatile memory

Abstract

The invention discloses a nonvolatile memory. A device unit structure comprises a vertical channel region and a gate structure. The gate structure covers one of the side surfaces on both sides of the width edge of the vertical channel region. The gate structure comprises a selection gate and a storage gate. A first gate dielectric layer is arranged between the selection gate and the vertical channel region in a spaced mode, and a first dielectric layer is arranged between the selection gate and the semiconductor substrate in a spaced mode. The storage gate is located at the top of the selection gate and spaced by a second dielectric layer. And a second gate storage medium layer is spaced between the storage gate and the vertical channel region. The surface of the vertical channel region covered by the gate structure is used for forming a vertical channel, a second vertical channel part is controlled by the storage gate, when charges are stored in the second gate storage medium layer, the storage bit is' 0 ', and otherwise, the storage bit is' 1 '. The size of the device can be reduced, so that the size miniaturization of the device can be conveniently realized; the storage stability can be improved; the service life can be prolonged; the working bias voltage can be reduced; and the reading and erasing speeds are increased.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, and in particular to a non-volatile memory. Background Art

[0002] Existing non-volatile memories store charge in structures such as a floating gate (FG) or a nitride layer of silicon-oxide-nitride-oxide-silicon (SONOS). With the development of Moore's Law, these existing non-volatile memories face problems such as size reduction and various reliability issues. Researchers have developed a variety of materials and structures to try to solve the memory bottleneck.

[0003] Existing non-volatile memories are all one-dimensional structures, such as one-dimensional NOR flash or one-dimensional embedded flash (e-flash). The working principle of one-dimensional non-volatile memories is to open a horizontal channel to allow current to flow and express '1' or '0' through the amount of charge stored in the floating gate or SONOS. The operating voltage needs to be greater than 5V, and the programming / erasing speed is slow.

[0004] However, if the one-dimensional single-layer device structure is simply expanded to a two-dimensional space, it often has various problems such as insufficient scalability, high power consumption, and poor stability and reliability. For example, V2T NOR flash memory has these problems. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a non-volatile memory which can reduce the size of the device so as to facilitate the miniaturization of the device; it can also improve the storage stability and lifespan, reduce the working bias voltage, and increase the reading and erasing speed.

[0006] In order to solve the above technical problems, the device unit structure of the non-volatile memory provided by the present invention includes: a vertical channel region and a gate structure.

[0007] The vertical channel region is composed of a first epitaxial layer formed on the top surface of the semiconductor substrate, and the vertical channel region has a second conductivity type doping.

[0008] The gate structure covers one of the side surfaces on both sides of the width side of the vertical channel region.

[0009] The gate structure includes a selection gate and a storage gate.

[0010] A first gate dielectric layer is spaced between the selection gate and the vertical channel region, and a first dielectric layer is spaced between the selection gate and the semiconductor substrate at the bottom.

[0011] The storage gate is located on the top of the selection gate and a second dielectric layer is spaced between the storage gate and the selection gate.

[0012] A second gate storage dielectric layer is spaced between the storage gate and the vertical channel region. The second gate storage dielectric layer has a charge storage function and forms a storage bit. The second gate storage dielectric layer is located on top of the first gate dielectric layer.

[0013] The surface of the vertical channel region covered by the gate structure is used to form a vertical channel, and the vertical channel is formed by the superposition of a first vertical channel portion and a second vertical channel portion. The first vertical channel portion is controlled by the selection gate, and the second vertical channel portion is controlled by the storage gate. When charges are stored in the second gate storage dielectric layer, the storage bit is '0' and the second vertical channel portion is disconnected; when the charges stored in the second gate storage dielectric layer are erased, the storage bit is '1' and the second vertical channel portion is turned on.

[0014] As a further improvement, a gate structure is provided on both sides of the width edge of the vertical channel region, two device unit structures share one vertical channel region and a device unit combination structure is formed by the two device unit structures sharing one vertical channel region.

[0015] As a further improvement, a first trench is formed in the area between the two gate structures in the device unit combination structure, the bottom surface of the first trench exposes the top surface of the semiconductor substrate, and the first epitaxial layer is a selective epitaxial layer grown from bottom to top from the top surface of the semiconductor substrate exposed by the bottom surface of the first trench.

[0016] As a further improvement, the semiconductor substrate comprises a silicon substrate.

[0017] As a further improvement, the first epitaxial layer includes a silicon epitaxial layer.

[0018] As a further improvement, the first gate dielectric layer includes a gate oxide layer.

[0019] As a further improvement, the selection gate is a polysilicon gate or a metal gate.

[0020] As a further improvement, the second gate storage dielectric layer includes an ONO layer or an ANO layer, the ONO layer includes an oxide layer, a nitride layer and an oxide layer stacked in sequence, and the ANO layer includes an aluminum oxide layer, a nitride layer and an oxide layer stacked in sequence.

[0021] As a further improvement, the storage gate is a polysilicon gate or a metal gate.

[0022] As a further improvement, a source region heavily doped with the first conductivity type is formed in the surface region of the semiconductor substrate at the bottom of the vertical channel region.

[0023] A drain region heavily doped with a first conductivity type is formed in a surface region at a top of the vertical channel region.

[0024] As a further improvement, the device unit structure is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the device unit structure is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0025] As a further improvement, the material of the first dielectric layer includes an oxide layer.

[0026] As a further improvement, the material of the second dielectric layer includes an oxide layer.

[0027] As a further improvement, the second dielectric layer extends between the first gate dielectric layer and the second gate storage dielectric layer.

[0028] As a further improvement, the first dielectric layer extends to the bottom of the first gate dielectric layer and extends between the vertical channel region at an edge position and the semiconductor substrate.

[0029] The present invention sets a vertical channel region and sets a gate structure on the side of the vertical channel region, which is beneficial to reducing the size of the device; the vertical channel region can be self-aligned and formed in the groove between the two gate structures, thereby further reducing the size of the device. Therefore, the present invention can easily achieve device size miniaturization.

[0030] The storage gate of the present invention is located on the top of the selection gate, and charges are stored through the second gate storage dielectric layer between the storage gate and the vertical channel region. Compared with the floating gate of the existing one-dimensional non-volatile memory or SONOS in which the storage layer is located in the bottom area of ​​the gate structure, the second gate storage dielectric layer of the present invention is located in the top area. This structure is conducive to operating the stored charge of the second gate storage dielectric layer, thereby improving the programming and erasing speeds, and is also conducive to improving the reading speed and reducing the operating voltage.

[0031] The present invention can also improve storage stability and life by using the second gate storage dielectric layer located on the side of the top area of ​​the vertical channel region as the charge storage layer.

[0032] The vertical channel region of the present invention is located on the top of the semiconductor substrate, which is beneficial to reducing the size of the vertical channel region, has a small parasitic effect, and can further improve the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0034] Figure 1 4 is a device structure diagram of a non-volatile memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] like Figure 1 , which is a device structure diagram of a non-volatile memory according to an embodiment of the present invention; a device unit structure 100 of a non-volatile memory according to an embodiment of the present invention includes: a vertical channel region 102 and a gate structure.

[0036] The vertical channel region 102 is composed of a first epitaxial layer formed on the top surface of the semiconductor substrate 101 , and the vertical channel region 102 has a second conductivity type doping.

[0037] In the embodiment of the present invention, the semiconductor substrate 101 includes a silicon substrate.

[0038] The first epitaxial layer includes a silicon epitaxial layer.

[0039] The gate structure covers one of the side surfaces on both sides of the width side of the vertical channel region 102 .

[0040] The gate structure includes a selection gate 103 and a storage gate 104 .

[0041] A first gate dielectric layer 105 is disposed between the select gate 103 and the vertical channel region 102 , and a first dielectric layer 107 is disposed between the select gate 103 and the semiconductor substrate 101 at the bottom.

[0042] The storage gate 104 is located on the top of the selection gate 103 , and a second dielectric layer 108 is spaced between the storage gate 104 and the selection gate 103 .

[0043] A second gate storage dielectric layer 106 is disposed between the storage gate 104 and the vertical channel region 102 . The second gate storage dielectric layer 106 has a charge storage function and forms a storage bit. The second gate storage dielectric layer 106 is located on top of the first gate dielectric layer 105 .

[0044] In the embodiment of the present invention, the material of the first dielectric layer 107 includes an oxide layer.

[0045] The material of the second dielectric layer 108 includes an oxide layer.

[0046] The second dielectric layer 108 extends between the first gate dielectric layer 105 and the second gate storage dielectric layer 106 .

[0047] The first dielectric layer 107 extends to the bottom of the first gate dielectric layer 105 and extends between the vertical channel region 102 and the semiconductor substrate 101 at the edge.

[0048] The surface of the vertical channel region 102 covered by the gate structure is used to form a vertical channel, and the vertical channel is formed by the superposition of a first vertical channel portion and a second vertical channel portion. The first vertical channel portion is controlled by the selection gate 103, and the second vertical channel portion is controlled by the storage gate 104. When charges are stored in the second gate storage dielectric layer 106, the storage bit is '0' and the second vertical channel portion is disconnected; when the charges stored in the second gate storage dielectric layer 106 are erased, the storage bit is '1' and the second vertical channel portion is turned on.

[0049] In the embodiment of the present invention, a gate structure is disposed on both sides of the width side of the vertical channel region 102, two device unit structures 100 share one vertical channel region 102, and a device unit combination structure is formed by the two device unit structures 100 sharing one vertical channel region 102. Figure 1 A device unit combination structure is shown in FIG.

[0050] A first trench is formed in the region between the two gate structures in the device unit combination structure, the bottom surface of the first trench exposes the top surface of the semiconductor substrate 101, and the first epitaxial layer is a selective epitaxial layer grown from bottom to top from the top surface of the semiconductor substrate 101 exposed by the bottom surface of the first trench. The vertical channel region 102 composed of the selective epitaxial layer is conducive to improving the process quality of the vertical channel region 102, and is also conducive to reducing the size of the vertical channel region 102, such as the width, which is conducive to improving device performance.

[0051] In the embodiment of the present invention, the first gate dielectric layer 105 is a gate oxide layer. In other embodiments, the first gate dielectric layer 105 can also be other dielectric layers as required.

[0052] The select gate 103 is a polysilicon gate. In other embodiments, the select gate 103 can also be a metal gate.

[0053] In the embodiment of the present invention, the second gate storage dielectric layer 106 is an ANO layer, and the storage gate 104 is a metal gate. In this way, the silicon in the vertical channel region 102, the ANO layer, and the metal gate form a BE-MANOS storage structure, where BE represents energy level engineering, and MANOS are the abbreviations of the metal gate, the ANO layer, and the silicon in the vertical channel region 102, respectively. This structure can realize charge storage.

[0054] In other embodiments, the second gate storage dielectric layer 106 may be an ONO layer, and the ONO layer includes an oxide layer, a nitride layer and an oxide layer stacked in sequence.

[0055] In the embodiment of the present invention, a heavily doped source region of the first conductivity type is formed in the surface region of the semiconductor substrate 101 at the bottom of the vertical channel region 102 .

[0056] A drain region heavily doped with the first conductivity type is formed in a surface region at the top of the vertical channel region 102 .

[0057] The device unit structure 100 is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the device unit structure 100 is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0058] The embodiment of the present invention sets a vertical channel region 102 and sets a gate structure on the side of the vertical channel region 102. This structure is conducive to reducing the size of the device; the vertical channel region 102 can be self-aligned and formed in the groove between the two gate structures, thereby further reducing the size of the device. Therefore, the embodiment of the present invention can easily achieve device size miniaturization.

[0059] The storage gate 104 of the embodiment of the present invention is located on the top of the selection gate 103, and charges are stored through the second gate storage dielectric layer 106 between the storage gate 104 and the vertical channel region 102. Compared with the floating gate or SONOS storage layer of the existing one-dimensional non-volatile memory structure located in the bottom area of ​​the gate structure, the second gate storage dielectric layer 106 of the embodiment of the present invention is located in the top area. This structure is conducive to operating the stored charge of the second gate storage dielectric layer 106, thereby improving the programming and erasing speeds, and is also conducive to improving the reading speed and reducing the operating voltage.

[0060] The embodiment of the present invention uses the second gate storage dielectric layer 106 located on the side of the top region of the vertical channel region 102 as a charge storage layer, thereby improving storage stability and lifespan.

[0061] The vertical channel region 102 of the embodiment of the present invention is located on the top of the semiconductor substrate 101, which is beneficial to reducing the size of the vertical channel region 102, has a small parasitic effect, and can further improve the performance of the device.

[0062] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A non-volatile memory, characterized in that: The device unit structure includes: a vertical channel region and a gate structure; The vertical channel region is composed of a first epitaxial layer formed on the top surface of the semiconductor substrate, and the vertical channel region has a second conductivity type doping; The gate structure covers one of the side surfaces on both sides of the width side of the vertical channel region; The gate structure includes: a selection gate and a storage gate; A first gate dielectric layer is disposed between the selection gate and the vertical channel region, and a first dielectric layer is disposed between the selection gate and the semiconductor substrate at the bottom; The storage gate is located on the top of the selection gate and a second dielectric layer is spaced between the storage gate and the selection gate; A second gate storage dielectric layer is disposed between the storage gate and the vertical channel region, the second gate storage dielectric layer has a charge storage function and forms a storage bit, and the second gate storage dielectric layer is located on top of the first gate dielectric layer; The surface of the vertical channel region covered by the gate structure is used to form a vertical channel, and the vertical channel is formed by the superposition of a first vertical channel portion and a second vertical channel portion. The first vertical channel portion is controlled by the selection gate, and the second vertical channel portion is controlled by the storage gate. When charges are stored in the second gate storage dielectric layer, the storage bit is '0' and the second vertical channel portion is disconnected; when the charges stored in the second gate storage dielectric layer are erased, the storage bit is '1' and the second vertical channel portion is turned on.

2. The non-volatile memory according to claim 1, wherein: A gate structure is disposed on both sides of the width edge of the vertical channel region, two device unit structures share one vertical channel region, and a device unit combination structure is formed by the two device unit structures sharing one vertical channel region.

3. The non-volatile memory according to claim 2, wherein: A first trench is formed in the region between the two gate structures in the device unit combination structure, the bottom surface of the first trench exposes the top surface of the semiconductor substrate, and the first epitaxial layer is a selective epitaxial layer grown from bottom to top from the top surface of the semiconductor substrate exposed by the bottom surface of the first trench.

4. The non-volatile memory according to claim 1, wherein: The semiconductor substrate includes a silicon substrate.

5. The non-volatile memory according to claim 4, wherein: The first epitaxial layer includes a silicon epitaxial layer.

6. The non-volatile memory according to claim 5, wherein: The first gate dielectric layer includes a gate oxide layer.

7. The nonvolatile memory according to claim 6, wherein: The selection gate is a polysilicon gate or a metal gate.

8. The non-volatile memory according to claim 5, wherein: The second gate storage dielectric layer includes an ONO layer or an ANO layer, the ONO layer includes an oxide layer, a nitride layer and an oxide layer stacked in sequence, and the ANO layer includes an aluminum oxide layer, a nitride layer and an oxide layer stacked in sequence.

9. The non-volatile memory according to claim 8, wherein: The storage gate is a polysilicon gate or a metal gate.

10. The non-volatile memory according to claim 1, wherein: forming a heavily doped source region of a first conductivity type in a surface region of the semiconductor substrate at the bottom of the vertical channel region; A drain region heavily doped with a first conductivity type is formed in a surface region at a top of the vertical channel region.

11. The non-volatile memory according to claim 10, wherein: The device unit structure is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the device unit structure is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

12. The non-volatile memory according to claim 1, wherein: The material of the first dielectric layer includes an oxide layer.

13. The non-volatile memory according to claim 1, wherein: The material of the second dielectric layer includes an oxide layer.

14. The non-volatile memory according to claim 1, wherein: The second dielectric layer extends between the first gate dielectric layer and the second gate storage dielectric layer.

15. The non-volatile memory according to claim 1, wherein: The first dielectric layer extends to the bottom of the first gate dielectric layer and extends between the vertical channel region at the edge position and the semiconductor substrate.

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