Planar gate VDMOS with low reverse recovery interference and preparation method thereof

Abstract

The invention provides a planar gate VDMOS with low reverse recovery interference and a preparation method thereof. A barrier layer is formed above a silicon carbide substrate provided with a drain metal layer, the barrier layer is etched to form a through hole, and ion implantation is performed on the silicon carbide substrate to form a plurality of buffer regions; removing the barrier layer, and performing epitaxial growth on the silicon carbide substrate to form a drift layer; a barrier layer is formed above the drift layer, etching and ion implantation are carried out, and a variable doping region, a P-type well region, a P-type source region and an N-type source region are formed; re-forming a barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a gate metal layer is formed; the method comprises the following steps: forming a buffer region in a device, re-forming a barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer, removing the barrier layer, and completing preparation, so that the buffer region is constructed in the device, the rising edge of reverse recovery overshoot of the device can be effectively reduced, and the external interference of the device is reduced.

Description

Technical Field

[0001] The invention relates to a low reverse recovery interference planar gate VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the performance requirements for devices in different fields have different emphases, but the overall requirements are higher voltage resistance, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short circuit reliability, etc.), and lower body diode conduction loss. Due to the fast reverse recovery speed of silicon carbide devices, the drain voltage overshoot caused by reverse recovery can easily cause the device to interfere with other circuits in the system, affecting system stability. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a low reverse recovery interference planar gate VDMOS and a preparation method thereof, and a buffer zone is constructed inside the device, which can effectively reduce the rising edge of the reverse recovery overshoot of the device and reduce the external interference of the device.

[0004] In a first aspect, the present invention provides a method for preparing a low reverse recovery interference planar gate VDMOS, comprising the following steps:

[0005] Step 1, forming a barrier layer on the silicon carbide substrate provided with a drain metal layer, etching the barrier layer to form a through hole, and performing ion implantation on the silicon carbide substrate to form a plurality of buffer zones;

[0006] Step 2: removing the barrier layer and performing epitaxial growth on the silicon carbide substrate to form a drift layer;

[0007] Step 3: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions into the drift layer to form a variable doping region;

[0008] Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region;

[0009] Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form a P-type source region;

[0010] Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the P-type well region to form an N-type source region;

[0011] Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer;

[0012] Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer;

[0013] Step 9: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0014] In a second aspect, the present invention provides a low reverse recovery interference planar gate VDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing a low reverse recovery interference planar gate VDMOS described in the first aspect.

[0015] The advantages of the present invention are:

[0016] 1. The present invention constructs a buffer zone in the silicon carbide substrate of the device, which can suppress the interference introduced by the sharp rising edge of the drain voltage spike caused by the reverse recovery current of the device parasitic body diode after the device is switched from on to off, thereby reducing the noise of the device and improving the robustness;

[0017] Second, a variable doping region is constructed inside the drift layer of the present invention, which can guide the current in the JFET region of the device to the region below the P-type well region of the device, thereby increasing the conductive area of ​​the device, reducing the on-resistance of the device and avoiding the heat concentration caused by the current concentration inside the device;

[0018] 3. In the present invention, a drift layer is provided between the variable doping region and the P-type well region, and this region can reduce the influence of the variable doping region on the device switch structure, thereby achieving the characteristic of only improving the device performance without affecting the original parameters of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0020] Figure 1 The schematic diagram of the low reverse recovery interference planar gate VDMOS of the present invention is shown in FIG.

[0021] Figure 2 A cross-sectional view of the process of a low reverse recovery interference planar gate VDMOS of the present invention Figure 1 .

[0022] Figure 3 A cross-sectional view of the process of a low reverse recovery interference planar gate VDMOS of the present invention Figure 2 .

[0023] Figure 4A cross-sectional view of the process of a low reverse recovery interference planar gate VDMOS of the present invention Figure 3 .

[0024] Figure 5 A cross-sectional view of the process of a low reverse recovery interference planar gate VDMOS of the present invention Figure 4 .

[0025] Figure 6 A cross-sectional view of the process of a low reverse recovery interference planar gate VDMOS of the present invention Figure 5 .

[0026] Figure 7 A cross-sectional view of the process of a low reverse recovery interference planar gate VDMOS of the present invention Figure 6 .

[0027] Figure 8 A cross-sectional view of the process of a low reverse recovery interference planar gate VDMOS of the present invention Figure 7 .

[0028] Fig. 9 A cross-sectional view of the process of a low reverse recovery interference planar gate VDMOS of the present invention Figure 8 .

[0029] Fig.10 A cross-sectional view of the process of a low reverse recovery interference planar gate VDMOS of the present invention Figure 9 . DETAILED DESCRIPTION

[0030] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0032] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0033] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0034] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] like Figures 1 to 10 As shown, the embodiment of the present application provides a method for preparing a low reverse recovery interference planar gate VDMOS, comprising the following steps:

[0036] Step 1, forming a barrier layer 8 on the silicon carbide substrate 1 provided with the drain metal layer 7, etching the barrier layer 8 to form a through hole, and performing ion implantation on the bottom of the silicon carbide substrate 1 to form a plurality of buffer zones 11;

[0037] Step 2, removing the barrier layer 8, and epitaxially growing on the silicon carbide substrate 1 to form a drift layer 2;

[0038] Step 3, forming a barrier layer 8 above the drift layer 2, etching the barrier layer 8 to form a through hole, and performing ion implantation into the drift layer 2 to form a second N-type doping region 212; removing the original barrier layer 8, re-forming the barrier layer 8, and performing ion implantation into the drift layer 2 to form a first N-type doping region 211, wherein the modified doping region 21 includes the first N-type doping region 211 and the second N-type doping region 212, wherein the concentration of the first N-type doping region 211 is less than the concentration of the second N-type doping region 212, and the inner side surface of the first N-type doping region 211 is connected to the inner side surface of the second N-type doping region 212;

[0039] Step 4, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and performing ion implantation into the drift layer 2 to form a P-type well region 3;

[0040] Step 5, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and performing ion implantation into the P-type well region 3 to form a P-type source region 31;

[0041] Step 6, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and performing ion implantation into the P-type well region 3 to form an N-type source region 32;

[0042] Step 7, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and depositing to form a gate dielectric layer 4;

[0043] Step 8, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, depositing metal, and forming a gate metal layer 5;

[0044] Step 9, remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, deposit metal to form a source metal layer 6, remove the barrier layer 8, and complete the preparation.

[0045] In this embodiment, preferably, the distance between the upper side of the variable doping region 21 and the lower side of the P-type well region 3 is 3-5 μm.

[0046] In this embodiment, preferably, the thickness of the buffer zone 11 is 300-500 nm.

[0047] In this embodiment, preferably, the width of the variable doping region 21 is equal to the width of the P-type well region 3 .

[0048] like Figure 1 As shown, the VDMOS obtained by the above manufacturing method includes:

[0049] A silicon carbide substrate 1, wherein a plurality of buffer zones 11 are provided in the silicon carbide substrate 1;

[0050] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1, a variable doping region 21 is provided in the drift layer 2, and a protrusion 22 is provided on the drift layer 2;

[0051] A P-type well region 3, wherein the lower side of the P-type well region 3 is connected to the upper side of the drift layer 2, and the inner side of the P-type well region 3 is connected to the outer side of the protrusion 22; a P-type source region 31 and an N-type source region 32 are provided in the P-type well region 3, and the P-type source region 31 is connected to the N-type source region 32; the P-type well region 3 is located directly above the variable doping region 21;

[0052] A gate dielectric layer 4, the lower side of which is connected to the protrusion 22 and the P-type well region 3 respectively;

[0053] A gate metal layer 5, wherein the gate metal layer 5 is connected to the gate dielectric layer 4;

[0054] A drain metal layer 6, wherein the drain metal layer 6 is respectively connected to the P-type well region 3, the P-type source region 31 and the N-type source region 32;

[0055] And, a drain metal layer 7 , wherein the drain metal layer 7 is connected to the lower side of the silicon carbide substrate 1 and each buffer region 11 .

[0056] In another embodiment of the present invention, the silicon carbide substrate 1, the drift layer 2 and the variable doping region 21 are all N-type; the buffer region 11 is P-type; the doping concentration of the silicon carbide substrate 1 is 2-8e18cm -3 ; The doping concentration of the buffer zone 11 is 1-4e18cm -3 , the doping concentration of drift layer 2 is 1-5e17cm -3 The doping concentration of the first N-type doping region 211 is 0.8-1.2e18cm -3 The doping concentration of the second N-type doping region 212 is 1.2-2e18cm -3 , the doping concentration of P-type well region 3 is 5-8e17 cm -3 The gate dielectric layer 4 is silicon dioxide, and the doping concentration of the N-type source region 32 is 2-8e18cm -3 , the doping concentration of the P-type source region 31 is 1-5e19cm -3The doping concentration of the N-type silicon carbide substrate 1 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 7, the P-type buffer 11 provides holes when the device is reversely recovered, the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and the on-resistance of the device, the N-type variable doping region 21 is to redistribute the internal current of the device, reduce the on-resistance of the device, and avoid current thermal concentration, the P-type well region 3 is to form a longitudinal withstand voltage structure of the device and a gate control structure of the device, and the N-type source region 32 and the P-type source region 31 are to form a low-resistance ohmic contact with the source metal layer 6;

[0057] The thickness of the silicon carbide substrate 1 of the device is 1 μm, the thickness of the P-type buffer zone 11 is 300-500nm, and the thickness of the N-type drift layer 2 is 10-30 μm, which are adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The thickness of the N-type variable doping region 21 is 1-3 μm, and the distance between the upper side of the N-type variable doping region 21 and the lower side of the P-type well region 3 is 3-5 μm, which is to achieve current redistribution on the basis of ensuring that the switching and withstand voltage characteristics of the device are not affected. The thickness of the P-type well region 3 is 500nm, which is to ensure the withstand voltage capability and gate control capability of the device. The thickness of the N-type source region 32 and the P-type source region 31 is 200nm, which is a compromise between the ion implantation process control capability and the conductive capability determined by the device gate control depth. The thickness of the source metal layer 6 is 200nm, and the thickness of the gate metal layer 5 is 150nm;

[0058] The P-type buffer layer 11 constructed in the silicon carbide substrate 1 makes the substrate hole injection process slow down due to the presence of initial holes during the substrate hole injection process when the device is switched from on to off, thereby reducing the rising edge speed when the device is switched from on to off, thereby reducing the high-frequency interference caused by reverse recovery of the device;

[0059] When the device electrons flow horizontally from the N-type source region 32 through the P-type well region 3 and then flow downward, as the downward flow depth increases, the device lateral electron flow area increases, and the N-type drift layer 2 cannot be used for electron continuous flow in the device near the P-type well region 3, resulting in an increase in the device on-resistance and a concentrated current distribution. The N-type variable doping region 21 reduces the resistance on the left and right sides of the device, so that the electrons begin to flow horizontally near the P-type well region 3, thereby reducing the overall device on-resistance and avoiding device current concentration.

[0060] The device reduces the reverse recovery current peak of the device by adding a P-type buffer zone 11 to the N-type silicon carbide substrate 1, reduces the reverse recovery voltage overshoot rising edge speed of the device, realizes the reverse recovery interference of the device, and improves the robustness of the device.

[0061] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a low reverse recovery interference planar gate VDMOS, characterized in that: The steps include: Step 1, forming a barrier layer on the silicon carbide substrate provided with a drain metal layer, etching the barrier layer to form a through hole, and performing ion implantation on the silicon carbide substrate to form a plurality of buffer zones; Step 2: removing the barrier layer and performing epitaxial growth on the silicon carbide substrate to form a drift layer; Step 3: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions into the drift layer to form a variable doping region; Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form a P-type source region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the P-type well region to form an N-type source region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 9: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a low reverse recovery interference planar gate VDMOS according to claim 1, characterized in that: The step 3 specifically comprises: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a second N-type doping region; The original blocking layer is removed, the blocking layer is re-formed, and ions are implanted into the drift layer to form a first N-type doping region, wherein the variable doping region includes a first N-type doping region and a second N-type doping region, wherein the concentration of the first N-type doping region is less than the concentration of the second N-type doping region, and the inner side surface of the first N-type doping region is connected to the inner side surface of the second N-type doping region.

3. The method for preparing a low reverse recovery interference planar gate VDMOS according to claim 1, characterized in that: The distance between the upper side of the variable doping region and the lower side of the P-type well region is 3-5 μm.

4. The method for preparing a low reverse recovery interference planar gate VDMOS according to claim 1, characterized in that: The thickness of the buffer zone is 300-500 nm.

5. The method for preparing a low reverse recovery interference planar gate VDMOS according to claim 1, characterized in that: The width of the variable doping region is equal to the width of the P-type well region.

6. A low reverse recovery interference planar gate VDMOS, characterized in that: The silicon carbide VDMOS is prepared by any one of the preparation methods of claim 1 to claim 5.

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