Test sample and preparation method thereof

Abstract

The invention provides a test sample and a preparation method thereof, and the preparation method comprises the steps: forming an initial sample: forming a groove in a semiconductor substrate layer, and enabling the groove to extend into a part of the semiconductor substrate layer from one side surface of the semiconductor substrate layer; forming a superlattice layer on the inner wall of the groove and the surface of the semiconductor substrate layer at the side part of the groove; forming an insulating protection layer on the surface of one side, deviating from the semiconductor substrate layer, of the superlattice layer; forming a conductive layer on the surface of one side, deviating from the superlattice layer, of the insulating protection layer, wherein the groove in one side, deviating from the insulating protection layer, of the conductive layer serves as a gap; and cutting the initial sample by adopting a focused ion beam to form a test sample, and enabling a cutting surface adopted by cutting to pass through the gap and to be vertical to the semiconductor substrate layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a test sample and a preparation method thereof. Background Art

[0002] In the field of photonic crystal surface emitting laser (PCSEL), the introduction of periodic two-dimensional photonic crystal micro-nano structures into the PCSEL through secondary epitaxy technology can control the light field mode to obtain higher performance. At the same time, the core technology of PCSEL is to prepare buried air holes. Different from the growth of materials on the traditional two-dimensional (2D) flat substrate, the process of growing buried air holes on the uneven three-dimensional (3D) micro-nano structure surface is quite complicated. There are also many difficulties in studying the dynamics of this process. First, three-dimensional (3D) micro-nano structures often have multiple crystal planes in different directions. During the secondary epitaxy process, the material will grow at different rates along different crystal directions based on different crystal planes at the same time. There are too many crystal planes involved, and the difficulty of research is also increased. Secondly, after the secondary epitaxy, the air holes are completely buried. The air holes must be exposed by cleavage or FIB (Focused Ion Beam) sample preparation before the next step of research can be carried out, which increases the difficulty of sample preparation.

[0003] Heterojunction-super lattice epitaxial growth technology is currently the main means to study the crystal orientation and dynamics of materials. It is characterized by periodic alternation of epitaxial layers of different components during epitaxy. Due to the difference in relative atomic mass and contrast of epitaxial layers of different components, transmission electron microscopy (TEM) can distinguish different epitaxial layers and measure the growth thickness of materials in different crystal orientations in a direction, thereby studying its growth mechanism. Preparing test samples through FIB is an important step. Summary of the invention

[0004] Therefore, the technical problem to be solved by the present invention is how to reduce the damage of the test sample, thereby providing a test sample and a preparation method thereof.

[0005] The present application provides a test sample, comprising: a semiconductor substrate layer, wherein the semiconductor substrate layer has a groove, wherein the groove extends from one side surface of the semiconductor substrate layer to a portion of the semiconductor substrate layer; a superlattice layer, located on the inner wall of the groove and the surface of the semiconductor substrate layer on the side of the groove; an insulating protective layer, located on the side surface of the superlattice layer away from the semiconductor substrate layer; and a conductive layer, located on the side surface of the insulating protective layer away from the insulating protective layer, wherein the groove on the side of the conductive layer away from the insulating protective layer serves as a gap.

[0006] Optionally, the material of the insulating protection layer contains at least silicon oxide.

[0007] Optionally, the width of the test sample in a first direction is 60 nm to 80 nm, and the first direction is parallel to the surface of the semiconductor substrate layer.

[0008] Optionally, the thickness of the insulating protective layer is 10nm~30nm.

[0009] Optionally, the concentration of Al atoms in the insulating protection layer decreases, increases, or remains unchanged in a direction from the superlattice layer to the conductive layer.

[0010] The present application also provides a method for preparing a test sample, comprising: forming an initial sample, comprising: forming a groove in a semiconductor substrate layer, wherein the groove extends from a side surface of the semiconductor substrate layer to a portion of the semiconductor substrate layer; forming a superlattice layer on an inner wall of the groove and a surface of the semiconductor substrate layer on a side of the groove; forming an insulating protective layer on a side surface of the superlattice layer away from the semiconductor substrate layer; forming a conductive layer on a side surface of the insulating protective layer away from the superlattice layer, wherein the groove on a side of the conductive layer away from the insulating protective layer serves as a gap; and cutting the initial sample using a focused ion beam to form a test sample, wherein a cutting surface used for cutting passes through the gap and is perpendicular to the semiconductor substrate layer.

[0011] Optionally, forming the insulating protection layer includes: forming a semiconductor film on a surface of the superlattice layer facing away from the semiconductor substrate layer, wherein the semiconductor film has Al atoms; and oxidizing the semiconductor film to form the insulating protection layer.

[0012] Optionally, the material of the semiconductor film includes Al y Ga (1-y) As, y is greater than 0.95 and less than 1.

[0013] Optionally, the superlattice layer and the semiconductor film are formed continuously in the same chamber.

[0014] Optionally, the superlattice layer and the semiconductor film are continuously formed in the same chamber using a metal organic chemical vapor deposition process.

[0015] Optionally, the concentration of Al atoms in the semiconductor film decreases, increases, or remains unchanged in a direction from the side of the semiconductor film toward the superlattice layer to the side of the semiconductor film away from the superlattice layer; the concentration of Al atoms in the insulating protective layer decreases, increases, or remains unchanged in a direction from the superlattice layer to the conductive layer.

[0016] The technical solution of the present invention has the following beneficial effects: In the method for preparing the test sample provided by the technical solution of the present invention, during the process of forming the conductive layer and the process of cutting the initial sample, the insulating protective layer can protect the superlattice layer and reduce the damage to the superlattice layer.

[0017] Furthermore, forming the insulating protective layer includes: forming a semiconductor film on the surface of the superlattice layer away from the semiconductor substrate layer, wherein the semiconductor film contains Al atoms; and oxidizing the semiconductor film so that the semiconductor film forms the insulating protective layer. The semiconductor film contains Al atoms, and due to the oxygen affinity of Al, the semiconductor film is easily oxidized to form the insulating protective layer, thereby achieving in-situ growth control.

[0018] Furthermore, the superlattice layer and the semiconductor film can be continuously formed in the same chamber, which can reduce the introduction of other impurity atoms into the interface between the superlattice layer and the semiconductor film, improve sample preparation efficiency, and ensure data in situ. Secondly, the superlattice layer and the semiconductor film are continuously formed in the same chamber, which causes minimal damage to the superlattice layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A flow chart of a method for preparing a test sample according to an embodiment of the present application; Figures 2 to 7 Schematic diagram of the structure of the test sample preparation process in one embodiment of the present application. DETAILED DESCRIPTION

[0021] On this basis, the embodiments of the present application provide a test sample and a preparation method thereof to reduce damage to the test sample.

[0022] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0024] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0025] An embodiment of the present invention provides a method for preparing a test sample, referring to Figure 1 ,include: Step S1: forming an initial sample, comprising: forming a groove in a semiconductor substrate layer, wherein the groove extends from a side surface of the semiconductor substrate layer to a part of the semiconductor substrate layer; forming a superlattice layer on an inner wall of the groove and a surface of the semiconductor substrate layer on a side of the groove; forming an insulating protection layer on a side surface of the superlattice layer away from the semiconductor substrate layer; forming a conductive layer on a side surface of the insulating protection layer away from the superlattice layer, wherein the groove on a side of the conductive layer away from the insulating protection layer serves as a gap; Step S2: using a focused ion beam to cut the initial sample to form a test sample, wherein the cutting surface passes through the gap and is perpendicular to the semiconductor substrate layer.

[0026] In this embodiment, during the process of forming the conductive layer and cutting the initial sample, the insulating protective layer can protect the superlattice layer and reduce damage to the superlattice layer.

[0027] In this embodiment, forming the insulating protective layer includes: forming a semiconductor film on the surface of the superlattice layer away from the semiconductor substrate layer, wherein the semiconductor film contains Al atoms; and oxidizing the semiconductor film so that the semiconductor film forms the insulating protective layer. The semiconductor film contains Al atoms, and due to the oxygen affinity of Al, the semiconductor film is easily oxidized to form the insulating protective layer, thereby achieving in-situ growth control.

[0028] Combine the following Figures 2 to 7 The preparation process of the test samples is described in detail.

[0029] refer to Figures 2 to 6 , forming the initial sample.

[0030] refer to Figure 2, a groove 110 is formed in the semiconductor substrate layer 100 , wherein the groove 110 extends from a side surface of the semiconductor substrate layer 100 to a portion of the semiconductor substrate layer 100 .

[0031] The material of the semiconductor substrate layer 100 may be a III-V compound semiconductor, a silicon wafer or sapphire. The III-V compound semiconductor includes but is not limited to GaAs, GaSb, GaN or InP.

[0032] One side surface of the semiconductor substrate layer 100 has a three-dimensional concave-convex structure, which includes a plurality of protrusions and grooves 110 corresponding to the protrusions. The size of the protrusions is micrometer-level or nanometer-level. The size of the grooves 110 is micrometer-level or nanometer-level.

[0033] refer to Figure 3 A superlattice layer 120 is formed on the inner wall of the groove 110 and the surface of the semiconductor substrate layer 100 at the side of the groove 110 .

[0034] In one embodiment, the process of forming the superlattice layer 120 includes metal organic chemical vapor deposition.

[0035] In one embodiment, forming the superlattice layer 120 includes: forming alternately stacked first semiconductor layers 121 and second semiconductor layers 122 on the inner wall of the groove 110 and the surface of the semiconductor substrate layer 100 at the side of the groove 110. The material of the second semiconductor layer 122 is different from that of the first semiconductor layer 121.

[0036] In one embodiment, the material of the first semiconductor layer 121 includes any one of AlAs, GaAs and AlGaAs. The material of the second semiconductor layer 122 includes any one of AlAs, GaAs and AlGaAs.

[0037] If the thickness of the first semiconductor layer 121 and the thickness of the second semiconductor layer 122 are too thick, the number of periods of the first semiconductor layer 121 and the second semiconductor layer 122 is limited, which makes it difficult to study the dynamics of the superlattice layer 120; if the thickness of the first semiconductor layer 121 and the thickness of the second semiconductor layer 122 are too thin, it is difficult to measure the thickness of the first semiconductor layer 121 and the second semiconductor layer 122, and it is difficult to distinguish the first semiconductor layer 121 and the second semiconductor layer 122 under a transmission electron microscope. If the difference between the thickness of the first semiconductor layer 121 and the thickness of the second semiconductor layer 122 is too small or too large, it will affect the first semiconductor layer 121 and the second semiconductor layer 122 under a transmission electron microscope and affect the difficulty of measuring the first semiconductor layer 121 and the second semiconductor layer 122. Therefore, in one embodiment, the thickness of the first semiconductor layer 121 is 8nm-15nm, such as 8nm, 10nm, 12nm or 15nm; the thickness of the second semiconductor layer 122 is 1nm-5nm, such as 1nm, 3nm or 5nm.

[0038] refer to Figure 4 and Figure 5 An insulating protection layer 131 is formed on a surface of the superlattice layer 120 that is away from the semiconductor substrate layer 100 .

[0039] refer to Figure 4 A semiconductor film 130 is formed on a surface of the superlattice layer 120 facing away from the semiconductor substrate layer 100 , wherein the semiconductor film 130 contains Al atoms.

[0040] In one embodiment, the material of the semiconductor film 130 includes Al y Ga (1-y) As, y is greater than 0.95 and less than 1. Using Al with high aluminum composition y Ga (1-y) As is conducive to the subsequent oxidation to form a dense composite aluminum oxide film, which is the subsequent insulating protective layer. The oxidation degree of the insulating protective layer and the thickness difference of the insulating protective layer can be observed by transmission electron microscopy in different crystal directions, as well as the reduction kinetics process.

[0041] In one embodiment, the process of forming the semiconductor film 130 includes a metal organic chemical vapor deposition process. The semiconductor film 130 is formed by the metal organic chemical vapor deposition process, and the surface of the super lattice layer 120 is minimally damaged.

[0042] In one embodiment, the superlattice layer 120 and the semiconductor film 130 are continuously formed in the same chamber, which can reduce the introduction of other impurity atoms into the interface between the superlattice layer 120 and the semiconductor film 130, improve sample preparation efficiency, and ensure data in situ.

[0043] In one embodiment, the superlattice layer 120 and the semiconductor film 130 are continuously formed in the same chamber using a metal organic chemical vapor deposition process, and the damage to the superlattice layer 120 is minimal.

[0044] In one embodiment, the thickness of the semiconductor film 130 is 10 nm to 30 nm. If the thickness of the semiconductor film 130 is too thin, it is not enough to oxidize to obtain a sufficient insulating protective layer, and the protective effect of the insulating protective layer 131 on the superlattice layer 120 is weakened; if the thickness of the semiconductor film 130 is too thick, it is not conducive to forming a gap with sufficient space, and it is difficult to determine the position of cutting the initial sample by the light transmittance of the gap, which increases the difficulty of sample preparation.

[0045] In one embodiment, the growth temperature used in the process of forming the semiconductor film 130 is 680° C.-700° C.

[0046] In one embodiment, the growth rate of semiconductor film 130 is 4 Å-8 Å / s.

[0047] refer to Figure 5 , the semiconductor film 130 is oxidized to form an insulating protection layer 131 of the semiconductor film 130.

[0048] In one embodiment, the process of oxidizing the semiconductor film 130 is a wet oxidation process, which provides a high temperature and high humidity water vapor environment to improve the density of the formed insulating protection layer 131. The insulating protection layer 131 improves the protection effect of the superlattice layer 120.

[0049] In one embodiment, the oxidation time of the wet oxidation process is 6 hours to 24 hours.

[0050] In other embodiments, the process of oxidizing the semiconductor film 130 is a dry oxidation process.

[0051] In one embodiment, the insulating protective layer 131 contains at least silicon oxide. Silicon oxide has a high hardness, and the insulating protective layer 131 has a good supporting performance, which is conducive to forming a thinner test sample in the future, and is convenient for photographing the structure of the test sample using a transmission electron microscope.

[0052] In one embodiment, the concentration of Al atoms in the semiconductor film 130 decreases or increases in the direction from the side of the semiconductor film 130 facing the superlattice layer 120 to the side of the semiconductor film 130 facing away from the superlattice layer 120. The degree of oxidation of the semiconductor film 130 in different crystal directions is different, and the thickness of the insulating protection layer 131 in different crystal directions is different. The concentration difference of Al atoms in the semiconductor film 130 can increase the thickness difference of the insulating protection layer 131 in different crystal directions. The kinetic process can be further restored by observing the gradual change characteristics of the insulating protection layer 131 under a transmission electron microscope. Accordingly, the concentration of Al atoms in the insulating protection layer 131 decreases or increases in the direction from the side of the insulating protection layer 131 facing the superlattice layer 120 to the side of the insulating protection layer 131 facing away from the superlattice layer 120.

[0053] In one embodiment, the concentration of Al atoms in the semiconductor film 130 remains unchanged in a direction from the side of the semiconductor film 130 toward the superlattice layer 120 to the side of the semiconductor film 130 away from the superlattice layer 120; the concentration of Al atoms in the insulating protective layer 131 remains unchanged in a direction from the side of the insulating protective layer 131 toward the superlattice layer 120 to the side of the insulating protective layer 131 away from the superlattice layer 120.

[0054] In one embodiment, when the material of the semiconductor film 130 includes Al y Ga (1-y) When As, the material of the insulating protection layer 131 is a mixture of Al2O3, Ga2O3 and As2O5.

[0055] In one embodiment, the insulating protection layer 131 includes a first sub-insulating protection layer and a second sub-insulating protection layer, wherein the second sub-insulating protection layer is located on a side of the first sub-insulating protection layer away from the superlattice layer 120, and the material of the second sub-insulating protection layer is a mixture of Al2O3, Ga2O3 and As2O5, and the material of the first sub-insulating protection layer is Al x Ga 1-x As y O 1-y .

[0056] refer to Figure 6 A conductive layer 140 is formed on a surface of the insulating protection layer 131 on a side away from the superlattice layer 120 , and the groove on the side of the conductive layer 140 away from the insulating protection layer 131 serves as a gap 110 a .

[0057] The process of forming the conductive layer 140 includes a sputtering process.

[0058] In the process of forming the conductive layer 140 by the sputtering process, the insulating protection layer 131 can protect the superlattice layer 120 , avoid ion bombardment of the superlattice layer 120 by the sputtering process, and reduce damage to the superlattice layer 120 .

[0059] In one embodiment, the concentration of Al atoms in the insulating protection layer 131 decreases or increases from the superlattice layer to the conductive layer. In another embodiment, the concentration of Al atoms in the insulating protection layer 131 remains unchanged from the superlattice layer to the conductive layer.

[0060] refer to Figure 7 The initial sample is cut using a focused ion beam 150 to form a test sample, and the cutting surface used for cutting passes through the gap 110 a and is perpendicular to the semiconductor substrate layer 100 .

[0061] The focused ion beam includes, for example, a Ga ion beam.

[0062] The insulating protection layer 131 can reduce the influence of the focused ion beam on forming a high current in the superlattice layer.

[0063] When the initial sample is cut by the focused ion beam 150 , the insulating protection layer 131 can protect the superlattice layer 120 .

[0064] Since the insulating protection layer 131 can protect the superlattice layer 120 , the success rate of preparing the test sample is improved.

[0065] The test sample is used for testing under a transmission electron microscope. Due to the different conductivity of the first semiconductor layer 121 and the second semiconductor layer 122, the first semiconductor layer 121 and the second semiconductor layer 122 can be clearly distinguished by using a transmission electron microscope.

[0066] The present application provides a test sample, comprising: a semiconductor substrate layer, wherein the semiconductor substrate layer has a groove, wherein the groove extends from one side surface of the semiconductor substrate layer to a portion of the semiconductor substrate layer; a superlattice layer, located on the inner wall of the groove and the surface of the semiconductor substrate layer on the side of the groove; an insulating protective layer, located on the side surface of the superlattice layer away from the semiconductor substrate layer; and a conductive layer, located on the side surface of the insulating protective layer away from the insulating protective layer, wherein the groove on the side of the conductive layer away from the insulating protective layer serves as a gap.

[0067] Optionally, the material of the insulating protection layer contains at least silicon oxide.

[0068] Optionally, the width of the test sample in a first direction is 60 nm to 80 nm, and the first direction is parallel to the surface of the semiconductor substrate layer.

[0069] Optionally, the thickness of the insulating protection layer is 10 nm-30 nm, for example, 10 nm, 20 nm or 30 nm.

[0070] Optionally, the concentration of Al atoms in the insulating protection layer decreases, increases, or remains unchanged in a direction from the superlattice layer to the conductive layer.

[0071] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A test sample, characterized in that: include: A semiconductor substrate layer, wherein the semiconductor substrate layer has a groove, and the groove extends from a side surface of the semiconductor substrate layer to a portion of the semiconductor substrate layer; A superlattice layer is located on the inner wall of the groove and the surface of the semiconductor substrate layer at the side of the groove; An insulating protection layer, located on a surface of the superlattice layer facing away from the semiconductor substrate layer; The conductive layer is located on a surface of the insulating protective layer on a side away from the insulating protective layer, and the groove on the side of the conductive layer away from the insulating protective layer serves as a gap.

2. The test sample according to claim 1, characterized in that: The insulating protection layer contains at least silicon oxide.

3. The test sample according to claim 1, characterized in that: The width of the test sample in a first direction is 60 nm to 80 nm, and the first direction is parallel to the surface of the semiconductor substrate layer.

4. The test sample according to claim 1, characterized in that: The thickness of the insulating protection layer is 10nm-30nm.

5. The test sample according to claim 1, characterized in that: The concentration of Al atoms in the insulating protection layer decreases, increases, or remains unchanged in a direction from the superlattice layer to the conductive layer.

6. A method for preparing a test sample, characterized in that: include: Forming an initial sample, including: forming a groove in a semiconductor substrate layer, the groove extending from a side surface of the semiconductor substrate layer to a portion of the semiconductor substrate layer; forming a superlattice layer on an inner wall of the groove and a surface of the semiconductor substrate layer on a side of the groove; forming an insulating protection layer on a side surface of the superlattice layer away from the semiconductor substrate layer; forming a conductive layer on a side surface of the insulating protection layer away from the superlattice layer, the groove on a side of the conductive layer away from the insulating protection layer serving as a gap; The initial sample is cut by using a focused ion beam to form a test sample, wherein a cutting surface used in the cutting passes through the gap and is perpendicular to the semiconductor substrate layer.

7. The method for preparing a test sample according to claim 6, characterized in that: The forming of the insulating protection layer comprises: forming a semiconductor film on the surface of the superlattice layer away from the semiconductor substrate layer, wherein the semiconductor film has Al atoms; and oxidizing the semiconductor film so that the semiconductor film forms the insulating protection layer.

8. The method for preparing a test sample according to claim 7, characterized in that: The material of the semiconductor film includes Al y Ga (1-y) As, y is greater than 0.95 and less than 1.

9. The method for preparing a test sample according to claim 7, characterized in that: The superlattice layer and the semiconductor film are continuously formed in the same chamber.

10. The method for preparing a test sample according to claim 9, characterized in that: The superlattice layer and the semiconductor film are continuously formed in the same chamber by adopting a metal organic chemical vapor deposition process.

11. The method for preparing a test sample according to claim 7, characterized in that: The concentration of Al atoms in the semiconductor film decreases from the side of the semiconductor film toward the superlattice layer to the side of the semiconductor film away from the superlattice layer, and the concentration of Al atoms in the insulating protection layer decreases, increases, or remains unchanged from the superlattice layer to the conductive layer.

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