Bit stream analysis and dynamic editing method for LUT resources in Xilinx FPGA

Abstract

The invention discloses a bit stream analysis and dynamic editing method for LUT resources in a Xilinx FPGA, and the method comprises the following steps: S1, intercepting bit stream data, and extracting the contents of all LUT resources in combination with the structure information of the FPGA; s2, generating a to-be-searched item list of bit stream storage values from the content of any target LUT truth table according to all possible bit stream arrangement modes according to a mapping relation between pins and bit streams; s3, traversing the list of items to be searched in the content extracted in the step S1, and calculating and configuring a target frame address and an intra-frame offset related to the LUT according to the physical address of the target LUT after positioning; s4, calling an ICAP interface, inputting a read command sequence, reading frame data containing target LUT information, and storing the frame data in a BRAM; and S5, calling an ICAP interface, inputting a write command sequence, modifying the frame data in the BRAM, and writing the modified frame data back to a corresponding frame. The problems that in the prior art, the analysis integrity of the arrangement mode of the LUT in the bit stream is insufficient, and the efficiency and precision are low when resources in the FPGA are dynamically reconfigured are solved.

Description

Technical Field

[0001] The invention belongs to the field of FPGA dynamic reconfiguration, and in particular relates to a bit stream parsing and dynamic editing method for LUT resources in Xilinx FPGA. Background Art

[0002] Thanks to its high parallelism and user-programmable features, FPGA has been increasingly widely used in the implementation of various high-performance computing. With the further increase in design complexity, how to accurately and effectively configure and manage the logic resources in it has important research significance. Xilinx provides an internal configuration access port (ICAP) for SRAM-based FPGAs for dynamic partial reconfiguration (DPR). After activating this interface, the configuration memory can be accessed at runtime and specific parts can be modified, while the rest of the parts can remain normal without being affected by these specific modifications.

[0003] Dynamic partial reconstruction can be used at different granularity levels, including partial bitstreams, IP cores, and basic logic components such as LUTs (Look up tables) and BRAMs. Since FPGA manufacturers do not disclose the proprietary format and mapping information of bitstreams, if you only have access to the bitstream file, if you want to further reconfigure the LUTs and other logic elements in it, you first need to parse and restore their distribution and arrangement in the bitstream to a certain extent. In recent years, researchers at home and abroad have designed high-performance ICAP controllers to read and write partial bitstreams or configuration frames to detect and correct faults in configuration memory; some studies have also implemented runtime reconfiguration at the LUT level, but have not detailed the specific storage and distribution of LUT configuration bits, or are only applicable to older FPGA devices, and there are few corresponding studies on 7 series and more advanced devices.

[0004] The prior art has the following problems:

[0005] (1) Existing literature and tools have little research on the addressing and configuration methods of LUTs and their mapping rules in bitstreams. There is a lack of effective methods to extract the storage location of LUT resources from bitstreams with high accuracy and speed and match their logical information with the content of the bitstream.

[0006] (2) Since it is impossible to accurately locate the LUT resources in the bitstream, especially the LUT of the specified logic function, the existing technology mainly focuses on the dynamic reconfiguration of part of the bitstream. The operation scope remains in a larger dimension. There is less research on targeted dynamic modification of finer-grained logic resources, which lacks accuracy and flexibility. Summary of the invention

[0007] In view of the above shortcomings in the prior art, the present invention provides an accurate and efficient bitstream parsing and dynamic editing method for LUT resources in Xilinx FPGA in order to overcome the above problems. After the location and logic information of LUT resources in the bitstream are quickly extracted and searched, the truth table content of the specified LUT can be modified through the ICAP interface at runtime to change its function. Different from the reconfiguration at the bitstream level, this method directly dynamically edits the logic function of the fine-grained resource LUT in the device, and can be operated during the operation of the device, thereby improving the accuracy and flexibility of FPGA configuration and management of internal logic resources.

[0008] The technical solution adopted by the present invention to solve the technical problem is:

[0009] A method for bitstream parsing and dynamic editing of LUT resources in Xilinx FPGA includes the following steps:

[0010] S1: intercepts the bitstream data, combines it with the FPGA structure information, and extracts the content of all LUT resources;

[0011] S2: According to the mapping relationship between pins and bitstreams, the contents of any target LUT truth table are arranged according to all possible bitstream arrangements to generate a list of bitstream storage value items to be searched;

[0012] S3: traverse the list of items to be searched in the content extracted by S1, and after locating, calculate the target frame address and the offset within the frame involved in configuring the LUT according to the physical address of the target LUT;

[0013] S4: Call the ICAP interface, input the read command sequence, read the frame data containing the target LUT information and store it into BRAM;

[0014] S5: Call the ICAP interface, input a write command sequence, modify the frame data in the BRAM and write it back to the corresponding frame.

[0015] Furthermore, in step S1, the extraction of the LUT content at each physical address includes the following steps:

[0016] S1-1: Create a blank project, do not instantiate any logic unit or I / O interface, and generate a blank bitstream comparison file;

[0017] S1-2: Select a reference CLB, instantiate each initial value of all LUTs in it to all 1s and generate a bit stream, and obtain the position range of the configuration bit set of the current LUT in the complete bit stream through the difference bits with the blank bit stream;

[0018] S1-3: Select another CLB to be tested, instantiate the LUTs in the reference CLB and the CLB to be tested to the same initial value, generate a bit stream and calculate the offset between the LUT configuration bit set addresses corresponding to the reference CLB and the CLB to be tested;

[0019] S1-4: Combined with the underlying structure of the FPGA, using the mapping information and offset information of each LUT configuration bit in the reference CLB in the bitstream, traverse the CLBs at all physical addresses in the chip to obtain the specific storage locations of the configuration bits of all LUTs therein in the bitstream;

[0020] S1-5: intercept the complete bitstream that has been loaded into the device for operation, extract the contents of all LUT resources in the bitstream according to the location information of the LUT resources obtained in S1-4, and correspond them to the physical addresses in the device.

[0021] Further, in step S2, the LUT truth table content corresponds to the generation of the stored value in the bit stream, including the following steps:

[0022] S2-1: IA mapping relationship extraction: Match the LUT input pins instantiated in the code with the actual LUT pins optimized by the FPGA synthesis tool, and restore the N possible pin arrangements of the N input LUT;

[0023] S2-2: INIT-BIT mapping relationship extraction: By instantiating each configuration bit of different types of LUTs separately and comparing them with the blank bit stream, the 2 N The INIT value of the bit truth table is the same as the 2 N The corresponding relationship between the storage order of bit BIT values;

[0024] S2-3: Generate items to be searched: Convert the original truth table content of the target LUT according to all possible pin arrangement combinations and bit value storage mapping relationships, and generate a list of items to be searched whose truth table content corresponds to the actual storage values ​​in the bit stream.

[0025] Furthermore, in step S3, the list of items to be searched obtained in S2-3 is traversed in the partial bitstream containing all LUT contents extracted in S1-5 to screen out the specific storage value and storage location of the target LUT in the bitstream, thereby determining the physical address of the target LUT.

[0026] The frame address set of all frames involved in configuring the LUT is derived from the physical coordinates of the CLB column and Slice, so as to prepare for the subsequent reading and writing of data on these specific frame addresses;

[0027] The offset of the 32-bit word where the LUT configuration bit is located in the relevant frame is derived from the vertical coordinate of the slice where it is located, so as to locate the specific address in the BRAM during modification and rewrite the frame data stored therein in a targeted manner;

[0028] The actual pin mapping relationship under the current search result is recorded in case that the original value is overwritten with the new truth table content in the future, and the new frame data can be converted by the determined mapping relationship and then obtained after bit stream mapping.

[0029] Further, in step S4, frame data is read using the ICAP interface, including the following steps:

[0030] S4-1: Initialization: Enable csib and rdwrb control signals, set the interface direction to write mode, synchronize the ICAP interface, reset CRC, etc.

[0031] S4-2. Input relevant parameters: Activate RCFG, and input the read-back start frame address and the total number of words to be read according to the target frame address set obtained in step 3;

[0032] S4-3: Execute readback: switch the interface direction to read mode, wait for several cycles and save the frame data read back through the ICAP interface in BRAM, and switch to write mode again after receiving all the read-back data to complete the desynchronization operation.

[0033] Further, in step S5, the modified frame data is written back using the ICAP interface, including the following steps:

[0034] S5-1: Initialization: Enable csib and rdwrb control signals, set the interface direction to write mode, synchronize the ICAP interface, reset CRC, etc.

[0035] S5-2. Input relevant parameters: After inputting the device IDCODE for verification, input the same write-back start frame address and the number of frames to be written back as when performing the read operation in step 4;

[0036] S5-3. Write back after modification: For all frame data read back, according to the offset information of the target LUT configuration bit in the frame, make targeted modifications to it, and input the modified write-back data in sequence through the ICAP interface;

[0037] S5-4: Secondary read-back verification: The read-back process is performed again on all data at the target frame address, and compared with the original data read to the BRAM in S4-3 to determine whether the rewrite operation is successful.

[0038] Beneficial effects of the present invention:

[0039] (1) The present invention provides a method for quickly and flexibly reconfiguring the logic function of any LUT. The method can realize dynamic reconfiguration of a LUT with specific content by calling the ICAP interface during the operation of the device. Compared with the method of modifying the content of the bitstream file and then re-burning it through an external interface such as JTAG, the hardware structure complexity is lower and the speed is faster.

[0040] (2) The present invention can search for the storage location of the LUT configuration value of any truth table content in the bit stream and obtain its corresponding frame address in the configuration memory, thereby performing targeted fine-grained modification on the corresponding data in the memory online, solving the problems of insufficient integrity of LUT information restoration, low efficiency, and low accuracy of FPGA resource reconfiguration in the prior art.

[0041] (3) Modifying the logical function of the LUT at runtime and accessing and manipulating the internal data of the FPGA in real time can be further developed into targeted modifications to the functions and algorithms implemented by the FPGA, thereby providing an effective means of performing content tampering, fault injection and other attacks directly at the configuration memory level. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a flow chart of the bitstream parsing and dynamic editing method for LUT resources in Xilinx FPGA;

[0043] Figure 2 State transition diagram for the ICAP interface read / write module state machine implementation. DETAILED DESCRIPTION

[0044] The specific embodiments of the present invention are described below.

[0045] A bitstream parsing and dynamic editing method for LUT resources in Xilinx FPGA, such as Figure 1 As shown, the following steps are included:

[0046] S1: intercept the FPGA bit stream data, combine it with the FPGA structure information, extract the content of all LUT resources and correspond them to their physical addresses respectively.

[0047] Currently, mainstream SRAM-based FPGA bitstreams are stored in external non-volatile memories such as Flash or EEPROM, and can usually be read out directly or obtained by eavesdropping on the FPGA's configuration bus during power-on.

[0048] Through the -report command in xdl.exe provided by Xilinx's official EDA tool ISE, you can obtain the structural information of the specified FPGA model and generate an xdlrc file including the number, location and all possible configuration states of various types of internal resources.

[0049] The extraction of LUT content at each physical address includes the following steps:

[0050] S1-1: Create a blank project, do not instantiate any logic unit or I / O interface, generate a blank bitstream comparison file, and turn off DRC design rule checking during the entire test process;

[0051] S1-2. Select a reference CLB, instantiate the initial value of one LUT in it to all 1s and generate a bit stream, and obtain the position range of all configuration bits of the LUT in the complete bit stream from the difference between it and the blank bit stream. Perform the same operation on other LUTs in the CLB and store the position information of these bit stream configuration bits accordingly;

[0052] S1-3: Select another CLB to be tested, instantiate the LUTs in the reference CLB and the CLB to be tested to the same initial value, generate bit streams respectively, and calculate the offset between the configuration bit addresses of each LUT in the reference and the CLB to be tested;

[0053] S1-4: Combined with the underlying structure and resource arrangement rules of the FPGA, using the mapping information and offset information of each LUT configuration bit in the reference CLB in the bitstream, traverse the CLBs at all physical addresses in the chip to obtain the specific storage locations of the configuration bits of all LUTs in the bitstream;

[0054] S1-5: intercept the complete bitstream file that has been loaded into the device for operation, extract the contents of all LUT resources therein according to the storage location information of the LUT resources in the bitstream obtained in S1-4, and correspond them to the physical addresses in the device.

[0055] S2: According to the mapping relationship between the pins of the LUT resources and the bitstream, the content of the truth table of the arbitrarily selected target LUT is converted according to all possible pin arrangements and the storage rules in the bitstream to generate a list of bitstream storage value items to be searched.

[0056] The LUT stores the extraction of mapping rules in the bitstream and the generation of items to be searched, including the following steps:

[0057] S2-1: IA mapping relationship extraction: The N input pins (I0-I N-1 ) and the on-chip pins (A0-A N-1) to correspond, restoring the N! possible pin arrangements of the N-input LUT in theory;

[0058] S2-2: Extraction of INIT-BIT mapping relationship: By instantiating each configuration bit of the N-input LUT separately and comparing it with the blank bit stream, the 2 N The INIT value of the bit truth table is the same as the 2 N The corresponding relationship of the storage order of the bit BIT value is shown in Table 1. The mapping rules of different types of LUTs in SLICEM and SLICEL in CLB are restored according to this operation;

[0059] The following table shows the storage arrangement of the LUT truth table contents in all SLICELs of a CLB column in the bitstream, involving the contents of 26 lines 2648-2673 of the bitstream file, and the storage format of each line in the bitstream is 4 32-bit words.

[0060] Table 1. LUT resource mapping rules in the configuration frame corresponding to SLICEL in a CLB column

[0061]

[0062] The row offset values ​​listed in the table are from the start bit of the header file of the bitstream. Due to different header file lengths, the row offset values ​​will be different. In the table, SX represents the ordinate position of a slice, and AX-DX represent the specific number of bits in the LUTA-LUTD 64-bit truth table configuration bits contained in a slice. For example, S50 in the table represents Slice_X0Y50, S51 represents Slice_X0Y51, and so on; B63 represents the 63rd bit of the initial value of the 64-bit truth table in LUTB, and so on.

[0063] S2-3: Generate items to be searched: Convert the original truth table content of any selected target LUT according to all possible pin arrangement combinations and bit value storage mapping relationships. With the help of script commands, a list of items to be searched corresponding to the actual storage values ​​in the bit stream can be automatically generated.

[0064] S3: traverse the list of items to be searched in the extracted bitstream content containing all LUT resources, and after locating, calculate all target frame addresses and intra-frame offsets involved in configuring the LUT according to the physical address of the target LUT.

[0065] After finding the storage location of the LUT content in the bitstream, firstly derive the frame address set of all frames involved in configuring the LUT according to the physical coordinates of the corresponding CLB column and Slice.

[0066] Taking the 7 series device as an example, a CLB configuration frame containing 101 32-bit words has a configuration range involving 50 slices in a column, including the contents of 4 LUTs belonging to the same slice. Therefore, only 2 bytes of a LUT can be configured. To configure a complete LUT, 4 consecutive frames are required. The starting frame address can be calculated from the coordinate information of the CLB and Slice where the LUT is located, as shown in Table 2.

[0067] The frame address consists of five parts. The block type of 000 represents CLB. The upper / lower selection bits and row address are determined by the position of the Clock Region. The column address is determined by the X coordinate of the CLB. The specific frame number address is determined by the X coordinate of the Slice.

[0068] Table 2. Frame address representation of LUT at a certain physical address

[0069]

[0070] After determining the frame address range, the offset of the 32-bit word where the LUT configuration bit is located in the relevant frame is derived from the Y coordinate of the slice where it is located, so as to locate the specific address in the BRAM during modification and perform targeted partial rewriting of the frame data stored therein.

[0071] In addition, the actual pin mapping relationship under the current search result needs to be recorded in case the original value is overwritten with the new truth table content in the future, and the determined mapping relationship can be used for conversion, and then the new frame data can be obtained after bit stream mapping.

[0072] S4: Call the ICAP interface, input a read command sequence, read the frame data at all target frame addresses containing the target LUT configuration information, and store it in the BRAM for subsequent use.

[0073] Using the ICAP interface to read frame data includes the following steps:

[0074] S4-1: Initialization: Enable csib and rdwrb control signals, set the interface direction to write mode, synchronize the ICAP interface, reset CRC, etc.

[0075] S4-2: Input relevant parameters: Activate RCFG, and input the read-back start frame address and the total number of words to be read according to the target frame address set obtained in step 3;

[0076] S4-3: Execute readback: switch the interface direction to read mode, wait for several cycles and save the frame data read back through the ICAP interface in BRAM, and switch to write mode again after receiving all the read-back data to complete the desynchronization operation.

[0077] The entire process of reading through the ICAP interface can be done by Figure 2 After activating the read function of the ICAP interface, you need to enter the relevant parameters, including the start frame address and the total number of words to read back, Nwords. Since the first frame of the data read back is an additional padding frame, for the 7 series FPGA, each frame contains 101 32-bit words, the continuous N words starting from the start frame address are read back. f When the content on the frame is N, the number of words that need to be read back is N words The calculation formula is: words =101×(N f +1).

[0078] It can be concluded that when reading back the contents of four adjacent frames involved in a LUT, N f =4, then N words =505.

[0079] S5: Call the ICAP interface, input a write command sequence, modify the frame data in the BRAM and write it to the same frame address as step S4, and read it back again to verify whether the operation is successful.

[0080] Using the ICAP interface to write back the modified frame data includes the following steps:

[0081] S5-1: Initialization: Enable csib and rdwrb control signals, set the interface direction to write mode, synchronize the ICAP interface, reset CRC, etc.

[0082] S5-2: Input relevant parameters: After inputting the device IDCODE for verification, input the same write-back start frame address and the number of frames to be written back as when performing the read operation in step 4;

[0083] S5-3: Execute modified write-back: For all frame data read back, modify them in a targeted manner according to the offset information of the target LUT configuration bit in the frame, and input the modified write-back data in sequence through the ICAP interface;

[0084] S5-4: Secondary read-back verification: The read-back process is performed again on all data at the target frame address, and compared with the original data stored in the BRAM in S4-3 to determine whether the rewrite operation is successful.

[0085] like Figure 2 As shown, the write command sequence is similar to the read command sequence process, the difference is that the device IDCODE needs to be given to establish communication with the chip, and the input start frame address and the number of readback words are consistent with the read operation.

[0086] After reading out the frame data in the BRAM in sequence, according to the specific offset and pin mapping relationship of the target LUT configuration content, the new truth table content is converted accordingly and overwritten to a specific position in the frame data, and the rest remains unchanged. The partially modified valid frame data is attached with the padding frame and input into the ICAP interface in sequence, completing a targeted change to the LUT content in the configuration memory. Specific embodiment:

[0088] In the embodiment of the present invention, the standard test set ISCAS85 circuit and two practical applications of AES and DES are selected as test codes, Xilinx Artix-7 XC7A35T is used as the target chip, and Vivado is used to compile these test codes to generate bit streams. Combined with the bit stream and the known target LUT truth table information, the method described in the present invention can be used to search and modify the used LUT resources in a targeted manner, such as the LUT that implements the XOR gate, AND gate, full adder or other arbitrary specified logic function in ISCAS85; the LUT that implements the S-box function in encryption algorithms such as DES and AES.

[0089] As shown in Table 3, the permutation calculation function performed by a DES S-box converts 6-bit input into 4-bit output, which can be implemented with four 6-input LUTs, each LUT containing a column of output results. A complete DES design usually includes 8 S-boxes, totaling 32 LUTs.

[0090] Table 3. LUT implementation of 6-bit-to-4-bit DES S-box

[0091]

[0092] As a standard algorithm, the content of each S-box, that is, the truth table content of the four 6-input LUTs, is fixed. With the help of the decoded pin-to-bitstream mapping relationship, 6! = 720 possible storage bit values ​​in the bitstream can be obtained for each type of LUT. For the bitstream content containing all LUT resources, by traversing and searching the 720 arrangements of each type of LUT in turn, the storage positions of the four LUTs configuring a single S-box in the bitstream and the frame address sets involved are determined respectively, and the remaining 7 S-boxes are similar. In practical applications, certain combinations and deduplication can be used to reduce the number of searches and improve the efficiency of search and positioning.

[0093] Taking the first S-box Sbox1 as an example, the fixed truth table configuration of the four LUTs required to perform the replacement function is as follows:

[0094] LUT1=(a64,...,a1)=64'b1000011010011101010010010111101010000110111001100111011000011001;

[0095] LUT2=(b64,...,b1)=64'b1011000011000111100001110001101101001001011110000010011010111101;

[0096] LUT3=(c64,...,c1)=64'b0010011111101001110101001001001001100000100111110001111100101001;

[0097] LUT4=(d64,...,d1)=64'b1001000101111011111010010000011001101111100000011011010001111000.

[0098] In the bitstream from which all LUT information is extracted, the corresponding contents of the above LUT configuration values ​​after pin and bitstream mapping are searched respectively, and the arrangement pattern actually stored in the configuration memory is obtained as follows:

[0099] LUT1=(a64,...,a1)=0xc3722dc9e3295e92;

[0100] LUT2=(b64,...,b1)=0xe52976c2a995cba4;

[0101] LUT3=(c64,...,c1)=0x8ee16ba4971c497a;

[0102] LUT4=(d64,...,d1)=0x586b615e8e712d9c.

[0103] After identifying and locating the four target LUTs that perform the S-box function, obtaining the corresponding physical address and calculating the target frame address, the ICAP interface can be activated, the frame address and word count information can be input, and the data can be accessed and manipulated online in real time, such as setting its content to zero to make it completely invalid; or setting it to be equal to the input so that its nonlinear characteristics are destroyed, thereby weakening the encryption algorithm and providing an effective attack method for analyzing and cracking the key.

[0104] Observe the output port of ICAP, and the reading results of frame data are as follows:

[0105] Data at frame address 0000121A: xxxxxxxx...xxxx 8ee1586b c372e529xxxxxxxx...xxxx;

[0106] Data at frame address 0000121B: xxxxxxxx...xxxx 6ba4615e 2dc976c2xxxxxxxx...xxxx;

[0107] Data at frame address 0000121C: xxxxxxxx...xxxx 971c8e71 e329a995xxxxxxxx...xxxx;

[0108] Data at frame address 0000121D: xxxxxxxx...xxxx 497a2d9c 5e92cba4xxxxxxxx...xxxx.

[0109] Keep the rest of the contents in the frame unchanged, clear the contents of the target LUT and write it back to the same frame address. The result of reading it back again is as follows, indicating a successful operation.

[0110] Data at frame address 0000121A: xxxxxxxx...xxxx 00000000 00000000xxxxxxxx...xxxx;

[0111] Data at frame address 0000121B: xxxxxxxx...xxxx 00000000 00000000xxxxxxxx...xxxx;

[0112] Data at frame address 0000121C: xxxxxxxx...xxxx 00000000 00000000xxxxxxxx...xxxx;

[0113] Data at frame address 0000121D: xxxxxxxx...xxxx 00000000 00000000xxxxxxxx...xxxx.

[0114] The results of this method for identifying and dynamically reconfiguring the LUT of the specified truth table content in the above-mentioned various circuits in the bitstream are shown in Table 4. This method can accurately and quickly realize the whole process of extracting and locating any LUT content in the bitstream and further modifying it in a targeted manner.

[0115] Table 4. Bitstream parsing and dynamic editing results of LUT resources

[0116]

[0117] The bitstream parsing and dynamic editing method for LUT resources in Xilinx FPGA provided by the present invention restores the accurate bitstream mapping and position information of any LUT resource, and dynamically reconfigures it through the designed ICAP read-write state machine, which helps to manage and allocate the internal resources of FPGA in a fine-grained manner, and further control and adjust the functions or output results realized by it in real time, flexibly and efficiently.

[0118] As described above, although the present invention has been shown and described with reference to specific specific embodiments, it should not be construed as limiting the present invention itself. Various changes in form and details may be made without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A method for bitstream parsing and dynamic editing of LUT resources in Xilinx FPGA, characterized in that: The steps include: S1, intercept the bit stream data, combine the FPGA structure information, and extract the content of all LUT resources; S2. According to the mapping relationship between pins and bitstreams, the contents of any target LUT truth table are arranged according to all possible bitstream arrangements to generate a list of bitstream storage value items to be searched; S3, traversing the list of items to be searched in the content extracted in S1, and calculating the target frame address and the offset within the frame involved in configuring the LUT according to the physical address of the target LUT after locating the items; S4, calling the ICAP interface, inputting a read command sequence, reading the frame data containing the target LUT information and storing it in the BRAM; S5, call the ICAP interface, input the write command sequence, modify the frame data in the BRAM and write it back to the corresponding frame; In step S1, the extraction of the LUT content at each physical address includes the following steps: S1-1: Create a blank project, do not instantiate any logic unit or I / O interface, and generate a blank bitstream comparison file; S1-2: Select a reference CLB, instantiate all LUT initial values ​​in it to all 1s and generate a bit stream, and obtain the position range of the configuration bit set of the current LUT in the complete bit stream through the difference bits with the blank bit stream; S1-3: Select another CLB to be tested, instantiate the LUTs in the reference CLB and the CLB to be tested to the same initial value, generate a bit stream and calculate the offset between the LUT configuration bit set addresses corresponding to the reference CLB and the CLB to be tested; S1-4: Combined with the underlying structure of the FPGA, using the mapping information and offset information of each LUT configuration bit in the reference CLB in the bitstream, traverse the CLBs at all physical addresses in the chip to obtain the specific storage locations of the configuration bits of all LUTs therein in the bitstream; S1-5: intercept the complete bitstream that has been loaded into the device for operation, extract the contents of all LUT resources in the bitstream according to the location information of the LUT resources obtained in S1-4, and correspond them to the physical addresses in the device; In step S2, the content of the LUT truth table corresponds to the generation of the stored value in the bit stream, including the following steps: S2-1: IA mapping relationship extraction: Match the LUT input pin I instantiated in the code with the actual LUT pin A optimized by the FPGA synthesis tool, and restore the N possible pin arrangements of the N input LUT; S2-2: INIT-BIT mapping relationship extraction: By instantiating each configuration bit of different types of LUTs separately and comparing them with the blank bit stream, the 2 N The INIT value of the bit truth table is the same as the 2 N The corresponding relationship between the storage order of bit BIT values; S2-3: Generate items to be searched: Convert the original truth table content of the target LUT according to all possible pin arrangement combinations and bit value storage mapping relationships, and generate a list of items to be searched whose truth table content corresponds to the actual storage values ​​in the bit stream.

2. The method for parsing and dynamically editing specific LUT resources in Xilinx FPGA according to claim 1, characterized in that: The target LUT includes LUT resources at any physical address, with any number of input pins, and implementing any logic function.

3. The method for parsing and dynamically editing specific LUT resources in Xilinx FPGA according to claim 1, characterized in that: When dynamically editing the LUT content, the ICAP state machine is designed and implemented to directly control the read and write enable signals of the ICAP primitive and input the command sequence to realize the complete process of read back, modify, and write back on the FPGA hardware.

4. The method for parsing and dynamically editing specific LUT resources in Xilinx FPGA according to claim 1, characterized in that: The read and write operations of the configuration memory using the ICAP interface are performed in frames; the process of modifying the target LUT content according to its configuration bit offset is further refined to each 32-bit word within the frame.

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