Method and device for improving quality of epitaxial wafer, epitaxial wafer and manufacturing method thereof

Abstract

The invention provides a method and device for improving the quality of an epitaxial wafer, the epitaxial wafer and a manufacturing method of the epitaxial wafer. The method for improving the quality of the epitaxial wafer comprises the following steps: matching the position of a surface defect of the epitaxial wafer with a contact position of a contact part in epitaxial process equipment to obtain a first surface defect matched with the contact position of the contact part; obtaining the morphology and the type of the first surface defect; and according to the morphology and the type of the first surface defect and the epitaxial layer thickness of the epitaxial wafer, determining an improvement means of the contact part so as to reduce the number of the first surface defect.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method and device for improving the quality of an epitaxial wafer, an epitaxial wafer and a manufacturing method thereof. Background Art

[0002] Silicon wafers made of semiconductors are widely used as substrates in the manufacturing process of semiconductor devices. Common types include polished wafers and epitaxial wafers. Polished wafers are made by slicing a single crystal ingot and performing mirror polishing, cleaning and other processes. Epitaxial wafers are made by forming a single crystal silicon epitaxial layer on the surface of the polished wafer by chemical vapor deposition and other methods.

[0003] With the continuous development of semiconductor technology, the quality requirements for silicon wafers are becoming more and more stringent. For epitaxial wafers, the surface defects of the epitaxial layer are the key factors affecting the quality of epitaxial wafers. Among the surface defects of the epitaxial layer, some surface defects come from the epitaxial process. Therefore, reducing the surface defects of the epitaxial layer generated during the epitaxial process can improve the quality of epitaxial wafers. Summary of the invention

[0004] The present disclosure provides a method and device for improving the quality of epitaxial wafers, as well as an epitaxial wafer and a method for manufacturing the same; the surface defects generated by contact components during the epitaxial process can be reduced, and the quality of the epitaxial wafer can be improved.

[0005] The technical solution of the present disclosure is achieved as follows: In a first aspect, the present disclosure provides a method for improving the quality of an epitaxial wafer, the method comprising: Matching the position of the surface defect of the epitaxial wafer with the contact position of a contact component in the epitaxial process equipment to obtain a first surface defect matching the contact position of the contact component; Acquire the morphology and type of the first surface defect; According to the morphology and type of the first surface defects and the thickness of the epitaxial layer of the epitaxial wafer, a means of improving the contact component is determined to reduce the number of the first surface defects.

[0006] In a second aspect, the present disclosure provides a device for improving the quality of epitaxial wafers, the device comprising: a matching unit, an acquisition unit and a determination unit; wherein: The matching unit is configured to match the position of the surface defect of the epitaxial wafer with the contact position of the contact component in the epitaxial process equipment to obtain a first surface defect that matches the contact position of the contact component; The acquisition unit is configured to acquire the morphology and type of the first surface defect; The determination unit is configured to determine improvement measures for the contact component to reduce the number of the first surface defects according to the morphology and type of the first surface defects and the thickness of the epitaxial layer of the epitaxial wafer.

[0007] In a third aspect, the present disclosure provides a device for improving the quality of epitaxial wafers, the device comprising: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the method for improving the quality of epitaxial wafers as described in the first aspect.

[0008] In a fourth aspect, the present disclosure provides a method for manufacturing an epitaxial wafer, the manufacturing method comprising: Determining means for improving contact components in epitaxial process equipment according to the method for improving epitaxial wafer quality as described in the first aspect; After adjusting the contact component according to the improvement means, an epitaxial process is performed on the polished wafer substrate.

[0009] In a fifth aspect, the present disclosure provides an epitaxial wafer, which is obtained by the method for manufacturing an epitaxial wafer described in the fourth aspect, and on the surface of the epitaxial wafer, the number of defects with a size less than 200 nm is less than 2.

[0010] The present disclosure provides a method and device for improving the quality of epitaxial wafers, as well as an epitaxial wafer and a method for manufacturing the same; after obtaining a first surface defect among the surface defects of the epitaxial wafer that matches the contact position of the contact component of the epitaxial process equipment, the improvement means of the contact component is determined according to the morphology and type of the first surface defect and the thickness of the epitaxial layer of the epitaxial wafer. After the adjustment of the contact component is completed by the above-mentioned improvement means, during the transmission process in the epitaxial process equipment, abnormal contact between the contact component and the substrate wafer is avoided, the surface defects on the surface of the epitaxial wafer caused by the contact component are reduced, and the quality of the epitaxial wafer is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Schematic top view of an epitaxial growth apparatus provided for the present disclosure.

[0012] Figure 2 A schematic diagram of the structure of a processing chamber for performing an epitaxial deposition process provided by the present disclosure.

[0013] Figure 3 A schematic flow chart of a method for improving epitaxial wafer quality provided in the present invention.

[0014] Figure 4 (A) is a schematic diagram of the contact position between the contact component of the robot provided at the factory interface and the edge of the wafer provided in the present invention.

[0015] Figure 4(B) is a schematic diagram of the contact position between the contact component of the robot and the edge of the wafer in the load lock chamber provided by the present invention.

[0016] Figure 4 (C) is a schematic diagram of the contact position between the contact component of the buffer area robot in the transfer chamber provided by the present invention and the edge of the wafer.

[0017] Figure 5 An exemplary wafer defect map is provided for the present disclosure.

[0018] Figure 6 Schematic diagram of the ESF defect morphology provided in the present disclosure.

[0019] Figure 7 A schematic diagram of forming a first surface defect of an epitaxial wafer from a second surface defect of a substrate wafer provided in the present disclosure.

[0020] Figure 8 Another method process for improving the quality of epitaxial wafers provided by the present disclosure.

[0021] Fig. 9 A schematic diagram of the composition of a device for improving the quality of epitaxial wafers provided by the present invention.

[0022] Fig.10 A schematic diagram of another device composition for improving epitaxial wafer quality provided by the present invention.

[0023] Fig.11 A schematic diagram of the structure of a computing device provided by the present disclosure. DETAILED DESCRIPTION

[0024] The technical solutions in the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings in the present disclosure.

[0025] See also Figure 1 , which shows a schematic top view of an epitaxial growth device 100 applicable to the technical solution of the embodiment of the present disclosure. The epitaxial growth device 100 generally includes: a factory interface (Factory Interface) 102, load lock (Loadlock) chambers 104, 106, a transfer chamber (Transfer chamber) 108, and a process chamber (Process chamber) 120, 122. Figure 1As shown, wafers in the epitaxial growth apparatus 100 (shown as gray circles in the figure) can be processed in various chambers and transferred between various chambers (shown as solid arrows and dashed arrows in the figure) without being exposed to the surrounding environment outside the epitaxial growth apparatus 100. For example, wafers can be processed in various chambers under low pressure (e.g., less than or equal to about 300 Torr) or vacuum environments or transferred between these various chambers without destroying the low pressure or vacuum environment between various processes performed on these wafers in the epitaxial growth apparatus 100. Figure 1 As shown, the epitaxial growth device 100 has more than one processing chamber, and can perform the epitaxial deposition process of multiple wafers in one batch, thereby improving the production efficiency of epitaxial wafers.

[0026] exist Figure 1 In the example shown, the factory interface 102 includes a docking station 140. The epitaxial growth apparatus 100 also includes a plurality of front opening unit (FOUP) 144 adapted to the docking station 140. In some examples, the epitaxial growth apparatus 100 can be operated by a robot ( Figure 1 ), the wafer can be transferred from the front-opening standard cabin 144 to the docking station 140, and then transferred from the docking station 140 to the load lock chambers 104, 106.

[0027] The load lock chambers 104, 106 have respective ports coupled to the factory interface 102 and respective ports coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports coupled to the process chambers 120, 122. In some examples, the ports may be slit openings with slit valves that can be connected to the process chambers 120, 122 by a robot ( Figure 1 The ports are used to allow wafers to pass through the ports and to provide sealing between the corresponding chambers to prevent gas from passing between the corresponding chambers. Generally speaking, in order to transfer a wafer through any port, the port is open; otherwise, the port is closed.

[0028] The load lock chambers 104, 106, the transfer chamber 108, and the processing chambers 120, 122 may be fluidly coupled to a gas and pressure control system ( Figure 1106). The gas and pressure control system may include one or more gas pumps (e.g., a turbo pump, a cryopump, a roughing pump, etc.), a gas source, various valves, and conduits fluidly coupled to various chambers. In operation, a robot of the factory interface 102 transfers a wafer from the FOUP 144 through a port to the load lock chamber 104 or 106. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chamber 108 at an internal low pressure or vacuum environment (which may include an inert gas). Thus, the pumping down of the load lock chamber 104 or 106 facilitates the passage of substrates between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

[0029] When the wafer is in the already evacuated load lock chamber 104 or 106, the robot transfers the wafer from the load lock chamber 104 or 106 through the port into the transfer chamber 108. The robot can then transfer the wafer to the processing chamber 120, 122 for processing.

[0030] The processing chamber 120 may be any suitable chamber for processing a wafer. In some examples, the processing chamber 120 may be used to perform a cleaning process, or to perform an etching process, or to perform a respective epitaxial deposition process.

[0031] For some examples, see Figure 2 , a processing chamber 120 for performing an epitaxial deposition process includes: a susceptor 10 and a susceptor support frame 20A. The susceptor 10 is capable of horizontally supporting a wafer W. The susceptor support frame 20A is capable of driving the susceptor 10 to rotate around a central axis X at a certain speed during vapor deposition. During the rotation of the susceptor 10, the wafer W rotates around the central axis X together with the susceptor 10. Specifically, the wafer W remains stationary relative to the susceptor 10, and a small gap G is provided between the radial edge of the susceptor 10 and an adjacent component 10A (e.g., a preheating ring).

[0032] The chamber RC is enclosed by an upper bell jar 30A and a lower bell jar 30B, and the chamber RC accommodates a base 10 and a base support frame 20A. The upper bell jar 30A and the lower bell jar 30B can be made of transparent quartz, for example. The base 10 divides the chamber RC into an upper reaction chamber RC1 and a lower reaction chamber RC2. The wafer W is accommodated in the upper reaction chamber RC1. The gas pressure in the upper reaction chamber RC1 is slightly greater than the gas pressure in the lower reaction chamber RC2 so that the gas in the upper reaction chamber RC1 enters the lower reaction chamber RC2 through the gap G.

[0033] An air inlet 40 and an exhaust port 50 are formed on the left and right sides of the chamber RC, respectively. Specifically, the air inlet 40 is used to transport reaction gases, such as silicon source gas, carrier gas and dopant gas, into the upper reaction chamber RC1. Silicon atoms are generated by the reaction of the silicon source gas and the carrier gas and deposited on the wafer W to form an epitaxial layer on the surface of the wafer W by vapor deposition. The epitaxial layer of the wafer W is doped with a dopant gas to obtain a desired resistivity. For example, chlorosilane-based gases such as trichlorosilane SiHCl3 or dichlorosilane SiH2Cl2 are used as silicon source gases. Hydrogen H2 is used as a carrier gas. Gases with doping elements such as diborane B2H6 or phosphine PH3 are used as dopant gases. The exhaust port 50 is used to discharge the reaction exhaust gas out of the chamber RC.

[0034] In order to grow an epitaxial layer on the wafer W, the reaction gas (silicon source gas and carrier gas) is driven to flow along the upper surface of the wafer W, and the wafer W supported by the susceptor 10 is heated to about 1000° C. to 1200° C. To this end, heat sources providing a high temperature reaction environment are respectively arranged above and below the chamber RC. Figure 1 As shown, the heat source may use a plurality of heating bulbs 60, such as infrared lamps or far infrared lamps. The plurality of heating bulbs 60 are disposed on the periphery of the upper bell jar 30A and the lower bell jar 30B to heat the susceptor 10 and the wafer W by radiant heat from above and below the chamber 2 through the upper bell jar 30A and the lower bell jar 30B.

[0035] exist Figure 2 In the processing chamber 120 shown, a wafer support rod 80A and a wafer support rod carrier 90 arranged directly below the wafer support rod 80A are also provided. Before vapor deposition, the upper bell jar 30A is opened. The wafer W is transferred from the transfer chamber 108 to the wafer support rod 80A by a robot manipulator (not shown in the figure). Then, the wafer support rod 80A is driven down by the descent of the wafer support rod carrier 90, so that the wafer W is loaded into the base 10. Finally, the upper bell jar 30A is closed to complete the process of moving the wafer to the inside of the chamber RC. After completing the process of moving the wafer to the inside of the chamber RC, vapor deposition is performed. After the vapor deposition is completed, the upper bell jar 30A is opened. The wafer support rod 80A is driven up by the rise of the wafer support rod carrier 90 to lift the epitaxial wafer from the base 10. Finally, the epitaxial wafer is moved from the inside of the chamber RC to the transfer chamber 108 by the robot manipulator. In addition, in Figure 2 The illustrated processing chamber 120 further includes a mounting member 70 for assembling various components of the processing chamber 120 .

[0036] In conjunction with the above-mentioned epitaxial growth device 100 and the example of the processing chamber 120, when performing an epitaxial process, such as an epitaxial deposition process using a vapor deposition process as an example, and during the transmission process of each chamber of the epitaxial growth device 100, the robot clamps the wafer by adjusting the telescopic size and layout angle of the manipulator, and controls the wafer to be transferred between the chambers. These manipulators for clamping the wafer are the components in the epitaxial growth device 100 that directly contact the edge of the wafer, and can be referred to as contact components in the present disclosure.

[0037] During the transmission process of the epitaxial process, if the contact components are not properly set in terms of telescopic dimensions and layout angles, these contact components will form defects on the edge of the substrate wafer surface during the transmission process. As the epitaxial deposition process continues to cover the single crystal epitaxial layer on the defect, the epitaxial wafer surface obtained by the substrate wafer will form surface defects at the corresponding positions of the defects formed on the edge of the substrate wafer surface.

[0038] In order to avoid the above-mentioned surface defects caused by the contact components on the epitaxial wafer, the present disclosure provides a solution to improve the quality of the epitaxial wafer, reduce the surface defects caused by the contact components on the surface of the epitaxial wafer, and improve the quality of the epitaxial wafer. Figure 3 , which shows a method for improving the quality of epitaxial wafers provided by the present disclosure, which method may include steps S301 to S303.

[0039] In step S301 , the position of the surface defect of the epitaxial wafer is matched with the contact position of the contact component in the epitaxial process equipment to obtain a first surface defect that matches the contact position of the contact component.

[0040] In some examples, the contact component is a component in the epitaxial process equipment 100 that can directly contact the edge of the wafer. Figure 1 Taking the epitaxial process equipment 100 as an example, during the wafer transfer process, the contact component may be a robot manipulator. For example, these robots may be robots arranged in a docking station 140 of a factory interface 102, robots in a load lock chamber 104 or 106, or robots that transfer wafers from a transfer chamber 108 to a processing chamber 120 or 122.

[0041] In some examples, the position where the contact component contacts the wafer edge on the wafer surface is the contact position. Figure 4 (A) Figure 4 (B) and Figure 4(C) shows the contact positions of the contact parts of the robot (FI Robot, Factory Interface) arranged at the docking station 140 of the factory interface 102, the robot (Loadlock Robot) in the load lock chamber 104 or 106, and the buffer robot (Buffer Robot) in the transfer chamber with the edge of the wafer, respectively. Figure 4 (A) Figure 4 (B) and Figure 4 As shown in the circled box in (C).

[0042] In some examples, surface defects of the epitaxial wafer may be scattered at any position on the surface of the epitaxial wafer. In the present disclosure, a wafer defect map (MAP) may be formed based on the positions of the surface defects of the epitaxial wafer on the wafer surface. It can be found that among all the surface defects of the epitaxial wafer, the surface defects caused by the contact parts will gather at the position on the surface of the epitaxial wafer corresponding to the contact position.

[0043] Based on the above findings, in some examples, matching the position of the surface defect of the epitaxial wafer with the contact position of a contact component in an epitaxial process device to obtain a first surface defect matching the contact position of the contact component includes: Matching, at the surface edge of the epitaxial wafer, a location where surface defects are concentrated with a contact location of the contact component; When the position where the surface defects gather and the contact position of the contact component match, the defect at the position where the surface defects gather is determined as the first surface defect.

[0044] In the above example, combined with Figure 5 The example of wafer defect map shown in the figure shows that: Figure 5 Below the wafer surface shown, the surface defects shown by the triangular points, circular points and diamond points are more "dense" and appear to be clustered. The present disclosure uses the number of defects that appear within a set area on the wafer surface to evaluate whether it is "clustered". For example, the set area is 2μm×2μm. If there is an area on the surface of the epitaxial wafer that meets the area of ​​the area, and the number of defects that appear in the area is greater than or equal to a set number threshold, such as 3-5, it means that the surface defects of the epitaxial wafer are clustered in the area.

[0045] According to the above example, at the surface edge of the epitaxial wafer, the present disclosure matches the location of the region where surface defects are concentrated with the contact position of the aforementioned contact component. If the location of the region where surface defects are concentrated matches the contact position of the contact component, then it can be considered that the surface defects in the region are caused by the contact component that matches it. The present disclosure determines the defects at the location where surface defects are concentrated as the first surface defects. For example, continue to refer to Figure 5 The surface defects shown in the circled box are clustered at the same location as Figure 4 If the contact position shown in (A) matches the contact position shown in (A), the surface defect in the circled box is the first surface defect.

[0046] In some examples, among the surface defects of the epitaxial wafer, there are surface defects that do not match the contact position of the contact component. In this case, the causes of the defects can be investigated for components other than the contact component in the epitaxial process equipment to eliminate such surface defects that are not caused by the contact component.

[0047] In step S302, the morphology and type of the first surface defect are obtained.

[0048] In some examples, after the first surface defect is obtained through the above step S301, a scanning electron microscope (SEM) can be used to detect the first surface defect to obtain the morphology and type of the first surface defect. In detail, the SEM uses a high-energy electron beam to scan the surface of the epitaxial wafer, and collects secondary electrons generated by the interaction between the high-energy electron beam and the epitaxial wafer surface materials to obtain a scanned image of the epitaxial wafer. Based on the scanned image, not only the type of defect can be determined, but also the morphology of the defect can be known.

[0049] It should be noted that the first surface defect is a surface defect caused by the contact component in the epitaxial wafer. Specifically, after the contact component forms a second surface defect on the surface edge of the substrate wafer of the epitaxial wafer, the single crystal epitaxial layer is continuously covered on the second surface defect of the substrate wafer during the epitaxial deposition process, resulting in the first surface defect formed on the surface of the epitaxial wafer at the position corresponding to the second surface defect of the substrate wafer being an epitaxial stacking fault (ESF) defect. Furthermore, depending on the size of the second surface defect, the morphology of the first surface defect formed on the surface of the epitaxial wafer is also different.

[0050] In some examples, the morphology and type of the first surface defect include at least: The first surface defect is an ESF defect, and the morphology is a polycrystalline epitaxial stacking fault type; The first surface defect is an ESF defect, and the morphology is a composite defect and stacking fault type of polysilicon growth; The first surface defect is an ESF defect, and the morphology is a composite epitaxial stacking fault type with surface fracture; The first surface defect is an ESF defect, and its morphology is an epitaxial growth protrusion type on the crystal plane (100).

[0051] For the above example, for example, Figure 6 (A) Figure 6 (B) Figure 6 (C) and Figure 6 (D) shows schematic diagrams of ESF defects with morphologies of polysilicon epitaxial stacking fault type, polysilicon growth composite defect and stacking fault type, surface fracture composite epitaxial stacking fault type, and epitaxial growth protrusion type on the crystal plane (100).

[0052] It should be noted that in Figure 6 In (A), the polysilicon epitaxial stacking fault type defect is the same or similar to the defect shown in Figure 21 in SEMI MF154. It covers a large area on the surface of the epitaxial wafer and is covered or surrounded by the epitaxial layer. From a visual point of view, the shape of the defect is close to spherical, with a certain curvature, many protrusions and depressions on the surface, no obvious geometric regularity, complex contours, and various abrupt parts. Figure 6 In (B), the composite defect of polysilicon growth and stacking faults is the same or similar to the defect shown in Figure 18 of SEMI MF154. Visually, the outline of the defect is close to a square, and the surface is usually rough and uneven. This is because the atoms squeeze and collide with each other during the stacking process, and the surface is uneven. Figure 6 In (C), the Compound Epitaxial Stacking Fault with a Broken Surface is the same or similar to the defect shown in Figure 19 in SEMIMF154. Visually, the defect is usually conical, with a wide bottom and a sharp top, and each layer is smaller than the next layer, showing a gradual shrinking trend as a whole. Figure 6In (D), the epitaxial growth hillock on (100) is the same or similar to the defect shown in Figure 9 in SEMIMF154. Visually, the defect is usually step-shaped, with the height and width of each layer being basically the same, forming layers of platforms, and the layers of these platforms are clear and orderly.

[0053] In some examples, when the first surface defect is not an ESF defect, it means that although these first surface defects match the contact position of the contact component, they are not caused by the contact component. Therefore, the cause of the defect can still be investigated for other components in the epitaxial process equipment except the contact component to eliminate such first surface defects that are not caused by the contact component.

[0054] In step S303 , according to the morphology and type of the first surface defects and the thickness of the epitaxial layer of the epitaxial wafer, a means of improving the contact component is determined to reduce the number of the first surface defects.

[0055] In the present disclosure, for the first surface defect belonging to the ESF defect, different morphologies can be characterized by the size of the first surface defect. It can be found that the size of the first surface defect is not only related to the thickness of the epitaxial layer deposited on the substrate wafer surface during the epitaxial deposition process, but also to the size of the second surface defect. Figure 7 As shown in the figure, when a layer with a thickness of t When the epitaxial layer is formed, if there is a diameter of d Second surface defects (such as Figure 7 As shown by the black dots in the figure, as the epitaxial deposition process continues to cover the second surface defect with a single crystal epitaxial layer (Epi-layer), the second surface defect will expand along the crystal plane (111), and eventually the size of the first surface defect formed on the surface of the epitaxial layer, that is, the surface of the epitaxial wafer, will be s Satisfy the following formula: .

[0056] It can be found that: since the size of the first surface defect is related to the morphology, it can be seen from the above formula and the different morphologies of the aforementioned ESF defects that when d / t ≥ 1, the morphology of ESF defect is polycrystalline epitaxial stacking fault type. d / t <1, the morphology of the ESF defect is a composite defect of polysilicon growth and a stacking fault type or a composite epitaxial stacking fault type of surface fracture. d / t When ≤0.2, the morphology of the ESF defect is an epitaxial growth protrusion type on the crystal plane (100).

[0057] Based on the above findings, in some examples, determining the means for improving the contact component to reduce the number of the first surface defects according to the morphology and type of the first surface defects and the thickness of the epitaxial layer of the epitaxial wafer includes: Determining a second surface defect size of the substrate of the epitaxial wafer at a position corresponding to the first surface defect according to the morphology and type of the first surface defect and the thickness of the epitaxial layer of the epitaxial wafer; The improvement measures of the contact component are determined according to the size of the second surface defects to reduce the number of the first surface defects.

[0058] For the above example, specifically, based on the findings of the above inventors, when the morphology and type of the first surface defect and the thickness of the epitaxial layer of the epitaxial wafer are known, the size of the second surface defect can be roughly known. For example, on the surface of an epitaxial wafer with an epitaxial layer thickness of 3.5 μm, when the first surface defect is an ESF defect and the morphology is an epitaxial growth convex type on the crystal plane (100), based on the above findings about the morphology corresponding to the epitaxial growth convex type on the crystal plane (100), d / t It can be determined that a second surface defect with a size less than 0.6 um exists on the surface of the substrate wafer at a position corresponding to the first surface defect.

[0059] In the present disclosure, the second surface defect is caused by the contact component, that is, if the expansion amount (or expansion size) and the layout angle of the contact component are not properly set, then the contact component will form a second surface defect at the contact position with the substrate wafer, and as the degree of suitability of the expansion size and the layout angle is worse, the size of the second surface defect is larger. Based on this, in some examples, taking the contact component as a robot arm arranged in the epitaxial process equipment as an example, the improvement means of determining the contact component according to the size of the second surface defect to reduce the number of the first surface defects includes: The telescopic size of the manipulator when clamping and the layout angle of the manipulator are determined according to the size of the second surface defect to reduce the number of the first surface defects.

[0060] For the above example, specifically, after knowing the size of the second surface defect, the telescopic size and layout angle of the contact component (i.e., the manipulator) can be adjusted according to the size, and the improvement means of the contact component described in step S303 is formed based on the adjustment values ​​of the telescopic size and layout angle of the contact component. It should be noted that after the adjustment of the contact component is completed by the above improvement means, for example, after adjusting the telescopic size and layout angle of the contact component, it is possible to avoid abnormal contact between the contact component and the substrate wafer during the transmission process in the epitaxial process equipment 100, thereby reducing the number of second surface defects generated on the surface of the substrate wafer, and further reducing the number of first surface defects of the epitaxial wafer.

[0061] In some examples, after the adjustment of the contact component is completed by improvement means, for example, after the adjustment of the telescopic size and layout angle of the contact component, the epitaxial process can be continued to be performed on the subsequent substrate wafer based on the adjusted telescopic size and layout angle. After the subsequent epitaxial wafer is obtained, the telescopic size and layout angle of the contact component are continued to be adjusted according to the above technical solution, and the epitaxial process is performed on the substrate wafer according to the telescopic size and layout angle obtained by the continued adjustment, so that the number and size of the first surface defects are reduced to the set standard through iterative adjustment.

[0062] Through the above technical solution, after obtaining the first surface defect among the surface defects of the epitaxial wafer that matches the contact position of the contact component of the epitaxial process equipment, the improvement means of the contact component is determined according to the morphology and type of the first surface defect and the thickness of the epitaxial layer of the epitaxial wafer. After the adjustment of the contact component is completed through the above improvement means, during the transmission process in the epitaxial process equipment, abnormal contact between the contact component and the substrate wafer is avoided, the surface defects on the surface of the epitaxial wafer caused by the contact component are reduced, and the quality of the epitaxial wafer is improved.

[0063] Based on the same inventive concept as the above technical solution, see Figure 8 , which shows another method flow for improving the quality of epitaxial wafers, the process may include: S801: Inspect the epitaxial wafer by optical inspection means to obtain the size and number of optical inspection defects on the surface of the epitaxial wafer.

[0064] In some examples, by Figure 1 After the epitaxial process equipment 100 shown in the figure manufactures the epitaxial wafer, the surface of the epitaxial wafer can be inspected by optical inspection means such as surface light scattering (LLS, Localized Light Scattering) scanning technology to obtain a wafer defect map of the epitaxial wafer, such as Figure 5 The following example is shown. Figure 5In the process of epitaxial wafer surface defects, Figure 5 Bright spot particles will appear at the location where the defect occurs, and the number of optical defects on the surface of the epitaxial wafer can be obtained by counting the bright spot particles. In addition to being able to identify the bright spot particles corresponding to the defect, the size of the defect can also be identified through optical detection.

[0065] S802: Compare the size and quantity of the optically detected defect with the size threshold and the quantity threshold respectively, and determine whether the size and quantity of the optically detected defect are greater than or equal to the size threshold and the quantity threshold respectively.

[0066] In the present disclosure, the size threshold and the number threshold can be used to characterize whether the surface defects of the epitaxial wafer are compliant. In some examples, the size threshold is exemplarily set to 200nm, and the number threshold is exemplarily set to 3ea. Of course, the above two thresholds can be determined according to the indicator requirements of the product, and this disclosure does not elaborate on this.

[0067] When the size of the optical detection defect on the surface of the epitaxial wafer is less than the size threshold, and the number of the optical detection defects on the surface of the epitaxial wafer is less than the number threshold, it is characterized that the surface defects of the epitaxial wafer are compliant, and it can also be indicated that the particle level in each chamber of the epitaxial process equipment meets the required standards. In this case, execute step S803: no adjustment is required to the epitaxial process equipment. It can be understood that when the size of the optical detection defect on the surface of the epitaxial wafer is less than the size threshold, and the number of optical detection defects on the surface of the epitaxial wafer is greater than or equal to the number threshold, although the number of surface defects is large, it usually does not affect the subsequent process. Therefore, in this case, the epitaxial wafer can still be considered compliant and step S803 is executed.

[0068] When the size of the optical detection defect on the surface of the epitaxial wafer is greater than or equal to the size threshold, and the number of optical detection defects on the surface of the epitaxial wafer is greater than or equal to the number threshold, execute step S804: determine whether there is an optical detection defect on the surface of the substrate wafer of the epitaxial wafer at the corresponding position of the optical detection defect on the surface of the epitaxial wafer.

[0069] For the above step S804, specifically, when the size of the optical detection defect on the surface of the epitaxial wafer is greater than or equal to the size threshold, and the number of optical detection defects on the surface of the epitaxial wafer is greater than or equal to the number threshold, the number of surface defects of the epitaxial wafer is large or the size is large, resulting in non-compliance. Based on the cause of the surface defects of the epitaxial wafer. Some of the surface defects of the epitaxial wafer are caused by the surface defects left over from the substrate wafer (such as the polished wafer) during the processing, and the other surface defects are caused by the epitaxial process equipment during the epitaxial process.

[0070] When the size of an optical detection defect on the surface of an epitaxial wafer is greater than or equal to a size threshold, and the number of optical detection defects on the surface of an epitaxial wafer is less than a number threshold, the defect still needs to be removed due to its large size, but since the number is small, there is no need to improve the process equipment, and the defect can be eliminated by cleaning the epitaxial wafer.

[0071] In order to identify surface defects caused by epitaxial process equipment from surface defects of epitaxial wafers, optical detection defects on the surface of the substrate wafer may be detected by optical detection means before the substrate wafer enters the epitaxial process equipment.

[0072] If optical inspection defects are detected at the same position on the substrate wafer surface and the epitaxial wafer surface, it can be confirmed that the optical inspection defects on the epitaxial wafer surface are caused by the optical inspection defects at the corresponding position on the substrate wafer surface, rather than by the epitaxial process equipment, which means that the epitaxial process equipment meets the required standards. In this case, step S803 is executed: no adjustment is required to the epitaxial process equipment.

[0073] If there is no optical detection defect of the epitaxial wafer at the corresponding position of the optical detection defect on the substrate wafer surface, it means that this part of the optical detection defect on the epitaxial wafer surface is not caused by the optical detection defect at the corresponding position of the substrate wafer surface, but is caused by the epitaxial process equipment during the epitaxial process. Therefore, the epitaxial process equipment needs to be adjusted.

[0074] Based on this, in the present disclosure, when there is no optical detection defect on the surface of the substrate wafer at a position corresponding to the optical detection defect on the surface of the epitaxial wafer, step S805 is performed: cleaning the epitaxial wafer.

[0075] Regarding step S805, it should be noted that by cleaning the epitaxial wafer, the impurity particles attached to the surface can be removed. A large part of these impurity particles are particles that adhere to the surface of the epitaxial wafer during the process of being taken out from the epitaxial process equipment and transferred to the optical detection. After these impurity particles are cleaned, it is possible to avoid detecting these impurity particles in the subsequent detection process, thereby improving the detection efficiency.

[0076] S806: Obtaining surface defects of the epitaxial wafer based on optically inspected defects on the surface of the cleaned epitaxial wafer.

[0077] Specifically, after cleaning the impurity particles attached to the surface of the epitaxial wafer, combined with the optical detection defects of the substrate wafer surface in the aforementioned step, the surface defects caused by the epitaxial process equipment can be screened out from the optical detection defects on the surface of the epitaxial wafer, that is, the surface defects of the epitaxial wafer described in step S806. For these surface defects of the epitaxial wafer, the contact components in the epitaxial process equipment can be adjusted through the process of steps S807 to S809 to reduce the number of these defects and improve the quality of the epitaxial wafer. In some examples, the wafer map of the particle precision alignment of the cleaned epitaxial wafer can be superimposed to identify the surface defects of the above-mentioned epitaxial wafer.

[0078] S807: Matching the position of the surface defect of the epitaxial wafer with the contact position of a contact component in the epitaxial process equipment to obtain a first surface defect that matches the contact position of the contact component.

[0079] S808: Obtain the morphology and type of the first surface defect.

[0080] S809: Determine, based on the morphology and type of the first surface defects and the thickness of the epitaxial layer of the epitaxial wafer, a means of improving the contact component to reduce the number of the first surface defects.

[0081] It should be noted that the process shown in steps S807 to S809 is similar to the above Figure 3 The method flow for improving the quality of epitaxial wafers is consistent with that shown in FIG. Figure 3 The corresponding implementation details of the method flow for improving the quality of epitaxial wafers are not described in detail in this disclosure.

[0082] for Figure 8 In some examples of the technical solution shown, after the contact component is adjusted by the improvement means, for example, the telescopic size and layout angle of the contact component are adjusted, the epitaxial process can be continued to be performed on the subsequent substrate wafer based on the adjusted telescopic size and layout angle. Figure 8The technical solution shown continues to adjust the telescopic size and layout angle of the contact component, and performs an epitaxial process on the substrate wafer according to the telescopic size and layout angle obtained by the continued adjustment. In this way, the number and size of the first surface defects are reduced to the set indicator requirements through iterative adjustment.

[0083] Based on the same inventive concept as the above technical solution, see Fig. 9 , which shows a device 90 for improving the quality of epitaxial wafers provided by the present disclosure, the device 90 comprises: a matching unit 901, an acquisition unit 902 and a determination unit 903; wherein, The matching unit 901 is configured to match the position of the surface defect of the epitaxial wafer with the contact position of the contact component in the epitaxial process equipment to obtain a first surface defect that matches the contact position of the contact component; The acquisition unit 902 is configured to acquire the morphology and type of the first surface defect; The determination unit 903 is configured to determine the improvement means of the contact component to reduce the number of the first surface defects according to the morphology and type of the first surface defects and the thickness of the epitaxial layer of the epitaxial wafer.

[0084] In some examples, the determining unit 903 is configured to: Determining a second surface defect size of the substrate of the epitaxial wafer at a position corresponding to the first surface defect according to the morphology and type of the first surface defect and the thickness of the epitaxial layer of the epitaxial wafer; The improvement measures of the contact component are determined according to the size of the second surface defects to reduce the number of the first surface defects.

[0085] In some examples, the contact component is a manipulator of a robot arranged in the epitaxial process equipment; accordingly, the determining unit 903 is configured to: The telescopic size of the manipulator when clamping and the layout angle of the manipulator are determined according to the size of the second surface defect to reduce the number of the first surface defects.

[0086] In some examples, the morphology and type of the first surface defect include at least: The first surface defect is an ESF defect, and the morphology is a polycrystalline epitaxial stacking fault type; The first surface defect is an ESF defect, and the morphology is a composite defect and stacking fault type of polysilicon growth; The first surface defect is an ESF defect, and the morphology is a composite epitaxial stacking fault type with surface fracture; The first surface defect is an ESF defect, and its morphology is an epitaxial growth protrusion type on the crystal plane (100).

[0087] In some examples, the matching unit 901 is configured to: Matching, at the surface edge of the epitaxial wafer, a location where surface defects are concentrated with a contact location of the contact component; When the position where the surface defects gather and the contact position of the contact component match, the defect at the position where the surface defects gather is determined as the first surface defect.

[0088] In some examples, the acquisition unit 902 is configured to: The morphology and type of the first surface defect detected by a scanning electron microscope are obtained.

[0089] For some examples, see Fig.10 The device 90 further includes a pre-processing unit 904 configured to: Inspecting the epitaxial wafer by optical inspection means to obtain the size and quantity of optical inspection defects on the surface of the epitaxial wafer; When the size of the optical detection defect on the surface of the epitaxial wafer is greater than or equal to a size threshold, and the number of the optical detection defects on the surface of the epitaxial wafer is greater than or equal to a number threshold, determining whether there is an optical detection defect on the surface of the substrate wafer of the epitaxial wafer at a position corresponding to the optical detection defect on the surface of the epitaxial wafer; When there is no optical detection defect on the surface of the substrate wafer at a position corresponding to the optical detection defect on the surface of the epitaxial wafer, cleaning the epitaxial wafer; Surface defects of the epitaxial wafer are obtained based on optically inspected defects on the surface of the cleaned epitaxial wafer.

[0090] Please refer to Fig.11 , which shows a structural block diagram of an apparatus 90 for improving the quality of epitaxial wafers provided by an exemplary embodiment of the present disclosure. In some examples, the aforementioned apparatus 90 for improving the quality of epitaxial wafers can be implemented as a computing device 110, and the computing device 110 is at least one of a smart phone, a smart watch, a desktop computer, a laptop, a virtual reality terminal, an augmented reality terminal, a wireless terminal, and a laptop portable computer. The computing device 110 has a communication function and can access a wired network or a wireless network. The computing device 110 can generally refer to one of a plurality of terminals, and those skilled in the art can know that the number of the above terminals can be more or less. In some examples, the computing device 110 can receive data based on the wired network or wireless network to which it is connected. It can be understood that the computing device 110 undertakes the calculation and processing work of the technical solution of the present disclosure, and the present disclosure does not limit this.

[0091] like Fig.11As shown, the computing device in the present disclosure may include one or more of the following components: a processor 1110 and a memory 1120 .

[0092] Optionally, the processor 1110 uses various interfaces and lines to connect various parts of the entire computing device, and executes various functions of the computing device and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 1120, and calling data stored in the memory 1120. Optionally, the processor 1110 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 1110 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processor (NPU), and a baseband chip. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing the content that needs to be displayed on the touch display; the NPU is used to implement artificial intelligence (AI) functions; and the baseband chip is used to process wireless communications. It is understandable that the above-mentioned baseband chip may not be integrated into the processor 1110, but may be implemented by a separate chip.

[0093] The memory 1120 may include a random access memory (RAM) or a read-only memory (ROM). Optionally, the memory 1120 includes a non-transitory computer-readable storage medium. The memory 1120 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 1120 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above various method embodiments, etc.; the data storage area may store data created according to the use of the computing device, etc.

[0094] In addition, those skilled in the art can understand that the structure of the computing device shown in the above drawings does not constitute a limitation on the computing device, and the computing device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently. For example, the computing device also includes a display screen, a camera assembly, a microphone, a speaker, a radio frequency circuit, an input unit, a sensor (such as an acceleration sensor, an angular velocity sensor, a light sensor, etc.), an audio circuit, a WiFi module, a power supply, a Bluetooth module and other components, which will not be described in detail here.

[0095] The present disclosure also provides a computer-readable storage medium storing at least one instruction, wherein the at least one instruction is used to be executed by a processor to implement the method for improving the quality of epitaxial wafers as described in the above embodiments.

[0096] The present disclosure also provides a computer program product, which includes computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computing device executes to implement the method for improving the quality of epitaxial wafers described in the above-mentioned embodiments.

[0097] In addition, the present disclosure also provides a method for manufacturing an epitaxial wafer, the method comprising: Determine the means for improving the contact components in the epitaxial process equipment according to the method for improving the quality of the epitaxial wafer as described in the above embodiments; After adjusting the contact component according to the improvement means, an epitaxial process is performed on the polished wafer substrate.

[0098] In addition, the present disclosure also provides an epitaxial wafer, which is obtained by the aforementioned epitaxial wafer manufacturing method, and on the surface of the epitaxial wafer, the number of defects with a size less than 200 nm is less than 2.

[0099] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the present disclosure can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. Storage media can be any available media that can be accessed by a general or special-purpose computer.

[0100] It should be noted that the technical solutions described in the present disclosure can be combined arbitrarily without conflict.

[0101] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for improving the quality of epitaxial wafers, characterized in that: The method comprises: Matching the position of the surface defect of the epitaxial wafer with the contact position of a contact component in the epitaxial process equipment to obtain a first surface defect matching the contact position of the contact component; Acquire the morphology and type of the first surface defect; According to the morphology and type of the first surface defects and the thickness of the epitaxial layer of the epitaxial wafer, a means of improving the contact component is determined to reduce the number of the first surface defects.

2. The method according to claim 1, characterized in that According to the morphology and type of the first surface defect and the thickness of the epitaxial layer of the epitaxial wafer, determining the improvement means of the contact component to reduce the number of the first surface defects, including: Determining a second surface defect size of the substrate of the epitaxial wafer at a position corresponding to the first surface defect according to the morphology and type of the first surface defect and the thickness of the epitaxial layer of the epitaxial wafer; According to the size of the second surface defects, improvement measures for the contact component are determined to reduce the number of the first surface defects.

3. The method according to claim 2, characterized in that The contact component is a manipulator of a robot arranged in the epitaxial process equipment; accordingly, the improvement means of the contact component is determined according to the size of the second surface defect to reduce the number of the first surface defects, including: The telescopic size of the manipulator when clamping and the layout angle of the manipulator are determined according to the size of the second surface defect to reduce the number of the first surface defects.

4. The method according to any one of claims 1 to 3, characterized in that: The morphology and type of the first surface defect include at least: The first surface defect is an ESF defect, and the morphology is a polycrystalline epitaxial stacking fault type; The first surface defect is an ESF defect, and the morphology is a composite defect and stacking fault type of polysilicon growth; The first surface defect is an ESF defect, and the morphology is a composite epitaxial stacking fault type with surface fracture; The first surface defect is an ESF defect, and its morphology is an epitaxial growth protrusion type on the crystal plane (100).

5. The method according to claim 1, characterized in that The step of matching the position of the surface defect of the epitaxial wafer with the contact position of a contact component in the epitaxial process equipment to obtain a first surface defect matching the contact position of the contact component comprises: Matching, at the surface edge of the epitaxial wafer, a location where surface defects are concentrated with a contact location of the contact component; When the position where the surface defects gather and the contact position of the contact component match, the defect at the position where the surface defects gather is determined as the first surface defect.

6. The method according to claim 1, characterized in that Before matching the position of the surface defect of the epitaxial wafer with the contact position of the contact component in the epitaxial process equipment, the method further includes: Inspecting the epitaxial wafer by optical inspection means to obtain the size and quantity of optical inspection defects on the surface of the epitaxial wafer; When the size of the optical detection defect on the surface of the epitaxial wafer is greater than or equal to a size threshold, and the number of the optical detection defects on the surface of the epitaxial wafer is greater than or equal to a number threshold, determining whether there is an optical detection defect on the surface of the substrate wafer of the epitaxial wafer at a position corresponding to the optical detection defect on the surface of the epitaxial wafer; When there is no optical detection defect on the surface of the substrate wafer at a position corresponding to the optical detection defect on the surface of the epitaxial wafer, cleaning the epitaxial wafer; Surface defects of the epitaxial wafer are obtained based on optical detection defects on the surface of the cleaned epitaxial wafer.

7. A device for improving the quality of epitaxial wafers, characterized in that: The device comprises: a matching unit, an acquisition unit and a determination unit; wherein, The matching unit is configured to match the position of the surface defect of the epitaxial wafer with the contact position of the contact component in the epitaxial process equipment to obtain a first surface defect that matches the contact position of the contact component; The acquisition unit is configured to acquire the morphology and type of the first surface defect; The determination unit is configured to determine improvement measures for the contact component to reduce the number of the first surface defects according to the morphology and type of the first surface defects and the thickness of the epitaxial layer of the epitaxial wafer.

8. A device for improving the quality of epitaxial wafers, characterized in that: The device comprises: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the method for improving the quality of epitaxial wafers as claimed in any one of claims 1 to 6.

9. A method for manufacturing an epitaxial wafer, characterized in that: The manufacturing method comprises: Determining means for improving the contact components in the epitaxial process equipment according to the method for improving the quality of epitaxial wafers according to any one of claims 1 to 6; After adjusting the contact component according to the improvement means, an epitaxial process is performed on the polished wafer substrate.

10. An epitaxial wafer, characterized in that: The epitaxial wafer is obtained by the method for manufacturing an epitaxial wafer according to claim 9, and the number of defects with a size less than 200 nm on the surface of the epitaxial wafer is less than 2.

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