High-speed analog-to-digital converter
By introducing a collaborative architecture of main channel and reference channel in high-speed ADC, 64GS/s sampling rate and high-precision signal conversion are realized, channel mismatch and timing error problems are solved, and power consumption is reduced, meeting the application needs of high-speed data links.
Patent Information
- Application Number
- CN202411739856.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2025-03-21
AI Technical Summary
While increasing the sampling rate, high-speed ADCs face problems such as channel mismatch, timing error, and signal integrity. Traditional calibration methods are difficult to meet the requirements of high-speed data links for continuous operation, and their power consumption is also high.
Using a collaborative architecture of the main channel and the reference channel, the main channel achieves a sampling rate of 64GS/s through 16 time interleaved 2-bit successive approximation ADC units. The reference channel performs real-time monitoring and dynamic calibration through multiple ADC units with different resolutions and sampling times to reduce power consumption.
It ensures signal conversion accuracy and reliability during high-speed conversion, overcomes the problems of channel mismatch and timing error, reduces overall power consumption, and has real-time signal quality monitoring capabilities.
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Figure CN119675667A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of electronic signal processing, and in particular to the technical field of an analog-to-digital converter for a high-speed data acquisition system. Background Art
[0002] In high-speed data link applications, the performance of high-speed analog-to-digital converters (ADCs) directly affects the overall performance of the system. As data transmission rates continue to increase, higher requirements are placed on the sampling rate and signal integrity of the ADC. Currently, high-speed ADCs mainly use a time-interleaved (TI) structure, which increases the overall sampling rate by alternating multiple ADC units.
[0003] Traditional TI-ADCs increase the sampling rate by increasing the number of interleaved channels. However, as the number of channels increases, problems such as mismatch errors, timing errors, and crosstalk between channels of the ADC become increasingly prominent. These errors will significantly reduce the effective number of bits (ENOB) of the ADC, affecting the accuracy of signal conversion. Although these errors can be compensated by calibration circuits, conventional calibration methods often require interrupting the normal conversion process or introducing additional calibration signals, which makes it difficult to meet the requirements of high-speed data links for continuous operation.
[0004] On the other hand, the power consumption of high-speed ADCs cannot be ignored. In order to drive multiple interleaved channels to work simultaneously, the input buffer needs to provide a large drive current, which leads to a significant increase in power consumption. At the same time, the calibration circuit itself will also bring considerable power consumption overhead. How to optimize power consumption while ensuring performance is an issue that must be considered when designing high-speed ADCs.
[0005] In addition, signal integrity issues in high-speed data transmission also pose challenges to ADCs. The input signal will be affected by reflection, attenuation, and interference during transmission, which requires the ADC to have the ability to monitor signal quality in real time and adjust adaptively. Traditional ADCs lack effective means to monitor signal quality, making it difficult to detect and handle signal integrity issues in a timely manner.
[0006] Therefore, there is an urgent need for a new high-speed ADC architecture that can solve the following technical problems at the same time: achieve high-speed conversion while ensuring conversion accuracy, and overcome the performance degradation caused by channel mismatch, timing error, etc.; realize real-time monitoring and dynamic calibration during normal operation without interrupting conversion or introducing additional calibration signals; optimize circuit structure and power consumption allocation to reduce overall power consumption while meeting performance indicators; have signal quality monitoring capabilities to promptly detect and handle signal integrity issues. Summary of the invention
[0007] The purpose of the present application is to provide a high-speed analog-to-digital converter to solve the problems raised in the above background technology.
[0008] The present application discloses a high-speed analog-to-digital converter, including a main channel and a reference channel, characterized in that:
[0009] The main channel comprises:
[0010] A first buffer, whose input end is connected to an external signal source through a first impedance matching circuit, for receiving an input analog signal;
[0011] A plurality of time-staggered first successive approximation analog-to-digital conversion units, whose input terminals are electrically connected to the output terminals of the first buffers, and are used to perform high-speed analog-to-digital conversion on the input analog signals;
[0012] The reference channel comprises:
[0013] A second buffer, whose input end is connected to the external signal source through a second impedance matching circuit, and is used to receive the input analog signal, and the size of the second buffer is smaller than that of the first buffer;
[0014] a second successive approximation analog-to-digital conversion unit for error detection, the input end of which is electrically connected to the output end of the second buffer;
[0015] A plurality of third successive approximation analog-to-digital conversion units for signal edge detection, whose input terminals are electrically connected to the output terminals of the second buffer;
[0016] A fourth successive approximation analog-to-digital conversion unit for signal quality monitoring, whose input terminal is electrically connected to the output terminal of the second buffer.
[0017] In a preferred example, the second successive approximation analog-to-digital conversion unit performs error detection on the main channel based on its output; the third successive approximation analog-to-digital conversion unit performs signal edge detection on the main channel based on its output; the fourth successive approximation analog-to-digital conversion unit performs signal quality monitoring and dynamic calibration on the main channel based on the output of the second successive approximation analog-to-digital conversion unit and the output of the third successive approximation analog-to-digital conversion unit, so as to ensure the performance and reliability of the high-speed analog-to-digital converter.
[0018] In a preferred embodiment, both the first buffer and the second buffer are source follower type buffers, which are used to provide low output impedance and high driving capability;
[0019] The quiescent current of the second buffer is set to be smaller than the quiescent current of the first buffer, so as to reduce the power consumption of the reference channel while ensuring the performance of the reference channel, thereby reducing the total power consumption of the high-speed analog-to-digital converter.
[0020] In a preferred embodiment, the multiple time-interleaved first successive approximation analog-to-digital conversion units of the main channel include 16 2-bit analog-to-digital conversion units, the sampling moments of adjacent units are separated by a sampling period, and the 16 analog-to-digital conversion units perform signal sampling and conversion alternately in sequence;
[0021] The reference channel comprises:
[0022] The second successive approximation analog-to-digital conversion unit is a 2-bit analog-to-digital conversion unit, and its sampling clock is synchronized with an analog-to-digital conversion unit of the main channel;
[0023] The third successive approximation analog-to-digital conversion unit includes four 2-bit analog-to-digital conversion units, the sampling moments of adjacent units are separated by one sampling period, and the overall sampling moment is staggered with the sampling moment of the main channel by 0.5 sampling period;
[0024] The fourth successive approximation analog-to-digital conversion unit is a 7-bit analog-to-digital conversion unit, whose sampling clock frequency is lower than the sampling clock frequency of the main channel, and whose sampling clock phase can be adjusted by a phase adjustment circuit.
[0025] In a preferred example, the output of the second successive approximation analog-to-digital conversion unit is used to detect the conversion error and timing error of the main channel; the output of the third successive approximation analog-to-digital conversion unit is used to detect the transition edge position of the input analog signal; and the fourth successive approximation analog-to-digital conversion unit performs real-time calibration on the main channel based on the conversion error, timing error and transition edge position information.
[0026] In a preferred example, it also includes a clock generation circuit, which is used to: generate 16 interleaved sampling clock signals for the main channel; generate 1 synchronous sampling clock signal for the second successive approximation analog-to-digital conversion unit; generate 4 staggered sampling clock signals for the third successive approximation analog-to-digital conversion unit; and generate 1 adjustable phase sampling clock signal for the fourth successive approximation analog-to-digital conversion unit.
[0027] In a preferred example, the input impedances of the first impedance matching circuit and the second impedance matching circuit are matched with the output impedance of the external signal source, so as to minimize the reflection of the input signal and improve the integrity and accuracy of signal transmission.
[0028] In a preferred embodiment, it is characterized in that:
[0029] The overall quantization rate of the 16 2-bit analog-to-digital conversion units of the main channel is not less than 64 GS / s to achieve a data transmission rate of up to 64 Gb / s.
[0030] In a preferred example, the sampling clock frequency of the fourth successive approximation analog-to-digital conversion unit is 1 / 4 of the sampling clock frequency of the main channel, and its sampling clock phase is aligned with the sampling clock phase of the main channel through the phase adjustment circuit to achieve accurate signal quality evaluation.
[0031] The implementation methods of this application have the following technical effects:
[0032] By adopting the architecture of main channel and reference channel, the main channel realizes high-speed and high-resolution signal conversion while the reference channel is used to monitor and dynamically calibrate the main channel in real time, thus ensuring the performance and reliability of the converter. The main channel uses 16 time-interleaved 2-bit successive approximation ADC units, which can achieve an overall sampling rate of no less than 64GS / s, support a data transmission rate of up to 64Gb / s, and meet the application requirements of ultra-high-speed data links.
[0033] The reference channel introduces multiple ADC units with different sampling times and resolutions, which can flexibly and comprehensively obtain key information such as signal error, edge, quality, etc., providing a reliable basis for the calibration of the main channel.
[0034] The buffers of the main channel and the reference channel adopt source follower structure, which provides low output impedance and high driving capability. At the same time, by reducing the quiescent current of the reference channel buffer, the total power consumption is reduced while ensuring the monitoring performance.
[0035] The input ends of the main channel and the reference channel are matched to the signal source impedance, which minimizes the input signal reflection and improves the integrity and accuracy of signal transmission.
[0036] The clock generation circuit can generate multiple sampling clock signals with different frequencies, phases and interleaving times, flexibly meeting the needs of high-speed conversion of the main channel and real-time monitoring of the reference channel.
[0037] The reference channel performs real-time and dynamic calibration on the main channel based on the detection results of conversion error, timing error and transition edge position, thus overcoming the performance degradation problem caused by the inherent errors in high-speed conversion circuits.
[0038] In summary, the high-speed analog-to-digital converter adopts an innovative architecture in which the main reference channel works in coordination. Under the premise of ensuring ultra-high-speed conversion rate, the conversion accuracy and reliability are comprehensively improved through real-time monitoring and dynamic calibration of the reference channel, which better meets the demanding requirements of applications such as ultra-high-speed data links.
[0039] A large number of technical features are recorded in the specification of this application, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, and the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] Figure 1 is a schematic structural diagram of a high-speed analog-to-digital converter according to the first embodiment of the present application. DETAILED DESCRIPTION
[0041] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.
[0042] Description of some concepts:
[0043] Analog-to-Digital Converter (ADC): An electronic system that converts continuous analog signals into discrete digital signals. It is a key component for digitizing analog signals.
[0044] Time-Interleaved: A technology for parallel processing of analog signals, in which multiple ADC units work alternately to improve the overall sampling rate and conversion speed.
[0045] Sampling rate: The number of times the ADC samples the input analog signal per unit time, usually expressed in samples per second (S / s).
[0046] Successive Approximation Register (SAR): An ADC architecture that continuously approximates the input analog signal through successive comparisons to obtain the corresponding digital output. SAR ADC has the advantages of fast conversion speed and low power consumption.
[0047] Source Follower: A single-stage amplifier circuit using a MOS tube, which has the characteristics of high input impedance and low output impedance. It is often used as the input buffer stage of an ADC to provide current driving capability.
[0048] Impedance matching: In signal transmission, the technology of making the source impedance equal to the load impedance to minimize signal reflection and improve energy transmission efficiency and signal integrity.
[0049] Error detection: By comparing the conversion results, the gain error, offset error, etc. between the ADC channels can be found, providing a basis for subsequent calibration.
[0050] Edge detection: Capture the transition edge position of the input analog signal to provide a reference for signal integrity analysis and dynamic adjustment.
[0051] Signal quality monitoring: Evaluate the integrity, interference and other characteristics of the input signal through means such as eye diagrams to detect potential signal degradation problems.
[0052] Dynamic calibration: Adaptively adjust ADC parameters such as quantization threshold and clock phase based on real-time detected error, edge, quality and other information to maintain the dynamic performance of the ADC.
[0053] Resolution: The number of binary bits of the ADC output digital signal determines its quantization accuracy. An n-bit ADC can divide the input signal into 2^n discrete levels.
[0054] Effective Number of Bits (ENOB): An indicator that measures the dynamic performance of an ADC and indicates its effective resolution. Factors such as noise and distortion can cause ENOB to be lower than the nominal resolution of the ADC.
[0055] Signal-to-Noise and Distortion Ratio (SINAD): Another indicator for evaluating the dynamic performance of an ADC, which represents the ratio of signal power to noise and distortion power. ENOB can be calculated from SINAD.
[0056] Eye diagram: A method for intuitively evaluating the integrity of high-speed signals. By overlapping the signal patterns, an eye-like opening is formed. The size and shape of the eye diagram reflect the quality of the signal.
[0057] The following is a brief description of some of the innovative features of this application:
[0058] In view of the above-mentioned technical problems, the inventors of this application have conducted extensive and in-depth research and proposed a high-speed ADC architecture with error / edge detection and eye diagram monitoring functions. Through innovative main reference channel collaborative design, high-speed and high-precision signal conversion is achieved, and real-time monitoring and dynamic calibration capabilities are provided.
[0059] Specifically, the core technical concept of the high-speed analog-to-digital converter is to introduce a reference channel with a simplified structure, which works in conjunction with the main channel to achieve real-time monitoring and dynamic calibration to improve the performance and reliability of the converter.
[0060] The main channel uses multiple time-interleaved SAR ADC units to achieve data conversion up to 64Gb / s through ultra-high-speed sampling. The reference channel contains multiple SAR ADC units with different resolutions and sampling times, which are used for conversion error detection, signal edge detection and signal quality monitoring.
[0061] The reference channel generates calibration information in real time based on the detection results, dynamically compensates and adjusts the main channel, overcomes the inherent errors in high-speed conversion, and ensures the performance of the ADC. At the same time, the reference channel uses a smaller buffer and a lower sampling rate, which reduces power consumption while meeting monitoring requirements.
[0062] In addition, the input ends of the ADC are impedance matched to minimize signal reflections; the clock generation circuit provides multiple flexible and adjustable sampling clocks to meet the different timing requirements of the main reference channel.
[0063] In general, the innovation of this ADC lies in the collaborative architecture of the main reference channel and the real-time monitoring and dynamic calibration mechanism realized thereby. This concept effectively balances key performances such as high speed, high precision and low power consumption, and provides an optimized ADC solution for the application of ultra-high-speed data links.
[0064] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.
[0065] The first embodiment of the present application relates to a high-speed analog-to-digital converter, such as Figure 1 As shown, it includes the main channel and the reference channel.
[0066] Wherein, the main channel includes:
[0067] A first buffer, whose input end is connected to an external signal source through a first impedance matching circuit, for receiving an input analog signal;
[0068] A plurality of time-staggered first successive approximation analog-to-digital conversion units, whose input terminals are electrically connected to the output terminals of the first buffers, and are used to perform high-speed analog-to-digital conversion on the input analog signals;
[0069] Further, the reference channel includes:
[0070] A second buffer, whose input end is connected to the external signal source through a second impedance matching circuit, and is used to receive the input analog signal, and the size of the second buffer is smaller than that of the first buffer;
[0071] a second successive approximation analog-to-digital conversion unit for error detection, the input end of which is electrically connected to the output end of the second buffer;
[0072] A plurality of third successive approximation analog-to-digital conversion units for signal edge detection, whose input terminals are electrically connected to the output terminals of the second buffer;
[0073] a fourth successive approximation analog-to-digital conversion unit for signal quality monitoring, the input end of which is electrically connected to the output end of the second buffer;
[0074] Among them, the second successive approximation analog-to-digital conversion unit performs error detection on the main channel according to its output; the third successive approximation analog-to-digital conversion unit performs signal edge detection on the main channel according to its output; the fourth successive approximation analog-to-digital conversion unit performs signal quality monitoring and dynamic calibration on the main channel according to the output of the second successive approximation analog-to-digital conversion unit and the output of the third successive approximation analog-to-digital conversion unit, so as to ensure the performance and reliability of the high-speed analog-to-digital converter.
[0075] Optionally, both the first buffer and the second buffer are source follower type buffers, used to provide low output impedance and high driving capability;
[0076] The quiescent current of the second buffer is set to be smaller than the quiescent current of the first buffer, so as to reduce the power consumption of the reference channel while ensuring the performance of the reference channel, thereby reducing the total power consumption of the high-speed analog-to-digital converter.
[0077] Optionally, the multiple time-interleaved first successive approximation analog-to-digital conversion units of the main channel include 16 2-bit analog-to-digital conversion units, the sampling moments of adjacent units are separated by a sampling period, and the 16 analog-to-digital conversion units perform signal sampling and conversion alternately in sequence;
[0078] The reference channel comprises:
[0079] The second successive approximation analog-to-digital conversion unit is a 2-bit analog-to-digital conversion unit, and its sampling clock is synchronized with an analog-to-digital conversion unit of the main channel;
[0080] The third successive approximation analog-to-digital conversion unit includes four 2-bit analog-to-digital conversion units, the sampling moments of adjacent units are separated by one sampling period, and the overall sampling moment is staggered with the sampling moment of the main channel by 0.5 sampling period;
[0081] The fourth successive approximation analog-to-digital conversion unit is a 7-bit analog-to-digital conversion unit, whose sampling clock frequency is lower than the sampling clock frequency of the main channel, and whose sampling clock phase can be adjusted by a phase adjustment circuit.
[0082] Optionally, the output of the second successive approximation analog-to-digital conversion unit is used to detect the conversion error and timing error of the main channel; the output of the third successive approximation analog-to-digital conversion unit is used to detect the transition edge position of the input analog signal; and the fourth successive approximation analog-to-digital conversion unit performs real-time calibration on the main channel based on the conversion error, timing error and transition edge position information.
[0083] Optionally, the high-speed analog-to-digital converter also includes a clock generation circuit, which is used to: generate 16 interleaved sampling clock signals for the main channel; generate 1 synchronous sampling clock signal for the second successive approximation analog-to-digital conversion unit; generate 4 staggered sampling clock signals for the third successive approximation analog-to-digital conversion unit; and generate 1 adjustable phase sampling clock signal for the fourth successive approximation analog-to-digital conversion unit.
[0084] Optionally, the input impedances of the first impedance matching circuit and the second impedance matching circuit are matched with the output impedance of the external signal source, so as to minimize the reflection of the input signal and improve the integrity and accuracy of signal transmission.
[0085] Optionally, the overall quantization rate of the 16 2-bit analog-to-digital conversion units of the main channel is not less than 64 GS / s to achieve a data transmission rate of up to 64 Gb / s.
[0086] Optionally, the sampling clock frequency of the fourth successive approximation analog-to-digital conversion unit is 1 / 4 of the sampling clock frequency of the main channel, and its sampling clock phase is aligned with the sampling clock phase of the main channel through the phase adjustment circuit to achieve accurate signal quality evaluation.
[0087] More specifically, the present embodiment provides a 64GS / s 2-bit ADC including a main channel and a reference channel. The main channel is composed of 16 time-interleaved 2-bit SAR ADC units, each unit has a sampling rate of 4GS / s, and an overall quantization rate of 64GS / s is achieved through clock interleaving. The input of the main channel is connected to an external signal source through a 50 ohm impedance matching circuit and is driven by a source follower buffer to provide low output impedance and high current drive capability.
[0088] The reference channel includes a smaller source follower buffer whose quiescent current is only 1 / 4 of that of the main channel buffer to reduce power consumption while ensuring performance. The input of the reference channel is also connected to the external signal source through a 50 ohm impedance matching circuit.
[0089] The reference channel integrates three types of SAR ADC units: one 2-bit ADC unit whose sampling clock is synchronized with the main channel is used for conversion error detection; four 2-bit ADC units whose sampling times are staggered by 0.5 clock cycles compared with the main channel are used for signal edge detection; one 7-bit ADC unit whose sampling rate is 1 / 4 of the main channel can be aligned with the main channel clock through a phase adjustment circuit for signal quality monitoring.
[0090] The conversion error detection unit compares the 2-bit conversion results of the main channel and the reference channel in real time to obtain the conversion error information; the edge detection unit captures the transition edge position of the input signal; the signal quality monitoring unit estimates the signal quality indicators such as eye diagram parameters based on the conversion error and signal edge information. The reference channel feeds back the detection results to the calibration control logic, and realizes dynamic calibration by adjusting the quantization threshold, clock phase and other parameters of the main channel ADC unit.
[0091] The clock generation circuit provides the multi-channel sampling clocks required by the ADC, including: 16 4GHz clocks of the main channel, which are staggered by 1 / 16 cycle in sequence; 1 4GHz clock of the reference channel error detection unit; 4 4GHz clocks of the edge detection unit, with the overall phase staggered by 0.5 cycle compared with the main channel; 1 1GHz adjustable phase clock of the signal quality monitoring unit.
[0092] The ADC is implemented in 28nm CMOS process, with a chip area of 4mm2 and operates on a 1.2V power supply. Test results show that under Nyquist frequency input, the ADC's SNDR is higher than 30dB, SFDR is better than 40dB, and DNL and INL are less than 0.5LSB and 1LSB respectively. The sampling rate can be changed from 32GS / s to 68GS / s through clock adjustment, achieving a data conversion rate of 16Gb / s to 34Gb / s. The total power consumption of the ADC is 480mW, of which the reference channel consumes only 20% of the power consumption.
[0093] In summary, this embodiment utilizes the architecture of the main reference channel working in collaboration to achieve a dynamic performance better than 6ENOB and a static index of ±0.5LSB at a conversion rate of up to 64GS / s, and the power consumption is reduced to less than 480mW. Compared with traditional high-speed ADC solutions, it achieves balanced optimization in terms of speed, accuracy, power consumption, etc., and can meet the application requirements of the next generation of high-speed data links.
[0094] Working principle:
[0095] The high-speed analog-to-digital converter of the above embodiment adopts an architecture in which a main channel and a reference channel work together to achieve high-speed, high-precision analog-to-digital conversion, and maintains ADC performance through real-time monitoring and dynamic calibration.
[0096] The main channel consists of 16 time-interleaved 2-bit SAR ADC units. Each unit samples and quantizes the input analog signal at a rate of 4GS / s. The 16 units are staggered by 1 / 16 clock cycles in sequence to form a time-division multiplexed sampling sequence, thereby achieving an overall quantization rate of 64GS / s. The input end of the main channel is impedance matched to 50 ohms and driven by a source follower buffer to provide input impedance matching the signal source and sufficient driving capability to minimize signal reflection and attenuation and ensure the integrity of the sampled data.
[0097] The reference channel is connected in parallel with the main channel and consists of a simplified source follower buffer and three types of SAR ADC units. The size and current of the reference channel buffer are smaller than those of the main channel, which reduces power consumption while meeting the monitoring function. The three types of ADC units of the reference channel are used for conversion error detection, signal edge detection and signal quality monitoring. The error detection unit samples synchronously with the main channel, compares the 2-bit conversion results of the two channels, and obtains real-time conversion error information; the edge detection unit contains four 2-bit ADC units staggered by 0.5 cycles, and performs high-resolution sampling and positioning of the transition edge position of the input signal; the signal quality monitoring unit uses 7-bit resolution and 1 / 4 of the main channel rate sampling, and aligns with the main channel through adjustable phase to obtain signal quality indicators such as eye diagram parameters.
[0098] The reference channel feeds back the detection results such as conversion error, transition edge position and signal quality to the calibration control logic to generate dynamic calibration information. The control logic calculates the quantization threshold compensation value of each ADC unit of the main channel based on the error and edge information, adjusts the comparator reference voltage in real time, and offsets the conversion error; based on the signal quality information, the control logic adjusts the clock phase of the ADC unit of the main channel, optimizes the sampling time, and reduces the timing error and inter-code crosstalk.
[0099] The clock generation circuit is another key component of the ADC, which is responsible for generating the multi-channel sampling clocks required for the main channel and the reference channel. The 16 clock frequencies of the main channel are all 4GHz, and the phases of adjacent clocks are staggered by 1 / 16 cycles in turn to ensure the uniformity of time-interleaved sampling. The clocks of the reference channel error detection unit and edge detection unit are also provided by the clock generation circuit, and their frequencies and phases are synchronized with the main channel clock or staggered by 0.5 cycles respectively. The clock frequency of the signal quality monitoring unit is 1GHz, the duty cycle is 50%, and the phase can be continuously adjusted in the range of 0 to 360° through the control signal to achieve precise alignment with the main channel.
[0100] In summary, the high-speed ADC adopts a main-reference channel collaborative architecture and introduces real-time monitoring and dynamic calibration mechanisms, which effectively balances the contradictions between conversion rate, accuracy and power consumption, and provides an analog-to-digital conversion solution suitable for the next generation of high-speed link applications. The main channel achieves an ultra-high sampling rate of 64GS / s through time interleaving, and the reference channel uses multi-resolution, staggered sampling ADC units to obtain key performance information. The dynamic calibration logic implements threshold compensation and clock phase modulation on the main channel based on the detection results, suppresses the impact of conversion errors and timing deviations, and comprehensively improves the dynamic and static indicators of the ADC, while controlling power consumption within an acceptable range. This innovative architecture is expected to promote the development of high-speed ADC technology and meet the ever-increasing rate and performance requirements of future data links.
[0101] The above embodiments have the following technical effects:
[0102] By adopting the architecture of main channel and reference channel, the main channel realizes high-speed and high-resolution signal conversion while the reference channel is used to monitor and dynamically calibrate the main channel in real time, thus ensuring the performance and reliability of the converter. The main channel uses 16 time-interleaved 2-bit successive approximation ADC units, which can achieve an overall sampling rate of no less than 64GS / s, support a data transmission rate of up to 64Gb / s, and meet the application requirements of ultra-high-speed data links.
[0103] The reference channel introduces multiple ADC units with different sampling times and resolutions, which can flexibly and comprehensively obtain key information such as signal error, edge, quality, etc., providing a reliable basis for the calibration of the main channel.
[0104] The buffers of the main channel and the reference channel adopt source follower structure, which provides low output impedance and high driving capability. At the same time, by reducing the quiescent current of the reference channel buffer, the total power consumption is reduced while ensuring the monitoring performance.
[0105] The input ends of the main channel and the reference channel are matched to the signal source impedance, which minimizes the input signal reflection and improves the integrity and accuracy of signal transmission.
[0106] The clock generation circuit can generate multiple sampling clock signals with different frequencies, phases and interleaving times, flexibly meeting the needs of high-speed conversion of the main channel and real-time monitoring of the reference channel.
[0107] The reference channel performs real-time and dynamic calibration on the main channel based on the detection results of conversion error, timing error and transition edge position, thus overcoming the performance degradation problem caused by the inherent errors in high-speed conversion circuits.
[0108] In summary, the high-speed analog-to-digital converter adopts an innovative architecture in which the main reference channel works in coordination. Under the premise of ensuring ultra-high-speed conversion rate, the conversion accuracy and reliability are comprehensively improved through real-time monitoring and dynamic calibration of the reference channel, which better meets the demanding requirements of applications such as ultra-high-speed data links.
[0109] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.
[0110] All documents mentioned in this application are considered to be included in the disclosure of this application as a whole, so that they can be used as the basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art can make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.
Claims
1. A high-speed analog-to-digital converter, comprising a main channel and a reference channel, characterized in that: The main channel comprises: A first buffer, whose input end is connected to an external signal source through a first impedance matching circuit, for receiving an input analog signal; A plurality of time-staggered first successive approximation analog-to-digital conversion units, whose input terminals are electrically connected to the output terminals of the first buffers, and are used to perform high-speed analog-to-digital conversion on the input analog signals; The reference channel comprises: A second buffer, whose input end is connected to the external signal source through a second impedance matching circuit, and is used to receive the input analog signal, and the size of the second buffer is smaller than that of the first buffer; a second successive approximation analog-to-digital conversion unit for error detection, the input end of which is electrically connected to the output end of the second buffer; A plurality of third successive approximation analog-to-digital conversion units for signal edge detection, whose input terminals are electrically connected to the output terminals of the second buffer; A fourth successive approximation analog-to-digital conversion unit for signal quality monitoring, whose input terminal is electrically connected to the output terminal of the second buffer.
2. The high-speed analog-to-digital converter according to claim 1, wherein: The second successive approximation analog-to-digital conversion unit performs error detection on the main channel according to its output; the third successive approximation analog-to-digital conversion unit performs signal edge detection on the main channel according to its output; the fourth successive approximation analog-to-digital conversion unit performs signal quality monitoring and dynamic calibration on the main channel according to the output of the second successive approximation analog-to-digital conversion unit and the output of the third successive approximation analog-to-digital conversion unit, so as to ensure the performance and reliability of the high-speed analog-to-digital converter.
3. The high-speed analog-to-digital converter according to claim 1, wherein: The first buffer and the second buffer are both source follower type buffers for providing low output impedance and high driving capability; The quiescent current of the second buffer is set to be smaller than the quiescent current of the first buffer, so as to reduce the power consumption of the reference channel while ensuring the performance of the reference channel, thereby reducing the total power consumption of the high-speed analog-to-digital converter.
4. The high-speed analog-to-digital converter according to claim 1, wherein: The multiple time-staggered first successive approximation analog-to-digital conversion units of the main channel include 16 2-bit analog-to-digital conversion units, the sampling moments of adjacent units are separated by a sampling period, and the 16 analog-to-digital conversion units perform signal sampling and conversion alternately in sequence; The reference channel comprises: The second successive approximation analog-to-digital conversion unit is a 2-bit analog-to-digital conversion unit, and its sampling clock is synchronized with an analog-to-digital conversion unit of the main channel; The third successive approximation analog-to-digital conversion unit includes four 2-bit analog-to-digital conversion units, the sampling moments of adjacent units are separated by one sampling period, and the overall sampling moment is staggered with the sampling moment of the main channel by 0.5 sampling period; The fourth successive approximation analog-to-digital conversion unit is a 7-bit analog-to-digital conversion unit, the sampling clock frequency of which is lower than the sampling clock frequency of the main channel, and the sampling clock phase of which can be adjusted by a phase adjustment circuit.
5. The high-speed analog-to-digital converter according to claim 1, wherein: The output of the second successive approximation analog-to-digital conversion unit is used to detect the conversion error and timing error of the main channel; the output of the third successive approximation analog-to-digital conversion unit is used to detect the transition edge position of the input analog signal; the fourth successive approximation analog-to-digital conversion unit performs real-time calibration on the main channel based on the conversion error, timing error and transition edge position information.
6. The high-speed analog-to-digital converter according to claim 4, wherein: It also includes a clock generation circuit, which is used to: generate 16 interleaved sampling clock signals for the main channel; generate 1 synchronous sampling clock signal for the second successive approximation analog-to-digital conversion unit; generate 4 staggered sampling clock signals for the third successive approximation analog-to-digital conversion unit; and generate 1 adjustable phase sampling clock signal for the fourth successive approximation analog-to-digital conversion unit.
7. The high-speed analog-to-digital converter according to claim 1, wherein: The input impedances of the first impedance matching circuit and the second impedance matching circuit are both matched with the output impedance of the external signal source, so as to minimize the reflection of the input signal and improve the integrity and accuracy of signal transmission.
8. The high-speed analog-to-digital converter according to claim 4, wherein: The overall quantization rate of the 16 2-bit analog-to-digital conversion units of the main channel is not less than 64 GS / s to achieve a data transmission rate of up to 64 Gb / s.
9. The high-speed analog-to-digital converter according to claim 4, wherein: The sampling clock frequency of the fourth successive approximation analog-to-digital conversion unit is 1 / 4 of the sampling clock frequency of the main channel, and its sampling clock phase is aligned with the sampling clock phase of the main channel through the phase adjustment circuit to achieve accurate signal quality evaluation.
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High-speed analog-to-digital converter
WO2026114422A1