Hardware processing device of digital signature algorithm

Abstract

The embodiment of the invention provides a hardware processing device for a digital signature algorithm. The device comprises a control logic module, a hash module, a lattice calculation module, a signature logic module and an authentication logic module, the control logic module is used for receiving input data and inputting the input data into the hash module to generate a random polynomial; inputting the random polynomial generated by the hash module into a lattice calculation module for lattice operation; calling the signature logic module to sign the lattice operation result to generate a signature value; and calling the authentication logic module to verify the validity of the signature value. According to the embodiment of the invention, the lattice hash module and the calculation module are independently provided instead of being placed in the signature logic module and the authentication logic module, so that the control logic module can directly call the hash module to generate the random polynomial and call the lattice calculation module to carry out lattice operation, the utilization rate of resources is improved, the operation speed of an algorithm is optimized, and the operation efficiency is improved. And the overall calculation performance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of post-quantum cryptography applications, and in particular to a hardware processing device for a digital signature algorithm. Background Art

[0002] Traditional public key digital signature algorithms are vulnerable to quantum computer attacks, so research institutions at home and abroad are actively designing post-quantum cryptographic algorithm standards that can resist traditional attacks and quantum computer attacks. Lattice-based algorithms are a type of algorithm that can theoretically resist quantum computer attacks, including encryption and decryption algorithms, key negotiation algorithms, and digital signature algorithms. However, the hardware acceleration solutions for this type of post-quantum cryptographic algorithm are still in their early stages, with low computational efficiency and high resource consumption, making it difficult to meet high-performance computing requirements. The high hardware cost also hinders the popularization of post-quantum cryptographic technology. Summary of the invention

[0003] In view of the above problems, an embodiment of the present invention is proposed to provide a hardware processing device for a digital signature algorithm that overcomes the above problems or at least partially solves the above problems.

[0004] According to a first aspect of an embodiment of the present invention, there is provided a hardware processing device for a digital signature algorithm, the device comprising: a control logic module, a hash module, a grid calculation module, a signature logic module and an authentication logic module;

[0005] The control logic module is used to receive input data, input the input data into the hash module to generate a random polynomial; input the random polynomial generated by the hash module into the lattice calculation module to perform lattice operation; call the signature logic module to sign the lattice operation result to generate a signature value; call the authentication logic module to verify the validity of the signature value;

[0006] The hash module is used to convert the original input data into a random polynomial;

[0007] The lattice calculation module is used to perform lattice operations on the random polynomial generated by the hash module; the lattice operations include: number theory transformation, and / or, inverse number theory transformation, and / or, modular reduction, and / or, polynomial multiplication;

[0008] The signature logic module is used to sign the lattice operation result to generate a signature value;

[0009] The authentication logic module is used to verify the validity of the signature value.

[0010] Optionally, the hash module includes a plurality of advanced hash algorithm modules;

[0011] The control logic module is used to divide the input data into blocks according to the input length to obtain multiple data blocks; call at least one advanced hash algorithm module to perform absorption processing and at least one extrusion processing on the multiple data blocks; and obtain a random polynomial according to the extrusion results corresponding to the multiple data blocks after the at least one extrusion processing;

[0012] The advanced hash algorithm module is used to perform XOR processing on the multiple data blocks and the preset initial value one by one in the absorption processing stage to obtain the absorption results corresponding to the multiple data blocks; in the extrusion processing stage, generate hash values ​​according to the absorption results corresponding to the multiple data blocks to obtain the extrusion results corresponding to the multiple data blocks; or generate hash values ​​according to the previous extrusion results corresponding to the multiple data blocks to obtain the extrusion results corresponding to the multiple data blocks.

[0013] Optionally, the advanced hash algorithm module includes an XOR module, a hash processing module and a status register;

[0014] The XOR module is used to perform XOR operations on the multiple data blocks and the preset initial values ​​in the status register one by one during the absorption stage to obtain absorption results corresponding to the multiple data blocks, and write the absorption results corresponding to the multiple data blocks into the status register;

[0015] The hash processing module is used to obtain the absorption results corresponding to the multiple data blocks in the status register during the extrusion processing stage, and generate hash values ​​according to the absorption results corresponding to the multiple data blocks to obtain the extrusion results corresponding to the multiple data blocks; or obtain the previous extrusion results corresponding to the multiple data blocks in the register, generate hash values ​​according to the previous extrusion results corresponding to the multiple data blocks, and obtain the extrusion results corresponding to the multiple data blocks.

[0016] Optionally, the control logic module is further used to obtain the extrusion results corresponding to the multiple data blocks stored in the status register after the hash processing module performs each extrusion processing.

[0017] Optionally, the advanced hash algorithm module is further used to call the XOR module a corresponding number of times according to the number of the multiple data blocks.

[0018] Optionally, the control logic module is further used to determine the number of times the at least one extrusion process is performed according to a preset generation rate.

[0019] Optionally, the grid calculation module includes a plurality of butterfly operation unit modules;

[0020] The control logic module is also used to call at least one of the butterfly operation unit modules to perform the number theory transformation, and / or the inverse number theory transformation, and / or the modular reduction, and / or the polynomial multiplication operations.

[0021] Optionally, the butterfly operation unit module includes four input ports and two output ports; the four input ports include: an A port, a B port, an M port and an ω port, the A port and the B port are used to input polynomial coefficients; the M port is used to input a control signal; the ω port is used to input a preset value, and the preset value is the root of the polynomial ring; the two output ports include: an E port and an O port, which are used to output calculation results.

[0022] Optionally, the butterfly operation unit module is used to input the control signal 1 to the M port and perform the number theoretic transformation operation when performing the number theoretic transformation operation; input the control signal 0 to the M port and perform the inverse number theoretic transformation operation when performing the inverse number theoretic transformation operation; when performing the modular reduction operation, input the control signal 0 to the M port and the coefficient 0 to the B port and perform the modular reduction operation; when performing the polynomial multiplication operation, input the control signal 1 to the M port, or input the control signal 0 to the M port and perform the polynomial multiplication operation.

[0023] Optionally, the device further comprises: a memory controller;

[0024] The control logic module is also used to call the memory controller to read and write the input data, the random polynomial generated by the hash module, the result of the lattice operation and the signature value.

[0025] The technical solution provided by the embodiments of the present invention may have the following beneficial effects:

[0026] The embodiment of the present invention provides a hardware processing device for a digital signature algorithm, the device comprising: a control logic module, a hash module, a lattice calculation module, a signature logic module and an authentication logic module; the control logic module is used to receive input data, input the input data into the hash module to generate a random polynomial; input the random polynomial generated by the hash module into the lattice calculation module to perform lattice operation; call the signature logic module to sign the lattice operation result to generate a signature value; call the authentication logic module to verify the validity of the signature value. The embodiment of the present invention separates the lattice hash module and the calculation module instead of placing them inside the signature logic module and the authentication logic module, so that the control logic module can directly call the hash module to generate a random polynomial and call the lattice calculation module to perform lattice operation, thereby improving resource utilization, optimizing the algorithm's running speed, and achieving an improvement in overall computing performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a structural block diagram of a hardware processing device of a digital signature algorithm provided by an embodiment of the present invention;

[0028] Figure 2 It is a structural block diagram of another hardware processing device of a digital signature algorithm provided by an embodiment of the present invention;

[0029] Figure 3 It is a structural block diagram of another hardware processing device of a digital signature algorithm provided by an embodiment of the present invention;

[0030] Figure 4 It is an internal logic circuit diagram of a butterfly operation unit module provided by an embodiment of the present invention;

[0031] Figure 5 It is a structural block diagram of an application scenario of a hardware processing device for a digital signature algorithm provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] One of the core concepts of the embodiments of the present invention is to separate the lattice hash module and the calculation module instead of placing them inside the signature logic module and the authentication logic module, so that the control logic module can directly call the hash module to generate a random polynomial and call the lattice calculation module to perform lattice operations, thereby improving resource utilization, optimizing the running speed of the algorithm, and achieving an improvement in overall computing performance.

[0034] Reference Figure 1 , shows a structural block diagram of a hardware processing device for a digital signature algorithm provided by an embodiment of the present invention, the device comprising: a control logic module 101, a hash module 102, a grid calculation module 103, a signature logic module 104 and an authentication logic module 105;

[0035] The control logic module 101 is used to receive input data, input the input data into the hash module to generate a random polynomial; input the random polynomial generated by the hash module into the lattice calculation module to perform lattice operation; call the signature logic module to sign the lattice operation result to generate a signature value; call the authentication logic module to verify the validity of the signature value;

[0036] In modern cryptographic systems, especially in the field of post-quantum cryptography, efficient control logic design is crucial to ensure the security and performance of the system. The control logic module 101 is one of the core components of the entire system, responsible for coordinating the workflow of each module to ensure the correct processing and secure transmission of data. Its main functions include receiving input data, generating random polynomials, performing lattice operations, generating signature values, and verifying the validity of signatures. Through carefully designed control logic, the control logic module 101 can achieve efficient computing performance while maintaining high security.

[0037] The control logic module receives input data from different sources, which may include user input, external device transmission, or information generated within the system. To ensure the security and integrity of the data, the control logic module passes these input data to the hash module. The hash module converts the input data into a random polynomial through complex mathematical operations. This process not only increases the randomness and unpredictability of the data, but also provides a basis for subsequent lattice operations. Subsequently, the control logic module passes the random polynomial generated by the hash module to the lattice calculation module. The lattice calculation module performs complex operations based on lattice theory, which are highly secure and resistant to attacks, and can encrypt, decrypt, and verify data. Through lattice operations, the system can ensure the confidentiality and integrity of the data and prevent the data from being tampered with or leaked during transmission and storage.

[0038] After the grid calculation module completes the operation, the control logic module calls the signature logic module. The signature logic module signs the result of the grid operation and generates a signature value. The signature value is an important proof of data integrity and source credibility. Through the signature, the system can ensure that the data has not been tampered with during transmission and storage. The signature logic module uses the preset signature algorithm to encrypt and verify the grid operation result and generate a unique signature value. Finally, the control logic module calls the authentication logic module to verify the validity of the signature value. The authentication logic module verifies the signature value through a series of preset rules and algorithms to ensure that it meets the security requirements of the system. If the signature value verification passes, it means that the data is credible and can be further processed or stored; if the verification fails, it means that the data may have been tampered with or there are other security issues, and the system will refuse to process the data. Through the above series of operations, the control logic module not only ensures the correct flow and processing of data, but also ensures the overall security and reliability of the system. This design enables the system to effectively resist various attacks and threats in a complex network environment and ensure the secure transmission and storage of data.

[0039] The hash module 102 is used to convert the original input data into a random polynomial;

[0040] The original input data can be any form of information, such as text, numbers or binary sequences, depending on the application scenario. These data usually have a certain structure and pattern, which can be easily analyzed and used by attackers. In order to prevent this from happening, the hash module 102 uses an advanced hash function to process the input data. The function of the hash function is to convert input data of any length into a hash value, which can be a random polynomial.

[0041] The generation of random polynomials is crucial to the security and anti-attack performance of the system. In post-quantum cryptography, lattice operations rely on the randomness and complexity of the input polynomial to generate secure keys or parameters. If the randomness of the input data is insufficient, an attacker may derive the key by analyzing the structure of the polynomial, thereby cracking the entire system. Therefore, the random polynomial generated by the hash module 102 must have a high degree of randomness and unpredictability to ensure the security of the lattice operation. In addition, random polynomials are also used to generate digital signatures. The signing process usually involves performing complex mathematical operations on the input data and the generated polynomial to generate a unique signature value. The generation of the signature value relies on the randomness of the polynomial, ensuring the uniqueness and unforgeability of the signature. The recipient can confirm the integrity of the data and the authenticity of the source by verifying the signature value.

[0042] The lattice calculation module 103 is used to perform lattice operations on the random polynomial generated by the hash module; the lattice operations include: number theory transformation, and / or, inverse number theory transformation, and / or, modular reduction, and / or, polynomial multiplication;

[0043] In the post-quantum cryptography system, the lattice computing module 103 is a core component, and its main task is to perform a series of complex lattice operations on the random polynomials generated by the hash module 102. These operations include number theoretic transform (NTT), inverse number theoretic transform (INTT), modular reduction, and polynomial multiplication. Through these operations, the lattice computing module 103 not only improves the computational efficiency of the system, but also ensures the security and integrity of the data.

[0044] Among them, number theoretic transformation is a variant of fast Fourier transform performed on finite fields, which is often used for efficient calculation of polynomial multiplication. In post-quantum cryptography, especially in lattice-based cryptographic algorithms, polynomial multiplication is a basic operation. The time complexity of traditional polynomial multiplication algorithms (such as the school book algorithm) is O, while the use of NTT can complete the same calculation in O time, significantly improving the computational efficiency. Number theoretic transformation makes polynomial multiplication simple and efficient by converting polynomials from coefficient representation to point value representation.

[0045] The inverse number-theoretic transformation is the inverse process of the number-theoretic transformation, which is used to convert the polynomial represented by the point value back to the coefficient representation. After completing the polynomial multiplication, the result needs to be converted from the point value representation back to the coefficient representation for further processing or output. The inverse number-theoretic transformation also has a time complexity of 0, ensuring the efficiency of the entire calculation process. Through the combined use of the number-theoretic transformation and the inverse number-theoretic transformation, the grid calculation module 103 can achieve efficient polynomial operations while maintaining high precision.

[0046] Modular reduction is another important step in lattice computing, which is used to restrict the calculation results to a finite field. In post-quantum cryptography, many algorithms need to operate on a finite field to ensure the uniqueness and security of the results. Modular reduction ensures that the range of the results is within a predetermined range by taking the coefficients of the polynomial modulo a certain modulus. This not only helps prevent overflow and data loss, but also improves the system's resistance to attacks. Modular reduction is often used in conjunction with number theoretic transformations and inverse number theoretic transformations to form a complete and efficient computing process.

[0047] Polynomial multiplication is one of the core operations of the lattice computing module 103, which is used to generate new polynomials or update existing polynomials. In post-quantum cryptography, polynomial multiplication is not only used for key generation and encryption processes, but also for signature generation and verification processes. Through an efficient polynomial multiplication algorithm, the lattice computing module 103 can quickly generate secure keys and signatures to ensure the integrity of the data and the authenticity of the source. Polynomial multiplication can include number theory transformations, inverse number theory transformations, and modular reduction operations to achieve optimal computing performance.

[0048] The signature logic module 104 is used to sign the lattice operation result to generate a signature value;

[0049] The signature logic module 104 ensures that the data has not been tampered with during transmission by signing the result of the lattice operation. In post-quantum cryptography, the secure transmission of data is crucial. Attackers may try to insert malicious data or modify legitimate data during data transmission to deceive or destroy the system. Through the signature mechanism, the receiver can verify the integrity of the data and ensure that the received data is exactly the same as the data sent by the sender. If the data is tampered with during transmission, the signature verification will fail and the receiver will refuse to accept the data.

[0050] The following are the specific operation steps and detailed descriptions of the signature logic module 104 generating the signature value: First, the signature logic module 104 receives the operation result from the lattice operation module. This result is usually a complex value or vector, representing the output of a certain mathematical operation. In order to ensure the integrity of the data and the authenticity of the source, the signature logic module 104 needs to sign the operation result. Next, the signature logic module 104 will select a suitable signature algorithm. Common signature algorithms include digital signature algorithms, elliptic curve digital signature algorithms, etc. The choice of which algorithm depends on the security requirements, performance requirements of the system and the characteristics of the processed data. After selecting the signature algorithm, the signature logic module 104 will generate a pair of keys: a private key and a public key. The private key is used for signing, and the public key is used to verify the validity of the signature. The private key must be kept strictly confidential and only the signature logic module 104 can access it. Then, the signature logic module 104 will use the private key to encrypt the lattice operation result. This encryption process usually involves performing some mathematical operation on the lattice operation result and the private key to generate a unique signature value. This signature value is a "fingerprint" of the lattice operation result, which can uniquely identify the result. The generated signature value is then appended to the lattice operation result to form a composite data structure containing the signature value and the original result. This composite data structure can be transmitted to other modules or systems for subsequent processing or verification. At the receiving end, the verification module can use the public key generated by the signature logic module 104 to verify the validity of the signature value. The verification process involves decrypting the signature value with the public key and comparing it with the original lattice operation result. If the comparison is successful, it means that the data has not been tampered with during the transmission process and the source is credible; otherwise, the data may have been tampered with or the source is untrustworthy.

[0051] In this way, the signature logic module 104 not only ensures the integrity and authenticity of the grid operation results, but also provides additional protection for the security of the system. The generation and verification process of the signature value is an important part of the modern information security system and is widely used in various scenarios that require data integrity and source verification.

[0052] The authentication logic module 105 is used to verify the validity of the signature value.

[0053] The authentication logic module 105 verifies the signature value by using the public key to check whether the signature value is generated by the legitimate sender and whether the data has not been tampered with during transmission. The specific process includes parsing the signature value, verifying the one-time signature, verifying the hierarchical signature and the final signature. Only when all the verification steps are passed can the recipient be sure of the integrity of the data and the authenticity of the source. This process not only prevents data tampering and man-in-the-middle attacks, but also ensures the security and credibility of the system, providing reliable security for application scenarios such as financial transactions, network communications and sensitive information exchange.

[0054] When verifying the validity of the signature value, the authentication logic module 105 mainly relies on the signature value, the public key and the original lattice operation result. The specific operation steps are as follows: First, the authentication logic module 105 receives the signature value and the lattice operation result from the signature logic module 104. The signature value is an encrypted value that represents the "fingerprint" of the lattice operation result, while the lattice operation result is the original mathematical operation output. In order to verify the integrity of the data and the authenticity of the source, the authentication logic module 105 needs to decrypt and compare the signature value. Next, the authentication logic module 105 will obtain the public key generated by the signature logic module 104. The public key is the corresponding part of the private key used in the signing process and is used to verify the validity of the signature value. The public key is public and can be accessed by any module or system that needs to verify the signature. Then, the authentication logic module 105 uses the public key to decrypt the signature value. This decryption process usually involves performing some mathematical operation on the signature value and the public key to restore the "fingerprint" of the original lattice operation result. This "fingerprint" is calculated by the signature logic module 104 when generating the signature value and is used to uniquely identify the lattice operation result. Next, the authentication logic module 105 will compare the decrypted "fingerprint" with the received lattice operation result. This comparison process usually involves recalculating the "fingerprint" of the lattice operation result and comparing it with the decrypted "fingerprint". If the two are completely consistent, it means that the signature value is valid, the data has not been tampered with during transmission, and the source is credible; otherwise, the signature value is invalid, the data may have been tampered with or the source is unreliable. If the signature value verification is successful, the authentication logic module 105 will generate a verification success signal and allow the lattice operation result to continue subsequent processing or use. If the signature value verification fails, the authentication logic module 105 will generate a verification failure signal and refuse to use the lattice operation result, and may trigger a security alarm or take other security measures.

[0055] In this way, the authentication logic module 105 ensures the integrity and authenticity of the grid operation results, providing additional protection for the security of the system. The verification process of the signature value is an important part of the modern information security system and is widely used in various scenarios that require data integrity and source verification, such as financial transactions, data transmission, identity authentication, etc. In practical applications, the authentication logic module 105 also needs to consider the balance between performance and security. For example, select a suitable signature algorithm, optimize the efficiency of decryption operations, ensure the secure distribution of public keys, etc. These factors will affect the accuracy of signature value verification and the overall security of the system.

[0056] Reference Figure 2 , shows a structural block diagram of a hardware processing device for another digital signature algorithm provided in an embodiment of the present invention.

[0057] In one embodiment, the hash module 102 includes multiple advanced hash algorithm modules 21; the control logic module 101 is used to divide the input data into blocks according to the input length to obtain multiple data blocks; call at least one advanced hash algorithm module 21 to perform absorption processing and at least one extrusion processing on the multiple data blocks; obtain a random polynomial based on the extrusion results corresponding to the multiple data blocks after the at least one extrusion processing; the advanced hash algorithm module 21 is used to perform XOR processing on the multiple data blocks and the preset initial value one by one in the absorption processing stage to obtain the absorption results corresponding to the multiple data blocks; in the extrusion processing stage, generate a hash value according to the absorption results corresponding to the multiple data blocks to obtain the extrusion results corresponding to the multiple data blocks; or generate a hash value according to the previous extrusion results corresponding to the multiple data blocks to obtain the extrusion results corresponding to the multiple data blocks.

[0058] The advanced hash algorithm module 21 may be a SHAKE (Secure Hash Algorithm Keccak) module. SHAKE is an extendable output function based on the Keccak algorithm and is part of the SHA-3 (Secure Hash Algorithm 3) family. Specifically, it may be SHA3-SHAKE128 (SHA-3 Extendable-Output Function (XOF) with 128-bit security strength) or SHA3-SHAKE256 (SHA-3 Extendable-Output Function (XOF) with 256-bit security strength). Keccak is a hash function based on a sponge structure. The SHAKE function can generate outputs of any length, which is different from the fixed-length outputs generated by the traditional SHA-2 and SHA-3 hash functions.

[0059] The control logic module 101 first divides the input data into multiple data blocks according to the length of the input data. This process ensures that the data processing is more efficient and controllable. The size of the blocks can be adjusted according to the specific application requirements and system performance. Block processing helps parallel computing and resource optimization, and improves the overall performance of the system. The control logic module 101 calls at least one advanced hash algorithm module 21 to process multiple data blocks. The advanced hash algorithm module 21 usually has strong security and flexibility and can generate outputs of any length. This process includes two main steps: absorption processing and extrusion processing. Absorption processing refers to gradually "absorbing" the input data blocks into the state of the hash algorithm. This process gradually merges each data block into the hash state through multiple iterations to ensure the integrity and randomness of the data. Absorption processing is the core step of the hash algorithm. By continuously updating the state, it ensures that the hash value finally generated has a high degree of randomness and unpredictability. Extrusion processing refers to "extruding" the required output from the state of the hash algorithm. This process can be performed multiple times, each time generating a fixed length of output. Through multiple extrusion processing, outputs of any length can be generated to meet the needs of different application scenarios. Extrusion processing ensures that the generated output has a high degree of randomness and consistency. According to the results of multiple extrusion processes, the control logic module 101 combines the generated outputs to form the final random polynomial. The random polynomial is the basis for subsequent lattice operations and signature generation, and its randomness and uniqueness are crucial to ensuring the security and reliability of the system. Through the absorption and extrusion processing of the advanced hash algorithm, the generated random polynomial has a high degree of randomness and unpredictability, and can effectively resist various attacks.

[0060] In one embodiment, the advanced hash algorithm module 21 includes an XOR module 211, a hash processing module 213 and a status register 212; the XOR module 211 is used to perform an XOR operation on the multiple data blocks and the preset initial value in the status register 212 one by one during the absorption stage to obtain absorption results corresponding to the multiple data blocks, and write the absorption results corresponding to the multiple data blocks into the status register 212; the hash processing module 213 is used to obtain the absorption results corresponding to the multiple data blocks in the status register 212 during the extrusion processing stage, and generate a hash value according to the absorption results corresponding to the multiple data blocks to obtain the extrusion results corresponding to the multiple data blocks; or, obtain the previous extrusion results corresponding to the multiple data blocks in the register, generate a hash value according to the previous extrusion results corresponding to the multiple data blocks, and obtain the extrusion results corresponding to the multiple data blocks.

[0061] The advanced hash algorithm module 21 includes an XOR module 211, a hash processing module 213 and a status register 212 to ensure efficient processing and secure conversion of input data. In the absorption processing stage, the XOR module 211 performs XOR operations on the data blocks with the preset initial values ​​in the status register 212 one by one, generates an absorption result and updates the status register. In the extrusion processing stage, the hash processing module 213 generates a hash value according to the absorption result in the status register 212 or the last extrusion result to obtain the final extrusion result. The status register 212 is used to store intermediate and final hash states to ensure the continuity and consistency of data. This design not only improves the efficiency and security of data processing, but also provides a solid foundation for subsequent lattice operations and signature generation, ensuring the overall performance and reliability of the system.

[0062] XOR operation is a simple and efficient bit operation with good mathematical properties. XOR operation satisfies the commutative law and the associative law, and the result of XORing any value with itself is zero, and the result of XORing any value with zero is itself. These properties make XOR operation widely used in data processing and encryption algorithms. In the absorption stage, XOR operation can gradually "absorb" the information of multiple data blocks into the state register 212. Each data block is XORed with the current value in the state register 212, which is equivalent to mixing the information of the data block with the information in the state register 212. This mixing operation helps to ensure that the information of each data block is evenly distributed in the state register 212, thereby enhancing the randomness and security of the data. Writing the result of the XOR operation back to the state register 212 can ensure that the value in the state register 212 is continuously updated to reflect the information of all processed data blocks. This gradual update method helps to maintain the integrity and consistency of the state register 212 and avoid information loss or duplication. The simplicity and efficiency of the XOR operation make it have low resource consumption and high processing speed in hardware implementation. This is especially important for scenarios that require fast processing of large amounts of data, such as encryption algorithms, hash functions, and stream ciphers.

[0063] Hash processing module 213, namely Keccak (Keccak cryptographic hash function). Keccak is an efficient hash function widely used in encryption and data integrity verification. It converts input data into a hash value of fixed length through a series of complex permutation and obfuscation operations. This conversion process is irreversible and collision-resistant, ensuring that the generated hash value can uniquely represent the input data and is difficult to be tampered with or forged. In the extrusion processing stage, the hash processing module 213 obtains the absorption results from the state register 212 and generates a hash value based on these results. This process is equivalent to compressing and summarizing the information accumulated in the absorption stage to generate an output of fixed length. This compression and summary operation helps to reduce the redundancy of data and improve the density and security of information. The hash processing module 213 also supports the generation of a new hash value based on the last extrusion result. This iterative processing method enables the hash processing module 213 to process a large amount of data and generate a new hash value in each iteration. This iterative processing not only improves the processing efficiency, but also enhances the randomness and unpredictability of the hash value, thereby improving the security of the system. The design of the hash processing module 213 fully utilizes the storage capacity of the state register 212 and the mathematical properties of the XOR operation. By taking the absorption result and the last extrusion result as input, the hash processing module 213 can generate a high-quality hash value to ensure the integrity of the data and the authenticity of the source. This design is not only applicable to single hash processing, but also to multiple iterative processing to meet the needs of different application scenarios.

[0064] like Figure 2 As shown, the start control logic module 101 controls the operation flow inside the advanced hash algorithm module 21, calls the XOR module 211 according to the length of the input data, performs XOR operation on multiple data blocks and the preset initial value in the state register 212, wherein the initial value is a 1600-bit zero value, and obtains the absorption results corresponding to the multiple data blocks. The hash processing module 213 obtains the absorption result in the state register in the extrusion processing stage, obtains the extrusion result according to the absorption result, and if multiple basic operations are required, the last extrusion result in the register is obtained in the subsequent extrusion processing to perform the extrusion operation and generate a hash value. Since the data length that the advanced hash algorithm module 21 needs to output may exceed 1600 bits, and the length of the state register 212 is only 1600 bits. Therefore, the current state can be set to 1 after the partial extrusion operation is completed, and after the extrusion operation is completed, jump to the waiting state, set the current state to 1, and then set the continuation signal to 1, and jump to the reading state, read the data from the state register and output the data from the output port. If the extrusion operation has not been completed, jump to the extrusion state again, repeat the above operation until all extrusion operations are completed and all data are output.

[0065] In one embodiment, the control logic module 101 is further configured to obtain the extrusion results corresponding to the multiple data blocks stored in the status register 212 after the hash processing module 213 performs an extrusion process each time.

[0066] After the hash processing module 213 completes an extrusion process, the control logic module 101 needs to obtain the extrusion result in time to ensure the continuity and consistency of the data flow and processing flow of the system. This timely acquisition and processing of the extrusion result helps to avoid data loss or processing delays and improve the overall efficiency of the system. After obtaining the extrusion result, the control logic module 101 can further process or store the extrusion result according to the specific needs of the system. For example, the extrusion result can be passed to other modules for verification, encryption or decryption operations, or the extrusion result can be stored in a memory or an external storage device for subsequent use.

[0067] In one embodiment, the advanced hash algorithm module 21 is further used to call the XOR module 211 a corresponding number of times according to the number of the multiple data blocks.

[0068] XOR operation satisfies the commutative law and the associative law, and the result of XORing any value with itself is zero, and the result of XORing any value with zero is itself. These properties make XOR operation widely used in data processing and encryption algorithms. By calling XOR module 211 a corresponding number of times, advanced hash algorithm module 21 can ensure that the information of each data block is evenly distributed to the status register 212, thereby enhancing the randomness and security of the data. Calling XOR module 211 according to the number of multiple data blocks helps to ensure the integrity and consistency of the hash algorithm. Each data block needs to be XORed with the current value in the status register 212 during the absorption phase to ensure that the information of all data blocks is correctly processed. This one-by-one processing method avoids information loss or duplication and ensures the accuracy and reliability of the hash result.

[0069] In one embodiment, the control logic module 101 is further used to determine the number of times the at least one extrusion process is performed according to a preset generation rate.

[0070] The preset generation rate refers to the number of hash values ​​or data blocks that the system needs to generate or process per unit time. The control logic module 101 determines the number of times of extrusion processing according to this rate to ensure that the system can meet the real-time requirements. For example, in high-speed data transmission or real-time encryption applications, the system needs to quickly generate a large number of hash values ​​to ensure the integrity and security of the data. By determining the number of times of extrusion processing according to the preset generation rate, the control logic module 101 can dynamically adjust the processing frequency to adapt to different application requirements. In addition, determining the number of times of extrusion processing helps to optimize the use of system resources. In some cases, the system may need to efficiently complete a large number of data processing tasks under limited resources (such as processor time, memory bandwidth). By determining the number of times of extrusion processing according to the preset generation rate, the control logic module 101 can avoid excessive consumption of resources while ensuring processing efficiency, thereby improving the overall performance and stability of the system.

[0071] In one embodiment, the lattice calculation module includes multiple butterfly operation unit modules; the control logic module 101 is also used to call at least one of the butterfly operation unit modules 22 to perform the number theory transformation, and / or the inverse number theory transformation, and / or the modular reduction, and / or the polynomial multiplication operations.

[0072] Reference Figure 3 , shows a structural block diagram of a hardware processing device for another digital signature algorithm provided in an embodiment of the present invention.

[0073] The butterfly operation unit module 22 is a core component for implementing complex mathematical operations. These operations are widely used in grid computing for operations such as polynomial multiplication and modular reduction, and have a high degree of parallelism and computational efficiency. By including multiple butterfly operation unit modules 22, the grid computing module can handle multiple computing tasks at the same time, improving the overall computing speed and throughput. The control logic module 101 is responsible for coordinating and managing the operation of each module to ensure the efficiency and stability of the system. In the grid computing process, number theory transformation, inverse number theory transformation, modular reduction and polynomial multiplication operations usually need to be executed in a specific order and under specific conditions. By calling at least one butterfly operation unit module 22, the control logic module 101 can flexibly allocate computing resources to ensure that each operation can be processed in a timely manner to avoid resource conflicts and processing delays.

[0074] In one embodiment, the butterfly operation unit module 22 includes four input ports and two output ports; the four input ports include: an A port, a B port, an M port and an ω port, the A port and the B port are used to input polynomial coefficients; the M port is used to input a control signal; the ω port is used to input a preset value, and the preset value is the root of the polynomial ring; the two output ports include: an E port and an O port, which are used to output calculation results.

[0075] Reference Figure 4 , shows an internal logic circuit diagram of a butterfly operation unit module 22 provided by an embodiment of the present invention. Since the operation forms of number theory transformation, inverse number theory transformation, modular reduction and polynomial multiplication are similar, the interface of the butterfly operation unit module 22 is unified, and the interface can be highly reused. By using only the butterfly operation unit module 22 to perform these calculations, the saved space can be used to copy multiple butterfly operation unit modules 22 to achieve parallel calculation, thereby improving the overall calculation performance.

[0076] In one embodiment, the butterfly operation unit module 22 is used to input the control signal 1 to the M port and perform the number theory transformation operation when performing the number theory transformation operation; input the control signal 0 to the M port and perform the inverse number theory transformation operation when performing the inverse number theory transformation operation; when performing the modular reduction operation, input the control signal 0 to the M port and the coefficient 0 to the B port and perform the modular reduction operation; when performing the polynomial multiplication operation, input the control signal 1 to the M port, or input the control signal 0 to the M port and perform the polynomial multiplication operation.

[0077] Different operations require different control signals to activate the corresponding operation logic. By inputting different control signals at the M port, the butterfly operation unit module 22 can accurately identify and execute the corresponding operation to ensure that each operation can be performed correctly. For example, number theory transformation and polynomial multiplication require the M port to input control signal 1, while inverse number theory transformation and modular reduction require the M port to input control signal 0. This design simplifies the control logic and reduces hardware complexity. Through a single control signal port (M port), the butterfly operation unit module 22 can flexibly switch different operations without the need for complex control circuits or multiple control signal ports. This simplified design improves the reliability and maintainability of the system.

[0078] In one embodiment, the apparatus further includes: a memory controller 105;

[0079] The control logic module 101 is further used to call the memory controller 105 to read and write the input data, the random polynomial generated by the hash module 102, the result of the lattice operation and the signature value.

[0080] The memory controller 105 is responsible for managing the memory resources of the system to ensure efficient storage and access of data. In complex computing tasks, such as lattice operations and signature generation, large amounts of data need to be frequently read and written. By calling the memory controller 105, the control logic module 101 can efficiently manage these data to ensure that they can be stored and read in a timely manner to avoid data loss or processing delays. Among them, the control logic module 101 also calls the memory controller 105 to read the extrusion results each time to obtain a polynomial input to the butterfly operation unit module 22. Calling the memory controller 105 to read and write data helps to optimize the use of system resources. Different data (such as input data, random polynomials, lattice operation results, and signature values) may require different storage strategies and access frequencies. By dynamically calling the memory controller 105, the control logic module 101 can allocate memory resources according to actual needs, avoid excessive consumption of resources, and improve the overall performance and efficiency of the system.

[0081] Reference Figure 5 , shows an application scenario structural block diagram of a hardware processing device for a digital signature algorithm provided by an embodiment of the present invention.

[0082] Applicable to a variety of computing devices and processors. These computing devices include laptops, tablets, notebooks, desktop computers, workstations, smartphones, wearable computing devices, embedded devices, routers, and other computing and communication devices. The processor can be a single-core or multi-core processor, a digital signal processor, a microcontroller, or other processing or control circuit. The memory can be any type of volatile or non-volatile memory or data storage device. The communication module is responsible for sending and receiving various information, including digital signatures, public keys, and other data.

[0083] The embodiment of the present invention provides a hardware processing device for a digital signature algorithm, the device comprising: a control logic module, a hash module, a lattice calculation module, a signature logic module and an authentication logic module; the control logic module is used to receive input data, input the input data into the hash module to generate a random polynomial; input the random polynomial generated by the hash module into the lattice calculation module to perform lattice operation; call the signature logic module to sign the lattice operation result to generate a signature value; call the authentication logic module to verify the validity of the signature value. The embodiment of the present invention separates the lattice hash module and the calculation module instead of placing them inside the signature logic module and the authentication logic module, so that the control logic module can directly call the hash module to generate a random polynomial and call the lattice calculation module to perform lattice operation, thereby improving resource utilization, optimizing the algorithm's running speed, and achieving an improvement in overall computing performance.

[0084] It should be noted that, for the sake of simplicity, the device embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the described action sequence, because according to the embodiments of the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0085] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0086] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0087] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0088] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0089] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0090] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0091] The hardware processing device of a digital signature algorithm provided by the present invention is introduced in detail above. Specific examples are used in this article to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A hardware processing device for a digital signature algorithm, characterized in that: include: Control logic module, hash module, grid calculation module, signature logic module and authentication logic module; The control logic module is used to receive input data, input the input data into the hash module to generate a random polynomial; input the random polynomial generated by the hash module into the lattice calculation module to perform lattice operation; call the signature logic module to sign the lattice operation result to generate a signature value; Calling the authentication logic module to verify the validity of the signature value; The hash module is used to convert the original input data into a random polynomial; The lattice calculation module is used to perform lattice operations on the random polynomial generated by the hash module; the lattice operations include: number theory transformation, and / or, inverse number theory transformation, and / or, modular reduction, and / or, polynomial multiplication; The signature logic module is used to sign the lattice operation result to generate a signature value; The authentication logic module is used to verify the validity of the signature value.

2. The device according to claim 1, characterized in that The hash module includes a plurality of advanced hash algorithm modules; The control logic module is used to divide the input data into blocks according to the input length to obtain multiple data blocks; Calling at least one advanced hash algorithm module to perform absorption processing and at least one extrusion processing on the multiple data blocks; Obtaining a random polynomial according to extrusion results corresponding to the plurality of data blocks after the at least one extrusion process; The advanced hash algorithm module is used to perform XOR processing on the multiple data blocks and the preset initial value one by one during the absorption processing stage to obtain absorption results corresponding to the multiple data blocks; In the extrusion processing stage, a hash value is generated according to the absorption results corresponding to the multiple data blocks to obtain the extrusion results corresponding to the multiple data blocks; or, a hash value is generated according to the previous extrusion results corresponding to the multiple data blocks to obtain the extrusion results corresponding to the multiple data blocks.

3. The device according to claim 2, characterized in that The advanced hash algorithm module includes an XOR module, a hash processing module and a status register; The XOR module is used to perform XOR operations on the multiple data blocks and the preset initial values ​​in the status register one by one during the absorption stage to obtain absorption results corresponding to the multiple data blocks, and write the absorption results corresponding to the multiple data blocks into the status register; The hash processing module is used to obtain the absorption results corresponding to the multiple data blocks in the status register during the extrusion processing stage, and generate hash values ​​according to the absorption results corresponding to the multiple data blocks to obtain the extrusion results corresponding to the multiple data blocks; or obtain the previous extrusion results corresponding to the multiple data blocks in the register, generate hash values ​​according to the previous extrusion results corresponding to the multiple data blocks, and obtain the extrusion results corresponding to the multiple data blocks.

4. The device according to claim 3, characterized in that The control logic module is further configured to obtain extrusion results corresponding to the multiple data blocks stored in the status register after the hash processing module performs extrusion processing each time.

5. The device according to claim 2, characterized in that The advanced hash algorithm module is also used to call the XOR module a corresponding number of times according to the number of the multiple data blocks.

6. The device according to claim 2, characterized in that The control logic module is further used to determine the number of times the at least one extrusion process is performed according to a preset generation rate.

7. The device according to claim 1, characterized in that The grid computing module includes a plurality of butterfly computing unit modules; The control logic module is also used to call at least one of the butterfly operation unit modules to perform the number theory transformation, and / or the inverse number theory transformation, and / or the modular reduction, and / or the polynomial multiplication operations.

8. The device according to claim 7, characterized in that The butterfly operation unit module includes four input ports and two output ports; the four input ports include: A port, B port, M port and ω port, the A port and B port are used to input polynomial coefficients; the M port is used to input control signals; the ω port is used to input preset values, and the preset values ​​are the roots of the polynomial ring; the two output ports include: E port and O port, which are used to output calculation results.

9. The device according to claim 8, characterized in that The butterfly operation unit module is used to input the control signal 1 to the M port and perform the number theory transformation operation when performing the number theory transformation operation; input the control signal 0 to the M port and perform the inverse number theory transformation operation when performing the inverse number theory transformation operation; when performing the modular simplification operation, input the control signal 0 to the M port and the coefficient 0 to the B port and perform the modular simplification operation; when performing the polynomial multiplication operation, input the control signal 1 to the M port, or input the control signal 0 to the M port and perform the polynomial multiplication operation.

10. The device according to claim 1, characterized in that The device also includes: a memory controller; The control logic module is also used to call the memory controller to read and write the input data, the random polynomial generated by the hash module, the result of the lattice operation and the signature value.

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