Network accelerator card signal indication method and device based on state feedback

Abstract

The invention provides a network accelerator card signal indication method and device based on state feedback in the technical field of network equipment signal indication. The method comprises the following steps: S1, setting a first timer, a second timer and a third timer 3 by a CPLD (Complex Programmable Logic Device); s2, after the network accelerator card is started, recording the power-on duration t2 of the CPU by taking the delta t2 as the time interval through the second timer; when the key is pressed down, recording the press-down duration t1 of the key by taking delta t1 as a time interval through the first timer, and recording the press-down duration t3 of the key by taking delta t3 as a time interval through the third timer; s3, based on the t1, the t2 and the t3, the CPLD identifies a key to trigger a startup and shutdown function, a reset function or a CMOS clearing function; and S4, in the operation process of the network accelerator card, controlling a double-color indicator lamp to indicate a starting state, a fault state or a host recognition state. The network accelerator card has the advantages that the functionality of the keys and the indicator lamps is greatly improved, and then the spatial layout of the network accelerator card is greatly optimized.

Description

Technical Field

[0001] The present invention relates to the technical field of network device signal indication, and in particular to a network acceleration card signal indication method and device based on state feedback. Background Art

[0002] Network accelerator cards are a growing category of network devices used to optimize network transmission, reduce latency, and improve data transmission efficiency. One design approach for network accelerator cards utilizes an x86 CPU, migrating server applications to a PCIe accelerator card with an integrated x86 CPU and multiple network ports. These cards are very densely packed, housing a CPU, memory, and at least two network ports, while also limiting the space available for interfaces. To meet the functional requirements of network accelerator cards, they include three SFP+ ports, ten optical ports, one USB Type-C port, one Micro USB port, one RJ45 management port, and three network port indicators. This complicates the interface panel space, making it impossible to accommodate power buttons, reset buttons, power indicators, and fault indicators. This compromises the functionality of the network accelerator card, which relies on buttons and indicators for signaling.

[0003] For example, Chinese utility model patent application number CN201620169928.7, classification number G08B25 / 10, discloses a novel computer network security alarm device that optimizes spatial layout by reusing function buttons and alarm indicators. Chinese invention patent application number CN201610925586.1, classification number G08B5 / 36, discloses a multifunctional signal indicator button, which also reuses indicators and buttons to optimize spatial layout.

[0004] Therefore, how to provide a network acceleration card signal indication method and device based on status feedback to improve the functionality of buttons and indicator lights, and then optimize the spatial layout of the network acceleration card, has become a technical problem that needs to be solved urgently. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a network acceleration card signal indication method and device based on state feedback, so as to improve the functionality of buttons and indicator lights, and further optimize the spatial layout of the network acceleration card.

[0006] In a first aspect, the present invention provides a network accelerator card signal indication method based on state feedback, comprising the following steps: Step S10: The CPLD of the network accelerator card sets a first timer for recording the duration of a key press, a second timer for recording the duration of a CPU power-on, and a third timer for recording the duration of a key press, wherein the maximum count values ​​of the first timer, the second timer, and the third timer are T1, T2, and T3, respectively, and the counting time intervals are Δt1, Δt2, and Δt3, respectively, and 4*T1=2*T2=T3, and Δt1<Δt2=Δt3; Step S20: After the network accelerator card is powered on, the second timer records the CPU power-on duration t2 at intervals of Δt2; when a key is pressed, the first timer records the key press duration t1 at intervals of Δt1, and the third timer records the key press duration t3 at intervals of Δt3; Step S30: The CPLD identifies the button status feedback based on t1, t2, and t3 to trigger a signal indication of a power on / off function, a reset function, or a clear CMOS function. Step S40: During the operation of the network acceleration card, the dual-color indicator light is controlled to provide a signal indication of the startup state, fault state, or host identification state.

[0007] Furthermore, in step S10, the value of T1 is 4 seconds, the value of T2 is 8 seconds, the value of T3 is 16 seconds, the value of Δt1 is 100 milliseconds, the value of Δt2 is 1 second, and the value of Δt3 is 1 second.

[0008] Furthermore, the step S20 is specifically as follows: When the button is pressed in the shutdown state, the CPLD detects that the voltage input of the power module is in the range of (2.4V, 3.3V) through the first voltage sensor, and detects that the CPU power signal CORE_OK is high through the second voltage sensor, and the network accelerator card is powered on. The second timer records the CPU power-on duration t2 at an interval of Δt2; when a key is pressed, the first timer records the key pressing duration t1 at an interval of Δt1, and the third timer records the key pressing duration t3 at an interval of Δt3; When the key is released, the counts of the first timer and the third timer are cleared; when a low level is detected in the CPU input, the count of the second timer is cleared.

[0009] Furthermore, in step S30, the power on / off function is triggered specifically as follows: The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state. Then, the CPLD sends a power-on / off signal PWRBTN to the CPU. If so, the CPLD: Determine whether t1 recorded by the first timer exceeds 3 seconds. If so, send a power-on / off signal PWRBTN to the CPU; if not, do not send the power-on / off signal PWRBTN to the CPU. The reset function is triggered specifically as follows: The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and does not send a reset signal RSTBTN to the CPU. If so, then: Read t1 recorded by the first timer to determine whether it satisfies 100 milliseconds ≤ t1 ≤ 1 second. If so, send a reset signal RSTBTN to the CPU; if not, do not send a reset signal RSTBTN to the CPU. The clear CMOS function is specifically as follows: The CPLD reads t3 recorded by the third timer, and sets the CMOS clear register when t3 is greater than 12 seconds, turns on the red light and keeps it on. After the first voltage sensor detects that the power module is powered off, it sends a clear CMOS signal CLEAR_CMOS to the RTC control circuit.

[0010] Furthermore, the step S40 specifically includes: Step S41: The CPLD sets a control mode register. During the operation of the network accelerator card, the CPLD determines the value of the control mode register. When the value is 0, it is the automatic control mode, and the process proceeds to step S42; when the value is 1, it is the manual control mode, and the process proceeds to step S43. Step S42: Divide the 2.24-second indication cycle time of the dual-color indicator light into seven 320-millisecond time slices, with the first four time slices used for status indication and the last three time slices used for cycle interval identification; when the status indication is flashing, the dual-color indicator light is on for 40 milliseconds and off for 280 milliseconds within one time slice; A shift register and a status register are set for the green light and the red light respectively; the values ​​of the shift register are 000000, 000001, 000011, 000111, 001111, 011111, 111111; the values ​​of the status register are 000000, 000001, 000011, 000111, 001111, which respectively represent off, flash once, flash twice, flash three times, and flash four times; The CPLD controls the green light to work based on the values ​​of the corresponding shift register and status register to indicate the startup status of the CPU; The CPLD controls the operation of the red light based on the values ​​of the corresponding shift register and status register to indicate a fault state; Step S43: Based on the control instruction input by the CPU, the CPLD controls the dual-color indicator light to turn on, off, or flash at 1 Hz to indicate the host recognition status.

[0011] In a second aspect, the present invention provides a network accelerator card signal indication method based on state feedback, comprising the following modules: A timer setting module, configured to set a first timer for recording a key press duration, a second timer for recording a CPU power-on duration, and a third timer for recording a key press duration in a CPLD of a network accelerator card, wherein maximum count values ​​of the first timer, the second timer, and the third timer are T1, T2, and T3, respectively, and counting time intervals are Δt1, Δt2, and Δt3, respectively, and 4*T1=2*T2=T3, and Δt1<Δt2=Δt3; The timer counting module is used to record the CPU power-on time t2 by the second timer at an interval of Δt2 after the network acceleration card is powered on; when a key is pressed, the first timer records the key press time t1 by an interval of Δt1, and the third timer records the key press time t3 by an interval of Δt3; A first signal indication module is used for the CPLD to identify the state feedback of the key based on the t1, t2 and t3 to trigger the signal indication of the power on / off function, the reset function or the clear CMOS function; The second signal indication module is used to control the dual-color indicator light to provide signal indication of the startup status, fault status or host identification status during the operation of the network acceleration card.

[0012] Furthermore, in the timer setting module, the value of T1 is 4 seconds, the value of T2 is 8 seconds, the value of T3 is 16 seconds, the value of Δt1 is 100 milliseconds, the value of Δt2 is 1 second, and the value of Δt3 is 1 second.

[0013] Furthermore, the timer counting module is specifically used to: When the button is pressed in the shutdown state, the CPLD detects that the voltage input of the power module is in the range of (2.4V, 3.3V) through the first voltage sensor, and detects that the CPU power signal CORE_OK is high through the second voltage sensor, and the network accelerator card is powered on. The second timer records the CPU power-on duration t2 at an interval of Δt2; when a key is pressed, the first timer records the key pressing duration t1 at an interval of Δt1, and the third timer records the key pressing duration t3 at an interval of Δt3; When the key is released, the counts of the first timer and the third timer are cleared; when a low level is detected in the CPU input, the count of the second timer is cleared.

[0014] Furthermore, in the first signal indication module, the power on / off function is triggered specifically as follows: The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state. Then, the CPLD sends a power-on / off signal PWRBTN to the CPU. If so, the CPLD: Determine whether t1 recorded by the first timer exceeds 3 seconds. If so, send a power-on / off signal PWRBTN to the CPU; if not, do not send the power-on / off signal PWRBTN to the CPU. The reset function is triggered specifically as follows: The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and does not send a reset signal RSTBTN to the CPU. If so, then: Read t1 recorded by the first timer to determine whether it satisfies 100 milliseconds ≤ t1 ≤ 1 second. If so, send a reset signal RSTBTN to the CPU; if not, do not send a reset signal RSTBTN to the CPU. The clear CMOS function is specifically as follows: The CPLD reads t3 recorded by the third timer, and sets the CMOS clear register when t3 is greater than 12 seconds, turns on the red light and keeps it on. After the first voltage sensor detects that the power module is powered off, it sends a clear CMOS signal CLEAR_CMOS to the RTC control circuit.

[0015] Furthermore, the second signal indication module specifically includes: The control mode selection unit is used for the CPLD to set a control mode register. During the operation of the network accelerator card, the CPLD determines the value of the control mode register. When the value is 0, it is the automatic control mode and the automatic control unit is called; when the value is 1, it is the manual control mode and the manual control unit is called; An automatic control unit, configured to divide the 2.24-second indication cycle time of the bi-color indicator light into seven 320-millisecond time slices, wherein the first four time slices are used for status indication and the last three time slices are used for cycle interval identification; when the status indication is flashing, the bi-color indicator light is on for 40 milliseconds and off for 280 milliseconds within one time slice; A shift register and a status register are set for the green light and the red light respectively; the values ​​of the shift register are 000000, 000001, 000011, 000111, 001111, 011111, 111111; the values ​​of the status register are 000000, 000001, 000011, 000111, 001111, which respectively represent off, flash once, flash twice, flash three times, and flash four times; The CPLD controls the green light to work based on the values ​​of the corresponding shift register and status register to indicate the startup status of the CPU; The CPLD controls the operation of the red light based on the values ​​of the corresponding shift register and status register to indicate a fault state; The manual control unit is used for the CPLD to control the dual-color indicator light to turn on, off, or flash at 1Hz to indicate the host recognition status based on the control instructions input by the CPU.

[0016] The advantages of the present invention are: 1. The CPLD of the network accelerator card sets the first, second, and third timers. After the network accelerator card is powered on, the second timer records the CPU power-on duration t2 at an interval of Δt2. When a key is pressed, the first timer records the key press duration t1 at an interval of Δt1, and the third timer records the key press duration t3 at an interval of Δt3. The difference between the first and third counters lies in the counting duration and accuracy. The CPLD then identifies the key status feedback based on t1, t2, and t3 to trigger the power on / off function, reset function, or clear CMOS function signal indication. During operation of the network accelerator card, the control mode register, shift register, and status register control the dual-color indicator light to indicate the startup status, fault status, or host identification status. That is, the power on / off function, reset function, and clear CMOS function signal indication are achieved through a single button, and the startup status, fault status, and host identification status signal indication are achieved through a single dual-color indicator light. This greatly improves the functionality of the button and indicator light, thereby greatly optimizing the spatial layout of the network accelerator card.

[0017] 2. By setting t2 recorded by the second timer to be equal to T2 and t1 recorded by the first timer to be in [100 milliseconds, 1 second], the reset signal RSTBTN is sent to the CPU. That is, the CPU needs to be powered on for more than 8 seconds and the key press duration must meet [100 milliseconds, 1 second] before the reset is initiated. If the key is pressed for less than 100 milliseconds, it is judged as a false operation, thereby greatly improving the accuracy of reset function recognition and the reliability of startup.

[0018] 3. By setting the t2 recorded by the second timer to be less than T2, the power-on / off signal PWRBTN is directly sent to the CPU. If t2 is equal to T2 and t1 recorded by the first timer exceeds 3 seconds, the power-on / off signal PWRBTN is sent to the CPU. This allows the network accelerator card to be powered on immediately by pressing the button when it is powered off. When the network accelerator card is powered on, the button must be pressed for more than 3 seconds to trigger the power-on / off function. That is, there is a time difference between the power-on / off function and the reset function. The button pressing duration is [100 milliseconds, 1 second] for the reset function, [1 second, 3 seconds] for an invalid action, and more than 3 seconds for the power-on / off function. This can effectively distinguish between the reset function and the power-on / off function, thereby greatly improving the reliability of the network accelerator card control.

[0019] 4. By setting the first timer and the third timer to record the duration of key presses, the maximum count value of the first timer is 4 seconds, and the maximum count value of the third timer is 16 seconds. The t3 recorded by the third timer needs to be greater than 12 seconds before the CMOS clear register is set. This can effectively identify whether the CMOS clear function is triggered, further improving the reliability and convenience of network acceleration card control.

[0020] 5. By dividing the 2.24-second indication cycle time of the dual-color indicator light into 7 320-millisecond time slices, the first 4 time slices are used for status indication, and the last 3 time slices are used for cycle interval identification; when the status indication is flashing, the dual-color indicator light is on for 40 milliseconds and off for 280 milliseconds in one time slice, allowing users to clearly identify the number of flashes and cycle intervals, thereby greatly improving the usability and functionality of the dual-color indicator light.

[0021] 6. By setting CPLD to control buttons and dual-color indicators, the corresponding functions and status indications can be executed even when the CPU is powered off, greatly improving the reliability of network acceleration card control. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] Figure 1 The present invention is a flow chart of a network acceleration card signal indication method based on state feedback.

[0024] Figure 2 It is a structural schematic diagram of a network acceleration card signal indicating device based on state feedback of the present invention.

[0025] Figure 3 This is a circuit principle block diagram of the network acceleration card of the present invention.

[0026] Figure 4 It is a circuit diagram of the RTC control circuit of the present invention.

[0027] Figure 5 Schematic diagram of the circuit for controlling mode switching of the present invention. DETAILED DESCRIPTION

[0028] The technical solution in the embodiments of the present application has the following overall idea: using the first timer, the second timer, and the third timer to identify the power on / off function, the reset function, and the CMOS clearing function of the button, and controlling the mode register, the shift register, and the status register to control the indicator light to indicate the startup state, the fault state, and the host identification state, so as to improve the functionality of the buttons and indicator lights, reduce the number of buttons and indicator lights arranged on the interface panel of the network acceleration card, and thereby optimize the spatial layout of the network acceleration card.

[0029] Please refer to Figures 1 to 5 As shown, the present invention requires the use of the following network acceleration card, including a CPLD, a CPU, an RTC control circuit, a button, a two-color indicator light, a pull-up resistor, a power module, a first voltage sensor, and a second voltage sensor; The RTC control circuit includes a diode D1, a MOS transistor Q1, a capacitor C1 and a resistor R1; After the capacitor C1 and the resistor R1 are connected in parallel, one end is connected to the source of the MOS transistor Q1 and to ground, and the other end is connected to the output end of the diode D1 and the gate of the MOS transistor Q1; the CPLD is respectively connected to the CPU, the button, the two-color indicator light, the pull-up resistor, the first voltage sensor, the second voltage sensor, and the input end of the diode D1; the output end of the power module is connected to the pull-up resistor and the first voltage sensor; and the input end of the second voltage sensor is connected to the CPU.

[0030] The button is a multifunctional touch switch with a jitter elimination function; the button is connected to a power module through a pull-up resistor and is connected to an input pin of the CPLD, and the power module is used to provide a 3.3V standby power supply.

[0031] The CPLD uses one pin (CORE_OK) to monitor the power-on status of the CPU. A low level indicates the shutdown state, and a high level indicates the power-on state. One pin (P3V3SB_OK) is used to monitor the standby power supply status of the power module. When the voltage is lower than 2.4V, the output low level indicates that the power has been cut off, otherwise it indicates that the power supply is normal. The CPLD sends a power on / off signal (PWRBTN) and a reset signal (RSTBTN) to the CPU and sends a clear CMOS signal (CLEAR_CMOS) to the RTC control circuit according to the action of the button.

[0032] When the button is released, the signal fed back to the CPLD is high. When the button is pressed, the signal fed back to the CPLD is low. The CPLD determines whether to send a power on / off signal (PWRBTN) or a reset signal (RSTBTN) to the CPU based on the low-level duration of the button and the status of CORE_OK.

[0033] A preferred embodiment of a network accelerator card signal indication method based on state feedback of the present invention includes the following steps: Step S10: The CPLD of the network accelerator card sets a first timer for recording the duration of a key press, a second timer for recording the duration of a CPU power-on, and a third timer for recording the duration of a key press. The maximum count values ​​of the first timer, the second timer, and the third timer are T1, T2, and T3, respectively. The counting time intervals are Δt1, Δt2, and Δt3, respectively. 4*T1=2*T2=T3, and Δt1<Δt2=Δt3. The first timer and the third timer are both used to record the duration of a key press, but differ in that the maximum count values ​​(the maximum value of the recording duration) and the counting time intervals (the resolution) are different. By setting Δt1<Δt3, that is, reducing the resolution of the third timer, resource usage can be reduced. Step S20: After the network accelerator card is powered on, the second timer records the CPU power-on duration t2 at intervals of Δt2; when a key is pressed, the first timer records the key press duration t1 at intervals of Δt1, and the third timer records the key press duration t3 at intervals of Δt3; Step S30: The CPLD identifies the button status feedback based on t1, t2, and t3 to trigger a signal indication of a power on / off function, a reset function, or a clear CMOS function. Step S40: During operation of the network accelerator card, the dual-color indicator light is controlled to indicate the startup status, fault status, or host identification status. The dual-color indicator light on the network accelerator card consists of a single green and red light. Green indicates the CPU startup status, while red indicates a fault status and clearing CMOS events. Different states are indicated by the number of flashes. When both the green and red lights are on, the dual-color indicator light turns orange. By default, the dual-color indicator light is automatically controlled by the CPLD. Manual control can also be enabled via the control mode register (manual_en). This allows the CPU to use the dual-color indicator light to indicate host identification status. The CPLD or CPU outputs the dual-color indicator light control signal, led_out.

[0034] In step S10, the value of T1 is 4 seconds, the value of T2 is 8 seconds, the value of T3 is 16 seconds, the value of Δt1 is 100 milliseconds, the value of Δt2 is 1 second, and the value of Δt3 is 1 second.

[0035] Specifically, the first timer has a maximum count value of 4 seconds and a counting interval of 100 milliseconds. It starts counting when a key is pressed and generates a low level, and stops counting and clears the count when the key is released. The second timer has a maximum count value of 8 seconds and a counting interval of 1 second. It starts counting when the second voltage sensor outputs a high level, and stops counting and clears the count when it outputs a low level. The third timer has a maximum count value of 16 seconds and a counting interval of 1 second. It starts counting when a key is pressed and generates a low level, and stops counting and clears the count when the key is released. The difference between the first and third counters lies in their counting duration and accuracy.

[0036] The step S20 is specifically as follows: When the button is pressed in the shutdown state, the CPLD detects that the voltage input of the power module is in the range of (2.4V, 3.3V) through the first voltage sensor, and detects that the CPU power signal CORE_OK is high through the second voltage sensor, and the network accelerator card is powered on. The second timer records the CPU power-on duration t2 at an interval of Δt2; when a key is pressed, the first timer records the key pressing duration t1 at an interval of Δt1, and the third timer records the key pressing duration t3 at an interval of Δt3; When the key is released, the counts of the first timer and the third timer are cleared; when a low level is detected in the CPU input, the count of the second timer is cleared.

[0037] In step S30, the power on / off function is triggered as follows: The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state. Then, the CPLD sends a power-on / off signal PWRBTN to the CPU. If so, the CPLD: Determine whether t1 recorded by the first timer exceeds 3 seconds. If so, send a power-on / off signal PWRBTN to the CPU; if not, do not send the power-on / off signal PWRBTN to the CPU. The power on / off control logic is that when the network accelerator card is in the off state, the button acts as the power on / off button, and when the card is just powered on, the button cannot be immediately switched to the reset button; when the network accelerator card is in the on state, long pressing for more than 3 seconds is recognized as the power on / off function.

[0038] The triggering of the reset function is specifically as follows: The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and does not send a reset signal RSTBTN to the CPU. If so, then: Read t1 recorded by the first timer to determine whether it satisfies 100 milliseconds ≤ t1 ≤ 1 second. If so, send a reset signal RSTBTN to the CPU; if not, do not send a reset signal RSTBTN to the CPU. The reset control logic is that when the network accelerator card is powered on, the button acts as a reset button.

[0039] The clear CMOS function is specifically as follows: The CPLD reads t3 recorded by the third timer, and sets the CMOS clear register when t3 is greater than 12 seconds, turns on the red light and keeps it on. After the first voltage sensor detects that the power module is powered off, it sends a clear CMOS signal CLEAR_CMOS to the RTC control circuit.

[0040] The control logic for clearing CMOS requires that a key press and hold for more than 12 seconds triggers a CMOS clear event (setting the CMOS clear register). The CPU normally clears CMOS by pulling the CPU's RTCRST_N signal low when the device is powered off. This requires the device to be powered off and a jumper cap shorting the RTCRST_N signal to ground. However, due to structural limitations of the network accelerator card, there's no space for a jumper cap on the I / O interface, nor is it convenient to open the chassis to install a jumper cap inside the card. Therefore, this function is implemented using a CPLD.

[0041] If the CPLD determines that t3 is greater than 12 seconds, it sets the CMOS clear register and turns on the red light to notify the user that the CMOS clearing process has not yet been performed. When the user disconnects the power supply to the network accelerator card, the P3V3SB_OK signal is triggered to go low. The power module (P3V3SB) is the last power supply on the network accelerator card to be powered off. At this time, all power supplies on the network accelerator card except the CPLD are powered off. The CPLD generates the CLEAR_CMOS signal based on the CMOS clear register. The CLEAR_CMOS signal is a 20ms high-level pulse signal.

[0042] When CLEAR_CMOS is high, capacitor C1 is quickly charged through diode D1, causing the gate of MOS transistor Q1 to become high and conduct, pulling down the RTCRST_N signal to trigger the clear CMOS action. When CLEAR_CMOS is low, diode D1 is cut off, and the charge on capacitor C1 can only be slowly discharged through resistor R1. After a few seconds, when the voltage of capacitor C1 falls below the threshold of MOS transistor Q1's gate, MOS transistor Q1 is disconnected and the RTCRST_N signal returns to its original state.

[0043] The step S40 specifically includes: Step S41: The CPLD sets a control mode register (manual_en). During the operation of the network accelerator card, the CPLD determines the value of the control mode register. When the value is 0, it is the automatic control mode, and the process proceeds to step S42; when the value is 1, it is the manual control mode, and the process proceeds to step S43. like Figure 5 As shown, in specific implementation, the control mode can be switched through reverse, AND gate, or OR gate. When manual_en=0, the auto_ctl signal controls the output of the dual-color indicator light; when manual_en=1, the auto_ctl signal is invalid, and the manual_ctl signal controls the output of the dual-color indicator light. Step S42: Divide the 2.24-second indication cycle time of the dual-color indicator light into seven 320-millisecond time slices, with the first four time slices used for status indication and the last three time slices used for cycle interval identification; when the status indication is flashing, the dual-color indicator light is on for 40 milliseconds and off for 280 milliseconds within one time slice; According to the demarcation of the time slice, the two-color indicator light has the following five states:

[0044] A shift register and a status register are set for the green light and the red light respectively; the values ​​of the shift register are 000000, 000001, 000011, 000111, 001111, 011111, 111111; the values ​​of the status register are 000000, 000001, 000011, 000111, 001111, which respectively represent off, flash once, flash twice, flash three times, and flash four times; The control relationship between the status register and the dual-color indicator light is shown in the following table:

[0045] The CPLD controls the green light to work based on the values ​​of the corresponding shift register and status register to indicate the startup status of the CPU; The CPLD controls the operation of the red light based on the values ​​of the corresponding shift register and status register to indicate a fault state; In specific implementation, the CPLD controls the dual-color indicator light based on the magnitude relationship between the shift register and status register values. For example, a comparator compares the shift register and status register values. If the shift register value is less than the status register value, the green light flashes for the corresponding time slice; otherwise, the green light turns off. As the CPU starts booting, the green light gradually flashes until the boot is complete (marked BOOT_OK), when the green light remains on. This allows users to determine the CPU's startup status based on the number of flashes. The red light indicates the fault level based on the number of flashes, with higher-level fault indications overriding lower-level fault indications.

[0046] That is, the value of the status register is fixed within 2.24 seconds, and the value of the shift register is cyclically shifted within 2.24 seconds. The number of flashes is determined by the size relationship of the value in each time slice. For example, when the value of the status register is 000011, the only values ​​of the shift register less than 000011 are 000000 and 000001, so it flashes twice.

[0047] Step S43: Based on the control instruction input by the CPU, the CPLD controls the dual-color indicator light to turn on, off, or flash at 1 Hz to indicate the host recognition status.

[0048] A preferred embodiment of a network acceleration card signal indication device based on state feedback of the present invention includes the following modules: A timer setting module is used for the CPLD of the network acceleration card to set a first timer for recording the duration of a key press, a second timer for recording the duration of a CPU power-on, and a third timer for recording the duration of a key press. The maximum count values ​​of the first timer, the second timer, and the third timer are T1, T2, and T3, respectively. The counting time intervals are Δt1, Δt2, and Δt3, respectively. 4*T1=2*T2=T3, and Δt1<Δt2=Δt3. The first timer and the third timer are both used to record the duration of a key press, but differ in that the maximum count values ​​(the maximum value of the recording duration) and the counting time interval (the resolution) are different. By setting Δt1<Δt3, that is, reducing the resolution of the third timer, resource usage can be reduced. The timer counting module is used to record the CPU power-on time t2 by the second timer at an interval of Δt2 after the network acceleration card is powered on; when a key is pressed, the first timer records the key press time t1 by an interval of Δt1, and the third timer records the key press time t3 by an interval of Δt3; A first signal indication module is used for the CPLD to identify the state feedback of the key based on the t1, t2 and t3 to trigger the signal indication of the power on / off function, the reset function or the clear CMOS function; The second signal indicator module is used to control the dual-color indicator light to indicate the startup status, fault status, or host identification status during network accelerator card operation. The dual-color indicator light on the network accelerator card consists of a single green and red light. Green indicates the CPU startup status, and red indicates fault status and clearing CMOS events. Different states are indicated by the number of flashes. When the green and red lights are on simultaneously, the dual-color indicator light displays orange. The dual-color indicator light is automatically controlled by the CPLD by default, but can be changed to manual control mode via the control mode register (manual_en). In this way, the CPU can also use this dual-color indicator light to indicate the host identification status.

[0049] In the timer setting module, the value of T1 is 4 seconds, the value of T2 is 8 seconds, the value of T3 is 16 seconds, the value of Δt1 is 100 milliseconds, the value of Δt2 is 1 second, and the value of Δt3 is 1 second.

[0050] Specifically, the first timer has a maximum count value of 4 seconds and a counting interval of 100 milliseconds. It starts counting when a key is pressed and generates a low level, and stops counting and clears the count when the key is released. The second timer has a maximum count value of 8 seconds and a counting interval of 1 second. It starts counting when the second voltage sensor outputs a high level, and stops counting and clears the count when it outputs a low level. The third timer has a maximum count value of 16 seconds and a counting interval of 1 second. It starts counting when a key is pressed and generates a low level, and stops counting and clears the count when the key is released. The difference between the first and third counters lies in their counting duration and accuracy.

[0051] The timer counting module is specifically used for: When the button is pressed in the shutdown state, the CPLD detects that the voltage input of the power module is in the range of (2.4V, 3.3V) through the first voltage sensor, and detects that the CPU power signal CORE_OK is high through the second voltage sensor, and the network accelerator card is powered on. The second timer records the CPU power-on duration t2 at an interval of Δt2; when a key is pressed, the first timer records the key pressing duration t1 at an interval of Δt1, and the third timer records the key pressing duration t3 at an interval of Δt3; When the key is released, the counts of the first timer and the third timer are cleared; when a low level is detected in the CPU input, the count of the second timer is cleared.

[0052] In the first signal indication module, the triggering of the power on / off function is specifically as follows: The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state. Then, the CPLD sends a power-on / off signal PWRBTN to the CPU. If so, the CPLD: Determine whether t1 recorded by the first timer exceeds 3 seconds. If so, send a power-on / off signal PWRBTN to the CPU; if not, do not send the power-on / off signal PWRBTN to the CPU. The power on / off control logic is that when the network accelerator card is in the off state, the button acts as the power on / off button, and when the card is just powered on, the button cannot be immediately switched to the reset button; when the network accelerator card is in the on state, long pressing for more than 3 seconds is recognized as the power on / off function.

[0053] The reset function is triggered specifically as follows: The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and does not send a reset signal RSTBTN to the CPU. If so, then: Read t1 recorded by the first timer to determine whether it satisfies 100 milliseconds ≤ t1 ≤ 1 second. If so, send a reset signal RSTBTN to the CPU; if not, do not send a reset signal RSTBTN to the CPU. The reset control logic is that when the network accelerator card is powered on, the button acts as a reset button.

[0054] The clear CMOS function is specifically as follows: The CPLD reads t3 recorded by the third timer, and sets the CMOS clear register when t3 is greater than 12 seconds, turns on the red light and keeps it on. After the first voltage sensor detects that the power module is powered off, it sends a clear CMOS signal CLEAR_CMOS to the RTC control circuit.

[0055] The control logic for clearing CMOS requires that a key press and hold for more than 12 seconds triggers a CMOS clear event (setting the CMOS clear register). The CPU normally clears CMOS by pulling the CPU's RTCRST_N signal low when the device is powered off. This requires the device to be powered off and a jumper cap shorting the RTCRST_N signal to ground. However, due to structural limitations of the network accelerator card, there's no space for a jumper cap on the I / O interface, nor is it convenient to open the chassis to install a jumper cap inside the card. Therefore, this function is implemented using a CPLD.

[0056] If the CPLD determines that t3 is greater than 12 seconds, it sets the CMOS clear register and turns on the red light to notify the user that the CMOS clearing process has not yet been performed. When the user disconnects the power supply to the network accelerator card, the P3V3SB_OK signal is triggered to go low. The power module (P3V3SB) is the last power supply on the network accelerator card to be powered off. At this time, all power supplies on the network accelerator card except the CPLD are powered off. The CPLD generates the CLEAR_CMOS signal based on the CMOS clear register. The CLEAR_CMOS signal is a 20ms high-level pulse signal.

[0057] When CLEAR_CMOS is high, capacitor C1 is quickly charged through diode D1, causing the gate of MOS transistor Q1 to become high and conduct, pulling down the RTCRST_N signal to trigger the clear CMOS action. When CLEAR_CMOS is low, diode D1 is cut off, and the charge on capacitor C1 can only be slowly discharged through resistor R1. After a few seconds, when the voltage of capacitor C1 falls below the threshold of MOS transistor Q1's gate, MOS transistor Q1 is disconnected and the RTCRST_N signal returns to its original state.

[0058] The second signal indication module specifically includes: The control mode selection unit is used by the CPLD to set a control mode register (manual_en). During the operation of the network accelerator card, the CPLD determines the value of the control mode register. When the value is 0, it is the automatic control mode and the automatic control unit is called; when the value is 1, it is the manual control mode and the manual control unit is called; like Figure 5 As shown, in specific implementation, the control mode can be switched through reverse, AND gate, or OR gate. When manual_en=0, the auto_ctl signal controls the output of the dual-color indicator light; when manual_en=1, the auto_ctl signal is invalid, and the manual_ctl signal controls the output of the dual-color indicator light. An automatic control unit, configured to divide the 2.24-second indication cycle time of the bi-color indicator light into seven 320-millisecond time slices, wherein the first four time slices are used for status indication and the last three time slices are used for cycle interval identification; when the status indication is flashing, the bi-color indicator light is on for 40 milliseconds and off for 280 milliseconds within one time slice; According to the demarcation of the time slice, the two-color indicator light has the following five states:

[0059] A shift register and a status register are set for the green light and the red light respectively; the values ​​of the shift register are 000000, 000001, 000011, 000111, 001111, 011111, 111111; the values ​​of the status register are 000000, 000001, 000011, 000111, 001111, which respectively represent off, flash once, flash twice, flash three times, and flash four times; The control relationship between the status register and the dual-color indicator light is shown in the following table:

[0060] The CPLD controls the green light to work based on the values ​​of the corresponding shift register and status register to indicate the startup status of the CPU; The CPLD controls the operation of the red light based on the values ​​of the corresponding shift register and status register to indicate a fault state; In specific implementation, the CPLD controls the dual-color indicator light based on the magnitude relationship between the shift register and status register values. For example, a comparator compares the shift register and status register values. If the shift register value is less than the status register value, the green light flashes for the corresponding time slice; otherwise, the green light turns off. As the CPU starts booting, the green light gradually flashes until the boot is complete (marked BOOT_OK), when the green light remains on. This allows users to determine the CPU's startup status based on the number of flashes. The red light indicates the fault level based on the number of flashes, with higher-level fault indications overriding lower-level fault indications.

[0061] That is, the value of the status register is fixed within 2.24 seconds, and the value of the shift register is cyclically shifted within 2.24 seconds. The number of flashes is determined by the size relationship of the value in each time slice. For example, when the value of the status register is 000011, the only values ​​of the shift register less than 000011 are 000000 and 000001, so it flashes twice.

[0062] The manual control unit is used for the CPLD to control the dual-color indicator light to turn on, off, or flash at 1Hz to indicate the host recognition status based on the control instructions input by the CPU.

[0063] In summary, the advantages of the present invention are: 1. The CPLD of the network accelerator card sets the first, second, and third timers. After the network accelerator card is powered on, the second timer records the CPU power-on duration t2 at an interval of Δt2. When a key is pressed, the first timer records the key press duration t1 at an interval of Δt1, and the third timer records the key press duration t3 at an interval of Δt3. The difference between the first and third counters lies in the counting duration and accuracy. The CPLD then identifies the key status feedback based on t1, t2, and t3 to trigger the power on / off function, reset function, or clear CMOS function signal indication. During operation of the network accelerator card, the control mode register, shift register, and status register control the dual-color indicator light to indicate the startup status, fault status, or host identification status. That is, the power on / off function, reset function, and clear CMOS function signal indication are achieved through a single button, and the startup status, fault status, and host identification status signal indication are achieved through a single dual-color indicator light. This greatly improves the functionality of the button and indicator light, thereby greatly optimizing the spatial layout of the network accelerator card.

[0064] 2. By setting t2 recorded by the second timer to be equal to T2 and t1 recorded by the first timer to be in [100 milliseconds, 1 second], the reset signal RSTBTN is sent to the CPU. That is, the CPU needs to be powered on for more than 8 seconds and the key press duration must meet [100 milliseconds, 1 second] before the reset is initiated. If the key is pressed for less than 100 milliseconds, it is judged as a false operation, thereby greatly improving the accuracy of reset function recognition and the reliability of startup.

[0065] 3. By setting the t2 recorded by the second timer to be less than T2, the power-on / off signal PWRBTN is directly sent to the CPU. If t2 is equal to T2 and t1 recorded by the first timer exceeds 3 seconds, the power-on / off signal PWRBTN is sent to the CPU. This allows the network accelerator card to be powered on immediately by pressing the button when it is powered off. When the network accelerator card is powered on, the button must be pressed for more than 3 seconds to trigger the power-on / off function. That is, there is a time difference between the power-on / off function and the reset function. The button pressing duration is [100 milliseconds, 1 second] for the reset function, [1 second, 3 seconds] for an invalid action, and more than 3 seconds for the power-on / off function. This can effectively distinguish between the reset function and the power-on / off function, thereby greatly improving the reliability of the network accelerator card control.

[0066] 4. By setting the first timer and the third timer to record the duration of key presses, the maximum count value of the first timer is 4 seconds, and the maximum count value of the third timer is 16 seconds. The t3 recorded by the third timer needs to be greater than 12 seconds before the CMOS clear register is set. This can effectively identify whether the CMOS clear function is triggered, further improving the reliability and convenience of network acceleration card control.

[0067] 5. By dividing the 2.24-second indication cycle time of the dual-color indicator light into 7 320-millisecond time slices, the first 4 time slices are used for status indication, and the last 3 time slices are used for cycle interval identification; when the status indication is flashing, the dual-color indicator light is on for 40 milliseconds and off for 280 milliseconds in one time slice, allowing users to clearly identify the number of flashes and cycle intervals, thereby greatly improving the usability and functionality of the dual-color indicator light.

[0068] 6. By setting CPLD to control buttons and dual-color indicators, the corresponding functions and status indications can be executed even when the CPU is powered off, greatly improving the reliability of network acceleration card control.

[0069] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A network acceleration card signal indication method based on state feedback, characterized in that: The steps include: Step S10, the CPLD of the network acceleration card sets a first timer for recording the duration of a key being pressed, a second timer for recording the duration of a CPU being powered on, and a third timer for recording the duration of a key being pressed, wherein the maximum count values ​​of the first timer, the second timer, and the third timer are T1, T2, and T3, respectively, and the counting time intervals are Δt1, Δt2, and Δt3, respectively, and 4*T1=2*T2=T3, and Δt1<Δt2=Δt3; Step S20: After the network acceleration card is powered on, the second timer is used to record the power-on time t2 of the CPU at a time interval of Δt2; when a key is pressed, the first timer is used to record the key pressing time t1 at a time interval of Δt1, and the third timer is used to record the key pressing time t3 at a time interval of Δt3; Step S30: The CPLD identifies the state feedback of the key based on t1, t2 and t3 to trigger the signal indication of the power on / off function, the reset function or the clear CMOS function; Step S40: During the operation of the network acceleration card, the dual-color indicator light is controlled to provide a signal indication of the startup state, fault state or host recognition state.

2. A network acceleration card signal indication method based on state feedback as claimed in claim 1, characterized in that: In the step S10, the value of T1 is 4 seconds, the value of T2 is 8 seconds, the value of T3 is 16 seconds, the value of Δt1 is 100 milliseconds, the value of Δt2 is 1 second, and the value of Δt3 is 1 second.

3. A network acceleration card signal indication method based on state feedback as claimed in claim 1, characterized in that: The step S20 is specifically as follows: When the button is pressed in the shutdown state, the CPLD detects that the voltage range of the power module input is (2.4V, 3.3V] through the first voltage sensor, and detects that the CPU power signal CORE_OK is high through the second voltage sensor, and the network acceleration card is powered on; The second timer records the CPU power-on time t2 at a time interval of Δt2; when a key is pressed, the first timer records the key pressing time t1 at a time interval of Δt1, and the third timer records the key pressing time t3 at a time interval of Δt3; When the key is released, the counts of the first timer and the third timer are cleared; when a low level is detected in the CPU input, the count of the second timer is cleared.

4. A network acceleration card signal indication method based on state feedback as claimed in claim 1, characterized in that: In step S30, the power on / off function is triggered specifically as follows: The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and sends a power-on / off signal PWRBTN to the CPU; if so, then: Determine whether t1 recorded by the first timer exceeds 3 seconds, if yes, send a power on / off signal PWRBTN to the CPU; if no, do not send a power on / off signal PWRBTN to the CPU; The triggering of the reset function is specifically as follows: The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and the reset signal RSTBTN is not sent to the CPU. If yes, then: Read t1 recorded by the first timer to determine whether 100 milliseconds ≤ t1 ≤ 1 second is satisfied. If so, send a reset signal RSTBTN to the CPU; if not, do not send a reset signal RSTBTN to the CPU. The clear CMOS function is specifically as follows: The CPLD reads t3 recorded by the third timer, sets the CMOS clear register when t3 is greater than 12 seconds, turns on the red light and keeps it on, and sends a clear CMOS signal CLEAR_CMOS to the RTC control circuit after detecting that the power module is powered off through the first voltage sensor.

5. The network acceleration card signal indication method based on state feedback according to claim 1, characterized in that: The step S40 specifically includes: Step S41, CPLD sets a control mode register. During the operation of the network acceleration card, CPLD determines the value of the control mode register. When the value is 0, it is an automatic control mode, and the process goes to step S42; when the value is 1, it is a manual control mode, and the process goes to step S43; Step S42, dividing the 2.24-second indication cycle time of the dual-color indicator light into 7 320-millisecond time slices, the first 4 time slices are used for status indication, and the last 3 time slices are used for cycle interval identification; when the status indication is flashing, within one time slice, the dual-color indicator light is on for 40 milliseconds and off for 280 milliseconds; A shift register and a status register are set for the green light and the red light respectively; the values ​​of the shift register are 000000, 000001, 000011, 000111, 001111, 011111, 111111; the values ​​of the status register are 000000, 000001, 000011, 000111, 001111, which respectively represent off, flash once, flash twice, flash three times, and flash four times; The CPLD controls the green light to work based on the corresponding values ​​of the shift register and the status register to indicate the startup status of the CPU; The CPLD controls the operation of the red light based on the corresponding values ​​of the shift register and the status register to indicate the fault status; Step S43, based on the control instruction input by the CPU, the CPLD controls the dual-color indicator light to turn on, off, or flash at 1 Hz to indicate the host recognition status.

6. A network acceleration card signal indication device based on state feedback, characterized in that: Includes the following modules: A timer setting module, used for the CPLD of the network acceleration card to set a first timer for recording the duration of a key being pressed, a second timer for recording the duration of a CPU being powered on, and a third timer for recording the duration of a key being pressed, wherein the maximum count values ​​of the first timer, the second timer, and the third timer are T1, T2, and T3, respectively, and the counting time intervals are Δt1, Δt2, and Δt3, respectively, and 4*T1=2*T2=T3, and Δt1<Δt2=Δt3; The timer counting module is used for recording the power-on time t2 of the CPU by the second timer at a time interval of Δt2 after the network acceleration card is turned on; when a key is pressed, the key pressing time t1 is recorded by the first timer at a time interval of Δt1, and the key pressing time t3 is recorded by the third timer at a time interval of Δt3; A first signal indication module, used for the CPLD to identify the state feedback of the key based on the t1, t2 and t3, so as to trigger the signal indication of the power on / off function, the reset function or the clear CMOS function; The second signal indication module is used to control the dual-color indicator light to provide signal indication of the startup status, fault status or host identification status during the operation of the network acceleration card.

7. A network acceleration card signal indication device based on state feedback as claimed in claim 6, characterized in that: In the timer setting module, the value of T1 is 4 seconds, the value of T2 is 8 seconds, the value of T3 is 16 seconds, the value of Δt1 is 100 milliseconds, the value of Δt2 is 1 second, and the value of Δt3 is 1 second.

8. A network acceleration card signal indication device based on state feedback as claimed in claim 6, characterized in that: The timer counting module is specifically used for: When the button is pressed in the shutdown state, the CPLD detects that the voltage range of the power module input is (2.4V, 3.3V] through the first voltage sensor, and detects that the CPU power signal CORE_OK is high through the second voltage sensor, and the network acceleration card is powered on; The second timer records the CPU power-on time t2 at a time interval of Δt2; when a key is pressed, the first timer records the key pressing time t1 at a time interval of Δt1, and the third timer records the key pressing time t3 at a time interval of Δt3; When the key is released, the counts of the first timer and the third timer are cleared; when a low level is detected in the CPU input, the count of the second timer is cleared.

9. A network acceleration card signal indication device based on state feedback as claimed in claim 6, characterized in that: In the first signal indication module, the triggering of the power on / off function is specifically: The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and sends a power-on / off signal PWRBTN to the CPU; if so, then: Determine whether t1 recorded by the first timer exceeds 3 seconds, if yes, send a power on / off signal PWRBTN to the CPU; if no, do not send a power on / off signal PWRBTN to the CPU; The triggering of the reset function is specifically as follows: The CPLD determines whether t2 recorded by the second timer is equal to T2. If not, it indicates that the power-on time is less than T2 or the power is in the power-off state, and the reset signal RSTBTN is not sent to the CPU. If yes, then: Read t1 recorded by the first timer to determine whether 100 milliseconds ≤ t1 ≤ 1 second is satisfied. If so, send a reset signal RSTBTN to the CPU; if not, do not send a reset signal RSTBTN to the CPU. The clear CMOS function is specifically as follows: The CPLD reads t3 recorded by the third timer, sets the CMOS clear register when t3 is greater than 12 seconds, turns on the red light and keeps it on, and sends a clear CMOS signal CLEAR_CMOS to the RTC control circuit after detecting that the power module is powered off through the first voltage sensor.

10. A network acceleration card signal indication device based on state feedback as claimed in claim 6, characterized in that: The second signal indication module specifically includes: The control mode selection unit is used for the CPLD to set a control mode register. During the operation of the network acceleration card, the CPLD determines the value of the control mode register. When the value is 0, it is an automatic control mode and the automatic control unit is called; when the value is 1, it is a manual control mode and the manual control unit is called; An automatic control unit, used to divide the 2.24-second indication cycle time of the two-color indicator light into seven 320-millisecond time slices, wherein the first four time slices are used for status indication and the last three time slices are used for cycle interval identification; when the status indication is flashing, the two-color indicator light is on for 40 milliseconds and off for 280 milliseconds in one time slice; A shift register and a status register are set for the green light and the red light respectively; the values ​​of the shift register are 000000, 000001, 000011, 000111, 001111, 011111, 111111; the values ​​of the status register are 000000, 000001, 000011, 000111, 001111, which respectively represent off, flash once, flash twice, flash three times, and flash four times; The CPLD controls the green light to work based on the corresponding values ​​of the shift register and the status register to indicate the startup status of the CPU; The CPLD controls the operation of the red light based on the corresponding values ​​of the shift register and the status register to indicate the fault status; The manual control unit is used for the CPLD to control the control instructions input by the CPU to control the two-color indicator light to turn on, off or flash at 1Hz to indicate the host recognition status.

Images