Interconnection structure and method for wafer-level chip integration system and system mainboard

Abstract

The invention discloses an interconnection structure and method for a wafer-level chip integration system and a system mainboard. The interconnection structure comprises an SoW system, a wafer pressing plate, a PCB-let array, a Pogo-pin vibrating needle, an alignment hole plate and a system main board. According to the invention, one side of the SoW system is connected with the PCB-let array, and meanwhile, a bonding pad communicated with a core particle power supply and a signal is led out from the back surface of the PCB-let array, so that first-stage interconnection and transition are realized, and a complex is obtained. In order to relieve the warping problem, the Pogo-pin vibrating needle is welded on a system mainboard, and after proper pressure is applied by a wafer pressing plate, the needle head and a bonding pad of the PCB-let array realize effective contact interconnection, so that second-stage interconnection and transition are completed. The method is compatible and suitable for a wafer-level integrated interconnection system of various (isomorphic and heterogeneous) core particles, and has the characteristics that the warping is insensitive, the wafer complex can be separated from a system mainboard, the system debugging is easy, and the like.

Description

Technical Field

[0001] The invention belongs to the field of electronic packaging, and relates to an interconnection structure and method of a wafer-level core particle integration system and a system mainboard. Background Art

[0002] With the slowdown of the progress of integrated circuit manufacturing technology and the gradual failure of Moore's Law, wafer-level packaging technology has shown great potential in the post-Moore era. Since the bonding of wafer-level chip integrated system (SoW, System On Wafer) and printed circuit board (PCB, Printed Circuit Board) can achieve high-density interconnection and low-cost assembly, this technology has gradually become a research hotspot in the packaging field. However, in practical applications, due to differences in material properties, the bonding process faces many challenges.

[0003] Currently, there are some technical solutions suitable for bonding SoW systems to PCBs. Some reports use metal bonding to achieve electrical connection of devices by making metal interconnect layers on the surface of SoW systems and PCBs. Metal bonding improves electrical conductivity and heat dissipation, but due to the large difference in thermal expansion coefficients between SoW systems and PCBs, warping and delamination are easily caused when bonding large-sized devices. Bonding technology based on conductive adhesive has certain advantages over existing solutions. The existing conductive adhesive bonding process mainly includes: (1) making pads on the surface of PCB; (2) coating conductive adhesive; (3) aligning SoW systems and PCBs; (4) thermal curing molding. Due to the limited thermal and electrical conductivity of conductive adhesives and the narrow process window, current technical solutions still cannot meet the needs of high-performance devices. On the other hand, due to the high process complexity and low production efficiency, the cost remains high.

[0004] Since the SoW system is mainly composed of silicon materials, while PCBs mostly use organic materials such as FR4, the physical and chemical properties of the two are significantly different, which directly affects the bonding quality. Therefore, the use of a stress buffer layer can improve the bonding reliability, but there is no relevant report yet. Summary of the invention

[0005] In order to solve the problems in the background technology, the present invention provides an interconnection structure between a wafer-level chip integration system and a system mainboard.

[0006] The technical solution adopted by the present invention is as follows:

[0007] An interconnection structure between a wafer-level core grain integrated system and a system mainboard, comprising a wafer-level core grain integrated system and a system mainboard, characterized in that it also comprises a wafer pressing plate, a printed substrate array, a spring pin and an alignment hole plate;

[0008] The wafer-level chip integration system comprises a whole silicon wafer, a chip is mounted on the first surface of the wafer, and contacts are arranged on the second surface; the printed substrate array is composed of a plurality of printed substrates on the same plane, the first surface of each printed substrate is bonded to the contacts of the wafer-level chip integration system, and a power supply and signal pad array is arranged on the second surface; one side of the system mainboard is provided with pads corresponding to the power supply and signal pad array;

[0009] The spring needle comprises a needle barrel and a needle head which are elastically interconnected, the needle barrel is provided with a needle seat for welding, and the number of the spring needles is the same as the number of pads in the power supply and signal pad array; a plurality of through holes are provided on the alignment hole plate, the needle seat of the spring needle is welded on the pad array on the first surface of the system mainboard, and the needle head passes through the through hole and contacts the power supply and signal pad array to form an electrical connection;

[0010] The wafer pressing plate is fixedly attached to the first surface of the wafer-level core grain integration system, and is used to evenly apply pressure to ensure that the spring pins are bonded to the power supply and signal pad arrays.

[0011] The interconnection structure also includes a main frame for installing and fixing the wafer-level core particle integration system, the alignment hole plate and the system main board; a layer of plastic pad is also provided on the surface of the main frame facing the system main board to buffer the pressure between the main frame and the system main board; the surface of the alignment hole plate is also provided with a groove for embedding the printed substrate array.

[0012] A heat sink is also installed on the surface of the core of the wafer-level core integration system, and a through hole for the heat sink to penetrate is provided in the middle of the wafer pressing plate.

[0013] The present invention also provides a method for preparing the above-mentioned wafer-level core particle integrated system and system mainboard interconnection structure, which comprises the following steps:

[0014] 1) The second surface of the wafer-level chip integrated system is furnace-welded with the first surface of the printed substrate array to complete the first-level interconnection and transition from the chip to the printed substrate array;

[0015] 2) Re-solder the spring pins, alignment hole plate, system main board and components on the main board;

[0016] 3) Fix the main frame, plastic pad and system mainboard through connectors;

[0017] 4) mounting a heat sink on the first surface of the wafer-level chip integrated system, and embedding the printed substrate array on the second surface of the wafer-level chip integrated system into the groove structure on the first surface of the alignment hole plate;

[0018] 5) The wafer pressing plate is pressed tightly against the first surface of the wafer-level core particle integration system and fixed with a connector to achieve the second-level interconnection and transition from the core particle array to the system mainboard.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] 1) The present invention uses a spring pin to achieve the bonding between the wafer-level core particle integration system and the system mainboard. The expansion and contraction of the spring pin can effectively solve the warping problem of the SoW system that is difficult to overcome by the traditional welding bonding method, and effectively increase the reliability of the bonding between the SoW and the system mainboard;

[0021] 2) The present invention uses a small printed substrate as an intermediate layer for bonding with the pogo pins on the wafer-level chip integration system and the system mainboard. The second surface pad of the printed substrate array and the pogo pins are detachably connected, without welding, and can be repeatedly pressed and separated, which is convenient for system upgrade and maintenance.

[0022] 3) The present invention adopts a wafer pressure plate to strengthen the bonding between the spring pins and the printed substrate array. The wafer pressure plate uniformly applies pressure to the first surface of the wafer-level core particle integration system, which can also improve the deformation of the wafer-level core particle integration system to a certain extent, making the bonding between its second surface and the spring pin array more reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a process flow chart of a method for realizing an interconnection structure between a wafer-level chip integration system and a system mainboard according to an embodiment of the present invention;

[0024] Figure 2 It is an exploded diagram of the overall structure of the interconnection between the wafer-level chip integration system and the system mainboard according to an embodiment of the present invention;

[0025] Figure 3 is a cross-sectional view of the interior of the interconnection structure between the wafer-level chip integration system and the system mainboard according to an embodiment of the present invention;

[0026] Figure 4 is a structural diagram of a heat sink block in one embodiment of the present invention;

[0027] Figure 5 is a structural diagram of a wafer pressing plate in one embodiment of the present invention;

[0028] Figure 6 is a first surface 3D structural diagram of a wafer-level chip integration system in one embodiment of the present invention;

[0029] Figure 7 is a second surface 2D structure diagram of a wafer-level chip integration system in one embodiment of the present invention;

[0030] Figure 8 is a second surface structure diagram of a printed substrate array in one embodiment of the present invention;

[0031] Fig. 9 is a first surface structural diagram of a printed substrate array in one embodiment of the present invention;

[0032] Fig.10 is a side structural diagram of a wafer-level type II complex in one embodiment of the present invention;

[0033] Fig.11 is a second surface structure diagram of a wafer-level type II complex in one embodiment of the present invention;

[0034] Fig.12 It is a structural diagram of the main frame in one embodiment of the present invention;

[0035] Fig.13 This is a structural diagram of an alignment orifice plate according to an embodiment of the present invention;

[0036] Fig.14 It is a structural diagram of a wafer support plate on the lower side of a mainboard in one embodiment of the present invention.

[0037] In the figure: 1. Heat sink; 2. Wafer pressure plate; 3. SoW system; 4. PCB-let array; 5. Main frame; 6. Plastic pad; 7. Pogo-pin spring pin; 8. Alignment hole plate; 9. System mainboard; 10. On-board components; 11. Pallet; 12. Wafer pallet pad; 13. Positioning screws; 14. Heat sink reserved hole; 15. Mounting screw hole; 16. Core particle; 17. Silicon wafer; 18. C4bump contact on the surface of SoW system; 19. Edge PCB-let; 2 0. Second surface solder pad of edge PCB-let; 21. Middle PCB-let; 22. Middle PCB-let solder pad; 23. First surface solder pad of PCB-let; 24. Reserved space for mainboard components; 25. First step; 26. Second step; 27. Reserved space for alignment plate; 28. Wafer pressure plate mounting screw hole; 29. ​​Pogo-pin through hole; 30. Alignment plate positioning column hole; 31. Heat dissipation hole for furnace; 32. Wafer support plate mounting screw hole; 33. Reserved hole for decoupling capacitor. DETAILED DESCRIPTION

[0038] The present invention utilizes the elastic expansion and contraction mechanism of the Pogo-pin spring needle itself to compensate for the overall warping of the wafer-level complex, and solves the problem that the wafer-level core integrated chip and the large-size system motherboard cannot be effectively bonded. At the same time, the present invention is compatible with and applicable to wafer-level integrated interconnection systems of various (homogeneous and heterogeneous) cores, and has the characteristics of being insensitive to warping, the wafer complex and the system motherboard can be separated, and the system is easy to debug.

[0039] The present invention is further described below in conjunction with the accompanying drawings and specific examples. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments of the present application, and it should be understood that the present application is not limited to the example embodiments described herein. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application. It should also be noted that, for ease of description, only the parts related to the present application are shown in the accompanying drawings, rather than all of them.

[0040] Example 1

[0041] The wafer-level chip integration system (SoW) is based on a whole silicon wafer, which tightly integrates multiple chips, thereby expanding the chip area to the wafer level size, greatly improving the computing power of the system. The system motherboard is a double-sided PCB, one side of which needs to achieve reliable electrical connection with the SoW system. In order to achieve the interconnection between the SoW system and the system motherboard, Figure 2 , 3 As shown, this embodiment provides an interconnection structure of a wafer-level chip integrated system (SoW) and a system mainboard, including a wafer-level integrated packaging system 3 composed of multiple chips and a silicon wafer, a wafer pressing plate 2, multiple small printed circuit boards (PCB-lets), multiple Pogo-pin spring pins 7, an alignment hole plate 8 and a system mainboard 9;

[0042] The SoW system 3 is as follows Figure 6 , 7 As shown, it is a double-sided wafer-level type I complex, including a silicon wafer 17 and a plurality of core particles 16. The core particles 16 are mounted only on one side of the silicon wafer 17. The side where the core particles 16 are mounted is the first surface of the SoW system 3, and the other side is the second surface, which is provided with a plurality of bump contacts (C4 bump contacts are used in this embodiment) for mounting the PCB-let array 4. The first surface of the SoW system 3 is provided with a plurality of heat sinks 1, as shown in FIG. Figure 4 As shown, the heat dissipation block 1 is used to dissipate heat from the core particle 16 to prevent the core particle 16 from overheating. The material of the heat dissipation block 1 can be a semiconductor with good thermal conductivity.

[0043] Multiple small printed circuit boards form a printed circuit board array (PCB-let array) on the same plane. The PCB-let array 4 is composed of multiple PCB-lets, which are small square PCBs with pads on both sides and a redistribution layer (RDL) inside. Fig. 9 As shown, the pads on one side of the PCB-let array 4 are smaller and have the same density as the pads on the second surface of the SoW system 3, which is the first surface of the PCB-let array 4. Figure 8As shown, the second surface of the PCB-let array 4 has larger and more sparse pads; the PCB-let array 4 is used to simplify the dense C4 bump contacts on the second surface of the SoW system 3 so that the density of the lead-out pads reaches the density that can be achieved by the spring pin. Specifically, the signals output by the C4 bump contacts with the same name on the second surface of the SoW system 3 are merged in the RDL layer inside the PCB-let, and then led out to the pads on the second surface of the PCB-let array 4. The signals that cannot be merged are directly passed through the RDL layer inside the PCB-let and then led out to the pads on the second surface. The C4 bump contacts on the second surface of the SoW system 3 are bonded to the pads on the first surface of the PCB-let array 4 to form an electrical connection, so that the SoW system 3 and the PCB-let array 4 form a wafer-level type II complex as a whole, as shown in FIG. Fig.10 , multiple PCB-lets are closely mounted on the second surface of the SoW system 3 to form a PCB-let array 4 protruding in a specific shape. At the same time, the power supply and signal pads on the second surface of the PCB-let array 4 form a power supply and signal pad array.

[0044] The Pogo-pin spring needle 7 is a retractable spring needle, including a syringe and a needle, which respectively constitute the two ends of the spring needle. The syringe and the needle are connected by a spring, and the needle can be compressed into the syringe under force. One end of the syringe is a needle seat that can be welded. The number of Pogo-pin spring needles 7 is consistent with the number of pads in the power and signal pad array. Multiple Pogo-pin spring needles 7 are arranged according to the arrangement of pads in the power and signal pad array to form a Pogo-pin array, corresponding to the power and signal pad array. The alignment hole plate 8 is a double-sided structure, with through holes corresponding to the Pogo-pin array inside, called Pogo-pin through holes 29. One side has a groove structure corresponding to the protruding shape of the PCB-let array 4, which is the first surface of the alignment hole plate 8, and the other side is the second surface of the alignment hole plate 8.

[0045] The system main board 9 is a double-sided PCB. The first surface of the system main board 9 has a pad array that is the same as the power supply and signal pad arrays, and the other surface is the second surface of the system main board 9 .

[0046] The pin holder of the Pogo-pin spring needle 7 is welded on the pad array of the system main board 9 and inserted into the through hole of the alignment hole plate 8, and the pin head is exposed from the first surface of the alignment hole plate 8; the raised PCB-let array 4 is embedded in the groove of the corresponding shape on the first surface of the alignment hole plate 8, realizing the electrical connection between the pad array on the second surface of the PCB-let and the Pogo-pin array, thereby realizing the electrical connection between the system main board 9 and the SoW system 3 as a whole. In order to ensure the reliability of the connection between the spring needle and the power and signal pad array, the length of the Pogo-pin spring needle 7 should be greater than the warpage of the wafer-level type II complex, which refers to the maximum height difference of an object in the vertical direction.

[0047] The wafer pressing plate 2 is fixedly attached to the first surface of the SoW system 3 through a structural member, so as to evenly apply pressure to the first surface of the SoW system 3 and ensure full bonding between the Pogo-pin array and the power and signal pad array on the PCB-let.

[0048] As a preferred solution of this embodiment, the silicon wafer 17 in the SoW system 3 has a redistribution layer inside for electrical interconnection of the two side surfaces. The wafer pressing plate 2 is a 3-10 mm thick metal rigid flat plate, and a heat sink reserved hole 14 is also provided in the middle of the wafer pressing plate 2. The Pogo-pin spring needle 7 is made of a low resistivity rigid metal, such as copper. The alignment hole plate 8 is an insulating heat-resistant material.

[0049] The present invention utilizes the elastic expansion and contraction mechanism of the Pogo-pin spring needle 7 itself to compensate for the overall warping of the wafer-level complex, and solves the problem that the wafer-level core integrated chip cannot be effectively bonded to the large-size system mainboard 9. The present invention utilizes the wafer pressure plate 2 and a number of fixings to appropriately apply pressure on the core side to ensure that the Pogo-pin spring needle 7 is fully bonded to the PCB-let pad. The present invention improves the reliability of the bonding between the Pogo-pin spring needle 7 and the PCB-let pad by aligning the orifice plate 8 of the Pogo-pin spring needle 7, and utilizes the groove on the needle side of the alignment orifice plate 8 to achieve alignment of the spring needle array with the pad array. The present invention is compatible with and applicable to wafer-level integrated interconnection systems of various (isomorphic and heterogeneous) cores, and has the characteristics of being insensitive to warping, the wafer complex and the system mainboard 9 being separable, and easy system debugging.

[0050] Example 2

[0051] like Figure 1 As shown, this embodiment provides a method for preparing an interconnection structure between the wafer-level chip integrated system and the system mainboard described in Embodiment 1, comprising the following steps:

[0052] Step 1): The second surface of the SoW system 3 is furnace-welded with the first surface of the PCB-let array 4 to complete the first-level interconnection and transition from the core particle 16 to the PCB-let array 4, forming a wafer-level type II complex;

[0053] Step 2): Re-solder the Pogo-pin, the alignment hole plate, the system mainboard and the components on the board;

[0054] Step 3): Fix the main frame 5 and the plastic pad 6 to the system mainboard with screws;

[0055] Step 4): Install the support plate 12 and the wafer support plate 11 at the ejector pins on the second surface of the system mainboard;

[0056] Step 5): Mount the heat sink 1 on the first surface of the SoW system 3, and embed the protrusion formed by the PCB-let array on its second surface into the groove structure on the first surface of the alignment hole plate;

[0057] Step 6): The wafer pressing plate is pressed tightly against the first surface of the SoW system through the structural connector and fixed with screws to achieve the second-level interconnection and transition from the core particle to the system mainboard.

[0058] First, step S1 is performed, wherein the second surface of the SoW system 3 has Figure 7 The dense C4 bump contacts are shown in the figure, of which the 8*8 part in the middle is mainly for power bump contacts, and the 8*1 part on the upper, lower, left and right edges is mainly for signal bump contacts. According to the distribution of C4 bump contacts on the second surface of the SoW system 3 and the work requirements, the PCB-let is designed and manufactured. The size of the obtained single PCB-let is about 20mm*20mm and the thickness is about 1.6mm. Finally, all the first surfaces of the PCB-let array 4 are as shown in the figure. Fig. 9 As shown, the pad size is comparable to the size of the C4 bump contact 18 on the second surface of the SoW system 3. The second surface of the PCB-let is as shown in FIG. Figure 8 As shown, the large pads 22 on the middle 8*8 PCB-let array are mainly the bump contacts of the power supply part, with a diameter of about 3mm, and the small pads 20 on the upper, lower, left and right edges of the 8*1 PCB-let array are mainly the bump contacts of the signal, with a diameter of about 1.2mm. Figure 7 The C4 bump contact array shown is Fig. 9 The pad array shown is bonded, where in order to reduce the warpage caused by the different thermal expansion coefficients of the silicon wafer and the PCB-let, the welding process needs to be specially designed and the process verification is carried out before actual mounting, and finally the warpage of the composite is as small as possible within 2 mm to meet the process requirements for the production of the Pogo-pin spring needle 7.

[0059] Then execute step S2. Customize the Pogo-pin spring needle 7 to ensure that it meets the warpage requirements of the wafer-level Type II complex. Copper is used as the material. The final Pogo-pin spring needle 7 has a telescopic length of about 1.8 mm. The diameters of the syringe and needle of the Pogo-pin spring needle 7 in the middle power supply part are about 1.5 mm and 0.9 mm, and the diameters of the syringe and needle of the edge signal part are about 1.2 mm and 0.6 mm. Design and manufacture the system motherboard 9 according to the chip working requirements and the distribution of the power and signal pad arrays, wherein the on-board devices 10 of the system motherboard 9 are mainly distributed on the second surface, including FPGA modules, power modules, interface modules, etc. At the same time, decoupling capacitors need to be placed at the second surface pins to ensure signal integrity and power integrity. Thinner patch devices can be placed in some areas of the first surface. Design and manufacture the alignment hole plate 8 according to the diameter and length of the Pogo-pin spring needle 7 and the distribution of the Pogo-pin array. The final alignment hole plate 8 is as shown in Fig.13 As shown, according to Figure 3 As shown, a certain height of space is left between the alignment hole plate 8 and the system mainboard 9 for heat dissipation during welding. Fig.13 As shown, the alignment plate 8 has a Pogo-pin through hole 29, a through hole for installation and positioning of the alignment plate 8, namely, the alignment plate positioning column hole 30, and a through hole for heat dissipation during welding, namely, the furnace heat dissipation hole 31. In order to reduce the probability of the pin being distorted during welding, the Pogo-pin through hole 29 of the alignment plate 8 is made as close to the diameter of the Pogo-pin pin 7 as possible. If the Pogo-pin pin 7 is welded first and then the alignment plate 8 is put on, the needle array and the alignment hole array may not be strictly aligned and cannot be put on. Therefore, the alignment plate 8 and the Pogo-pin pin 7 are fixed at the specified position of the system motherboard 9 first and then welded together in the furnace, which can avoid this problem. The alignment plate 8 needs to be made of heat-resistant, insulating rigid material. All the devices on the second surface are first welded in the furnace, and then the Pogo-pin pin 7 and the remaining devices on the first surface are welded in the furnace.

[0060] Then execute step S3. The main frame 5 is as follows Fig.12As shown, it is made of aluminum alloy, and its core structure is the middle multi-level steps and the middle hollowing with the same shape as the alignment hole plate 8. The reserved space 27 of the alignment hole plate is hollowed out to allow the alignment hole plate 8 fixed on the first surface of the system main board 9 to be just inserted. The second step 26 is an integral circular step, which is used to embed the wafer of the SoW system 3 to increase the stability of the structure. The first step 25 is an integral circular step, which is used to embed the wafer pressure plate 2 to increase the stability of the structure. The main frame 5 is also provided with a reserved space 24 for main board components, which is also hollowed out and is reserved for the space for the components on the first surface of the system main board 9. There needs to be a layer of plastic pad 6 with the same shape as the lower surface of the system main board 9 between the main frame 5 and the system main board 9 to buffer the pressure between the rigid main frame 5 and the system main board 9. The pad material can be selected from PC material. After completing step S5, the Pogo-pin array on the first surface of the alignment hole plate 8 is exposed from 27 of the structural frame 5.

[0061] Then, step S4 is performed. The position of the support plate 12 in the overall structure is as follows: Figure 2 and Figure 3 As shown, it is mounted on the second surface of the system mainboard 9. The structure of the support plate 12 is as shown Fig.14 As shown, the whole material is aluminum alloy, on which there are wafer support plate mounting screw holes 32 and decoupling capacitor reserved holes 33, the decoupling capacitor reserved holes 33 are through holes reserved for the decoupling capacitor installation position, and the wafer support plate mounting screw holes 32 are screw holes for installation. Similar to step S5, a pad is also needed between the support plate 12 and the system mainboard 9 to buffer the pressure, which is called the wafer support plate pad 11, and the pad material can be selected from PC material.

[0062] Then, step S5 is executed. The heat sink 1 and the first surface of the SoW system 3 can be bonded together by silicone grease. Before bonding, the mounting position of each heat sink 1 needs to be marked in advance to ensure that the heat sink 1 can pass through the heat sink reserved hole 14 of the wafer pressing plate 2. After the heat sink 1 is fixed, the wafer-level II type & heat sink complex is embedded as a whole. Fig.12 In the multi-step and hollow structure of the main frame 5, as Fig.13 As shown, the first surface of the alignment orifice plate 8 has Fig.11 The PCB-let array 4 shown has a groove with a shape that completely corresponds to that of the groove, in which the PCB-let of the composite is embedded, and the wafer is embedded in the second step 26.

[0063] Finally, step S6 is performed. The structure of the wafer pressing plate 2 is as follows Figure 5 As shown, after the wafer pressing plate 2 is embedded into the first step 25 of the main frame 5, the wafer pressing plate 2 is fixed to the structural parts with screws. After being fixed, the wafer pressing plate 2 can apply uniform pressure to the first surface of the SoW system 3, thereby improving the deformation of the wafer-level type II complex to a certain extent, making the bonding between its second surface and the Pogo-pin array more reliable.

[0064] The present invention uses Pogo-pin spring pins to achieve the bonding between SoW and the system motherboard. The expansion and contraction of the spring pins can effectively solve the warping problem of SoW that is difficult to overcome by the traditional welding bonding method, and effectively increase the reliability of the bonding between SoW and the system motherboard. At the same time, the present invention uses PCB-let as the middle layer for the bonding between the SoW system and the Pogo-pin spring pins on the system motherboard. The second plane pad of the PCB-let and the Pogo-pin spring pin are detachably connected, without welding, and can be repeatedly pressed and separated, which is convenient for system upgrade and maintenance, and has high commercial utilization value.

[0065] The above-mentioned embodiments only express several implementation methods of the present invention, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. For ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. An interconnection structure between a wafer-level chip integrated system and a system mainboard, comprising a wafer-level chip integrated system and a system mainboard, characterized in that: It also includes a wafer press plate, a printed substrate array, spring pins and an alignment hole plate; The wafer-level chip integration system comprises a whole silicon wafer, a chip is mounted on the first surface of the wafer, and contacts are arranged on the second surface; the printed substrate array is composed of a plurality of printed substrates on the same plane, the first surface of each printed substrate is bonded to the contacts of the wafer-level chip integration system, and a power supply and signal pad array is arranged on the second surface; one side of the system mainboard is provided with pads corresponding to the power supply and signal pad array; The spring needle comprises a needle barrel and a needle head which are elastically interconnected, the needle barrel is provided with a needle seat for welding, and the number of the spring needles is the same as the number of pads in the power supply and signal pad array; a plurality of through holes are provided on the alignment hole plate, the needle seat of the spring needle is welded on the pad array on the first surface of the system mainboard, and the needle head passes through the through hole and contacts the power supply and signal pad array to form an electrical connection; The wafer pressing plate is fixedly attached to the first surface of the wafer-level core grain integration system, and is used to evenly apply pressure to ensure that the spring pins are bonded to the power supply and signal pad arrays.

2. The interconnection structure of the wafer-level chip integration system and the system mainboard according to claim 1, characterized in that: The interconnection structure also includes a main frame for installing and fixing the wafer-level core particle integration system, the alignment hole plate and the system main board; a layer of plastic pad is also provided on the surface of the main frame facing the system main board to buffer the pressure between the main frame and the system main board; the surface of the alignment hole plate is also provided with a groove for embedding the printed substrate array.

3. The interconnection structure of the wafer-level chip integration system and the system mainboard according to claim 2, characterized in that: A heat sink is also installed on the surface of the core of the wafer-level core integration system, and a through hole for the heat sink to penetrate is provided in the middle of the wafer pressing plate.

4. The interconnection structure of the wafer-level chip integration system and the system mainboard according to claim 1, characterized in that: The wafer-level core particle integration system is a silicon wafer with a plurality of core particles mounted on one side, and a redistribution layer is provided inside the silicon wafer.

5. The interconnection structure of the wafer-level chip integration system and the system mainboard according to claim 1, characterized in that: The contact is a C4 bump contact.

6. The interconnection structure of the wafer-level chip integration system and the system mainboard according to claim 1, characterized in that: The printed substrate array is used for power supply and signal transmission of the core particles. There are pads on both sides of the surface. The pads on the first surface are small and dense, and the pads on the second surface are large and sparse. The signals output by the contacts on the second surface of the silicon wafer enter the printed substrate array through the pads on the first surface of the printed substrate array, and are led out from the second surface through the internal redistribution layer, and some of the signals are merged in the redistribution layer.

7. The interconnection structure of the wafer-level chip integration system and the system mainboard according to claim 1, characterized in that: The wafer pressing plate is a metal rigid flat plate with a thickness of 3-10 mm.

8. The interconnection structure of the wafer-level chip integration system and the system mainboard according to claim 1, characterized in that: A space for heat dissipation for welding is reserved between the alignment hole plate and the system mainboard; a heat dissipation hole for heat dissipation through welding is also arranged on the alignment hole plate.

9. The interconnection structure of the wafer-level chip integration system and the system mainboard according to claim 1, characterized in that: The length of the spring pin is greater than the warpage of the composite composed of the wafer-level chip integrated system and the printed substrate array.

10. A method for preparing the wafer-level chip integrated system and system mainboard interconnection structure according to claim 3, characterized in that: It includes the following steps: 1) The second surface of the wafer-level chip integrated system is furnace-welded with the first surface of the printed substrate array to complete the first-level interconnection and transition from the chip to the printed substrate array; 2) Re-solder the spring pins, alignment hole plate, system main board and components on the main board; 3) Fix the main frame, plastic pad and system mainboard through connectors; 4) mounting a heat sink on the first surface of the wafer-level chip integrated system, and embedding the printed substrate array on the second surface of the wafer-level chip integrated system into the groove structure on the first surface of the alignment hole plate; 5) The wafer pressing plate is pressed tightly against the first surface of the wafer-level core particle integration system and fixed with a connector to achieve the second-level interconnection and transition from the core particle array to the system mainboard.

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