Optimized layout method for FPGA (Field Programmable Gate Array) wiring based on maximum independent set

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) wiring optimized layout method based on a maximum independent set. The method comprises the following steps: S1, defining a detailed layout optimization object by an FPGA architecture; s2, efficiently analyzing an occupation condition of a legalized layout logic unit; s3, solving the maximum independent set of the FPGA netlist; s4, selecting a moving optimization object and a candidate position; s5, determining a line length evaluation algorithm; s6, designing a moving cost oriented to wiring optimization; s7, using the maximum independent set to globally optimize the layout; s8, directionally optimizing the layout; and S9, outputting a detailed layout result. Compared with the prior art, the algorithm has the advantages that the algorithm searches a global maximum independent set to construct an optimization object, a proper moving target position is searched for the optimization object, falling into a local optimal solution of line length optimization is avoided, and on the premise that the global legality and the time sequence of an FPGA circuit netlist are not disturbed, the algorithm can improve the optimization efficiency of the FPGA circuit netlist. The overall wire length required in the wiring stage is obviously optimized, and the congestion density of a global circuit netlist is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design automation, and specifically refers to a method for optimizing the layout of FPGA wiring based on the maximum independent set. Background Art

[0002] With the rapid growth of the overall scale of FPGA devices, the integration level is getting higher and higher, and the number of internal interconnections has increased explosively. The wiring problem has gradually become the most time-consuming step in the entire FPGA EDA process, occupying a large part of the entire design cycle. The traditional layout and wiring process usually includes three stages: global placement, detailed placement, and wiring. The main goal of the global placement stage is to determine the approximate positions of each logic unit and try to optimize indicators such as timing and congestion. Global placement algorithms usually use methods such as simulated annealing and quadratic programming to strive to find a better unit placement scheme within the global scope. At present, certain achievements have been made in the research of global placement. For example, the global placement method based on machine learning can effectively improve the placement quality and efficiency. The detailed placement stage is to further adjust and optimize the unit positions on the basis of the global placement to meet various constraints, such as timing constraints, congestion constraints, etc. Detailed placement algorithms usually use methods such as greedy algorithms and force-directed algorithms to strive to find an optimal unit placement scheme within the local scope. At present, the research on detailed placement mainly focuses on how to better handle various constraints and how to improve the robustness of the placement.

[0003] According to observation experience, even if the optimization goal has been achieved in the global placement stage, and the placement and legalization of units have been completed (that is, eliminating unit overlaps and meeting various placement constraints), there may still be room for further optimization of the demand for wiring resources. Without significantly disturbing the timing performance and unit density distribution of the global placement, by making small adjustments and movements to the unit positions, the wiring topology can be further optimized, the wiring length and congestion can be reduced, thereby improving the wiring success rate and timing performance. This local optimization method can further tap the wiring potential while maintaining the advantages of the global placement, shorten the FPGA design cycle, and improve the design efficiency. The present invention proposes a new detailed placement method for wiring optimization based on the maximum independent set search algorithm. Without disturbing the existing global placement and signal timing, relying on the legalized FPGA netlist and timing file, it searches for the global maximum independent set and modules with lower congestion density for unit movement, and finally realizes the optimization of wiring resources and congestion resources in the wiring stage of FPGA. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for optimizing the layout of FPGA wiring based on the maximum independent set in view of the deficiencies mentioned in the above background art.

[0005] To solve the above technical problems, the technical solution provided by the present invention is: a method for optimizing the layout of FPGA wiring based on the maximum independent set, which includes the following steps:

[0006] S1. Define the detailed layout optimization object for the FPGA architecture;

[0007] S2. Efficiently analyze the occupancy of legalized layout logic units;

[0008] S3. Solve the maximum independent set of the FPGA netlist;

[0009] S4. Select the optimization object to be moved and the candidate positions;

[0010] S5. Determine the wire length evaluation algorithm;

[0011] S6. Design the movement cost for wiring optimization;

[0012] S7. Use the maximum independent set to globally optimize the layout;

[0013] S8. Directionally optimize the layout;

[0014] S9. Output the detailed layout result.

[0015] Furthermore, in step S1, the architecture model part of the FPGA: programmable logic units (CLBs), programmable interconnection resources (such as global interconnection resource switch boxes SB and regional interconnection resource switch boxes CB), input / output units (IO), and built-in IP resources (such as DSP modules and memory blocks);

[0016] The core unit of the FPGA is the programmable logic unit (CLB), which is composed of a look-up table (LUT), a flip-flop (DFF), and a multiplexer;

[0017] There are 8 LUT6s and 16 DFFs in the CLBs. Among them, the LUT and DFF with connection relationships in the same CLB form a BLE unit. Define the position of a CLB in the FPGA architecture as (x 0 , y 0 ), then the position coordinates of the LUT among them are (x 0 , y 0 , z i ), and the position coordinates of the DFF are (x 0 , y 0 , z j ).

[0018] Furthermore, in step S2, the occupancy of the same CLB needs to be initialized, and the position coordinate z of each movable unit LUT (DFF) is initialized and definedi (z j ) maps the 00 state (0 state). In addition, to parse the other fixed part of LUT and DFF cells existing in the netlist and perform subsequent algorithm steps efficiently, this step divides the 01 and 11 states into fixed and non-fixed types. The same applies to DFFs;

[0019] Update the occupancy of the overall CLBs. Traverse all the cells in the netlist. At this time, the position z of each LUT (DFF) i (z j ) starts to transfer from the 00 state (0 state). When the traversed cell is a fixed cell, it will transfer to the fixed 01 state (fixed 1 state). The netlist LUT6X structure is directly transferred to the fixed 11 state, the fixed LUT6 is transferred to the fixed 01 state, and the same applies to others. For non-fixed LUTs, it first transfers to the 01 state. If the same coordinates are traversed later, it will transfer to the 11 state. The same applies to DFFs.

[0020] Furthermore, in step S3, map the netlist to a hypergraph. According to the size of the netlist, use the greedy algorithm to find the maximum independent set in the circuit netlist. In the detailed layout, the clock wire net is not within the scope of optimization;

[0021] First, traverse all the movable cells v in the circuit netlist G and assign a state value State[v] to all the cells v;

[0022] Initially, the states of all hyperpoints are false. Then, traverse all v in the circuit netlist G. If the state of the currently visited hyperpoint v is false, set the state of the currently visited cell v to true and add it to the maximum independent set S;

[0023] Next, traverse all the hyperpoints u included in all the adjacent hyperedges of the hyperpoint v. If the states of these points are false, set them to true;

[0024] Repeat this operation until the states of all hyperpoints in the hypergraph G are not false. At this time, output the maximum independent set S, which is an approximate maximum independent set of the hypergraph searched by the algorithm.

[0025] Furthermore, in step S4, after finding the global netlist maximum independent set, take the LUT or DFF in the independent set as one of the optimization objects, and find the BEL cells composed of them at the same CLB coordinate position as the complete optimization object. For the moving position, according to the properties of the maximum independent set, select the CLB position that has a connection relationship with the LUT or DFF in the current independent set and has a different CLB position as the candidate position;

[0026] For the selection of the moving candidate positions, the CLB positions without connection relationships near the optimization object can also be selected in a certain way to increase the optimization solution space.

[0027] Furthermore, in step S5, the wire length evaluation model includes the Manhattan distance model and the Steiner tree model. The Steiner tree model can be solved by the open-source FLUTE library. The basic idea of wire length evaluation is to compare the optimization effects of the weighted critical wire lengths and non-critical wire lengths before and after the movement. If the difference before and after is greater than 0, it belongs to positive optimization.

[0028] For the evaluation of the critical wire lengths in the netlist, the Manhattan distance model is adopted. The optimization object is the movable unit in the CLB. Therefore, for the optimization object, the wire length evaluations of the overall fan-in and fan-out need to be considered. Since in the critical wire lengths, the fan-out of unit A, such as port O0, to the fan-in of unit B, such as port I0, can be equivalent to the fan-in I0 of unit B to port O0 of unit A. Therefore, for the evaluation of the critical wire lengths of the optimization object to be moved, it can be equivalent to the Manhattan distance from the object to be moved to the unit with a critical wire length connection relationship. Taking BEL as the object to be moved, calculate the Manhattan distances between the units with connection relationships with BEL before and after the movement in turn. The difference in distances before and after reflects the optimization effect of the critical wire lengths.

[0029] For the evaluation of the non-critical wire lengths of the wire nets in the netlist, the Steiner tree model is generally adopted. The FLUTE library provides an interface for calculating the Steiner tree model of the wire nets. For the BEL of the optimization object to be moved in the CLB, in addition to calculating the Steiner tree wire length of the non-critical wires of the fan-out wire nets of the entire BEL object, it is also necessary to calculate the Steiner tree wire length of the non-critical wires of the driving units of the fan-in wire nets. The two parts are weighted, and the difference before and after the movement can be obtained to get the degree of wire length optimization effect before and after the movement.

[0030] This algorithm sets a threshold for the number of wire nets according to the netlist situation, that is, if the number of units connected to a wire net exceeds this threshold, the Manhattan wire length model is selected to approximately equivalent the Steiner tree model.

[0031] Furthermore, in step S6, the cost of moving to the candidate position needs to consider the legality of moving to this CLB position and the change in the congestion density situation. First, consider whether the LUT or DFF after the movement meets the corresponding wire net number constraints in the CLB of this candidate position, as well as the constraints on the clock and control signal wire nets. In addition, simultaneously update the number of clocks in the clock region. If it exceeds the number of clocks, it is also illegal. If this legality check is not met, directly return a cost of positive infinity.

[0032] Next, after satisfying the legalization check related to the line network, check whether the pin density in the candidate position exceeds the set threshold. This threshold can be selected as the lower limit of the pin density of a certain proportion of CLBs. According to the mathematical relationship, if the pin density of the CLB of each candidate position after the move does not exceed the threshold density, then the average pin density of the CLB of the optimized selected proportion will be less than or equal to the threshold. Similarly, if the pin density of the CLB of the candidate position after the move exceeds the threshold density, a positive infinite cost is returned.

[0033] If it is less than or equal to the pin density threshold, the critical line length and non-critical line length after the move can be calculated, and the weighted lengths of these two parts are used as the overall line length. The difference with the length before the move is calculated and returned as the final optimization cost. If the difference is less than 0 and the smaller it is, the smaller the cost is, indicating that the optimized line length is more, and vice versa.

[0034] Finally, when selecting the moving position, the candidate position with a difference less than 0 and the lowest cost is preferentially selected for moving, and then the corresponding resource change is updated.

[0035] Further, in step S7, the movable units of the largest independent set in the netlist found in each iteration are traversed, and the optimization object BEL is constructed using the movable units, that is, the LUT and DFF combination with a connection relationship in the CLB position of the independent point;

[0036] Using CLBs at different positions connected by independent points as candidate positions for movement, in order to optimize the movement of most of the movable units of each line network, an iteration number is set according to the actual size of each netlist. When the movable units in the current maximum independent set are traversed, we mark each unit of the maximum independent set as visited, and according to step S3, find the unvisited maximum independent set in the netlist from the unmarked movable units, and repeat steps S4, S5, and S6 until the iteration number is reached.

[0037] Further, in step S8, when the maximum independent set optimization reaches a certain number of iterations, the CLB object with a low pin port density in the netlist is found. Since there are relatively few interconnected wire nets of mobile units in this part of the CLB, the position of the mobile units in this part of the CLB can be optimized by moving or merging, so as to further reduce the wiring length;

[0038] Consistent with S7, the movable units in the CLB with pin port density lower than a certain threshold are searched to construct optimization objects and find corresponding candidate positions, and the candidate positions with the smallest cost less than 0 are found to perform the move operation, and the resource status is updated. The above steps are repeated until the set number of iterations is reached.

[0039] Further, in step S9, the optimized circuit netlist is output to complete the final detailed layout.

[0040] After adopting the above method, the present invention has the following advantages: By converting the circuit netlist into the form of a hypergraph, the algorithm finds the global maximum independent set to construct the optimization object, and finds a suitable moving target position for the optimization object, avoiding falling into the local optimal solution of wire length optimization. The algorithm proposed by the present invention can significantly optimize the overall wire length required in the routing stage without disturbing the global legality and timing of the FPGA circuit netlist, where it can significantly optimize the critical wire length in the wire length and reduce the congestion density of the global circuit netlist. Description of the Drawings

[0041] Figure 1 It is a flowchart of an invention applying a routing optimization layout method based on the maximum independent set to the FPGA detailed layout;

[0042] Figure 2 It is a schematic diagram of an invention applying a routing optimization layout method based on the maximum independent set to efficiently analyze the occupancy of FPGA logic units;

[0043] Figure 3 It is a schematic diagram of an invention applying a routing optimization layout method based on the maximum independent set to select the optimization object and candidate positions in the FPGA detailed layout;

[0044] Figure 4 It is a schematic diagram of an invention applying a routing optimization layout method based on the maximum independent set to design the moving cost in the FPGA detailed layout;

[0045] Figure 5 It is a flowchart of an invention applying a routing optimization layout method based on the maximum independent set to the global optimization and directional optimization layout of the FPGA netlist. Detailed Embodiment

[0046] A detailed layout method driven by routing optimization in the FPGA layout stage proposed by the present invention aims to design an optimization model to optimize the logic units and the overall routing wire length of the whole in the premise of not disturbing the legalized layout and considering indicators such as critical wire length and congestion density. The specific method is to first efficiently parse the existing FPGA constraints and netlist files, construct the maximum independent set based on the legalized netlist, and define the object to be moved and its moving candidate area, so as to establish an optimization problem for the layout oriented to routing optimization. Then, a directional search is performed on the optimization problem, and finally, the logic unit area with a lower congestion density is further optimized to finally complete the optimization of the detailed layout.

[0047] The present invention will be further described in detail below with reference to the drawings.

[0048] Combined with the attached Figures 1-5 , specifically the following steps

[0049] S1. Define the object of detailed layout optimization

[0050] Before formulating the optimization model, some necessary definitions and explanations are required. The architecture of an FPGA usually consists of the following main parts: programmable logic units (CLBs), programmable interconnect resources (such as global interconnect resource switch boxes SB and regional interconnect resource switch boxes CB), input / output units (IO), and built-in IP resources (such as DSP modules and memory blocks). The core unit of an FPGA is the programmable logic unit (CLB), which usually consists of a look-up table (LUT), a flip-flop (DFF), and a multiplexer.

[0051] The CLBs contain 8 LUT6s (which can accommodate various complex look-up table permutations and combinations with a total input not exceeding 6 and an output not exceeding 2) and 16 DFFs. Among them, the connected LUT and DFF in the same CLB form a BLE unit. Define the position of a CLB in the FPGA architecture as (x0, y0), then the position coordinates of the LUTs therein are (x 0 , y 0 , z i ), and the position coordinates of the DFFs are (x 0 , y 0 , z j ). Where i = 0, 1,..., 7, j = 0, 1,..., 15.

[0052] After the FPGA completes the legalized layout, it will output a circuit netlist containing the position and interconnection relationship of each unit, which includes marking whether each unit is movable. For most movable LUT and DFF units, they are the optimization objects of the model.

[0053] S2. Efficiently parse the occupancy of legalized layout logic units

[0054] The occupancy of the same CLB needs to be initialized. Initialize and define the position coordinate z i (z j ) of each movable unit LUT (DFF) to map the 00 state (0 state). Among them, for the LUT, 00 represents an empty position, 01 represents that there is only one LUT at this unit position, and 11 represents that there are two LUTs with the same coordinates at this unit position, forming an LUT6. In addition, to parse the fixed part of the other LUT and DFF units existing in the netlist and perform the subsequent algorithm steps efficiently, this step divides the 01 and 11 states into fixed and non-fixed types. The same applies to the DFF.

[0055] To update the occupancy of the overall CLBs, it is necessary to traverse all the cells in the netlist. At this time, the position z of each LUT (DFF) i (z j ) starts to transfer from the 00 state (0 state). If the traversed cell is a fixed cell, it will transfer to the fixed 01 state (fixed 1 state). Due to the large number of LUT6X in the netlist, considering its structure, in this invention patent, it is directly transferred to the fixed 11 state. For some fixed LUT6s, they are transferred to the fixed 01 state, and so on. For non-fixed LUTs, they are first transferred to the 01 state, and if the same coordinates are traversed subsequently, they will transfer to the 11 state. For DFFs, it is the same reason.

[0056] S3. Solve the maximum independent set of the FPGA netlist

[0057] In an FPGA, logic resources such as DFFs, CARRYs, LUTs, etc. can be regarded as supernodes in a graph, and the connections between devices such as signal lines can be regarded as hyperedges in the graph. The netlist file details the connection relationships between various components in the circuit. When performing operations such as moving points, due to the complex connection relationships, negative optimization may occur. To find devices with relatively simple connection relationships, that is, devices with relatively small moving costs, we map the netlist to a hypergraph and use a greedy algorithm according to the size of the netlist to find the maximum independent set in the circuit netlist. In detailed placement, the clock wire network is not within the scope of optimization.

[0058] First, traverse all the movable cells v in the circuit netlist G and assign a state value State[v] to all cells v. Initially, the states of all supernodes are false. Then traverse all v in the circuit netlist G. If the state of the currently visited supernode v is false, set the state of the currently visited cell v to true and add it to the maximum independent set S. Next, traverse all the supernodes u included in all the adjacent hyperedges of the supernode v. If the states of these points are false, set them to true. Repeat this operation until the states of all supernodes in the hypergraph G are not false. At this time, output the maximum independent set S, which is an approximate maximum independent set of the hypergraph searched by the algorithm. The specific algorithm implementation of the circuit netlist based on the greedy strategy is as follows:

[0059]

[0060]

[0061] S4. Select the optimization object to be moved and the candidate positions

[0062] After finding the maximum independent set of the global netlist, the LUTs or DFFs in the independent set are taken as one of the optimization objects, and the BEL cells at the same CLB coordinate position composed of them are found as the complete optimization objects. For the moving positions, according to the properties of the maximum independent set, we select the CLB positions that are connected to the LUTs or DFFs in the current independent set and have different CLB positions as the candidate positions. Since this part is independent of each other, it is suitable to use multi-threading to process the calculation of the moving cost subsequently.

[0063] In addition, the selection of candidate positions for movement can also be done by selecting CLB positions that have no connection relationship near the optimization object in a certain way, increasing the solution space for optimization. Considering the computational cost, the algorithm selects some CLB positions within the coordinate ranges of the BEL and multiple candidate positions that have no connection relationship with the optimization object as the new candidate positions, increasing the possibility of finding the shortest path from the moved object to each connected unit after movement.

[0064] S5. Determine the wire length evaluation algorithm

[0065] The wire length evaluation model includes the Manhattan distance model and the Steiner tree model, and the Steiner tree model can be solved by the open-source FLUTE library. The basic idea of wire length evaluation is to compare the optimization effects of the weighted critical wire length and non-critical wire length before and after movement. If the difference before and after is greater than 0, it belongs to positive optimization. For the evaluation of the critical wire length in the netlist, the Manhattan distance model is used, and the optimizable unit in the CLB is the object. Therefore, for the optimizable object, the wire length evaluation of the overall fan-in and fan-out needs to be considered. Since in the critical wire length, the fan-out of unit A, such as port O0, to the fan-in of unit B, such as port I0, can be equivalent to the fan-in I0 of unit B to port AO0 of unit A. Therefore, for the evaluation of the critical wire length of the optimizable object to be moved, it can be equivalent to the Manhattan distance from the object to be moved to the unit that has a critical wire length connection relationship with it. Taking the BEL as the object to be moved, calculate the Manhattan distance between the units connected to the BEL before and after movement in turn. The difference in distance before and after reflects the optimization effect of the critical wire length.

[0066] RSMT is a wiring method similar to the minimum spanning tree. Compared with the minimum spanning tree, the minimum Steiner tree allows additional points to be added outside the given points to minimize the sum of the edge weights of the tree. For the non-critical wire length of the wire nets in the netlist, the Steiner tree model is generally used for evaluation, and the FLUTE library provides an interface for calculating the Steiner tree model of the wire nets. For the BEL of the optimizable object to be moved in the CLB, in addition to calculating the Steiner tree wire length of the non-critical wires of the fan-out wire nets of the entire BEL object, it is also necessary to calculate the Steiner tree wire length of the non-critical wires of the driving units of the fan-in wire nets. The two parts are weighted, and the difference before and after movement is calculated to obtain the degree of wire length optimization effect before and after movement.

[0067] Although RSMT is closest to the actual wiring effect and can evaluate the non-critical wire length, it is not efficient for some wire networks with extremely large fan-outs when using the FLUTE library and takes more time. In the actual algorithm design, this algorithm sets a threshold for the number of wire networks according to the netlist situation, that is, if the number of cells connected to a wire network exceeds this threshold, the Manhattan wire length model is selected to approximately equivalent the Steiner tree model.

[0068] S6. Design the moving cost for wiring optimization

[0069] The cost of moving to a candidate location needs to consider the legality of moving to this CLB location and the change in congestion density. We first consider whether the LUT or DFF after moving meets the corresponding wire network number constraints in the CLB of this candidate location, as well as the constraints on clock and control signal wire networks. For example, there is only one CLOCK signal wire network in each Bank. In addition, the number of clocks in the clock region is updated simultaneously. If it exceeds the number of clocks, it is also illegal. If this legality check is not met, a cost of positive infinity is directly returned.

[0070] Next, after passing the legality check related to the wire network, we need to check whether the pin density in the candidate location exceeds the set threshold. This threshold can be selected as a certain proportion of the lower limit of the pin density of the CLB. According to the mathematical relationship, if the pin density of the CLB of each candidate location after moving does not exceed this threshold density, the average pin density of the optimized selected proportion of CLBs will be less than or equal to this threshold. Similarly, if the pin density of the CLB of the candidate location after moving exceeds the threshold density, a cost of positive infinity is returned. If it is less than or equal to the pin density threshold, the critical wire length and non-critical wire length after moving can be calculated, and the sum of these two parts of wire lengths weighted as the overall wire length situation, and then the difference from before moving is calculated, and this difference is returned as the final optimized cost. If the difference is less than 0 and the smaller it is, the smaller the cost, indicating that the more the wire length is optimized, and vice versa. Finally, we preferentially select the candidate location with a difference less than 0 and the smallest cost among the selected moving locations for moving, and then update the corresponding resource change situation.

[0071] S7. Use the maximum independent set to globally optimize the layout

[0072] Traverse the movable units of the maximum independent set found in the netlist in each iteration, and use them to construct the optimization object BEL, that is, the combination of LUT and DFF with connection relationships in the CLB positions where the independent points are located. Use the CLBs at non-identical positions connected by the independent points as the candidate positions for movement. In order to optimize the movement of most movable units of each net, according to the actual situation of each netlist scale, we set an iteration number. When the movable units in the current maximum independent set are traversed, we mark that each unit in this maximum independent set has been visited, and find the unvisited maximum independent set in the netlist from the unmarked movable units according to step S3, and repeat steps S4, S5, and S6 until the iteration number is reached.

[0073] S8. Oriented Optimization of Layout

[0074] After the maximum independent set optimization reaches a certain number of iterations, we find the CLB objects with relatively low pin densities in the netlist at this time. Since the wire connections between the movable units inside this part of the CLBs are relatively few, the positions of the movable units in this part of the CLBs can be optimized by moving or merging, further reducing the wire length of the routing. Consistent with S7, we find these movable units in the CLBs with pin densities lower than a certain threshold to construct the optimization object and find the corresponding candidate positions, and move to the candidate position with a cost less than 0 and the minimum, and update the resource situation. Repeat the above steps until the set iteration number is reached.

[0075] S9. Output the Detailed Layout Result

[0076] Output the optimized circuit netlist to complete the final detailed layout.

[0077] When the present invention is specifically implemented: The content of the present invention will be further described below in conjunction with the implementation examples. In this implementation example, we select 11 publicly available real netlists and implement the detailed layout algorithm involved in the present invention.

[0078] S1. Define the Detailed Layout Optimization Object

[0079] The FPGA architecture model involved in this example consists of diverse logic resources, including programmable logic blocks (CLBs), block random access memories (Block RAMs), digital signal processors (DSPs), input / output (IO) interfaces, and complex IP modules. These resources are arranged in columns inside the FPGA chip, forming an array structure. As the basic logic unit, the CLB can implement basic combinational logic, look-up tables, and sequential logic functions, and provides a dedicated fast carry logic chain for performing efficient arithmetic addition and subtraction operations. The widths of the RAM and DSP resources are the same as those of the CLB, but they occupy multiple CLB units in height. Multiple CLBs and dedicated logic units share a clock domain, Clock Region. Inside each Clock Region, a certain number of clock signals can be accommodated, usually limited to between 28 clock signals.

[0080] Each CLB contains 2 independent regions (BANKs), and each BANK contains 4 6-input 2-output look-up tables (LUTs), 8 flip-flops (DFFs), and a fast carry chain. The LUTs in the CLB are numbered from 0 to 7 from bottom to top, and the DFFs are numbered from 0 to 15 from bottom to top. Since the look-up table is a 2-output design, it can accommodate various complex look-up table permutations and combinations with the sum of inputs not exceeding 6 and the number of outputs not exceeding 2. Define the position of a CLB in the FPGA architecture as (x 0 ,y 0 ), then the position coordinates of the LUTs therein are (x 0 ,y 0 ,z i ), and the position coordinates of the DFFs are (x 0 ,y 0 ,z j ). Where i = 0, 1,..., 7, j = 0, 1,..., 15.

[0081] Among the 11 publicly available netlists, information on various logic resource units, the position of each unit, and the interconnection relationships is included, which includes marking whether each unit is movable. The scales of the number of LUTs and DFFs in the 11 publicly available real netlists are in the ranges of 50,000 - 200,000 and 50,000 - 300,000 respectively. For most of the movable LUT and DFF units among them, they will be the objects of optimization for the model.

[0082] S2. Efficiently parse and legalize the occupancy of layout logic units

[0083] First, initialize the position coordinate z of each movable unit LUT (DFF) in the CLB i (z j)Map the 00 state (0 state). Traverse all the cells in the netlist once, and for each position z of each LUT (DFF) i (z j ) starts to transfer from the 00 state (0 state). If the traversed cell is a fixed cell, it will transfer to the fixed 01 state (fixed 1 state). Since there are a large number of LUT6X in the 11 publicly available netlists, considering their structure, in this invention patent, it is directly transferred to the fixed 11 state; for the DRAM in this embodiment, considering that its structure is composed of 4 LUTs, the 4 LUTs of the corresponding BANK are converted from the initialized 00 state to the fixed 01 state; for some fixed LUT6s, they are transferred to the fixed 01 state, and so on. For non-fixed LUTs, they are first transferred to the non-fixed 01 state, and if the same coordinates are traversed later, they will transfer to the 11 state. The same applies to DFFs.

[0084] S3. Solve the maximum independent set of the FPGA netlist

[0085] In this embodiment, logical resources such as DFFs and LUTs can be regarded as hypernodes in the graph, and the connections between logical resources are regarded as hyperedges in the graph to construct a hypergraph model. According to the size of the netlist, a greedy algorithm is used to find the maximum independent set in the circuit netlist. Among them, the clock wire net and fixed logical resources are not within the scope of optimization.

[0086] First, traverse all the movable cells v in the circuit netlist G, and assign a state value State to all the cells v, which is false initially. Then, traverse all v in the circuit netlist G. If the state of the currently visited hypernode v is false, set the state of the currently visited cell v to true and add it to the maximum independent set S. Finally, sequentially judge all other hypernodes u in all the adjacent hyperedges of the hypernode v. If the states of these points are false, set them to true. Repeat this operation until the states of all hypernodes in the hypergraph G are not false. At this time, output the maximum independent set S.

[0087] S4. Select the optimization objects to be moved and candidate positions

[0088] Find the BEL cells composed of LUTs or DFFs in the independent set at the same CLB coordinate position as the optimization objects.

[0089] For the candidate positions, first select the CLB positions that are connected to the LUTs or DFFs in the current independent set and have different CLB positions. Assume that the minimum x - coordinate and y - coordinate of the candidate positions are xmin and ymin, and the maximum are xmax and ymax. Then, additionally select the CLB positions that have no connection relationship with the adjacent coordinates of the optimization object. Finally, select the CLB with coordinates (xmin + d, ymin + d) that has no connection relationship with the optimization object as the supplementary candidate position, where xmin < xmax, ymin < ymax, and d < min{(xmax - xmin), (ymax - ymin)}.

[0090] S5. Determine the wire - length evaluation algorithm

[0091] For the critical wire - length evaluation in the netlist, the Manhattan distance model is adopted. The optimization object is the movable unit in the CLB. The BEL constructed by the movable unit is used as the object to be moved. The Manhattan distances between the units connected to the BEL before and after the movement are calculated in sequence. The difference in distances before and after the movement reflects the optimization effect of the critical wire - length.

[0092] For the non - critical wire - lengths of the nets in the netlist, the Steiner tree model is used for evaluation, and the FLUTE library is used to calculate the wire - length of the Steiner tree model of the net. For the BEL of the optimization object to be moved in the CLB, the wire - length of the Steiner tree of the non - critical wires of the fan - out nets of the entire BEL object and the wire - length of the Steiner tree of the non - critical wires of the driving units of the fan - in nets are calculated, and the two parts are weighted.

[0093] In this implementation example, a threshold of the number of nets is set according to the netlist situation, that is, if the number of units connected to a net exceeds 50, then the Manhattan wire - length model is selected to approximately equivalent the Steiner tree model for equivalent calculation of the non - critical wire - length.

[0094] Compare the optimization effects of the weighted critical wire - length and non - critical wire - length before and after the movement. If the difference before and after is greater than 0, it belongs to positive optimization.

[0095] S6. Design the movement cost for routing optimization

[0096] First, consider whether the LUT or DFF after the movement satisfies the constraint of the number of nets corresponding to the CLB at the candidate position, as well as the constraints on the clock and control signal nets. In this implementation example, for 8 DFFs within the same Bank, it is required that the clock nets and the reset signal must be the same, and the number of ce signals does not exceed 2. Additionally, the number of clocks in the clock region is updated simultaneously. If it exceeds the 28 - way clock number of this implementation example's Clock Region, it is also illegal. If it is illegal, directly return a cost of positive infinity.

[0097] After satisfying the CLB-related legalization checks, we need to check whether the pin density in the candidate position exceeds the set threshold. In this implementation example, this threshold selects the lowest pin density s among the top 5% of the pin density in the overall CLB. If the pin density of the CLB in the candidate position exceeds the threshold density s after the move, a positive infinite cost is returned. If it is less than or equal to the pin density threshold s, the critical line length and non-critical line length after the move can be calculated, and the two parts of the line length are weighted at a ratio of 4:1 as the overall line length. The difference between the calculated and before the move is returned as the final optimized cost. Finally, this implementation example selects the candidate position with a difference less than 0 and the smallest cost to move, and then updates the corresponding resource changes.

[0098] S7. Global optimization of layout using maximum independent sets

[0099] In this implementation example, the number of iterations is set according to the actual situation of the scale of the 11 netlists. After traversing the movable units in the current maximum independent set, the algorithm marks that each unit in the current maximum independent set has been visited. According to step S3, the unmarked movable units continue to search for the unvisited maximum independent set in the netlist, and steps S4, S5, and S6 are repeated until the number of iterations is reached.

[0100] S8. Directional optimization layout

[0101] When the maximum independent set optimization reaches a certain number of iterations, this implementation example searches for movable cells in CLBs with a pin density lower than 0.9*s in the netlist to construct the optimization object BEL. Consistent with S7, steps S4, S5, and S6 are repeated until the number of iterations is reached.

[0102] S9. Output detailed layout results

[0103] The test environment of this example is carried out on a server based on the operating system Ubuntu 20.04.4LTS, the CPU model is Intel(R)Xeon(R)Platinum 8368CPU@2.40GHz, and the memory is 70G. The optimized netlist after detailed layout is output and compared with the one before detailed layout, the algorithm test results are as follows:

[0104] Table: Experimental results of the public test set

[0105]

[0106]

[0107] Under the condition of meeting legalization and without deteriorating the pin density, the running efficiency of all test results is high. The average bus length is optimized by 12.61%, among which the average critical wire length is optimized by 19.58% and the non-critical wire length is optimized by 10.40%. Overall, for all cases, both the critical wire length and the non-critical wire length can be optimized to a certain extent, and the running efficiency is high. Among them, the critical wire length of case1, case2, case6 and case10 can be optimized by more than 20%, but the optimization effect of the non-critical wire length of case8 is average. In addition, for the pin density, it is reduced by 1.58% on average under the premise of meeting the requirements.

[0108] In summary, from the publicly available test benchmarks, the algorithm proposed by the present invention has certain effects and efficiency, and can effectively reduce the wiring resources required in the future wiring stage and reduce the congestion density to a certain extent in the detailed layout of FPGA.

[0109]

[0110] The above description of the present invention and its implementation manners is not restrictive, and the actual structure is not limited thereto. All in all, if those of ordinary skill in the art are inspired by it and design similar structural modes and embodiments without creative efforts without departing from the spirit of the present invention, they shall fall within the protection scope of the present invention.

Claims

1. A FPGA routing optimization layout method based on maximum independent sets, characterized by: It includes the following steps: S1.FPGA architecture defines detailed layout optimization objects; S2. Efficiently analyze the occupancy of legalized layout logic units; S3. Solve the maximum independent set of FPGA netlist; S4. Select the optimization object and candidate position to be moved; S5. Determine the line length evaluation algorithm; S6. Design mobile cost for routing optimization; S7. Globally optimize the layout using the maximum independent set; S8. Directional optimization layout; S9. Output detailed layout results.

2. The FPGA routing optimization layout method based on maximum independent sets according to claim 1, characterized in that: In step S1, the architecture model part of FPGA: programmable logic cells (CLBs), programmable interconnect resources (such as global interconnect resource switch box SB and regional interconnect resource switch box CB), input and output cells (IO) and built-in IP resources (such as DSP modules and memory blocks); The core unit of FPGA is the programmable logic unit (CLB), which consists of a lookup table (LUT), a flip-flop (DFF), and a multiplexer. CLBs contain 8 LUT6 and 16 DFFs. The connected LUTs and DFFs in the same CLB form a BLE unit. The position of a CLB in the FPGA architecture is defined as (x0, y0). The position coordinates of the LUTs are (x0, y0, z i ), the position coordinates of DFF are (x0, y0, z j ).

3. The FPGA routing optimization layout method based on maximum independent sets according to claim 2, characterized in that: In step S2, the occupancy of the same CLB needs to be initialized to define the position coordinates z of each movable unit LUT (DFF) i (z j ) maps the 00 state (0 state). In addition, in order to parse the other fixed LUT and DFF units in the netlist and efficiently perform the subsequent algorithm steps, this step divides the 01 and 11 states into fixed and non-fixed types. For DFF, the same applies; Update the occupancy of the entire CLBs and traverse all the cells in the netlist. At this time, the position z of each LUT (DFF) i (z j ) starts from the 00 state (0 state). When the traversed unit is a fixed unit, it will be transferred to the fixed 01 state (fixed 1 state), and the netlist LUT6X structure will be directly transferred to the fixed 11 state. The fixed LUT6 is transferred to the fixed 01 state. The others are similar. For non-fixed LUTs, it will be transferred to the 01 state first. If the same coordinates are traversed later, it will be transferred to the 11 state. The same is true for DFF.

4. The FPGA routing optimization layout method based on maximum independent sets according to claim 3 is characterized in that: In step S3, the netlist is mapped into a hypergraph, and a greedy algorithm is used according to the size of the netlist to find the largest independent set in the circuit netlist. In the detailed layout, the clock line net is not optimized. First, traverse all movable cells v in the circuit netlist G and assign a state value State[v] to all cells v; Initially, all superpoint states are false, then all v in the circuit netlist G are traversed. If the state of the currently visited superpoint v is false, the state of the currently visited unit v is set to true, and it is added to the maximum independent set S; Next, traverse all the superpoints u contained in all the adjacent hyperedges of the superpoint v, and if the status of these points is false, set it to true; Repeat this operation until the status of all superpoints in the hypergraph G is not false. At this time, the maximum independent set S is output, which is an approximate maximum independent set of the hypergraph searched by the algorithm.

5. The FPGA routing optimization layout method based on maximum independent sets according to claim 4 is characterized in that: In step S4, after finding the maximum independent set of the global netlist, the LUT or DFF in the independent set is taken as one of the optimization objects, and the BEL units composed of it at the same CLB coordinate position are found as the complete optimization object. For the moved position, according to the properties of the maximum independent set, the CLB position that has a connection relationship with the LUT or DFF in the current independent set and has a different CLB position is selected as the candidate position; For the selection of the candidate position of the move, a CLB position with no connection relationship near the optimization object can also be selected in a certain way to increase the solution space of the optimization.

6. The FPGA routing optimization layout method based on maximum independent sets according to claim 5, characterized in that: In step S5, the line length evaluation model includes a Manhattan distance model and a Steiner tree model, wherein the Steiner tree model can be solved by the open source FLUTE library. The basic idea of ​​line length evaluation is to compare the weighted optimization effects of the critical line length and the non-critical line length before and after the move. If the difference before and after is greater than 0, it is a positive optimization. For the evaluation of critical line length in the netlist, the Manhattan distance model is used. The optimization object is the movable unit in the CLB. Therefore, for the optimization object, the overall fan-in and fan-out line length evaluation needs to be considered. Since in the critical line length, the fan-out of unit A, such as port O0, to the fan-in of unit B, such as port I0, can be equivalent to the fan-in port I0 of unit B to port AO0 of unit, therefore, for the evaluation of the critical line length of the optimization object to be moved, it can be equivalent to the Manhattan distance from the object to be moved to the unit with which it has a critical line length connection relationship. BEL is taken as the object to be moved, and the Manhattan distances between the units with a connection relationship with BEL before and after the move are calculated in turn. The difference in distance before and after the move reflects the optimization effect of the critical line length. The Steiner tree model is generally used to evaluate the non-critical line length of the wire net in the netlist. The FLUTE library provides an interface for calculating the Steiner tree model of the wire net. For the optimization object BEL to be moved in the CLB, in addition to calculating the Steiner tree line length of the non-critical line of the fan-out wire net of the entire BEL object, it is also necessary to calculate the Steiner tree line length of the non-critical line of the driver unit of the fan-in wire net. The two parts are weighted and the difference before and after the move is calculated to obtain the degree of wire length optimization effect before and after the move; This algorithm sets a threshold for the number of wire nets according to the netlist situation. That is, if the number of units connected to a wire net exceeds the threshold, the Manhattan wire length model is chosen to approximate the equivalent Steiner tree model.

7. The FPGA routing optimization layout method based on maximum independent sets according to claim 6, characterized in that: In step S6, the cost of moving to the candidate position needs to consider the legality of moving to the CLB position and the change in congestion density. First, consider whether the moved LUT or DFF meets the corresponding network quantity constraint in the CLB of the candidate position, as well as the constraints on the clock and control signal network. In addition, the number of clocks in the clock area is updated at the same time. If it exceeds the number of clocks, it is also illegal. If the legality check is not met, a positive infinite cost is directly returned; Next, after satisfying the legalization check related to the line network, check whether the pin density in the candidate position exceeds the set threshold. This threshold can be selected as the lower limit of the pin density of a certain proportion of CLBs. According to the mathematical relationship, if the pin density of the CLB of each candidate position after the move does not exceed the threshold density, then the average pin density of the CLB of the optimized selected proportion will be less than or equal to the threshold. Similarly, if the pin density of the CLB of the candidate position after the move exceeds the threshold density, a positive infinite cost is returned. If it is less than or equal to the pin density threshold, the critical line length and non-critical line length after the move can be calculated, and the weighted lengths of these two parts are used as the overall line length. The difference with the length before the move is calculated and returned as the final optimization cost. If the difference is less than 0 and the smaller it is, the smaller the cost is, indicating that the optimized line length is more, and vice versa. Finally, when selecting the moving position, the candidate position with a difference less than 0 and the lowest cost is preferentially selected for moving, and then the corresponding resource change is updated.

8. The FPGA routing optimization layout method based on maximum independent sets according to claim 7, characterized in that: In step S7, the movable units of the largest independent set in the netlist found in each iteration are traversed, and the optimization object BEL is constructed using the movable units, that is, the LUT and DFF combination with a connection relationship in the CLB position of the independent point; Using CLBs at different positions connected by independent points as candidate positions for movement, in order to optimize the movement of most of the movable units of each line network, an iteration number is set according to the actual size of each netlist. When the movable units in the current maximum independent set are traversed, we mark each unit of the maximum independent set as visited, and according to step S3, find the unvisited maximum independent set in the netlist from the unmarked movable units, and repeat steps S4, S5, and S6 until the iteration number is reached.

9. The FPGA routing optimization layout method based on maximum independent sets according to claim 8, characterized in that: In step S8, when the maximum independent set optimization reaches a certain number of iterations, the CLB object with a low pin port density in the netlist is found. Since there are relatively few interconnected wires of mobile units in this part of the CLB, the position of the mobile units in this part of the CLB can be optimized by moving or merging, so as to further reduce the wiring length; Consistent with S7, the movable units in the CLB with pin port density lower than a certain threshold are searched to construct optimization objects and find corresponding candidate positions, and the candidate positions with the smallest cost less than 0 are found to perform the move operation, and the resource status is updated. The above steps are repeated until the set number of iterations is reached.

10. The FPGA routing optimization layout method based on maximum independent sets according to claim 9, characterized in that: In step S9, the optimized circuit netlist is output to complete the final detailed layout.

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