Physical simulation model of ferroelectric neuron circuit and design method thereof

Abstract

The invention relates to a physical simulation model of a ferroelectric neuron circuit and a design method thereof, and the method comprises the steps: building the physical simulation model of the ferroelectric neuron circuit according to the corresponding relation between the polarization intensity of a ferroelectric layer in a ferroelectric field effect transistor and the voltage of the ferroelectric layer, the surface charge density of the ferroelectric layer, and the source voltage of the ferroelectric field effect transistor, and predicting the working state of the ferroelectric neuron circuit according to the physical simulation model. Meanwhile, a corresponding experimental design method is further developed according to the provided model. The physical simulation model combining the ferroelectric polarization flipping and the dynamic characteristics of the ferroelectric neuron circuit has very high physical reliability; the design method provided by the invention can guide the specific design of the experiment, significantly reduces the trial and error cost of the experiment manufacturing of the ferroelectric neuron circuit, and provides a physical basis for the further development of the ferroelectric neuron circuit in electronic design automation software.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor integrated circuit design and manufacturing, and particularly to a physical simulation model of a ferroelectric neuron circuit and a design method thereof. Background Art

[0002] Ferroelectric field effect transistors (FeFETs) have characteristics such as rich dynamic characteristics of ferroelectric polarization reversal, and thus have great potential in simulating neuron behavior. For a ferroelectric neuron with a 1T-1FeFET structure, that is, a ferroelectric neuron model composed of a MOSFET transistor and a ferroelectric field effect transistor, the ferroelectric layer is simplified to an ideal logic switch, and it is artificially stipulated that the triggering condition of this logic switch can basically reproduce the experimental situation. However, there is no further research and disclosure on the design method of realizing a ferroelectric neuron oscillator with this structure in experiments.

[0003] In the related art, ferroelectric neuron circuits with different structures, although their working mechanisms have certain differences, are all closely related to the reversal of ferroelectric polarization. Therefore, a compact model that can accurately describe the reversal of ferroelectric polarization and combine it with the dynamic characteristics of the neuron circuit is highly needed. However, a neuron model integrating the two does not yet exist. For the 1T-1FeFET structure ferroelectric neuron model in the related art, since it is only a behavioral-level model and does not involve the underlying physical principles, it is difficult to meet the need for guiding the design of experimental implementation. Therefore, it is of great significance to develop a design process that can clearly guide experimental implementation. Summary of the Invention

[0004] In view of this, based on the ferroelectric neuron with a 1T-1FeFET structure, the present disclosure proposes a physical simulation model of a ferroelectric neuron circuit and a design method thereof.

[0005] According to one aspect of the present disclosure, a circuit simulation method is provided, including: establishing a physical simulation model of a ferroelectric neuron circuit according to the correspondence between the polarization intensity of the ferroelectric layer in the ferroelectric field effect transistor and the ferroelectric layer voltage, the surface charge density of the ferroelectric layer, and the source voltage of the ferroelectric field effect transistor; predicting the working state of the ferroelectric neuron circuit according to the physical simulation model, wherein the ferroelectric neuron circuit is a neuron circuit composed of ferroelectric field effect transistors. In an example, a design method (or design process) that can guide the specific design of experiments can be developed according to the physical simulation model, predict the working state of the ferroelectric neuron circuit, and guide the specific design and implementation of experiments according to the design method.

[0006] In a possible implementation, the ferroelectric neuron circuit includes the ferroelectric field-effect transistor, the discharge transistor, and the load capacitor. The gate of the discharge transistor receives a first input pulse signal, the gate of the ferroelectric field-effect transistor receives a second input pulse signal, the drain of the ferroelectric field-effect transistor receives a bias voltage, and the drain of the discharge transistor, the source of the ferroelectric field-effect transistor, and the first end of the load capacitor are connected to generate an output signal. Among them, the drain of the discharge transistor is both the source of the ferroelectric field-effect transistor and the first end of the load capacitor, and the drain of the discharge transistor is used to generate the output signal.

[0007] In a possible implementation, the surface charge density of the ferroelectric layer is determined according to the polarization intensity of the ferroelectric layer in the ferroelectric field-effect transistor, the ferroelectric layer voltage, and the ferroelectric layer thickness. The ferroelectric layer voltage is determined according to the external gate-source voltage, the internal gate-source voltage, and the surface charge density of the internal gate in the ferroelectric field-effect transistor. The surface charge density of the internal gate is determined according to the internal gate-source voltage, the internal gate-drain voltage, and the transistor device parameters in the ferroelectric field-effect transistor. And the ratio of the surface charge density of the ferroelectric layer to the surface charge density of the internal gate is equal to the first ratio of the ferroelectric layer capacitance area to the transistor gate capacitance area in the ferroelectric field-effect transistor. The source voltage of the ferroelectric field-effect transistor is determined according to the charging current of the ferroelectric field-effect transistor and the discharging current of the discharge transistor.

[0008] In a possible implementation, based on the physical simulation model, a set of design methods is developed to predict the working state of the ferroelectric neuron circuit, including: determining whether the bias voltage of the ferroelectric neuron circuit is within a preset voltage range; when the bias voltage is within the preset voltage range, determining whether the first ratio of the ferroelectric layer capacitance area to the transistor gate capacitance area in the ferroelectric field-effect transistor of the ferroelectric neuron circuit is within a first preset range; when the first ratio is within the first preset range, determining whether the second ratio between the channel width-to-length ratio of the ferroelectric field-effect transistor and the channel width-to-length ratio of the discharge transistor is within a second preset range; when the second ratio is within the second preset range, predicting the working state of the ferroelectric neuron circuit as: the output signal of the ferroelectric neuron circuit is an oscillation signal.

[0009] In a possible implementation, when the gate-source capacitance and the gate-drain capacitance per unit area of the ferroelectric field-effect transistor are constants, the upper limit of the preset voltage range is the product of the third ratio of the total capacitance per unit area of the ferroelectric field-effect transistor to the gate-drain capacitance and the gate voltage of the ferroelectric field-effect transistor, and the lower limit of the preset voltage range is the gate voltage of the ferroelectric field-effect transistor; the upper limit of the first preset range is determined according to the total capacitance per unit area of the ferroelectric field-effect transistor and the ferroelectric layer thickness, and the lower limit of the first preset range is determined according to the total capacitance per unit area of the ferroelectric field-effect transistor, the gate-source capacitance, the gate-drain capacitance, the ferroelectric layer thickness, the gate voltage of the ferroelectric field-effect transistor, and the bias voltage; the upper limit of the second preset range is determined according to the oscillation valley voltage, the threshold voltage of the transistor, the bias voltage, the gate voltage of the discharge transistor, the gate voltage of the ferroelectric field-effect transistor, and the ferroelectric layer voltage, and the lower limit of the second preset range is determined according to the gate voltage of the discharge transistor, the gate voltage of the ferroelectric field-effect transistor, the threshold voltage of the transistor, and the oscillation peak voltage.

[0010] In a possible implementation, the ferroelectric field-effect transistor is a single-domain ferroelectric field-effect transistor.

[0011] According to one aspect of the present disclosure, there is provided a ferroelectric neuron circuit simulation model system constructed by the method as described above. The ferroelectric neuron circuit simulation system simulates the working state of the ferroelectric neuron circuit, and the ferroelectric neuron circuit simulation system includes the ferroelectric field-effect transistor simulation element, the discharge transistor simulation element, and the load capacitance simulation element.

[0012] According to one aspect of the present disclosure, there is provided a circuit simulation device. The device includes: an establishment module for establishing a physical simulation model of the ferroelectric neuron circuit according to the correspondence between the polarization intensity of the ferroelectric layer in the ferroelectric field-effect transistor and the ferroelectric layer voltage, the surface charge density of the ferroelectric layer, and the source voltage of the ferroelectric field-effect transistor; a prediction module for predicting the working state of the ferroelectric neuron circuit according to the physical simulation model, where the ferroelectric neuron circuit is a neuron circuit based on a ferroelectric field-effect transistor.

[0013] In a possible implementation, the ferroelectric neuron circuit includes the ferroelectric field-effect transistor, the discharge transistor, and the load capacitor. The gate of the discharge transistor receives a first input pulse signal, the gate of the ferroelectric field-effect transistor receives a second input pulse signal, the drain of the ferroelectric field-effect transistor receives a bias voltage, and the drain of the discharge transistor, the source of the ferroelectric field-effect transistor, and the first end of the load capacitor are connected to generate an output signal. Among them, the drain of the discharge transistor is both the source of the ferroelectric field-effect transistor and the first end of the load capacitor, and the drain of the discharge transistor is used to generate the output signal.

[0014] In a possible implementation, the surface charge density of the ferroelectric layer is determined according to the polarization intensity of the ferroelectric layer in the ferroelectric field-effect transistor, the ferroelectric layer voltage, and the ferroelectric layer thickness. The ferroelectric layer voltage is determined according to the external gate-source voltage, the internal gate-source voltage, and the surface charge density of the internal gate electrode in the ferroelectric field-effect transistor. The surface charge density of the internal gate electrode is determined according to the internal gate-source voltage, the internal gate-drain voltage, and the transistor device parameters in the ferroelectric field-effect transistor, and the ratio of the surface charge density of the ferroelectric layer to the surface charge density of the internal gate electrode is equal to the first ratio of the ferroelectric layer capacitance area to the transistor gate capacitance area in the ferroelectric field-effect transistor. The source voltage of the ferroelectric field-effect transistor is determined according to the charging current of the ferroelectric field-effect transistor and the discharging current of the discharge transistor.

[0015] In a possible implementation, the prediction module is configured to: determine whether the bias voltage of the ferroelectric neuron circuit is within a preset voltage range; when the bias voltage is within the preset voltage range, determine whether the first ratio of the ferroelectric layer capacitance area to the transistor gate capacitance area in the ferroelectric field-effect transistor of the ferroelectric neuron circuit is within a first preset range; when the first ratio is within the first preset range, determine whether the second ratio between the channel width-to-length ratio of the ferroelectric field-effect transistor and the channel width-to-length ratio of the discharge transistor is within a second preset range; when the second ratio is within the second preset range, predict the working state of the ferroelectric neuron circuit as: the output signal of the ferroelectric neuron circuit is an oscillation signal.

[0016] In a possible implementation, when the gate-source capacitance and the gate-drain capacitance per unit area of the ferroelectric field-effect transistor are constants, the upper limit of the preset voltage range is the product of the third ratio of the total capacitance per unit area of the ferroelectric field-effect transistor to the gate-drain capacitance and the gate voltage of the ferroelectric field-effect transistor, and the lower limit of the preset voltage range is the gate voltage of the ferroelectric field-effect transistor; the upper limit of the first preset range is determined according to the total capacitance per unit area of the ferroelectric field-effect transistor and the ferroelectric layer thickness, and the lower limit of the first preset range is determined according to the total capacitance per unit area of the ferroelectric field-effect transistor, the gate-source capacitance, the gate-drain capacitance, the ferroelectric layer thickness, the gate voltage of the ferroelectric field-effect transistor, and the bias voltage; the upper limit of the second preset range is determined according to the oscillation valley voltage, the threshold voltage of the transistor, the bias voltage, the gate voltage of the discharge transistor, the gate voltage of the ferroelectric field-effect transistor, and the ferroelectric layer voltage, and the lower limit of the second preset range is determined according to the gate voltage of the discharge transistor, the gate voltage of the ferroelectric field-effect transistor, the threshold voltage of the transistor, and the oscillation peak voltage.

[0017] In a possible implementation, the ferroelectric field-effect transistor is a single-domain ferroelectric field-effect transistor.

[0018] According to another aspect of the present disclosure, there is provided an electronic device, including: a processor; a memory for storing instructions executable by the processor; wherein, the processor is configured to implement the above method when executing the instructions stored in the memory.

[0019] According to another aspect of the present disclosure, there is provided a non-volatile computer-readable storage medium, on which computer program instructions are stored, wherein the computer program instructions implement the above method when executed by a processor.

[0020] According to another aspect of the present disclosure, there is provided a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code, when the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0021] Through the circuit simulation method of the embodiments of the present disclosure, a physical simulation model of a ferroelectric neuron circuit can be established based on the correspondence between the polarization intensity of the ferroelectric layer and the ferroelectric layer voltage in a ferroelectric field-effect transistor, the surface charge density of the ferroelectric layer, and the source voltage of the ferroelectric field-effect transistor, and the working state of the ferroelectric neuron circuit can be predicted according to the physical simulation model. This physical simulation model that combines ferroelectric polarization reversal with the dynamic characteristics of the ferroelectric neuron circuit has high physical reliability and can significantly reduce the trial-and-error cost of experimentally fabricating the ferroelectric neuron circuit. At the same time, predicting the working state of the ferroelectric neuron circuit through the physical simulation model can provide a physical basis for the further development of the ferroelectric neuron circuit in electronic design automation software.

[0022] Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings, which are included in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the present disclosure and are used to explain the principles of the present disclosure.

[0024] Figure 1 FIG. shows a flowchart of a circuit simulation method according to an embodiment of the present disclosure.

[0025] Figure 2 FIG. shows a schematic diagram of a ferroelectric neuron circuit according to an embodiment of the present disclosure.

[0026] Figure 3 FIG. shows a circuit schematic diagram of a leakage integrator according to an embodiment of the present disclosure.

[0027] Figure 4 FIG. shows a schematic diagram of a simulation result of a physical simulation model according to an embodiment of the present disclosure.

[0028] Figure 5 FIG. shows a schematic diagram of a static L-K curve analysis of a physical simulation model according to an embodiment of the present disclosure.

[0029] Figure 6 FIG. shows a schematic diagram of a design flow of a ferroelectric neuron circuit according to an embodiment of the present disclosure.

[0030] Figure 7 FIG. shows a schematic diagram of the effect of a ferroelectric neuron circuit according to an embodiment of the present disclosure.

[0031] Figure 8 FIG. shows a block diagram of a circuit simulation apparatus according to an embodiment of the present disclosure.

[0032] Figure 9 FIG. shows a block diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. Like reference numerals in the drawings denote functionally identical or similar elements. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0034] As used herein, the term "exemplary" means "serving as an example, embodiment, or illustration". Any embodiment described herein as "exemplary" is not necessarily to be construed as superior or better than other embodiments.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present disclosure, "a plurality" means two or more unless otherwise specifically defined.

[0036] In the present disclosure, unless otherwise clearly defined and limited, terms such as "mounted", "connected", "coupled", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0037] As used herein, the term "and / or" is merely a description of the associated relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" as used herein represents any one of a plurality or any combination of at least two of a plurality. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set composed of A, B, and C.

[0038] To better illustrate the present disclosure, numerous specific details are given in the following detailed description. Those skilled in the art should understand that the present disclosure can be implemented without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art are not described in detail so as to highlight the gist of the present disclosure.

[0039] Figure 1 A flowchart showing a circuit simulation method according to an embodiment of the present disclosure. As Figure 1 shown, the method includes:

[0040] In step S11, a physical simulation model of the ferroelectric neuron circuit is established according to the correspondence between the polarization intensity of the ferroelectric layer and the ferroelectric layer voltage in the ferroelectric field-effect transistor, the surface charge density of the ferroelectric layer, and the source voltage of the ferroelectric field-effect transistor.

[0041] In step S12, according to the physical simulation model, the operating state of the ferroelectric neuron circuit is predicted. In an example, a design method (or design process) that can guide the specific design of the experiment can be developed based on the physical simulation model to predict the operating state of the ferroelectric neuron circuit, and the specific design implementation of the experiment can be guided according to the design method.

[0042] This physical simulation model that combines ferroelectric polarization reversal with the dynamic characteristics of the ferroelectric neuron circuit has high physical reliability and can significantly reduce the trial-and-error cost of experimentally fabricating the ferroelectric neuron circuit. At the same time, predicting the operating state of the ferroelectric neuron circuit through the physical simulation model can provide a physical basis for the further development of the ferroelectric neuron circuit in electronic design automation software.

[0043] In a possible implementation manner, the circuit simulation method of the embodiments of the present disclosure can be executed by an electronic device such as a terminal device or a server. The terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. The method can be implemented by the processor calling computer-readable instructions stored in the memory. Alternatively, the method can be executed by the server.

[0044] In some possible implementation manners, the circuit simulation method can be implemented by the processor calling computer-readable instructions stored in the memory. In an example, the processor can be a general-purpose processor such as a central processing unit (CPU) or a graphics processing unit (GPU), or can be an artificial intelligence processor such as an artificial intelligence (AI) chip.

[0045] In a possible implementation, the ferroelectric neuron circuit is a neuron circuit based on ferroelectric field effect transistors. Among them, the ferroelectric field effect transistor can be polarized under the action of an electric field, and this polarization state can still be maintained for a period of time after the electric field is removed, similar to the accumulation and leakage of biological neurons. The ferroelectric neuron circuit can be used to simulate the working mechanism of biological neurons. This circuit can receive, integrate, and transmit voltage pulse signals, thereby simulating the excitatory and inhibitory states of neurons.

[0046] In a possible implementation, the ferroelectric field effect transistor is a single-domain ferroelectric field effect transistor. The ferroelectric layer of the single-domain ferroelectric field effect transistor has a single spontaneous polarization direction, that is, the entire ferroelectric layer can be regarded as a single ferroelectric domain.

[0047] Figure 2 A schematic diagram showing a ferroelectric neuron circuit according to an embodiment of the present disclosure is as Figure 2 shown. The ferroelectric neuron circuit includes the ferroelectric field effect transistor FeFET, the discharge transistor T, and the load capacitor C. The gate of the discharge transistor T receives a first input pulse signal, the gate of the ferroelectric field effect transistor FeFET receives a second input pulse signal, and the drain of the ferroelectric field effect transistor FeFET receives a bias voltage V DD , the drain of the discharge transistor T, the source of the ferroelectric field effect transistor FeFET, and the first end of the load capacitor C are connected to generate an output signal (for example, the source voltage V of the ferroelectric field effect transistor FeFET S ), and the source of the discharge transistor T and the second end of the load capacitor C are both grounded. Among them, the drain of the discharge transistor T is both the source of the ferroelectric field effect transistor FeFET and the first end of the load capacitor C, and the drain of the discharge transistor T is used to generate an output signal.

[0048] As Figure 2 shown, when certain conditions are met, these structures can achieve the function of an oscillator. In essence, it is to use the ferroelectric field effect transistor FeFET to charge the load capacitor C with a charging current I D , and the discharge transistor T discharges the load capacitor C with a discharge current I M , and periodically charge and discharge the load capacitor C. Both the ferroelectric field effect transistor FeFET and the discharge transistor T are N-type metal-oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field Effect Transistor, MOSFET).

[0049] In a possible implementation, to simulate the "leaky-integrate-and-fire" behavior of neurons, a leak integrator can be connected to the gate terminals of the firing transistor T and the ferroelectric field-effect transistor FeFET.

[0050] Optionally, the ferroelectric neuron circuit further includes a first leak integrator and a second leak integrator. The first leak integrator is connected to the gate of the firing transistor T, and the second leak integrator is connected to the gate of the ferroelectric field-effect transistor FeFET. In this way, the excitatory input can be formed into a first input pulse signal through the first leak integrator and sent to the gate of the firing transistor; the inhibitory input can be formed into a second input pulse signal through the second leak integrator and sent to the gate of the ferroelectric field-effect transistor FeFET.

[0051] Figure 3 The circuit schematic diagram of the leak integrator according to an embodiment of the present disclosure is shown, as Figure 3 shown, each leak integrator may include a diode, a first resistor R S , a second resistor R p , an integrating capacitor C p . The anode of the diode receives the input pulse V x , the cathode of the diode is connected to the first end of the first resistor R S . The second end of the first resistor R S , the first end of the second resistor R p , and the first end of the integrating capacitor C p are connected to provide a pulse signal. The second end of the second resistor R p , and the second end of the integrating capacitor C p are grounded.

[0052] It should be understood Figure 3 that only one feasible structure of the leak integrator is given. The leak integrator can be implemented by capacitors and resistors, and in actual applications, the circuit structure of the leak integrator can be adjusted according to specific application scenarios. The embodiments of the present disclosure do not limit this.

[0053] In a possible implementation, the ferroelectric neuron circuit further includes an inverter connected to the first end of the load capacitor C. The output signal of the ferroelectric neuron circuit can be the voltage value of the load capacitor C digitized by the inverter.

[0054] Optionally, a certain voltage pulse is applied to the gate terminals of the ferroelectric field-effect transistor FeFET and the firing transistor T. When the frequency of the input pulse V x is appropriate, such that the gate voltage V GM of the firing transistor T, the gate voltage V GFWhen it reaches the appropriate range, it will cause the output voltage V of the load capacitance C s to oscillate. The inverter pair is digitized and its result is output, which is manifested as a neuron firing.

[0055] Optionally, in the ferroelectric neuron circuit as shown in Figure 2 , the structure of the ferroelectric field-effect transistor FeFET can be referred to Figure 2 in the dashed part. The gate dielectric layer of the field-effect transistor can be replaced with a ferroelectric layer composed of a ferroelectric material to obtain the ferroelectric field-effect transistor FeFET.

[0056] As shown in Figure 2 , the ferroelectric field-effect transistor FeFET has a ferroelectric polarization phenomenon. Under the action of an external electric field, the internal charge distribution changes, resulting in a potential change, and its polarization state changes with the change of the external voltage. For the convenience of description, the gate terminal outside the ferroelectric layer is denoted as the external gate (G terminal), the gate terminal inside the ferroelectric layer is denoted as the internal gate (g terminal), the external gate voltage is denoted as V G , that is, the gate voltage V of the ferroelectric field-effect transistor FeFET GF , the internal gate voltage is denoted as V g , the source voltage is denoted as V S , that is, the output voltage of the ferroelectric neuron circuit, the drain voltage is denoted as V D , that is, the bias voltage V DD , the voltage between the external gate and the source is denoted as the external gate-source voltage V GS , the voltage between the internal gate and the source is denoted as the internal gate-source voltage V gs , the equivalent capacitance between the internal gate and the source is denoted as the gate-source capacitance C gs , the equivalent capacitance between the internal gate and the drain is denoted as the gate-drain capacitance C gd .

[0057] In a possible implementation manner, in step S11, the corresponding relationship between the polarization intensity of the ferroelectric layer and the ferroelectric layer voltage in the ferroelectric field-effect transistor FeFET can be obtained. For example, assuming a single-domain ferroelectric field-effect transistor FeFET as an example, the change of the ferroelectric polarization with the applied voltage of the ferroelectric layer in the single-domain ferroelectric field-effect transistor FeFET can be described by the L-K equation (Landau-Khalatnikov), that is:

[0058]

[0059] where V FE represents the ferroelectric layer voltage, P represents the polarization intensity of the ferroelectric layer, t represents time, t FE represents the ferroelectric layer thickness, α and β represent the Landau coefficients, and ρ represents the viscosity coefficient related to the ferroelectric dynamic behavior.

[0060] It should be understood that the ferroelectric layer of a multi-domain ferroelectric field-effect transistor is composed of multiple small regions (i.e., ferroelectric domains) with different spontaneous polarization directions. For a multi-domain ferroelectric field-effect transistor FeFET, the situation of multi-domain ferroelectric flipping can be described by a multi-domain L-K curve. The difference is that the coercive field ξ of the multi-domain ferroelectric layer satisfies a Gaussian distribution. Therefore, it is only necessary to replace formula (1) with a system of equations composed of N L-K equations. Through simulation, it is found that the difficulty of realizing neuron oscillation is higher than that of a single-domain ferroelectric field-effect transistor FeFET. Therefore, it will not be elaborated here too much. The single-domain case can be referred to, and the single-domain case will be mainly analyzed here.

[0061] In the example, the surface charge density of the ferroelectric layer can also be obtained. The surface charge density of the ferroelectric layer is determined according to the polarization intensity of the ferroelectric layer, the voltage of the ferroelectric layer, and the thickness of the ferroelectric layer in the ferroelectric field-effect transistor FeFET. The surface charge density of the ferroelectric layer can be written as:

[0062]

[0063] where Q FE represents the surface charge density of the ferroelectric layer, P represents the polarization intensity of the ferroelectric layer, ε represents the dielectric constant, V FE represents the voltage of the ferroelectric layer, and t FE represents the thickness of the ferroelectric layer.

[0064] The voltage V of the ferroelectric layer FE is determined according to the external gate-source voltage V of the ferroelectric field-effect transistor FeFET GS , the internal gate-source voltage V gs , and the surface charge density of the internal gate electrode, that is:

[0065] V FE = V GS - V gs (Q MOS ) (3)

[0066] where V GS represents the external gate-source voltage of the ferroelectric field-effect transistor FeFET, V FE represents the voltage of the ferroelectric layer, and Q MOS represents the surface charge density of the internal gate electrode of the ferroelectric field-effect transistor FeFET, that is, the amount of charge per unit area at the gate terminal in the ferroelectric layer. This surface charge density of the internal gate electrode can be measured through experiments or calculated from the voltages applied to each terminal of the transistor.

[0067] In order to couple the ferroelectric layer with the transistor, the charge conservation constraint condition can be adopted. The surface charge density Q of the internal gate electrode MOSis determined according to the first ratio of the ferroelectric layer capacitance area to the transistor gate capacitance area in the ferroelectric field-effect transistor (FeFET) and the surface charge density Q of the ferroelectric layer FE determined;

[0068] Q MOS = κ 1 Q FE (4)

[0069] where κ 1 represents the first ratio of the ferroelectric layer capacitance area S FE to the transistor gate capacitance area S MOS , that is: κ 1 = S FE / S MOS .

[0070] It can be seen therefrom that the surface charge density Q of the inner gate MOS is determined according to the inner gate-source voltage V gs , the inner gate-drain voltage V gd and the transistor device parameters, and the surface charge density Q of the ferroelectric layer FE and the ratio of the surface charge density Q of the inner gate MOS is equal to the first ratio κ of the ferroelectric layer capacitance area S FE to the transistor gate capacitance area S MOS in the ferroelectric field-effect transistor (FeFET). 1 .

[0071] In the example, the source voltage V of the ferroelectric field-effect transistor (FeFET) can also be obtained S , and the source voltage V of the ferroelectric field-effect transistor (FeFET) S is determined according to the charging current of the ferroelectric field-effect transistor (FeFET) and the discharging current of the discharging transistor. For example, Kirchhoff's law can be used for the load capacitor C, that is:

[0072]

[0073] where V s is the source voltage of the ferroelectric field-effect transistor (FeFET), that is, the voltage of the load capacitor C, and can be used as the output signal of the ferroelectric neuron circuit. t represents time, and I D represents the charging current of the ferroelectric field-effect transistor (FeFET) to the load capacitor C, that is, the drain-source current of the ferroelectric field-effect transistor (FeFET), and I M represents the discharging current of the discharging transistor T to the load capacitor C, that is, the drain-source current of the discharging transistor T, and c represents the capacitance value of the load capacitor.

[0074] To more accurately describe the charging current I of the ferroelectric field-effect transistor (FeFET), D , and the discharging current I of the discharging transistor T M , the magnitude thereof can be calculated by using the drift-diffusion formula and the theoretical method of the Quasi Fermi Level Phase Space (QFLPS) of the transistor, and the calculation can be accelerated, which can be expressed as:

[0075]

[0076] wherein, I D represents the charging current of the ferroelectric field-effect transistor (FeFET) to the load capacitor C, and I M represents the discharging current of the discharging transistor T to the load capacitor C, V DD represents the bias voltage, and V s represents the source voltage of the ferroelectric field-effect transistor (FeFET), that is, the drain voltage of the discharging transistor T, μ D represents the electron mobility of the ferroelectric field-effect transistor (FeFET), and μ M represents the electron mobility of the discharging transistor T, W D represents the channel width of the ferroelectric field-effect transistor (FeFET), L D represents the channel length of the ferroelectric field-effect transistor (FeFET), W M represents the channel width of the discharging transistor T, L M represents the channel length of the discharging transistor T, n D represents the electron concentration of the ferroelectric field-effect transistor (FeFET), and n M represents the electron concentration of the discharging transistor T, ε F,D represents the electron quasi-Fermi level of the ferroelectric field-effect transistor (FeFET), and ε F,M represents the electron quasi-Fermi level of the discharging transistor T.

[0077] According to the Gauss's law of the transistor gate electric field, the electron concentration n D and the electron quasi-Fermi level ε F,D of the ferroelectric field-effect transistor (FeFET) can be modulated by the internal gate-source voltage V gs (see the label in Figure 1 ); the electron concentration n M and the electron quasi-Fermi level ε F,M of the discharging transistor T can be modulated by the gate voltage V GM of the discharging transistor T.

[0078] It should be understood that the embodiments of the present disclosure are not limited to the expression form of the current, for example, including any current calculation method that can describe an n-type transistor.

[0079] The physical simulation model of the ferroelectric neuron circuit can be obtained by combining formulas (1) to (6). This physical simulation model can be used to predict the output signal V of the ferroelectric neuron circuit. s The physical simulation model can also simulate or predict the changes of the ferroelectric layer polarization intensity P, the gate-source voltage V of the ferroelectric field effect transistor FeFET, and the gs , the charging current I of the load capacitor C D and the discharge current I M of changes.

[0080] It should be understood that the physical simulation model can be run on a circuit simulator. Since equation (6) contains an integral and the set of equations formed by equations (1) to (6) is a nonlinear differential equation, the physical simulation model of the ferroelectric neuron circuit can be realized by designing a corresponding numerical method.

[0081] Among them, numerical methods are used to solve problems that cannot be solved by analytical methods. Through techniques such as approximation and iteration, continuous mathematical problems can be converted into discrete numerical problems, thereby obtaining approximate solutions to the problems. Numerical methods may include finite difference method, finite element method, finite volume method, spectral method, boundary element method, etc. The embodiments of the present disclosure do not limit the types of numerical methods.

[0082] In the related art, the LK equation developed from Landau theory can cover the dynamic phenomena of known ferroelectric layers. However, the LK equation has not been used for the simulation of neuron-level devices (such as ferroelectric neuron circuits). Through the physical simulation model of the embodiment of the present disclosure, the LK equation can be combined with external circuit conditions, which is physically complete. The physical simulation model can predict the working state of ferroelectric neurons under different parameters (conditions), which not only greatly deepens the understanding of the dynamic characteristics of ferroelectric neurons, but also provides a theoretical basis for further development of the design process.

[0083] In step S11, a physical simulation model is obtained, and in step S12, the working state of the ferroelectric neuron circuit can be predicted according to the physical simulation model.

[0084] In order to better analyze the ferroelectric neuron circuit using the physical simulation model, the gate voltage V of the discharge transistor T can be GM and the gate voltage V of the ferroelectric field effect transistor FeFET GF All are set to fixed values. For the complete behavior of neurons, it is only necessary to connect leakage integrators at the gates of the discharge transistor T and the ferroelectric field effect transistor FeFET to obtain the settlement results of the voltage pulse. By setting the parameters reasonably, the above physical simulation model can simulate neuronal oscillations.

[0085] Figure 4 Schematic diagram showing the simulation results of a physical simulation model according to an embodiment of the present disclosure, as Figure 4 shown, in the initial state, the output voltage V of the physical simulation model s is equal to 0. Due to the charging current I of the load capacitor C D being greater than the discharging current I M , the output voltage V corresponding to the load capacitor C S rises. During the process of the output voltage V s rising, for the ferroelectric field-effect transistor FeFET, the external gate-source voltage V GS decreases (V GS = V GF - V s ), the polarization intensity P of the ferroelectric layer decreases, resulting in a decrease in the internal gate-source voltage V gs and a decrease in the charging current I D . At the same time, due to the sudden change phenomenon of the polarization intensity P of the ferroelectric layer in the single-domain ferroelectric physical simulation model (i.e., a single domain flips), at a certain moment, the internal gate-source voltage V gs of the ferroelectric field-effect transistor FeFET suddenly decreases. At this time, the ferroelectric field-effect transistor FeFET enters the subthreshold region and the ferroelectric field-effect transistor FeFET is in the "off" state. At this time, the discharging current I M is greater than the charging current I D , resulting in the output voltage V corresponding to the load capacitor C s beginning to decrease. During the process of the output voltage V s decreasing, the external gate-source voltage V GS of the ferroelectric field-effect transistor FeFET increases, the polarization intensity P of the ferroelectric layer increases, resulting in an increase in the internal gate-source voltage V gs of the ferroelectric field-effect transistor FeFET and an increase in the charging current I D . Similarly, due to the sudden change in the polarization intensity P of the ferroelectric layer, at a certain moment, the internal gate-source voltage V gs of the ferroelectric field-effect transistor FeFET suddenly increases. Accordingly, the charging current I D also suddenly increases, and the ferroelectric field-effect transistor FeFET is in the "on" state. At this time, the charging current I D is greater than the amplification current I M , resulting in the output voltage V corresponding to the load capacitor C s beginning to rise. The ferroelectric neuron continuously cycles in the above two processes, thus resulting in the oscillation phenomenon of the output voltage V s .

[0086] Since as Figure 2The ferroelectric neuron circuit shown has two symmetric n-type transistors, namely the ferroelectric field-effect transistor FeFET and the discharge transistor T. The difference between them is that the ferroelectric field-effect transistor FeFET has a ferroelectric layer structure at the gate, while the discharge transistor T does not have a ferroelectric layer structure at the gate. Since the relative relationship between the two will be concerned during the analysis, it can be assumed that these two transistors are fabricated using the same material. At the same time, the ratio of the channel width-to-length ratios of the two is denoted as the second ratio κ. 2 , that is: where, W D represents the channel width of the ferroelectric field-effect transistor FeFET, L D represents the channel length of the ferroelectric field-effect transistor FeFET, W M represents the channel width of the discharge transistor T, and L M represents the channel length of the discharge transistor T. It should be noted that the above assumption and the introduction of the second ratio κ 2 are only for facilitating the quantification of the relative relationship between the ferroelectric field-effect transistor FeFET and the discharge transistor T, and do not impose any constraints on the applicable range of the physical simulation model.

[0087] Figure 5 FIG. shows a schematic diagram of the static L-K curve analysis of the physical simulation model according to an embodiment of the present disclosure. As Figure 5 shown, the ferroelectric neuron oscillation can be analyzed using the static L-K equation, which satisfies:

[0088] V FE = t FE (αP + βP 3 ) (7)

[0089] where, V FE represents the ferroelectric layer voltage of the ferroelectric field-effect transistor FeFET, t FE represents the ferroelectric layer thickness of the ferroelectric field-effect transistor FeFET, P represents the polarization intensity of the ferroelectric layer of the ferroelectric field-effect transistor FeFET, and α, β represent the Landau coefficients.

[0090] Combining the charge conservation constraint condition shown in formula (4), the expression of the surface charge density Q FE of the ferroelectric layer shown in formula (2), and the representation of the inner gate charge surface density Q MOS shown in formula (3), the relationship between the polarization intensity P of the ferroelectric layer and the ferroelectric layer voltage V FE and the voltages of each terminal of the ferroelectric field-effect transistor FeFET can be obtained.

[0091] In this way, the specific expression form F(·) of the polarization intensity P of the ferroelectric layer can depend on the inner gate charge surface density Q MOSThe representation method can be, for example, experimental data or the calculation by combining the voltages of each terminal of the transistor. Here, it is denoted as:

[0092] P = F(κ 1 , V FE , V s , V GF , V DD )(8)

[0093] Wherein, P represents the polarization intensity of the ferroelectric layer of the ferroelectric field-effect transistor FeFET, κ 1 represents the first ratio of the ferroelectric layer capacitance area S FE of the ferroelectric field-effect transistor FeFET and the gate capacitance area S MOS of the transistor, that is: κ 1 = S FE / S MOS , V FE represents the ferroelectric layer voltage, V s represents the source voltage of the ferroelectric field-effect transistor FeFET, that is, the output voltage of the ferroelectric neuron circuit, V GF represents the gate voltage of the ferroelectric field-effect transistor FeFET, V DD represents the bias voltage, that is, the drain voltage of the ferroelectric field-effect transistor FeFET.

[0094] Therefore, according to formula (8), the relationship curve of P-V FE can be plotted. Here, for the convenience of expression, it can be represented as a straight line in Figure 5 . It should be understood that this is only for the convenience of expression, and the actual situation may depend on the specific parameters of the device, which does not affect the next analysis.

[0095] By analyzing the dynamic characteristics of the physical simulation model of the ferroelectric neuron circuit, it can be obtained that: when the output voltage V s of the ferroelectric neuron circuit reaches the oscillation peak value V smax , the polarization intensity P of the ferroelectric layer of the ferroelectric field-effect transistor FeFET suddenly changes to a minimum value, that is, corresponding to Figure 5 changing from point B to point C; when the output voltage V s of the ferroelectric neuron circuit reaches the oscillation valley value V smin , the polarization intensity P of the ferroelectric layer of the ferroelectric field-effect transistor FeFET suddenly changes to a maximum value, that is, corresponding to Figure 5 changing from point D to point A; therefore, the ferroelectric neuron system will repeat through the ABCD cycle. Curve AD and curve BC respectively satisfy being tangent to the static L-K curve at point D and point B.

[0096] In a possible implementation, in step S12, a design method (or design process) that can guide the specific design of the experiment is developed according to the physical simulation model, the working state of the ferroelectric neuron circuit is predicted, and the specific design of the experiment is implemented according to the design method. Among them, step S12 may include: determining whether the bias voltage V of the ferroelectric neuron circuit DD is within a preset voltage range; when the bias voltage V DD is within the preset voltage range, determining whether the first ratio κ of the ferroelectric layer capacitance area S FE and the transistor gate capacitance area S MOS of the ferroelectric field effect transistor FeFET in the ferroelectric neuron circuit 1 is within a first preset range; otherwise, reset the bias voltage V DD , until the bias voltage V of the ferroelectric neuron circuit DD is within the preset voltage range, and then determine whether the first ratio κ 1 is within the first preset range.

[0097] When the first ratio κ 1 is within the first preset range, determine whether the second ratio between the channel width-to-length ratio of the ferroelectric field effect transistor FeFET and the channel width-to-length ratio of the discharge transistor T is within a second preset range; otherwise, reset the first ratio κ 1 , until the first ratio κ 1 is within the first preset range, and then determine whether the second ratio κ 2 is within the second preset range. Among them, W D represents the channel width of the ferroelectric field effect transistor FeFET, L D represents the channel length of the ferroelectric field effect transistor FeFET, W M represents the channel width of the discharge transistor T, and L M represents the channel length of the discharge transistor T;

[0098] When the second ratio κ 2 is within the second preset range, predict the working state of the ferroelectric neuron circuit as: the output signal V of the ferroelectric neuron circuit s is an oscillation signal; otherwise, reset the second ratio κ 2 , until the second ratio κ 2 is within the second preset range to enable the ferroelectric neuron circuit to output an oscillation signal.

[0099] It should be understood that in practical applications, the voltage preset range, the first preset range, and the second preset range can be determined according to factors such as the working principle of the ferroelectric neuron circuit, the electrical characteristics of components, the material parameters of components, and the actual application scenario. The embodiments of the present disclosure do not make specific limitations on this.

[0100] In this way, a design rule corresponding to the physical simulation model of the ferroelectric neuron circuit is provided, which can clearly guide the implementation of experiments, improve the physical reliability of the ferroelectric neuron model, and significantly reduce the trial-and-error cost of experimentally manufacturing the system. It guides the design, testing, and application of the ferroelectric neuron circuit, helps engineers better understand the performance and characteristics of the ferroelectric neuron circuit, provides a physical basis for the further development of the ferroelectric neuron circuit in electronic design automation software (EDA), and thus enables more accurate debugging and optimization.

[0101] Figure 6 A schematic diagram showing the design flow of the ferroelectric neuron circuit according to an embodiment of the present disclosure is as follows Figure 6 As shown, when the material parameters related to each device in the ferroelectric neuron circuit and the device parameters such as the thickness of the ferroelectric layer and the oxide layer are determined, the user can input relevant device material parameters, such as including the Landau coefficients α, β, the dielectric constant ε, and the ferroelectric layer thickness t FE , the oxide layer thickness t of etc. The circuit simulation method of the embodiments of the present disclosure can determine the design rules of voltage, the first ratio, and the second ratio according to the relevant device material parameters that the user can input. For example, according to the relevant device material parameters that the user can input, the program code for calculating the voltage preset range, the first preset range, and the second preset range can be called to determine the voltage preset range, the first preset range, and the second preset range; or for another example, the voltage preset range, the first preset range, and the second preset range can also be determined by looking up a table. The embodiments of the present disclosure do not make limitations on this.

[0102] In this way, a suitable bias voltage V DD can be set according to the given parameters, and then a suitable first ratio κ 1 can be set according to the configuration voltage and the device material related parameters, and further, a suitable second ratio κ 1 can be set according to the configuration voltage, the device material related parameters, and the second ratio κ 2 .

[0103] In a possible implementation manner, the embodiments of the present disclosure provide a voltage design rule for the ferroelectric neuron circuit. A suitable voltage condition needs to provide sufficient conditions for the ferroelectric layer to flip, that is, the output voltage V s of the ferroelectric neuron circuit needs to be greater than the gate voltage V of the ferroelectric field effect transistor FeFET at certain momentsGF ; Meanwhile, throughout the process, the output voltage V of the ferroelectric neuron circuit S obviously satisfies the bias voltage V DD > V s , so it can be deduced that at certain moments V s > V GF 's sufficient condition:

[0104] V DD > V GF (9)

[0105] wherein, V DD represents the bias voltage, that is, the drain voltage of the ferroelectric field-effect transistor FeFET, and V GF represents the gate voltage of the ferroelectric field-effect transistor FeFET, which can be used as the lower limit of the voltage preset range.

[0106] For formula (8), the polarization intensity P of the ferroelectric layer of the ferroelectric field-effect transistor FeFET can be taken as 0, and the relationship f s between the output voltage V of the ferroelectric neuron circuit, the first ratio κ 1 , the ferroelectric layer voltage V FE , the gate voltage V GF of the ferroelectric field-effect transistor FeFET, and the bias voltage V DD can be obtained. Denote it as V 1 = f s (κ 1 , V 1 , V FE , V GF , V DD ), where κ 1 represents the first ratio of the ferroelectric layer capacitance area S FE of the ferroelectric field-effect transistor FeFET and the transistor gate capacitance area S MOS , that is: κ 1 = S FE / S MOS , V FE represents the ferroelectric layer voltage, V GF represents the gate voltage of the ferroelectric field-effect transistor FeFET, V DD represents the bias voltage, that is, the drain voltage of the ferroelectric field-effect transistor FeFET. Meanwhile, throughout the process, the output voltage V of the ferroelectric neuron circuit S obviously satisfies V S > V GND , and V GND represents the ground voltage, that is, it satisfies:

[0107] f 1 (κ 1 , VFE , V GF , V DD ) > 0 (10)

[0108] The sufficient conditions for Equation (10) can be obtained through scaling or other mathematical processes, and are denoted as:

[0109] f 2 (V GF , V DD ) > 0 (11)

[0110] In summary, Equations (9) and (11) give the conditions that the gate voltage V GF and the bias voltage V DD of the ferroelectric field-effect transistor FeFET need to satisfy. By solving Equations (9) and (11), the preset voltage range can be determined. At the same time, it should be noted that the gate voltage V GF of the ferroelectric field-effect transistor FeFET and the gate voltage V GM of the discharge transistor T should be relatively close, preferably not exceeding an order of magnitude.

[0111] In a possible implementation, the embodiment of this disclosure provides a design rule for a first ratio κ 1 , where the first ratio κ 1 = S FE / S MOS , S FE represents the capacitance area of the ferroelectric layer, and S MOS represents the capacitance area of the transistor gate.

[0112] A suitable first ratio κ 1 needs to match the capacitance of the ferroelectric layer and the capacitance of the transistor. Reflected in the P-V Figure 5 curve shown in FE , it means that the curve represented by Equation (8) can be tangent to the static L-K curve. Combining Equations (7) and (8) gives:

[0113]

[0114] where κ 1 represents the first ratio of the capacitance area S FE of the ferroelectric layer and the capacitance area S MOS of the transistor gate, that is: κ 1 = S FE / S MOS , V FE represents the ferroelectric layer voltage, V s represents the source voltage of the ferroelectric field-effect transistor FeFET, that is, the output voltage of the ferroelectric neuron circuit, t FErepresents the thickness of the ferroelectric layer, P represents the polarization intensity of the ferroelectric layer of the ferroelectric field effect transistor FeFET, α and β represent the Landau coefficients, and F(·) represents the ratio of the polarization intensity P to the first value κ 1 , ferroelectric layer voltage V FE , output voltage V s The mapping relationship.

[0115] It should be understood that in order to highlight the relationship between the variables contained in the expression, and because formula (8) F(κ 1 ,V FE ,V s ,V GF ,V DD ) The gate voltage V of the ferroelectric field effect transistor FeFET GF and bias voltage V DD is a fixed value, so it is ignored in the expression here. Combining formula (7) and formula (8), Figure 5 Points B and D satisfy the tangency relationship, that is:

[0116]

[0117] Among them, κ 1 represents the ferroelectric layer capacitance area S FE and transistor gate capacitance area S MOS The first ratio of κ is: 1 =S FE / S MOS , V FE represents the ferroelectric layer voltage, V s represents the source voltage of the ferroelectric field effect transistor FeFET, that is, the output voltage of the ferroelectric neuron circuit, t FE represents the thickness of the ferroelectric layer, P represents the polarization intensity of the ferroelectric layer of the ferroelectric field effect transistor FeFET, α and β represent the Landau coefficients, and F(·) represents the ratio of the polarization intensity P to the first value κ 1 , ferroelectric layer voltage V FE , output voltage V s The mapping relationship.

[0118] At the same time Figure 5 The output voltage V of the ferroelectric neuron circuit is s Reaching the peak voltage V smax Corresponding to the mutation from point B to point C, the voltage of the ferroelectric layer before the mutation is V FE1 ; Similarly, the output voltage V s Reaching the valley voltage V smin Corresponding to the mutation from point D to point A, the voltage of the ferroelectric layer before the mutation is V FE2 Combining formula (7), formula (8) and formula (13), we can get V smax, V FE1 , V smin , V FE2 The expressions of, here are denoted as respectively:

[0119]

[0120] Among them, κ 1 represents the first ratio of the ferroelectric layer capacitance area S FE and the transistor gate capacitance area S MOS , that is: κ 1 = S FE / S MOS , V FE1 represents the ferroelectric layer voltage corresponding to the peak voltage V smax before mutation, V FE2 represents the ferroelectric layer voltage corresponding to the valley voltage V smin before mutation, g 1 (·) represents the mapping relationship between the ferroelectric layer voltage V smax corresponding to the peak voltage V FE1 before mutation and the first ratio κ 1 , g 2 (·) represents the mapping relationship between the ferroelectric layer voltage V smin corresponding to the valley voltage V FE2 before mutation and the first ratio κ 1 , g 3 (·) represents the mapping relationship between the peak voltage V smax and the first ratio κ 1 , g 1 (κ 1 ), g 4 (·) represents the mapping relationship between the valley voltage V smin and the first ratio κ 1 , g 2 (κ 1 ).

[0121] Since the output voltage V s of the ferroelectric neuron circuit is restricted within [V GND , V DD during the neuron oscillation, so V DD > V smax and V smin > 0:

[0122]

[0123] In summary, by combining formula (12) and formula (16), the appropriate range of the first ratio κ 1 can be given, that is, the first preset range.

[0124] In a possible implementation, an embodiment of the present disclosure provides a second ratio κ 2 design rules wherein, W D represents the channel width of the ferroelectric field-effect transistor FeFET, and L D represents the channel length of the ferroelectric field-effect transistor FeFET, W M represents the channel width of the discharge transistor T, and L M represents the channel length of the discharge transistor T.

[0125] The appropriate second ratio κ 2 needs to make the output voltage V of the ferroelectric neuron circuit s during the oscillation process, be able to reach the threshold voltage at which the ferroelectric polarization flips, that is, the lower limit of the second ratio κ 2 is that when the output voltage V of the ferroelectric neuron circuit s rises to the equilibrium voltage, it can just make the ferroelectric polarization flip downward; the upper limit of the second ratio κ 2 is that when the output voltage V of the ferroelectric neuron circuit s rises to the equilibrium voltage, it can just make the ferroelectric polarization flip upward.

[0126] Next, the lower limit of the second ratio κ 2 can be solved, that is, the lower limit of the second preset range. When the second ratio κ 2 is relatively small, both the ferroelectric field-effect transistor FeFET and the discharge transistor T are in the saturation region. Denote the expression of the transistor saturation region current as I DS,SAT (V gs , V ds ), where V gs represents the internal gate-source voltage of the ferroelectric field-effect transistor FeFET, and V ds represents the drain-source voltage of the ferroelectric field-effect transistor FeFET. From the current balance, we can obtain:

[0127] κ 2 I DS,SAT (V GF - g 1 (κ 1 ) - V TH - V bal1 , V DD - V bal1 )

[0128] = I DS,SAT (V GM - V TH , V bal1 ) (17)

[0129] wherein, V THis the threshold voltage of a transistor (such as a ferroelectric field-effect transistor FeFET or a discharge transistor T), V GF represents the gate voltage of the ferroelectric field-effect transistor FeFET, V GM represents the gate voltage of the discharge transistor T, κ 1 represents the first ratio, κ 2 represents the second ratio, g 1 (·) represents the peak voltage V before mutation smax corresponding ferroelectric layer voltage V FE1 with the first ratio κ 1 mapping relationship, V DD represents the bias voltage, I DS,SAT represents the expression of the transistor saturation region current, V bal1 is the equilibrium voltage at this time. Solving the above equation gives the equilibrium voltage V bal1 , denoted as:

[0130] V bal1 = H 1 (κ 2 , g 1 (κ 1 ), V TH , V GF , V DD , V GM )(18)

[0131] where H 1 (·) represents the mapping relationship between the equilibrium voltage V bal1 and the second ratio κ 2 , the peak voltage V before mutation smax corresponding ferroelectric layer voltage g 1 (κ 1 ), the threshold voltage V TH , the gate voltage V of the ferroelectric field-effect transistor FeFET GF , the bias voltage V DD , the gate voltage V of the discharge transistor T GM .

[0132] Combining the meaning of the lower limit of the second ratio κ 2 , according to formula (18) and formula (15), the following formula can be obtained:

[0133] H 1 (κ 2 , g 1 (κ 1 ), V TH , V GF , V DD , V GM ) > g 3 (κ 1, g 1 (κ 1 )) (19)

[0134] Similarly, the second ratio κ can be solved as follows 2 The upper limit, that is, the upper limit of the second preset range. When the second ratio κ 2 is relatively large, the ferroelectric field effect transistor FeFET is in the subthreshold region, and the discharge transistor T is still in the saturation region. Denote the subthreshold region current expression of the transistor as I DS,SUB (V gs , V ds ). From the current balance, we can get

[0135] κ 2 I DS,SUB (V GF - g 2 (κ 1 ) - V TH - V bal2 , V DD - V bal2 )

[0136] = I DS,SAT (V GM - V TH , V bal2 ) (20)

[0137] Among them, V TH is the threshold voltage of the transistor (such as the ferroelectric field effect transistor FeFET or the discharge transistor T), V GF represents the gate voltage of the ferroelectric field effect transistor FeFET, V GM represents the gate voltage of the discharge transistor T, κ 1 represents the first ratio, κ 2 represents the second ratio, g 2 (·) represents the mapping relationship between the ferroelectric layer voltage V smin corresponding to the valley voltage V before mutation and the first ratio κ FE2 , V 1 represents the bias voltage, I DD represents the expression of the transistor saturation region current, and V DS,SAT is the equilibrium voltage at this time bal2

[0138] The equilibrium voltage V at this time can be solved and denoted as bal2 :

[0139] V bal2 = H 2 (κ 2 , g 2 (κ 1 ), V TH ​, V GF , V DD , V GM ), (21)

[0140] Among them, H 2 (·) represents the balanced voltage V bal2 and the second ratio κ 2 , the valley voltage V before mutation smin corresponding ferroelectric layer voltage g 2 (κ 1 ), the threshold voltage V TH , the gate voltage V of the ferroelectric field effect transistor FeFET GF , the bias voltage V DD , the gate voltage V of the discharge transistor T GM the mapping relationship between them.

[0141] Combined with the meaning of the upper limit of the second ratio κ 2 , it can be obtained that:

[0142] H 2 (κ 2 , g 2 (κ 1 ), V TH , V GF , V DD , V GM ), V 4 (κ 1 , g 2 (κ 1 )) (22)

[0143] In summary, formulas (19) and (22) can give the appropriate range of the second ratio κ 2 , that is, the second preset range.

[0144] To better understand the technical solution of the present disclosure, it will be further described below in conjunction with an embodiment. Referring to the above, the gate charge density Q MOS inside the ferroelectric field effect transistor FeFET can be obtained by calculation or measured by experiment, and there is a certain difference between the two. The gate charge density Q MOS inside the ferroelectric field effect transistor FeFET obtained by calculation is generally the case of an ideal transistor, while the gate charge density Q MOS inside the ferroelectric field effect transistor FeFET measured by experiment often includes the influence of non-rational factors such as device defects. No matter which method is used, the gate charge density Q MOS inside the ferroelectric field effect transistor FeFET can be expressed as:

[0145] Q MOS = C gs(V g -V s )+C gd (V g -V d ) (23)

[0146] where C MOS = C gs + C gd , C MOS represents the total capacitance per unit area of the ferroelectric field-effect transistor FeFET, C gs represents the gate-source capacitance per unit area of the ferroelectric field-effect transistor FeFET, C gd represents the gate-drain capacitance per unit area of the ferroelectric field-effect transistor FeFET, V g represents the internal gate voltage of the ferroelectric field-effect transistor FeFET, V d represents the drain voltage of the ferroelectric field-effect transistor FeFET, V s represents the source voltage of the ferroelectric field-effect transistor FeFET. Using the design process introduced above, Equation (8) can be written as:

[0147]

[0148] where P represents the polarization intensity of the ferroelectric layer of the ferroelectric field-effect transistor FeFET, C MOS represents the total capacitance per unit area of the ferroelectric field-effect transistor FeFET, κ 1 represents the first ratio of the ferroelectric layer capacitance area S FE and the transistor gate capacitance area S MOS of the ferroelectric field-effect transistor FeFET, that is: κ 1 = S FE / S MOS , ε 0 represents the vacuum permittivity, ε r represents the relative permittivity, t FE represents the ferroelectric layer thickness, V FE represents the ferroelectric layer voltage, V s represents the source voltage of the ferroelectric field-effect transistor FeFET, which is also the output voltage of the ferroelectric neuron circuit, V GF represents the gate voltage of the ferroelectric field-effect transistor FeFET, V DD represents the bias voltage, which is also the drain voltage of the ferroelectric field-effect transistor FeFET, C gs represents the gate-source capacitance per unit area of the ferroelectric field-effect transistor FeFET, C gd represents the gate-drain capacitance per unit area of the ferroelectric field-effect transistor FeFET.

[0149] Gate charge density Q in ferroelectric field effect transistor FeFET MOS Different representation methods are reflected in the gate-source capacitance C per unit area of the ferroelectric field effect transistor FeFET gs , gate-drain capacitance C gd There are different mapping relationships. Here, for the convenience of giving an explicit expression to clearly illustrate the specific implementation of the design process, the gate-source capacitance C gs , gate-drain capacitance C gd can be taken as a constant. Therefore, formula (24) appears as a straight line in the P-V FE curve, that is, as shown in Figure 5 .

[0150] In a possible implementation, when the gate-source capacitance C gs and the gate-drain capacitance C gd per unit area of the ferroelectric field effect transistor FeFET are constants, the upper limit of the preset voltage range is the product of the third ratio of the total capacitance C MOS per unit area of the ferroelectric field effect transistor FeFET to the gate-drain capacitance C gd and the gate voltage V of the ferroelectric field effect transistor FeFET, and the lower limit of the preset voltage range is the gate voltage V GF of the ferroelectric field effect transistor FeFET. GF .

[0151] For example, formula (10) can be written as: As a sufficient condition, formula (11) can be written as: Combined with formula (9), its voltage design rule, that is, the preset voltage range of the bias voltage V DD can be written as:

[0152]

[0153] Among them, C MOS represents the total capacitance per unit area of the ferroelectric field effect transistor FeFET, C gd represents the gate-drain capacitance per unit area of the ferroelectric field effect transistor FeFET, C gs represents the gate-source capacitance per unit area of the ferroelectric field effect transistor FeFET, V GF represents the gate voltage of the ferroelectric field effect transistor FeFET, V DD represents the bias voltage, that is, the drain voltage of the ferroelectric field effect transistor FeFET, κ 1 represents the first ratio of the ferroelectric layer capacitance area S FE of the ferroelectric field effect transistor FeFET to the transistor gate capacitance area S MOS ε0 represents the vacuum dielectric constant, ε r represents the relative dielectric constant, t FE represents the thickness of the ferroelectric layer.

[0154] In a possible implementation, the gate-source capacitance C per unit area of ​​the ferroelectric field effect transistor FeFET is gs and gate-drain capacitance C gd When the upper limit of the first preset range is a constant, the total capacitance C per unit area of ​​the ferroelectric field effect transistor FeFET is calculated based on the total capacitance C per unit area of ​​the ferroelectric field effect transistor FeFET. MOS , ferroelectric layer thickness t FE The lower limit of the first preset range is determined based on the total capacitance C per unit area of ​​the ferroelectric field effect transistor FeFET. MOS , gate-source capacitance C gs , gate-drain capacitance C gd , the thickness of the ferroelectric layer t FE , the gate voltage V of the ferroelectric field effect transistor FeFET GF , the bias voltage V DD Sure.

[0155] For example, we can differentiate formula (24), and since the derivative α of the Landau coefficient α ′ <0, the derivative of the Landau coefficient β ′ >0, formula (12) can be written as: Among them, C MOS represents the total capacitance per unit area of ​​the ferroelectric field effect transistor FeFET, κ 1 represents the ferroelectric layer capacitance area S FE and transistor gate capacitance area S MOS The first ratio of κ is: 1 =S FE / S MOS , t FE represents the thickness of the ferroelectric layer, α ′ represents the derivative of the Landau coefficient α, ε 0 represents the vacuum dielectric constant, ε r represents the relative dielectric constant, t FE represents the thickness of the ferroelectric layer.

[0156] Combined with the size relationship of the selected parameters (|α ′ |ε r ε 0 -1<0), formula (12) can be further written as:

[0157]

[0158] Among them, C MOSrepresents the total capacitance per unit area of the ferroelectric field-effect transistor FeFET, κ 1 represents the area S of the ferroelectric layer capacitance FE and the area S of the transistor gate capacitance MOS of the first ratio, that is: κ 1 = S FE / S MOS , t FE represents the thickness of the ferroelectric layer, α represents the Landau coefficient, ε 0 represents the vacuum permittivity, ε r represents the relative permittivity, t FE represents the thickness of the ferroelectric layer.

[0159] Equation (14) can be written as:

[0160]

[0161] where, V FE1 represents the ferroelectric layer voltage corresponding to the peak voltage V smax before the mutation, C MOS represents the total capacitance per unit area of the ferroelectric field-effect transistor FeFET, κ 1 represents the area S of the ferroelectric layer capacitance FE and the area S of the transistor gate capacitance MOS of the first ratio, that is: κ 1 = S FE / S MOS , t FE represents the thickness of the ferroelectric layer, α, β represent the Landau coefficients, ε 0 represents the vacuum permittivity, ε r represents the relative permittivity, t FE represents the thickness of the ferroelectric layer.

[0162] Equation (15) can be written as:

[0163]

[0164] where, V smax(smin) represents the peak voltage V smax or the valley voltage V smin , C MOS represents the total capacitance per unit area of the ferroelectric field-effect transistor FeFET, C gd represents the gate-drain capacitance per unit area of the ferroelectric field-effect transistor FeFET, C gs represents the gate-source capacitance per unit area of the ferroelectric field-effect transistor FeFET, V GF represents the gate voltage of the ferroelectric field-effect transistor FeFET, V DD represents the bias voltage, κ 1 represents the area S of the ferroelectric layer capacitanceFE and the first ratio of the ferroelectric layer capacitance area S MOS to the transistor gate capacitance area S, i.e., κ 1 = S FE / S MOS , where t FE represents the ferroelectric layer thickness, α and β represent Landau coefficients, and ε 0 represents the vacuum permittivity, and ε r represents the relative permittivity, and t FE represents the ferroelectric layer thickness.

[0165] Substituting formula (28) into formula (16), we can solve for:

[0166] κ 1 > (1 - |α|ε) -1 [|α|c + (-v + w) 1 / 3 + (-v - w) 1 / 3 (29)

[0167] where κ 1 represents the first ratio of the ferroelectric layer capacitance area S FE to the transistor gate capacitance area S, c = C MOS t MOS , v = bc / 2(1 - |α|ε), FE , u = bε / 3(1 - |α|ε), , C C MOS represents the total capacitance per unit area of the ferroelectric field effect transistor FeFET, C gd represents the gate-drain capacitance per unit area of the ferroelectric field effect transistor FeFET, C gs represents the gate-source capacitance per unit area of the ferroelectric field effect transistor FeFET, V GF represents the gate voltage of the ferroelectric field effect transistor FeFET, V DD represents the bias voltage, ε represents the permittivity, α and β represent Landau coefficients, and t FE represents the ferroelectric layer thickness.

[0168] Formulas (26) and (29) give the design rules for the first ratio κ 1 , that is, the first preset range. Among them, formula (26) is the upper limit of the first preset range, and formula (29) is the lower limit of the first preset range.

[0169] In a possible implementation, when the gate-source capacitance C gs and the gate-drain capacitance C gd per unit area of the ferroelectric field effect transistor FeFET are constants, the upper limit of the second preset range is determined according to the oscillation valley voltage V smin, the threshold voltage V of the transistor TH , the bias voltage V DD , the gate voltage V of the discharge transistor T GM , the gate voltage V of the ferroelectric field-effect transistor FeFET GF , the ferroelectric layer voltage V FE is determined. The lower limit of the second preset range is based on the gate voltage V of the discharge transistor T GM , the gate voltage V of the ferroelectric field-effect transistor FeFET GF , the threshold voltage V of the transistor TH , the oscillation peak voltage V smax is determined.

[0170] For example, the saturation region current expression I of the transistor DS,SAT (V gs , V ds ) and the subthreshold region current expression I DS,SUB (V gs , V ds ) are respectively taken as:

[0171]

[0172] Among them, V gs represents the internal gate-source voltage of the ferroelectric field-effect transistor FeFET, V ds represents the drain-source voltage of the ferroelectric field-effect transistor FeFET, V TH represents the threshold voltage of the transistor (including the ferroelectric field-effect transistor FeFET or the discharge transistor T), C ox represents the gate oxide capacitance of the ferroelectric field-effect transistor FeFET, that is, the capacitance generated by the oxide layer formed under the gate, μ n represents the magnetic permeability of the transistor, W represents the channel width of the transistor, L represents the length of the transistor, T represents the temperature, N c represents the equivalent channel state density of the transistor, q represents the electric charge of an electron, and K represents the Boltzmann constant.

[0173] Substituting formula (30) and formula (31) into formula (17)-(20), the lower limit of the second ratio κ 2 can be solved:

[0174]

[0175] Among them, V FE1 represents the ferroelectric layer voltage corresponding to the peak voltage V smax before mutation, V TH represents the threshold voltage of the transistor (including the ferroelectric field-effect transistor FeFET or the discharge transistor T), V GFrepresents the gate voltage of the ferroelectric field-effect transistor FeFET, V GM represents the gate voltage of the discharge transistor T.

[0176] Substituting Equation (30) and Equation (31) into Equation (21)-(22), the second ratio κ can be solved 2 Upper limit:

[0177]

[0178] where V FE2 represents the valley voltage V before mutation smin corresponding ferroelectric layer voltage, V TH represents the threshold voltage of the transistor (including the ferroelectric field-effect transistor FeFET or the discharge transistor T), V GF represents the gate voltage of the ferroelectric field-effect transistor FeFET, V GM represents the gate voltage of the discharge transistor T, V DD represents the bias voltage, C ox represents the gate oxide capacitance of the ferroelectric field-effect transistor FeFET, that is, the capacitance generated by the oxide layer formed under the gate, e represents the elementary charge, usually taken as 1.6×10 -19 Coulomb, μ n represents the permeability of the transistor, W represents the channel width of the transistor, L represents the length of the transistor, T represents the temperature, N c represents the equivalent channel state density of the transistor, q represents the charge of an electron, and K represents the Boltzmann constant.

[0179] Equation (32) and Equation (33) give the design rules for the second ratio κ 2 , that is, the second preset range, which contains V smax(smin) and V FE1(FE2) See Equation (27) and Equation (28).

[0180] Two approximations are made in the above process, that is, the capacitance of the transistor is a constant value, and a piecewise current model is adopted. Comparing the conditions given by the above formula with the results of numerical simulation, Figure 7 shows a schematic diagram of the ferroelectric neuron circuit effect according to an embodiment of the present disclosure, as Figure 7 shown, as Figure 7 shown, the amplitude of the neuron oscillation (that is, the output voltage V s ) is plotted against the first ratio κ 1 , the second ratio κ 2 . The corresponding amplitude for non-oscillation is 0. It can be seen that the results of the expression are in good agreement with the results of numerical simulation, proving the reliability and feasibility of this work.

[0181] In summary, the circuit simulation method of the present disclosure embodiments can combine the physical characteristics of transistors and the L-K equation to determine the variation information of the ferroelectric polarization in the ferroelectric neuron circuit with respect to the applied voltage of the ferroelectric layer according to the device parameters and voltage conditions, and predict the working states of the ferroelectric neuron circuit under different parameters. Since this method starts from the perspective of static L-K curve analysis, it can combine various physical quantities related to the working mechanism of the ferroelectric neuron circuit (such as ferroelectric polarization reversal) with the dynamic characteristics of the device (or circuit), guiding the specific experimental implementation, which is beneficial to improving the physical reliability of the ferroelectric neuron model and significantly reducing the trial-and-error cost of experimentally manufacturing this system. At the same time, the parameter range judgment criterion therein can also provide a physical basis for the further development of future ferroelectric neuron circuits in electronic design automation software (EDA). It can be seen that the circuit simulation method of the present disclosure embodiments can, on the one hand, be applied to circuit simulation to simulate the experimental phenomena of the ferroelectric neuron circuit, and on the other hand, provide design guidance for the implementation of the ferroelectric neuron circuit.

[0182] In a possible implementation manner, the ferroelectric neuron circuit simulation model system is constructed by using the method described in steps S11 to S12. The ferroelectric neuron circuit simulation system simulates the working state of the ferroelectric neuron circuit. The ferroelectric neuron circuit simulation system includes the ferroelectric field-effect transistor simulation element, the discharge transistor simulation element, and the load capacitance simulation element. The gate of the discharge transistor simulation element receives the first input pulse signal, the gate of the ferroelectric field-effect transistor simulation element receives the second input pulse signal, the drain of the ferroelectric field-effect transistor simulation element receives the bias voltage, and the drain of the discharge transistor simulation element, the source of the ferroelectric field-effect transistor simulation element, and the first end of the load capacitance simulation element are connected to generate an output signal.

[0183] Figure 8 The block diagram of the circuit simulation device according to the embodiments of the present disclosure is shown, as Figure 8 shown, the device includes:

[0184] A building module 81, configured to establish a physical simulation model of the ferroelectric neuron circuit according to the correspondence between the polarization intensity of the ferroelectric layer in the ferroelectric field-effect transistor and the ferroelectric layer voltage, the surface charge density of the ferroelectric layer, and the source voltage of the ferroelectric field-effect transistor;

[0185] A prediction module 82, configured to predict the working state of the ferroelectric neuron circuit according to the physical simulation model; in an example, a design method (or design process) that can guide the specific design of the experiment can be developed according to the physical simulation model to predict the working state of the ferroelectric neuron circuit, and the specific design implementation of the experiment can be guided according to the design method.

[0186] Among them, the ferroelectric neuron circuit is a neuron circuit composed of ferroelectric field-effect transistors.

[0187] In a possible implementation manner, the ferroelectric neuron circuit includes the ferroelectric field-effect transistor, a discharge transistor, and a load capacitor. The gate of the discharge transistor receives a first input pulse signal, the gate of the ferroelectric field-effect transistor receives a second input pulse signal, the drain of the ferroelectric field-effect transistor receives a bias voltage, and the drain of the discharge transistor, the source of the ferroelectric field-effect transistor, and the first end of the load capacitor are connected to generate an output signal. Among them, the drain of the discharge transistor is both the source of the ferroelectric field-effect transistor and the first end of the load capacitor, and the drain of the discharge transistor is used to generate the output signal.

[0188] In a possible implementation manner, the surface charge density of the ferroelectric layer is determined according to the polarization intensity of the ferroelectric layer in the ferroelectric field-effect transistor, the voltage of the ferroelectric layer, and the thickness of the ferroelectric layer. The voltage of the ferroelectric layer is determined according to the external gate-source voltage, the internal gate-source voltage, and the surface charge density of the internal gate in the ferroelectric field-effect transistor. The surface charge density of the internal gate is determined according to the internal gate-source voltage, the internal gate-drain voltage, and the transistor device parameters in the ferroelectric field-effect transistor. And the ratio of the surface charge density of the ferroelectric layer to the surface charge density of the internal gate is equal to the first ratio of the ferroelectric layer capacitance area to the transistor gate capacitance area in the ferroelectric field-effect transistor. The source voltage of the ferroelectric field-effect transistor is determined according to the charging current of the ferroelectric field-effect transistor and the discharging current of the discharge transistor.

[0189] In a possible implementation manner, the prediction module 82 is configured to: determine whether the bias voltage of the ferroelectric neuron circuit is within a preset voltage range; when the bias voltage is within the preset voltage range, determine whether the first ratio of the ferroelectric layer capacitance area to the transistor gate capacitance area in the ferroelectric field-effect transistor of the ferroelectric neuron circuit is within a first preset range; when the first ratio is within the first preset range, determine whether the second ratio between the channel width-length ratio of the ferroelectric field-effect transistor and the channel width-length ratio of the discharge transistor is within a second preset range; when the second ratio is within the second preset range, predict the working state of the ferroelectric neuron circuit as: the output signal of the ferroelectric neuron circuit is an oscillation signal.

[0190] In a possible implementation, when the gate-source capacitance and the gate-drain capacitance per unit area of the ferroelectric field-effect transistor are constants, the upper limit of the preset voltage range is the product of the third ratio of the total capacitance per unit area of the ferroelectric field-effect transistor to the gate-drain capacitance and the gate voltage of the ferroelectric field-effect transistor, and the lower limit of the preset voltage range is the gate voltage of the ferroelectric field-effect transistor; the upper limit of the first preset range is determined according to the total capacitance per unit area of the ferroelectric field-effect transistor and the ferroelectric layer thickness, and the lower limit of the first preset range is determined according to the total capacitance per unit area of the ferroelectric field-effect transistor, the gate-source capacitance, the gate-drain capacitance, the ferroelectric layer thickness, the gate voltage of the ferroelectric field-effect transistor, and the bias voltage; the upper limit of the second preset range is determined according to the oscillation valley voltage, the threshold voltage of the transistor, the bias voltage, the gate voltage of the discharge transistor, the gate voltage of the ferroelectric field-effect transistor, and the ferroelectric layer voltage, and the lower limit of the second preset range is determined according to the gate voltage of the discharge transistor, the gate voltage of the ferroelectric field-effect transistor, the threshold voltage of the transistor, and the oscillation peak voltage.

[0191] In a possible implementation, the ferroelectric field-effect transistor is a single-domain ferroelectric field-effect transistor.

[0192] In some embodiments, the functions or modules included in the device provided in the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0193] The embodiments of the present disclosure also propose a computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above methods are implemented. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0194] The embodiments of the present disclosure also propose an electronic device, including: a processor; a memory for storing instructions executable by the processor; wherein, the processor is configured to implement the above methods when executing the instructions stored in the memory.

[0195] The embodiments of the present disclosure also provide a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in the processor of an electronic device, the processor in the electronic device executes the above methods.

[0196] Figure 9 is a block diagram of an electronic device shown according to an exemplary embodiment. For example, the electronic device 1900 can be provided as a server or a terminal device. Refer toFigure 9 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by a memory 1932 for storing instructions executable by the processing component 1922, such as application programs. The application programs stored in the memory 1932 may include one or more modules each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0197] The electronic device 1900 may also include a power component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958 (I / O interface). The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server TM , Mac OS X TM , Unix TM , Linux TM , FreeBSD TM or the like.

[0198] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as the memory 1932 including computer program instructions, and the above computer program instructions can be executed by the processing component 1922 of the electronic device 1900 to complete the above method.

[0199] The present disclosure may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium having thereon computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0200] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, -- but is not limited to -- an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device such as a punched card or raised structures in grooves having instructions stored thereon, and any suitable combination of the foregoing. The computer-readable storage medium used herein is not construed as being a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0201] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to respective computing / processing devices, or can be downloaded to an external computer or an external storage device through a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include a copper transmission cable, an optical fiber transmission, a wireless transmission, a router, a firewall, a switch, a gateway computer, and / or an edge server. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing / processing device.

[0202] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as the "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or, alternatively, may be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, by using the state information of the computer-readable program instructions to customize an electronic circuit, such as a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer-readable program instructions to implement various aspects of the present disclosure.

[0203] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0204] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that the instructions, when executed by the processor of the computer or other programmable data processing apparatus, create a means for implementing the functions / acts specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises a manufacture including instructions for implementing various aspects of the functions / acts specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0205] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, causing a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process such that the instructions executed on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in one or more boxes of the flowchart and / or block diagram.

[0206] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of code, or a portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two consecutive blocks may in fact be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified function or act, or by a combination of dedicated hardware and computer instructions.

[0207] The embodiments of the present disclosure have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the market, or to enable other ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A circuit simulation method, characterized in that: The method comprises: A physical simulation model of a ferroelectric neuron circuit is established according to the corresponding relationship between the polarization intensity of the ferroelectric layer and the voltage of the ferroelectric layer in the ferroelectric field effect transistor, the surface charge density of the ferroelectric layer, and the source voltage of the ferroelectric field effect transistor; The working state of the ferroelectric neuron circuit is predicted according to the physical simulation model, wherein the ferroelectric neuron circuit is a neuron circuit based on ferroelectric field effect transistors.

2. The method according to claim 1, characterized in that The ferroelectric neuron circuit includes the ferroelectric field effect transistor, a discharge transistor, and a load capacitor. The gate of the discharge transistor receives a first input pulse signal, the gate of the ferroelectric field effect transistor receives a second input pulse signal, the drain of the ferroelectric field effect transistor receives a bias voltage, the drain of the discharge transistor is the source of the ferroelectric field effect transistor and is also the first end of the load capacitor. The drain of the discharge transistor is used to generate an output signal.

3. The method according to claim 2, characterized in that The surface charge density of the ferroelectric layer is determined based on the polarization strength of the ferroelectric layer, the ferroelectric layer voltage, and the thickness of the ferroelectric layer in the ferroelectric field effect transistor; the ferroelectric layer voltage is determined based on the external gate-source voltage, the internal gate-source voltage, and the internal gate charge surface density in the ferroelectric field effect transistor; the internal gate charge surface density is determined based on the internal gate-source voltage, the internal gate-drain voltage, and transistor device parameters in the ferroelectric field effect transistor; and the ratio of the surface charge density of the ferroelectric layer to the internal gate charge surface density is equal to the first ratio of the ferroelectric layer capacitance area and the transistor gate capacitance area in the ferroelectric field effect transistor; the source voltage of the ferroelectric field effect transistor is determined based on the charging current of the ferroelectric field effect transistor and the discharge current of the discharge transistor.

4. The method according to claim 2, characterized in that: Predicting the working state of the ferroelectric neuron circuit according to the physical simulation model includes: Determining whether the bias voltage of the ferroelectric neuron circuit is within a preset voltage range; When the bias voltage is within the preset voltage range, determining whether a first ratio of a ferroelectric layer capacitance area to a transistor gate capacitance area in the ferroelectric field effect transistor of the ferroelectric neuron circuit is within a first preset range; In the case where the first ratio is within the first preset range, determining whether a second ratio between the channel width-to-length ratio of the ferroelectric field effect transistor and the channel width-to-length ratio of the discharge transistor is within a second preset range; When the second ratio is within the second preset range, it is predicted that the working state of the ferroelectric neuron circuit is: the output signal of the ferroelectric neuron circuit is an oscillation signal.

5. The method according to claim 4, characterized in that When the gate-source capacitance and the gate-drain capacitance per unit area of ​​the ferroelectric field effect transistor are constants, The upper limit of the voltage preset range is the product of the third ratio of the total capacitance per unit area of ​​the ferroelectric field effect transistor to the gate-drain capacitance and the gate voltage of the ferroelectric field effect transistor, and the lower limit of the voltage preset range is the gate voltage of the ferroelectric field effect transistor; The upper limit of the first preset range is determined according to the total capacitance per unit area of ​​the ferroelectric field effect transistor and the thickness of the ferroelectric layer, and the lower limit of the first preset range is determined according to the total capacitance per unit area of ​​the ferroelectric field effect transistor, the gate-source capacitance, the gate-drain capacitance, the thickness of the ferroelectric layer, the gate voltage of the ferroelectric field effect transistor, and the bias voltage; The upper limit of the second preset range is determined based on the oscillation valley voltage, the threshold voltage of the transistor, the bias voltage, the gate voltage of the discharge transistor, the gate voltage of the ferroelectric field effect transistor, and the ferroelectric layer voltage; the lower limit of the second preset range is determined based on the gate voltage of the discharge transistor, the gate voltage of the ferroelectric field effect transistor, the threshold voltage of the transistor, and the oscillation peak voltage.

6. The method according to any one of claims 1 to 5, characterized in that The ferroelectric field effect transistor is a single-domain ferroelectric field effect transistor.

7. A ferroelectric neuron circuit simulation model system, characterized in that: The ferroelectric neuron circuit simulation system is constructed using the method described in any one of claims 1 to 6, and simulates the working state of the ferroelectric neuron circuit. The ferroelectric neuron circuit simulation system includes the ferroelectric field effect transistor simulation element, the discharge transistor simulation element, and the load capacitor simulation element.

8. A circuit simulation device, characterized in that: The device comprises: Establishing a module for establishing a physical simulation model of a ferroelectric neuron circuit according to the corresponding relationship between the polarization intensity of the ferroelectric layer and the voltage of the ferroelectric layer in the ferroelectric field effect transistor, the surface charge density of the ferroelectric layer, and the source voltage of the ferroelectric field effect transistor; A prediction module is used to predict the working state of the ferroelectric neuron circuit according to the physical simulation model, wherein the ferroelectric neuron circuit is a neuron circuit based on ferroelectric field effect transistors.

9. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to implement the method described in any one of claims 1 to 6 when executing the instructions stored in the memory.

10. A non-volatile computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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