Test method for accelerated evaluation of thermal cycle failure of silver sintering interconnection structure

Abstract

The invention provides a test method for evaluating thermal cycle failure of a silver sintering interconnection structure. The test method comprises the following steps: constructing a silver sintering acceleration function and designing acceleration parameters; setting up an acceleration test device; characterizing the sintered sample to be detected; carrying out an accelerated thermal shock experiment on the to-be-tested sintered sample; judging whether the to-be-tested sintered sample subjected to the accelerated thermal shock test is invalid, if so, performing the next step, and if not, returning to the previous step; and characterizing the failed sintering sample to be detected. The method and the device are simple and easy to implement, the number of thermal cycles is shortened on the basis that the thermal failure of the silver sintering interconnection product can be reflected, the thermal reliability of the product can be evaluated within one day, and the failure life of the product can be predicted.

Description

Technical Field

[0001] The present application relates to the technical field of material evaluation, and in particular to a test method and device for evaluating thermal cycle failure of a silver sintered interconnect structure. Background Art

[0002] With the increase in the number of electric vehicles in my country, SiC modules used in automotive electric drive systems have also ushered in a major strategic opportunity period. The integration and assembly density of power chips have been continuously improved accordingly, and the frequent start-stop and increasingly harsh working environment of electric vehicles have led to increasingly severe problems in chip junction temperature increase and safety and reliability. Therefore, higher requirements are placed on the heat dissipation capacity and high-temperature reliability of the interconnect layer, which is the key channel for interface heat dissipation in the packaging structure. Thanks to its excellent properties such as low sintering temperature (200-300°C), high interconnection strength, high operating temperature (theoretically up to 700°C), strong electrical conductivity and strong thermal conductivity, low-temperature sintered silver is gradually becoming a thermal interface material that can be widely used in the packaging of wide-bandgap semiconductor devices. Many well-known power device manufacturers around the world (such as Continental AG, etc.) have begun to gradually apply sintered silver interconnect technology to the production and manufacturing of new energy vehicle accessories.

[0003] The chip connection technology based on sintered silver paste requires a metal intermediate layer between the silver paste and the substrate to achieve a robust connection between them. For example, the direct bonded copper (DBC) substrate containing a Cu layer is one of the most widely used substrates in power electronics. However, since copper is very easy to oxidize at high temperatures, an oxide film is generated at the interface. The formed oxide film will hinder the atomic diffusion and the formation of metal bonds with interconnection materials such as sintered silver, reducing the connection strength. Therefore, in order to avoid oxidation of the substrate surface and improve the connection strength with the interconnection material, the substrate needs to be metal plated, such as Au, Ni, Ag, etc.

[0004] During the service life of power devices, the switching of current and the fluctuation of ambient temperature will cause the devices to be affected by alternating temperatures. The chip and substrate in the device have a large mismatch in thermal expansion coefficient (CTE) due to different materials. Sintered silver, as a connection material, will be subject to thermomechanical stress caused by CTE mismatch. When the stress exceeds the yield strength of the solder joint, permanent plastic deformation will occur inside the solder joint. As the strain accumulates, cracks inside the solder joint nucleate and grow, eventually causing the solder joint to fail.

[0005] In the process of research and development and design of electronic products, thermal cycling or thermal shock tests can be used for early potential fault screening, reliability evaluation, life assessment, etc. of electronic products, so as to improve the reliability of electronic products and ensure the service life of electronic products. However, at present, there is still a problem of long cycle in the thermal cycling test that causes product failure. For example, in the thermal cycling process at -50 to 250 °C with a high and low temperature holding time of 30 minutes each, partial crack generation will only occur after 500 cycles (Doi: 10.1016 / j.matdes.2022.111389, 10.1007 / s10854-021-06549-3). In engineering practice, it is always hoped that the thermal reliability of electronic products can be evaluated within a shorter time, such as 24 hours. Therefore, it is necessary to seek an accelerated thermal failure method that can quickly evaluate product failure. Summary of the Invention

[0006] In view of this, in view of the technical problem that the existing thermal cycling test has a long cycle and cannot meet the requirement of quickly evaluating product thermal failure in engineering practice, the present invention provides a test method that can quickly complete the evaluation of product thermal stress failure by building a simple test device.

[0007] To solve the above problems, the present application adopts the following technical solutions:

[0008] One of the purposes of the present application is to provide a test method for accelerating the evaluation of thermal cycling failure of silver sintered interconnect structures, including the following steps:

[0009] Construct an acceleration function and design acceleration parameters;

[0010] Build a test device and set the conditions of the test device according to the acceleration parameters;

[0011] Characterize the sintered sample to be tested;

[0012] Conduct an accelerated thermal shock experiment on the sintered sample to be tested according to the test device, and judge whether the sintered sample to be tested after the accelerated thermal shock experiment fails. If so, proceed to the next step; if not, conduct the accelerated thermal shock experiment again.

[0013] Characterize the failed sintered sample to be tested.

[0014] In some of the embodiments, in the step of constructing the acceleration function, the acceleration function is constructed based on the physics of failure, combining the Bayerer model and the Norris-Landzberg model, as follows:

[0015]

[0016]

[0017] Among them, AF is the acceleration factor; ΔT 加速 and ΔT 标准 are the junction temperature fluctuations under accelerated and standard temperature cycling conditions; N 加速 and N 标准 are the number of cycles per hour under accelerated and standard temperature cycling conditions; T jmax加速 and T jmax标准 are the maximum junction temperatures under accelerated and standard temperature cycling conditions, with the unit of K; T jmin加速 and T jmin标准 are the minimum junction temperatures under accelerated and standard temperature cycling conditions; m and n are constant coefficients, related to the type of silver sintered interconnect structure, and can be determined by the method of controlling variables. The value range of m is 3 to 5, and the value range of n is -1.8 to 0.8; the acceleration parameters include ΔT 加速 , T jmax加速 , N 加速 and T jmin加速 .

[0018] In some of the embodiments, the selection range of T jmax加速 is from 0 to 10 °C, and the temperature difference between T jmax加速 and T jmin加速 is not less than the junction temperature fluctuation ΔT j of the standard thermal cycle test, but does not exceed 50 °C of the junction temperature fluctuation of the standard thermal cycle test. N 加速 is not higher than 24 times, but not less than 6 times, and the residence time at the maximum or minimum junction temperature is not less than 1 min, and the conversion time does not exceed 15 s.

[0019] In some of the embodiments, the acceleration factor AF is not less than 5.

[0020] In some of the embodiments, in the step of building the test device, the test device includes a controllable hot stage, a cold stage and a low temperature constant temperature bath. The controllable hot stage serves as the hot end of the accelerated thermal shock experiment, and the cold stage serves as the cold end of the accelerated thermal shock experiment. The side wall of the cold stage is provided with inlets and outlets, and the inside of the side wall can be filled with circulating coolant, and the temperature of the circulating coolant is controlled by the low temperature constant temperature bath.

[0021] In some of the embodiments, the test device further includes a numerically controlled moving table and a robotic arm. The robotic arm is fixed on the numerically controlled moving table, and the robotic arm is moved by moving the numerically controlled moving table to realize the conversion of the sintered sample to be tested between the controllable hot stage and the cold stage, and any conversion time is less than 15 s.

[0022] In some of these embodiments, the test device further includes a multi-port visual thermometer, which can monitor the temperatures of the copper plate surface and the controllable hot table surface in real time, and the temperature fluctuation does not exceed 2°C.

[0023] In some of these embodiments, in the step of characterizing the sintered sample to be tested, the sintered sample to be tested is characterized by a scanning electron microscope or a transmission electron microscope or an electron probe. The metal layer on the upper interface of the sintered sample to be tested is a gold-plated layer, and the metal layer on the lower interface of the sintered sample to be tested is a gold-plated layer or a nickel-plated layer or a silver-plated layer or a copper-plated layer. The thickness of the metal layer is between 0.1 and 10 μm, and the gold-plated layer or nickel-plated layer or silver-plated layer or copper-plated layer can be prepared by electroplating or electroless plating or magnetron sputtering.

[0024] In some of these embodiments, the sintered interconnect material of the sintered sample to be tested is sintered silver paste, and the sintered silver paste is nano silver paste or micro silver paste or composite silver paste.

[0025] In some of these embodiments, in the step of performing an accelerated thermal shock experiment on the sintered sample to be tested and determining whether the sintered sample to be tested after the accelerated thermal shock experiment fails, it specifically includes:

[0026] If the sintered sample to be tested after the accelerated thermal shock experiment shows obvious delamination and the delamination ratio reaches more than 5%, it is determined that the sintered sample to be tested fails.

[0027] In some of these embodiments, the crack existence area of the sintered sample to be tested that fails in the accelerated thermal shock experiment should be consistent with that in the standard thermal cycle test. The life of the sample under the standard thermal cycle is the accelerated experiment life multiplied by the acceleration factor.

[0028] In some of these embodiments, in the step of characterizing the failed sintered sample to be tested, it specifically includes the following steps: characterizing the failed sintered sample to be tested by a scanning electron microscope or a transmission electron microscope or an electron probe.

[0029] Another object of the present application also provides a test system for evaluating the thermal cycle failure of a silver sintered interconnect structure, including:

[0030] A parameter design module, configured to construct an acceleration function and design acceleration parameters;

[0031] A test device, configured to set the test device conditions according to the acceleration parameters;

[0032] A pre-characterization module, configured to characterize the sintered sample to be tested;

[0033] A judgment module, configured to perform an accelerated thermal shock experiment on the sintered sample to be tested and judge whether the sintered sample to be tested after the accelerated thermal shock experiment fails. If so, proceed to the next step; if not, perform the accelerated thermal shock experiment again.

[0034] A structure characterization module, configured to characterize the failed sintered sample to be tested.

[0035] The present application adopts the above technical solutions, and the beneficial effects are as follows:

[0036] The test method and device for evaluating the thermal cycle failure of a silver sintered interconnect structure provided by the present application include: constructing an acceleration function and designing acceleration parameters; characterizing the sintered sample to be tested; building an accelerated test device and performing an accelerated thermal shock experiment on the sintered sample to be tested; judging whether the sintered sample to be tested after the accelerated thermal shock experiment fails. If so, proceed to the next step, and if not, return to the previous step; characterizing the failed sintered sample to be tested. The above method and device are simple and easy to implement, shorten the number of thermal cycles on the premise of equally reflecting the thermal failure of silver sintered interconnect products, can complete the evaluation of the thermal reliability of products within one day, and predict the failure life of products. Description of the Drawings

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments of the present application or the prior art. Obviously, the following described drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0038] Figure 1 It is a flowchart of the steps of the test method for evaluating the thermal cycle failure of a silver sintered interconnect structure provided by an embodiment of the present invention.

[0039] Figure 2 It is a schematic structural diagram of the test device provided by an embodiment of the present invention.

[0040] Figure 3 It is a schematic structural diagram of the test system for evaluating the thermal cycle failure of a silver sintered interconnect structure provided by an embodiment of the present invention.

[0041] Figure 4 It is a schematic diagram of the composition of the sintered sample provided by Embodiment 1 of the present invention.

[0042] Figure 5 It is the microstructure morphology of the sintered sample provided by Embodiment 1 of the present invention.

[0043] Figure 6 It is the ultrasonic analysis result of the samples provided by Embodiment 1 and Comparative Example 1 of the present invention.

[0044] Figure 7 The accelerated sample tissue morphology provided by Embodiment 1 of the present invention.

[0045] Figure 8 The sintered sample tissue morphology provided by Embodiment 2 of the present invention.

[0046] Figure 9 The schematic diagram of the ultrasonic analysis results of the samples provided by Embodiment 2 and Comparative Example 2 of the present invention.

[0047] Figure 10 The accelerated sample tissue morphology provided by Embodiment 2 of the present invention.

[0048] Figure 11 The standard cycle sample tissue morphology provided by Comparative Example 1 of the present invention.

[0049] Figure 12 The standard cycle sample tissue morphology provided by Comparative Example 2 of the present invention. Detailed implementation manners

[0050] The embodiments of the present application are described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application, but should not be construed as limiting the present application.

[0051] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.

[0052] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality" means two or more unless otherwise specifically defined.

[0053] In order to make the purpose, technical solutions and advantages of the present application more clear, the following takes an electroplated Au copper flange silver sintered sample as an example, and in combination with the accompanying drawings and embodiments, the present application is further described in detail.

[0054] Please refer to Figure 1, the flowchart of the steps of the test method for evaluating the thermal cycle failure of the silver sintered interconnect structure provided by the embodiment of the present application includes the following steps S110 to S150, and the implementation methods of each step are described in detail below.

[0055] Step S110: Construct an acceleration function and design acceleration parameters.

[0056] In this embodiment, an acceleration function is constructed based on the Norris-Landzberg model (Doi: 10.1147 / rd.133.0266) and the Bayerer model (Doi: 10.1016 / j.microrel.2018.01.009) improved from the Coffin-Manson law (Doi: 10.1109 / PEDS.1997.618742).

[0057] Specifically, the acceleration function is as follows:

[0058]

[0059]

[0060] Among them, AF is the acceleration factor; ΔT 加速 and ΔT 标准 are the junction temperature fluctuations under the accelerated and standard thermal cycle conditions; N 加速 and N 标准 are the number of cycles per hour under the accelerated and standard thermal cycle conditions; T jmax加速 and T jmax标准 are the maximum junction temperatures under the accelerated and standard thermal cycle conditions, with the unit of K; T jmin加速 and T jmin标准 are the minimum junction temperatures under the accelerated and standard thermal cycle conditions; m and n are constant coefficients related to the type of silver sintered interconnect structure, which can be determined by the method of controlling variables. The value range of m is 3 to 5, and the value range of n is -1.8 to 0.8; the acceleration parameters include ΔT 加速 , T jmax加速 , N 加速 and T jmin加速 .

[0061] Furthermore, the acceleration parameters include ΔT 加速 , T jmax加速 , N 加速 and T jmin加速 . The selection of acceleration parameters should ensure that the value of the acceleration factor is not less than 5. The selection range of T jmax加速 is 0 to 10 °C, and the temperature difference between T jmax加速 and T jmin加速 is not less than the junction temperature fluctuation ΔT j, but not exceeding the junction temperature fluctuation of the standard thermal cycle test by 50 °C. N 加速 Not higher than 24 times, but not lower than 6 times, where the residence time at the maximum or minimum junction temperature is not less than 1 min, and the conversion time does not exceed 15 s.

[0062] It can be understood that the determination of the values of n and m can be obtained by fitting through the design of experiments (DOE) of controlling variables. In this application, through experiments, it is determined that the value of n is -0.5 and the value of m is 3.77 in the acceleration function under the conditions of the standard thermal cycle (-65 to 150 °C, cycle period 30 min) for accelerating the evaluation of the gold-plated semi-sintered silver interconnect structure. The acceleration parameter is ΔT 加速 , T jmax加速 , N 加速 and T jmin加速 .

[0063] Step S120: Set up the test device.

[0064] Please refer to Figure 2 , the test device includes a controllable hot stage 110, a cold stage 120 and a low-temperature constant temperature bath 130. The controllable hot stage 110 serves as the hot end of the accelerated thermal shock experiment, and the cold stage 120 serves as the cold end of the accelerated thermal shock experiment. The side wall of the cold stage 120 is provided with inlets and outlets, and circulating coolant can be introduced into the inside of the side wall. The temperature of the circulating coolant is controlled by the low-temperature constant temperature bath 130. A circulating water pump 140 is arranged in the low-temperature constant temperature bath 130, and under the action of the circulating water pump 140, the circulating coolant enters the side wall of the copper plate.

[0065] Further, the test device further includes a numerically controlled moving stage 150 and a robotic arm 160. The robotic arm is fixed on the numerically controlled moving stage 150, and by moving the numerically controlled moving stage 150, the robotic arm is driven to move to realize the conversion of the sintered sample to be tested between the controllable hot stage 110 and the cold stage 120, and the conversion time for any one time is less than 15 s.

[0066] Further, the test device further includes a multi-port visual temperature measuring instrument 170. The multi-port visual temperature measuring instrument 170 can monitor the temperature on the surface of the copper plate and the surface of the controllable hot stage in real time, and the temperature fluctuation does not exceed 2 °C.

[0067] Step S130: Characterize the sintered sample to be tested.

[0068] In this embodiment, the sintered sample to be tested is characterized by a scanning electron microscope or a transmission electron microscope or an electron probe.

[0069] Further, the metal layer on the upper interface of the sintered sample to be tested is a gold plating layer, and the metal layer on the lower interface of the sintered sample to be tested is a gold plating layer or a nickel plating layer or a silver plating layer or a copper plating layer. The thickness of the metal layer is between 0.1 and 10 μm, and the gold plating layer or nickel plating layer or silver plating layer or copper plating layer can be prepared by electroplating or electroless plating or magnetron sputtering.

[0070] In this embodiment, the sintered interconnect material is sintered silver paste, which can be nano silver paste, micro silver paste or composite silver paste.

[0071] Step S140: Perform an accelerated thermal shock test on the sintered sample to be tested, and determine whether the sintered sample to be tested after the accelerated thermal shock test fails.

[0072] In this embodiment, the sintered sample to be tested is placed on a hot table with a surface temperature maintained at T jmax for a certain time t, and then moved to a cold table with a surface temperature of T jmin for a certain time t.

[0073] Further, in actual operation, when placing the sample on the hot and cold tables, a 50-100 g weight is needed to ensure that the bottom surface of the sample is in full contact with the table.

[0074] In this embodiment, if obvious delamination occurs in the sintered sample to be tested after the accelerated thermal shock test and the delamination ratio reaches more than 5%, it is determined that the sample fails.

[0075] Step S150: Characterize the failed sintered sample to be tested.

[0076] In this embodiment, in the step of characterizing the failed sintered sample to be tested, it specifically includes the following steps: characterizing the failed sintered sample to be tested by scanning electron microscopy or transmission electron microscopy or electron probe.

[0077] It can be understood that in the step of characterizing the failed sintered sample to be tested, the crack existence area of the sintered sample to be tested that fails in the accelerated thermal shock test should be consistent with that in the standard thermal cycle test.

[0078] In this embodiment, the actual thermal cycle failure life of the sample is the accelerated test failure cycle coefficient multiplied by the acceleration factor.

[0079] The test method for evaluating the thermal cycle failure of the silver sintered interconnect structure provided in this embodiment shortens the number of thermal cycles while equally reflecting the thermal failure of the gold-plated sintered interconnect product, and can complete the evaluation of the thermal reliability of the product and predict the product failure life within one day.

[0080] Please refer to Figure 3 , and there is also provided a test system for evaluating the thermal cycle failure of a silver sintered interconnect structure, including:

[0081] A parameter design module 310 is configured to construct an acceleration function and design acceleration parameters;

[0082] A test device 320 is configured to set the test device conditions according to the acceleration parameters;

[0083] A pre-characterization module 330 is configured to characterize a sintered sample to be tested;

[0084] A judgment module 340 is configured to perform an accelerated thermal shock test on the sintered sample to be tested and judge whether the sintered sample to be tested after the accelerated thermal shock test fails. If so, proceed to the next step; if not, perform the accelerated thermal shock test again;

[0085] A structure characterization module 350 is configured to characterize the failed sintered sample to be tested.

[0086] For the test system for evaluating the thermal cycle failure of the silver sintered interconnect structure provided in the above embodiments of the present application, the detailed implementation manner can be referred to the above test method, which will not be elaborated here.

[0087] The test system for evaluating the thermal cycle failure of the silver sintered interconnect structure provided in this embodiment shortens the number of thermal cycles on the premise of equally reflecting the thermal failure of the gold-plated sintered interconnect product, and can complete the evaluation of the thermal reliability of the product and predict the failure life of the product within one day.

[0088] To further understand the present invention, the present invention will be described below in conjunction with examples. However, the examples are only used to further illustrate the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0089] Example 1:

[0090] In the present invention, a gold layer is electroplated on a copper substrate by electroplating, and semi-sintered silver paste is filled on the substrate by screen printing. Then, an Si chip also plated with a gold layer is placed on the upper end surface of the silver paste as a simulated chip to form a sandwich-type joint ( Figure 4 ). The prepared sample is placed in a tube furnace filled with nitrogen for pressureless sintered interconnect. The sintering process is sintering at 180 - 250 °C for 30 - 45 min.

[0091] The microstructure of the sintered sample is as Figure 5 shown, and the average connection rates of the upper and lower interfaces are 74.8% and 62.7% respectively. From the ultrasonic scanning results ( Figure 6 a), it can be seen that the sintering quality of the sample is excellent, and no delamination or crack occurs. The average shear quality of the sintered sample is 47.2 Mpa, far superior to the shear standard of 15 Mpa. At this time, the fracture mode of the sample is composite fracture, that is, the fracture surface partially occurs at the substrate-side interface and partially occurs at the chip-side interface.

[0092] Place the sample in Figure 3 the simple hot and cold device shown. The maximum and minimum values of the junction temperature of the simple hot and cold device are set to 240 ± 2 °C and 5 ± 2 °C respectively. The residence time of the sample at the maximum and minimum values of the junction temperature is set to 60 ± 5 s. At this time, the acceleration factor is calculated to be 20 ± 2.

[0093] After 25 accelerated thermal cycles, the ultrasonic result of the sample is shown in Figure 6 b). It can be seen that there is an obvious delamination phenomenon in the sample at this time. Through tissue analysis, it can be known that Figure 7 ), at this time, the crack propagates along the lower interface of the sample, that is, the failure position of the sample occurs on the Ag-Au interface side of the substrate. Based on the accelerated test, it is predicted that the sample will fail after about 500 cycles in the standard thermal cycle.

[0094] Example 2:

[0095] In the present invention, a gold layer is electroplated on a copper substrate by electroplating, and semi-sintered silver paste is filled on the substrate by screen printing. Then, a Si chip also plated with a gold layer is placed on the upper end face of the silver paste as a simulated chip to form a sandwich-type joint. The prepared sample is placed in a tube furnace filled with nitrogen for pressureless sintering interconnection. The sintering process is sintering at 180 - 250 °C for 75 - 90 min.

[0096] The microstructure of the sintered sample is as shown in Figure 8 . The average connection rates of the upper and lower interfaces are 80.0% and 79.0% respectively. From the ultrasonic scanning result, it can be known that Figure 9 in a), the sintering quality of the sample is excellent, and no delamination or crack occurs. The average shear quality of the sintered sample is 55.7 Mpa. At this time, the fracture surface of the sample mainly occurs at the chip-side interface.

[0097] Place the sample in Figure 3 the simple hot and cold device shown. The maximum and minimum values of the junction temperature of the simple hot and cold device are set to 240 ± 2 °C and 5 ± 2 °C respectively. The residence time of the sample at the maximum and minimum values of the junction temperature is set to 60 ± 5 s. At this time, the acceleration factor is calculated to be 20.

[0098] After 50 accelerated thermal cycles, the ultrasonic microstructure of the sample is as shown in Figure 9 b. It can be seen that there is an obvious delamination phenomenon in the sample at this time. Through Figure 10 tissue analysis, it can be known that at this time, the crack propagates along the upper interface of the sample, that is, the failure position of the sample occurs on the chip-side Ag-Au interface side. Based on the accelerated test, it is predicted that the sample will fail after about 1000 cycles in the standard thermal cycle.

[0099] Comparative Example 1

[0100] The sample preparation is the same as that in Example 1

[0101] The sample was placed in a standard thermal cycle test chamber, the thermal cycle conditions were -65 to 150°C, and the sample stayed at the maximum and minimum junction temperature for 5 minutes. Compared with Example 1, the sample did not show obvious delamination until 500 cycles. Figure 6 As shown in c. Figure 11 According to the microstructure analysis, the failure position caused by the standard thermal cycle is the same as that in Example 1, which is at the interface on the substrate side.

[0102] Comparative Example 2

[0103] Sample preparation is the same as in Example 2

[0104] The sample was placed in a standard thermal cycle test chamber, the thermal cycle conditions were -65 ~ 150 ° C, and the sample stayed at the maximum and minimum junction temperature for 5 minutes. After 500 cycles, the sample did not have a clear delamination from the ultrasonic results, and no obvious long cracks were found from the cross-sectional microstructure analysis. After 1000 thermal cycles, combined with ultrasound ( Figure 9 c) and cross-sectional organization ( Figure 12 ) analysis shows that delamination occurs at the chip side interface, and the crack extends along the interface. Therefore, according to the organizational analysis, the failure position caused by the standard thermal cycle is the same as in Example 2, both at the chip side interface.

[0105] It can be understood that the technical features of the above-described embodiments can be arbitrarily combined. In order to make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The above are only preferred embodiments of the present application, and only specifically describe the technical principles of the present application. These descriptions are only for explaining the principles of the present application and cannot be interpreted as limiting the scope of protection of the present application in any way. Based on the explanation here, any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application, and other specific implementation methods of the present application that can be associated with the technicians in this field without creative work, should be included in the scope of protection of the present application.

Claims

1. A test method for accelerating the evaluation of the thermal cycle failure of a silver sintered interconnect structure, characterized in that Including the following steps: Construct an acceleration function and design acceleration parameters; Set up a test device and set the test device conditions according to the acceleration parameters; Characterize the sintered sample to be tested; Conduct an accelerated thermal shock experiment on the sintered sample to be tested according to the test device, and determine whether the sintered sample to be tested after the accelerated thermal shock experiment fails. If so, proceed to the next step; if not, conduct the accelerated thermal shock experiment again; Characterize the failed sintered sample to be tested.

2. The test method for accelerating the evaluation of the thermal cycle failure of the silver sintered interconnect structure according to claim 1, wherein In the step of constructing the acceleration function, the acceleration function is constructed based on the physics of failure, combining the Bayerer model and the Norris-Landzberg model, as follows: where AF is the acceleration factor; ΔT 加速 and ΔT 标准 are the junction temperature fluctuations under the accelerated and standard temperature cycling conditions; N 加速 and N 标准 are the number of cycles per hour under the accelerated and standard temperature cycling conditions; T jmax加速 and T jnax标准 are the maximum junction temperatures under the accelerated and standard temperature cycling conditions, with the unit of K; T jmin加速 and T jmin标准 are the minimum junction temperatures under the accelerated and standard temperature cycling conditions, with the unit of K; m and n are constant coefficients related to the types of silver sintered interconnect structures and can be determined by the method of controlling variables. The value range of m is 3 to 5, and the value range of n is -1.8 to 0.8; the acceleration parameters include ΔT 加速 , T jmax加速 , N 加速 and T jmib加速 .

3. The test method for accelerating the evaluation of the thermal cycle failure of the silver sintering interconnect structure according to claim 2, characterized in that, T jmax加速 Select a range of 0 to 10 °C, T jmax加速 The temperature difference from T jmin加速 shall not be lower than the junction temperature fluctuation ΔT of the standard thermal cycle test j , but shall not exceed 50 °C, the junction temperature fluctuation of the standard thermal cycle test, N 加速 shall not be higher than 24 times, but shall not be lower than 6 times, where the residence time at the maximum or minimum junction temperature shall not be lower than 1 min, and the conversion time shall not exceed 15 s.

4. The test method for accelerating the evaluation of the thermal cycle failure of the silver sintering interconnect structure according to claim 3, characterized in that, The acceleration factor AF is not less than 5.

5. The test method for accelerating the evaluation of the thermal cycle failure of the silver sintering interconnect structure according to claim 1, wherein In the step of setting up the test device, the test device includes a controllable hot stage, a cold stage and a low-temperature constant temperature bath. The controllable hot stage serves as the hot end of the accelerated thermal shock experiment, and the cold stage serves as the cold end of the accelerated thermal shock experiment. The side wall of the cold stage is provided with inlets and outlets, and circulating coolant can be introduced into the interior of the side wall. The temperature of the circulating coolant is controlled by the low-temperature constant temperature bath.

6. The test method for accelerating the evaluation of the thermal cycling failure of the silver sintered interconnect structure according to claim 5, wherein, The test device further includes a numerically controlled moving stage and a robotic arm. The robotic arm is fixed on the numerically controlled moving stage, and the robotic arm is moved by moving the numerically controlled moving stage to realize the conversion of the sintered sample to be tested between the controllable hot stage and the cold stage. The conversion time for any one time is less than 15 s.

7. The test method for accelerating the evaluation of the thermal cycle failure of the silver sintered interconnect structure according to claim 5, characterized in that, The test device further includes a multi-port visual thermometer, which can real-time monitor the temperatures of the copper plate surface and the controllable hot stage surface, and the temperature fluctuation does not exceed 2°C.

8. The test method for accelerating the evaluation of the thermal cycle failure of the silver sintered interconnect structure according to claim 1, wherein In the step of characterizing the sintered sample to be tested, the sintered sample to be tested is characterized by a scanning electron microscope or a transmission electron microscope or an electron probe. The metal layer on the upper interface of the sintered sample to be tested is a gold-plated layer, and the metal layer on the lower interface of the sintered sample to be tested is a gold-plated layer or a nickel-plated layer or a silver-plated layer or a copper-plated layer. The thickness of the metal layer is between 0.1 and 10 μm, and the gold-plated layer or nickel-plated layer or copper-plated layer can be prepared by electroplating or electroless plating or magnetron sputtering.

9. The test method for accelerating the evaluation of the thermal cycle failure of the silver sintering interconnect structure according to claim 1, characterized in that, The sintering interconnect material of the sintered sample to be tested is sintered silver paste, and the sintered silver paste is nano silver paste or micro silver paste or composite silver paste.

10. The test method for accelerating the evaluation of the thermal cycling failure of the silver sintered interconnect structure according to claim 1, characterized in that, In the step of conducting the accelerated thermal shock experiment on the sintered sample to be tested and determining whether the sintered sample to be tested after the accelerated thermal shock experiment fails, it specifically includes: If obvious delamination occurs in the sintered sample to be tested after the accelerated thermal shock experiment and the delamination ratio reaches more than 5%, it is determined that the sintered sample to be tested fails.

11. The test method for evaluating the thermal cycling failure of the silver sintered interconnect structure according to claim 10, characterized in that The crack existence area of the sintered sample to be tested that fails after the accelerated thermal shock experiment should be consistent with the standard thermal cycle test. The life of the sample under the standard thermal cycle is the accelerated experiment life multiplied by the acceleration factor.

12. The test method for evaluating the thermal cycle failure of the silver sintered interconnect structure according to claim 1, characterized in that, In the step of characterizing the failed sintered sample to be tested, it specifically includes the following steps: characterizing the failed sintered sample to be tested by a scanning electron microscope or a transmission electron microscope or an electron probe.

13. A test system for evaluating the thermal cycling failure of a silver sintered interconnect structure, characterized in that, Including: A parameter design module for constructing an acceleration function and designing acceleration parameters; A test device for setting the test device conditions according to the acceleration parameters; A pre-characterization module for characterizing the sintered sample to be tested; A judgment module for performing an accelerated thermal shock experiment on the sintered sample to be tested and judging whether the sintered sample to be tested after the accelerated thermal shock experiment fails. If so, proceed to the next step; if not, perform the accelerated thermal shock experiment again; A structure characterization module for characterizing the failed sintered sample to be tested.

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