Level conversion circuit, chip and electronic equipment

Abstract

The invention discloses a level conversion circuit, a chip and electronic equipment, and the level conversion circuit comprises an input / output circuit and a voltage-withstanding control circuit. The input and output circuit comprises a first input switch, a second input switch, a first output control switch, a second output control switch, a first output switch, a second output switch, a third output switch, a fourth output switch, a first selection switch, a second selection switch, a third selection switch and a fourth selection switch. A first input switch, a second input switch, a first output control switch, a second output control switch, a first output switch, a second output switch, a third output switch, a fourth output switch, a first selection switch, a second selection switch, a third selection switch, a fourth selection switch and a voltage withstanding control circuit are mutually combined. And when the power supply voltage input into the second power supply end exceeds the upper limit of the withstand voltage range of the single switch, the problem of reliability degradation or failure of the switch in the input / output circuit is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of level conversion, and in particular to a level conversion circuit, chip, and electronic device. Background Art

[0002] In order to reduce costs and achieve higher driving capabilities, a level shifter (LS) circuit is usually used to convert low voltage to achieve high voltage output. Alternatively, there is a level mismatch problem when different circuits communicate. If the voltage difference between the two circuits is too large, it will cause circuit damage. At this time, a level shifter circuit is usually set between the two circuits to convert the voltage through the level shifter circuit so that the voltage of the two circuits is consistent.

[0003] Typically, a level shifter circuit consists of multiple switching transistors to achieve voltage conversion. However, these switching transistors have a certain voltage tolerance range, and with the evolution of semiconductor technology, the voltage tolerance of these switching transistors has gradually decreased. As a result, in actual operation, the power supply voltage input to the level shifter circuit may exceed the voltage tolerance range of the switching transistors, causing reliability degradation or even failure of the switching transistors. Summary of the Invention

[0004] The present application provides a level conversion circuit, a chip, and an electronic device for preventing reliability degradation or failure of a switching tube when the power supply voltage input to the level conversion circuit is higher than the voltage withstand range of the switching tube.

[0005] In the first aspect, an embodiment of the present application provides a level conversion circuit, which includes: an input-output circuit and a voltage resistance control circuit. The input-output circuit includes: a first input switch, a second input switch, a first output control switch, a second output control switch, a first output switch, a second output switch, a third output switch, a fourth output switch, a first selection switch, a second selection switch, a third selection switch, and a fourth selection switch; wherein the control electrode of the first input switch is connected to the first signal input terminal, the first electrode of the first input switch is connected to the first power supply terminal, the second electrode of the first input switch is connected to the first electrode of the first selection switch, the second electrode of the first selection switch is connected to the first electrode of the first output switch, the control electrode of the first output control switch is used to receive the first output control signal, the first electrode of the first output control switch is connected to the second power supply terminal, the second electrode of the first output control switch is connected to the first electrode of the second selection switch, the second electrode of the second selection switch is connected to the first electrode of the second output switch, and the second electrode of the first output switch is connected to the first electrode of the second output switch. The first electrode of the second input switch and the second electrode of the second output switch are both connected to the first signal output terminal, the control electrode of the second input switch is connected to the second signal input terminal, the first electrode of the second input switch is connected to the first power supply terminal, the second electrode of the second input switch is connected to the first electrode of the third selection switch, the second electrode of the third selection switch is connected to the first electrode of the third output switch, the control electrode of the second output control switch is used to receive the second output control signal, the first electrode of the second output control switch is connected to the second power supply terminal, the second electrode of the second output control switch is connected to the first electrode of the fourth selection switch, the second electrode of the fourth selection switch is connected to the first electrode of the fourth output switch, the second electrode of the third output switch and the second electrode of the fourth output switch are both connected to the second signal output terminal, and the control electrodes of the first selection switch, the second selection switch, the third selection switch, and the fourth selection switch are all connected to the selection control terminal. With this arrangement, when the power supply voltage input to the second power supply terminal exceeds the upper limit of the withstand voltage range of a single switch in the input-output circuit, the first signal output terminal is pulled low by the first input switch, the first selection switch, and the first output switch, thereby ensuring that the reliability of the first input switch, the first selection switch, and the first output switch will not degrade or fail.

[0006] When the power supply voltage input to the second power supply terminal exceeds the upper limit of the voltage withstand range of a single switch in the input-output circuit, the first signal output terminal is pulled high through the first output control switch, the second selection switch, and the second output switch, thereby ensuring that the first output control switch, the second selection switch, and the second output switch will not experience reliability degradation or failure.

[0007] When the power supply voltage input to the second power supply terminal exceeds the upper limit of the voltage withstand range of a single switch in the input-output circuit, the second signal output terminal is pulled low through the second input switch, the third selection switch, and the third output switch, thereby ensuring that the second input switch, the third selection switch, and the third output switch will not experience reliability degradation or failure.

[0008] When the power supply voltage input to the second power supply terminal exceeds the upper limit of the voltage tolerance range of a single switch in the input-output circuit, the second signal output terminal is pulled high through the second output control switch, the fourth selection switch, and the fourth output switch, thereby ensuring that the second output control switch, the fourth selection switch, and the fourth output switch will not experience reliability degradation or failure.

[0009] Furthermore, the withstand voltage control circuit has a first input terminal connected to the first withstand voltage control terminal, a second input terminal connected to the first signal output terminal, a third input terminal connected to the second signal output terminal, a first output terminal connected to the control electrode of the first output switch, a second output terminal connected to the control electrode of the second output switch, a third output terminal connected to the control electrode of the third output switch, and a fourth output terminal connected to the control electrode of the fourth output switch. Furthermore, the withstand voltage control circuit is configured to output the voltage at the first withstand voltage control terminal or the first signal output terminal to the control electrode of the first output switch, output the voltage at the first withstand voltage control terminal or the first signal output terminal to the control electrode of the second output switch, output the voltage at the first withstand voltage control terminal or the second signal output terminal to the control electrode of the third output switch, and output the voltage at the first withstand voltage control terminal or the second signal output terminal to the control electrode of the fourth output switch. Therefore, by providing a withstand voltage control circuit, when the power supply voltage input to the second power supply terminal exceeds the upper limit of the withstand voltage range of a single switch among the first output switch, the second output switch, the third output switch, and the fourth output switch, the withstand voltage control circuit can be used to adjust the voltage of the control electrode of the first output switch, the second output switch, the third output switch, and the fourth output switch, so that the voltage difference between the control electrode and the second electrode of the first output switch, the second output switch, the third output switch, and the fourth output switch is less than or equal to the upper limit of the withstand voltage range, thereby ensuring that the first output switch, the second output switch, the third output switch, and the fourth output switch will not experience reliability degradation or failure.

[0010] The level conversion circuit in the embodiment of the present application can be applied to the scenario of level conversion of differential signals. Based on this, the signal input by the first signal input terminal and the second signal input terminal can be a differential signal, and the signal output by the first signal output terminal and the second signal output terminal can also be a differential signal.

[0011] In some embodiments, the withstand voltage control circuit includes a first withstand voltage control subcircuit, a second withstand voltage control subcircuit, a third withstand voltage control subcircuit, and a fourth withstand voltage control subcircuit. The first withstand voltage control subcircuit has a first input connected to the first withstand voltage control terminal, a second input connected to the first signal output terminal, and an output connected to the control electrode of the first output switch. The first withstand voltage control subcircuit is configured to output the voltage of the first withstand voltage control terminal or the first signal output terminal to the control electrode of the first output switch in response to the voltages of the first withstand voltage control terminal and the first signal output terminal. With this configuration, the first withstand voltage control subcircuit adjusts the voltage of the control electrode of the first output switch so that the voltage difference between the control electrode of the first output switch and the first signal output terminal is less than or equal to the upper limit of the withstand voltage range of the first output switch, thereby avoiding reliability degradation or failure of the first output switch.

[0012] Furthermore, the second withstand voltage control subcircuit has a first input terminal connected to the first withstand voltage control terminal, a second input terminal connected to the first signal output terminal, and an output terminal connected to the control terminal of the second output switch. The second withstand voltage control subcircuit is configured to output the voltage at the first withstand voltage control terminal or the first signal output terminal to the control terminal of the second output switch in response to the voltages at the first withstand voltage control terminal and the first signal output terminal. With this configuration, the second withstand voltage control subcircuit adjusts the voltage at the control terminal of the second output switch so that the voltage difference between the control terminal of the second output switch and the first signal output terminal is less than or equal to the upper limit of the withstand voltage range of the second output switch, thereby preventing reliability degradation or failure of the second output switch.

[0013] Furthermore, the first input terminal of the third withstand voltage control subcircuit is connected to the first withstand voltage control terminal, the second input terminal is connected to the second signal output terminal, and the output terminal is connected to the control terminal of the third output switch. The third withstand voltage control subcircuit is used to output the voltage of the first withstand voltage control terminal or the second signal output terminal to the control terminal of the third output switch in response to the voltage of the first withstand voltage control terminal and the second signal output terminal. With this configuration, the third withstand voltage control subcircuit adjusts the voltage of the control terminal of the third output switch so that the voltage difference between the control terminal of the third output switch and the second signal output terminal is less than or equal to the upper limit of the withstand voltage range of the third output switch, thereby avoiding reliability degradation or failure of the third output switch.

[0014] Furthermore, the fourth withstand voltage control subcircuit has a first input terminal connected to the first withstand voltage control terminal, a second input terminal connected to the second signal output terminal, and an output terminal connected to the control terminal of the fourth output switch. The fourth withstand voltage control subcircuit is configured to output the voltage of the first withstand voltage control terminal or the second signal output terminal to the control terminal of the fourth output switch in response to the voltages of the first withstand voltage control terminal and the second signal output terminal. With this configuration, the fourth withstand voltage control subcircuit adjusts the voltage of the control terminal of the fourth output switch so that the voltage difference between the control terminal of the fourth output switch and the second signal output terminal is less than or equal to the upper limit of the withstand voltage range of the fourth output switch, thereby preventing reliability degradation or failure of the fourth output switch.

[0015] In some embodiments, the first withstand voltage control subcircuit includes a first control switch and a second control switch, wherein the control electrode of the first control switch is connected to the first withstand voltage control terminal, the first electrode of the first control switch is connected to the first signal output terminal, and the second electrode of the first control switch is connected to the control electrode of the first output switch. Furthermore, the control electrode of the second control switch is connected to the first signal output terminal, the first electrode of the second control switch is connected to the first withstand voltage control terminal, and the second electrode of the second control switch is connected to the control electrode of the first output switch. This arrangement can achieve a simple first withstand voltage control subcircuit, making it relatively simple to use and reducing production costs.

[0016] In some embodiments, the second withstand voltage control subcircuit includes a third control switch and a fourth control switch, wherein the control electrode of the third control switch is connected to the first withstand voltage control terminal, the first electrode of the third control switch is connected to the first signal output terminal, and the second electrode of the third control switch is connected to the control electrode of the second output switch. Furthermore, the control electrode of the fourth control switch is connected to the first signal output terminal, the first electrode of the fourth control switch is connected to the first withstand voltage control terminal, and the second electrode of the fourth control switch is connected to the control electrode of the second output switch. This arrangement can achieve a simple second withstand voltage control subcircuit, making it relatively simple to use and reducing production costs.

[0017] In some embodiments, the second withstand voltage control subcircuit further includes a fifth control switch, wherein a control electrode of the fifth control switch is connected to the second withstand voltage control terminal, a first electrode of the fifth control switch is connected to the first withstand voltage control terminal, and a second electrode of the fifth control switch is connected to the control electrode of the second output switch. With this arrangement, by combining the conduction and disconnection of the fifth control switch, the level shifter can switch operating modes in different voltage application scenarios.

[0018] In some embodiments, the third withstand voltage control subcircuit includes a sixth control switch and a seventh control switch, wherein the control electrode of the sixth control switch is connected to the first withstand voltage control terminal, the first electrode of the sixth control switch is connected to the second signal output terminal, and the second electrode of the sixth control switch is connected to the control electrode of the third output switch. Furthermore, the control electrode of the seventh control switch is connected to the second signal output terminal, the first electrode of the seventh control switch is connected to the first withstand voltage control terminal, and the second electrode of the seventh control switch is connected to the control electrode of the third output switch. This arrangement achieves a simple third withstand voltage control subcircuit, making it easier to use and reducing production costs.

[0019] In some embodiments, the fourth withstand voltage control subcircuit includes an eighth control switch and a ninth control switch, wherein the control electrode of the eighth control switch is connected to the first withstand voltage control terminal, the first electrode of the eighth control switch is connected to the second signal output terminal, and the second electrode of the eighth control switch is connected to the control electrode of the fourth output switch. Furthermore, the control electrode of the ninth control switch is connected to the second signal output terminal, the first electrode of the ninth control switch is connected to the first withstand voltage control terminal, and the second electrode of the ninth control switch is connected to the control electrode of the fourth output switch. This arrangement achieves a simple fourth withstand voltage control subcircuit, making it easier to use and reducing production costs.

[0020] In some embodiments, the fourth withstand voltage control subcircuit further includes a tenth control switch, wherein a control electrode of the tenth control switch is connected to the second withstand voltage control terminal, a first electrode of the tenth control switch is connected to the first withstand voltage control terminal, and a second electrode of the tenth control switch is connected to the control electrode of the fourth output switch. With this arrangement, by combining the conduction and disconnection of the tenth control switch, the level shifter can switch operating modes in different voltage application scenarios.

[0021] In some embodiments, the level shifting circuit further includes: a first conduction control circuit and a second conduction control circuit, wherein the input of the first conduction control circuit is connected to the second electrode of the first input switch, the output of the first conduction control circuit is connected to the control electrode of the first output switch, and the first conduction control circuit is used to control whether the second electrode of the first input switch and the control electrode of the first output switch are connected or disconnected. Furthermore, the input of the second conduction control circuit is connected to the second electrode of the second input switch, the output of the second conduction control circuit is connected to the control electrode of the third output switch, and the second conduction control circuit is used to control whether the second electrode of the second input switch and the control electrode of the third output switch are connected or disconnected. With this arrangement, by combining the control of the first and second conduction control circuits, the level shifting circuit can switch operating modes in different voltage application scenarios.

[0022] In some embodiments, the first conduction control circuit includes a first conduction control switch and a second conduction control switch, wherein the control electrode of the first conduction control switch is connected to the first conduction control terminal, the first electrode of the first conduction control switch is connected to the second electrode of the first input switch, and the second electrode of the first conduction control switch is connected to the first electrode of the second conduction control switch. Furthermore, the control electrode of the second conduction control switch is connected to the second conduction control terminal, and the second electrode of the second conduction control switch is connected to the control electrode of the first output switch. This configuration can achieve a simple first conduction control circuit, making it easier to use and reducing production costs.

[0023] In some embodiments, the second conduction control circuit includes a third conduction control switch and a fourth conduction control switch, wherein the control electrode of the third conduction control switch is connected to the first conduction control terminal, the first electrode of the third conduction control switch is connected to the second electrode of the second input switch, and the second electrode of the third conduction control switch is connected to the first electrode of the fourth conduction control switch. Furthermore, the control electrode of the fourth conduction control switch is connected to the second conduction control terminal, and the second electrode of the fourth conduction control switch is connected to the control electrode of the third output switch. This configuration achieves a second conduction control circuit with a simple structure, which is relatively simple to implement and can also reduce production costs.

[0024] In some embodiments, the first output control signal and the second output control signal may be input through two different ports respectively, or the first output control signal and the second output control signal may be input through the same port.

[0025] To reduce the number of external ports connected to the level shifter circuit and ease wiring complexity, in some embodiments, the control electrode of the first output control switch is connected to the control electrode of the third output switch, so that the signal from the control electrode of the third output switch serves as the first output control signal to control the first output control switch on or off. Furthermore, the control electrode of the second output control switch is connected to the control electrode of the first output switch, so that the signal from the control electrode of the first output switch serves as the second output control signal to control the second output control switch on or off. This arrangement eliminates the need to connect the control electrodes of the first and second output control switches to additional external ports.

[0026] In some embodiments, the first signal input terminal and the second signal input terminal are used to connect to different ports, and the first signal output terminal and the second signal output terminal are used to connect to different ports.

[0027] In some embodiments, the level conversion circuit further includes an inverter, wherein the first signal input terminal and the input terminal of the inverter are connected to the same port, the second signal input terminal is connected to the output terminal of the inverter, and the first signal output terminal and the second signal output terminal are connected to different ports. This configuration can reduce the number of input terminals.

[0028] In a second aspect, embodiments of the present application further provide a chip comprising: an input circuit, an output circuit, and a level conversion circuit, wherein the input of the level conversion circuit is connected to the input circuit for receiving an input voltage from the input circuit. Furthermore, the output of the level conversion circuit is connected to the output circuit for transmitting an output voltage to the output circuit. The level conversion circuit is the level conversion circuit described in the first aspect or any possible implementation of the first aspect.

[0029] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a circuit board and a chip, wherein the chip is disposed on the circuit board, wherein the chip is the chip described in the second aspect or any possible implementation of the second aspect.

[0030] In addition, the technical effects of the corresponding schemes in the second and third aspects can refer to the technical effects that can be obtained by the corresponding scheme in the first aspect, and the repeated parts will not be described in detail. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0032] Figure 2 A schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0033] Figure 3 A schematic diagram of a circuit structure of a level conversion circuit provided in an embodiment of the present application;

[0034] Figure 4 A schematic diagram of another circuit structure of the level conversion circuit provided in an embodiment of the present application;

[0035] Figure 5 A schematic diagram of a specific circuit structure of a level conversion circuit provided in an embodiment of the present application;

[0036] Figure 6 A signal timing diagram provided in an embodiment of the present application;

[0037] Figure 7 A schematic diagram of another circuit structure of the level conversion circuit provided in an embodiment of the present application;

[0038] Figure 8A schematic diagram of another specific circuit structure of the level conversion circuit provided in an embodiment of the present application;

[0039] Figure 9a Another signal timing diagram provided in an embodiment of the present application;

[0040] Figure 9b Another signal timing diagram provided in an embodiment of the present application;

[0041] Figure 10 This is another specific circuit structure diagram of the level conversion circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operating methods in the method embodiments can also be applied to device embodiments or system embodiments. It should be noted that in the description of the present application, "multiple" can be understood as "at least two". In addition, it should be understood that in the description of the present application, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0043] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be modified as needed, and such modifications are included in the scope of protection of this application. The drawings of this application are only for illustrative purposes and do not represent true proportions.

[0044] It is understandable that the switch in the embodiment of the present application can be a switch tube, which includes, for example, but is not limited to, one or more of various types of switching devices such as a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), and a silicon carbide (SiC) MOSFET. The embodiment of the present application will not list them one by one. In addition, each switch can include a first electrode, a second electrode, and a control electrode, wherein the control electrode is used to control the closing or opening of the switch. When the switch is closed, current can be transmitted between the first electrode and the second electrode of the switch. When the switch is open, current cannot be transmitted between the first electrode and the second electrode of the switch. Taking MOSFET as an example, the control electrode of the switch is the gate, the first electrode of the switch can be the source, the second electrode can be the drain, or the first electrode can be the drain and the second electrode can be the source.

[0045] In order to facilitate understanding of the technical solution provided by the embodiments of the present application, its specific application scenario is first explained below.

[0046] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 1 In the embodiment of the present application, the electronic device includes a housing 100, a circuit board 200 and a chip 210 disposed in the housing 100, and the chip 210 is disposed on the circuit board 200. In addition to the chip 210, other electronic components may be disposed in the circuit board 200. The circuit board 200 may be used to supply power to the chip 210 and other electronic components or transmit signals.

[0047] Exemplarily, the electronic device can be a computer device with a chip, such as a server, a desktop computer, a personal computer, etc., or it can also be a portable electronic device with a processor chip, such as a mobile phone, a tablet computer, a car-mounted device, etc. The chip 210 can be a graphics processing unit (GPU), a central processing unit (CPU), an artificial intelligence (AI) chip, a system on chip (SoC), etc., which have logic operation capabilities, or can be other types of analog-to-digital converters, digital-to-analog converters, application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and other programmable logic devices, switch logic devices, hardware components, or any combination thereof. In the embodiment of the present application, the electronic device is described as a server as an example. In addition, the circuit board includes, for example, but is not limited to, a printed circuit board (PCB).

[0048] Figure 2 A schematic diagram of the structure of the chip provided in the embodiment of the present application. Figure 2 , chip 210 may include: an input circuit 211, an output circuit 213, and a level shifter circuit 212 (LS). The input end of the level shifter circuit 212 is connected to the input circuit 211, and the output end of the level shifter circuit 212 is connected to the output circuit 213. During operation, the input circuit 211 may output a signal, and the level shifter circuit 212 receives the signal, performs level shift on the signal, and outputs it to the output circuit 213. The output circuit 213 may perform corresponding operations based on the received signal. For example, the output circuit 213 may be a buffer or other types of circuits.

[0049] Typically, the level shifter circuit 212 is composed of a plurality of switches to realize the function of voltage conversion. Taking the switch as MOSFET as an example, as the semiconductor process evolves, the withstand voltage of MOSFET is also slowly reduced. For example, MOSFET evolves from the original withstand voltage 3.3V, 2.5V device to the withstand voltage 1.8V device. Under advanced semiconductor process, the withstand voltage of MOSFET is lower (for example, 1.8V or even 1.2V). And 3.3V is a common external power supply voltage. If 3.3V is input into the level shifter circuit 212 as the power supply voltage, it will cause the power supply voltage to exceed the withstand voltage of MOSFET, thereby causing MOSFET (especially the MOSFET connected to the signal output terminal) to have reliability degradation or failure problem. For this reason, the embodiment of the present application provides a level shifter circuit 212, which, when the power supply voltage is higher than the withstand voltage range of MOSFET, avoids the reliability degradation or failure problem of MOSFET.

[0050] Figure 3 A schematic diagram of a circuit structure of a level conversion circuit provided in an embodiment of the present application. Figure 3The level conversion circuit 212 may include: an input-output circuit 10 and a withstand voltage control circuit 20. The input-output circuit 10 includes: a first input switch KN1, a second input switch KN2, a first output control switch KS1, a second output control switch KS2, a first output switch KO1, a second output switch KO2, a third output switch KO3, a fourth output switch KO4, and a first selection switch KX1, a second selection switch KX2, a third selection switch KX3, and a fourth selection switch KX4. The control electrode of the first input switch KN1 is connected to the first signal input terminal VIN1, the first electrode of the first input switch KN1 is connected to the first power supply terminal VSS, the second electrode of the first input switch KN1 is connected to the first electrode of the first selection switch KX1, the second electrode of the first selection switch KX1 is connected to the first electrode of the first output switch KO1, the control electrode of the first output control switch KS1 is used to receive the first output control signal, the first electrode of the first output control switch KS1 is connected to the second power supply terminal VDDH, the second electrode of the first output control switch KS1 is connected to the first electrode of the second selection switch KX2, the second electrode of the second selection switch KX2 is connected to the first electrode of the second output switch KO2, and the second electrode of the first output switch KO1 and the second electrode of the second output switch KO2 are both connected to the first signal output terminal VOUT1 The control electrode of the second input switch KN2 is connected to the second signal input terminal VIN2, the first electrode of the second input switch KN2 is connected to the first power supply terminal VSS, the second electrode of the second input switch KN2 is connected to the first electrode of the third selection switch KX3, the second electrode of the third selection switch KX3 is connected to the first electrode of the third output switch KO3, the control electrode of the second output control switch KS2 is used to receive the second output control signal, the first electrode of the second output control switch KS2 is connected to the second power supply terminal VDDH, the second electrode of the second output control switch KS2 is connected to the first electrode of the fourth selection switch KX4, the second electrode of the fourth selection switch KX4 is connected to the first electrode of the fourth output switch KO4, and the second electrodes of the third output switch KO3 and the fourth output switch KO4 are both connected to the second signal output terminal VOUT2. Furthermore, the control electrodes of the first selection switch KX1, the second selection switch KX2, the third selection switch KX3, and the fourth selection switch KX4 are all connected to the selection control terminal XC.

[0051] With this arrangement, when the power supply voltage input to the second power supply terminal VDDH exceeds the upper limit of the withstand voltage range of a single switch in the input-output circuit 10, the first signal output terminal VOUT1 is pulled low through the first input switch KN1, the first selection switch KX1, and the first output switch KO1, thereby ensuring that the first input switch KN1, the first selection switch KX1, and the first output switch KO1 will not experience reliability degradation or failure.

[0052] Furthermore, when the power supply voltage input to the second power supply terminal VDDH exceeds the upper limit of the withstand voltage range of a single switch in the input-output circuit 10, the first signal output terminal VOUT1 is pulled high through the first output control switch KS1, the second selection switch KX2, and the second output switch KO2, thereby ensuring that the first output control switch KS1, the second selection switch KX2, and the second output switch KO2 will not experience reliability degradation or failure.

[0053] Furthermore, when the power supply voltage input to the second power supply terminal VDDH exceeds the upper limit of the withstand voltage range of a single switch in the input-output circuit 10, the second signal output terminal VOUT2 is pulled low through the second input switch KN2, the third selection switch KX3, and the third output switch KO3, thereby ensuring that the second input switch KN2, the third selection switch KX3, and the third output switch KO3 will not experience reliability degradation or failure.

[0054] Furthermore, when the power supply voltage input to the second power supply terminal VDDH exceeds the upper limit of the withstand voltage range of a single switch in the input-output circuit 10, the second signal output terminal VOUT2 is pulled high through the second output control switch KS2, the fourth selection switch KX4, and the fourth output switch KO4, thereby ensuring that the second output control switch KS2, the fourth selection switch KX4, and the fourth output switch KO4 will not experience reliability degradation or failure.

[0055] In a specific implementation, the voltage of the second power supply terminal VDDH is greater than the voltage of the first power supply terminal VSS. Based on this, when the voltage of the second power supply terminal VDDH is input to the first signal output terminal VOUT1, the voltage of the first signal output terminal VOUT1 can be pulled up. When the voltage of the first power supply terminal VSS is input to the first signal output terminal VOUT1, the voltage of the first signal output terminal VOUT1 can be pulled down. Similarly, when the voltage of the second power supply terminal VDDH is input to the second signal output terminal VOUT2, the voltage of the second signal output terminal VOUT2 can be pulled up. When the voltage of the first power supply terminal VSS is input to the second signal output terminal VOUT2, the voltage of the second signal output terminal VOUT2 can be pulled down.

[0056] The level conversion circuit 212 in the embodiment of the present application can be used in scenarios where differential signals are level converted. Based on this, the signals input to the first signal input terminal VIN1 and the second signal input terminal VIN2 can be differential signals, and the signals output by the first signal output terminal VOUT1 and the second signal output terminal VOUT2 can also be differential signals. Furthermore, the first signal input terminal VIN1 and the second signal input terminal VIN2 can be connected to different ports, which can be the output terminals of the input circuit 211. In addition, the first signal output terminal VOUT1 and the second signal output terminal VOUT2 can also be connected to different ports, which can be the input terminals of the output circuit 213.

[0057] In the embodiment of the present application, the first output control signal and the second output control signal can be inputted from two different ports respectively, or the first output control signal and the second output control signal can be inputted from the same port. Further, in order to reduce the number of external ports connected to the level conversion circuit 212 and reduce the wiring difficulty, refer to Figure 3 The control electrode of the first output control switch KS1 can be connected to the control electrode of the third output switch KO3, so that the signal at the control electrode of the third output switch KO3 serves as the first output control signal to control the first output control switch KS1 to be turned on or off. Furthermore, the control electrode of the second output control switch KS2 can be connected to the control electrode of the first output switch KO1, so that the signal at the control electrode of the first output switch KO1 serves as the second output control signal to control the second output control switch KS2 to be turned on or off. This configuration eliminates the need to connect the control electrodes of the first output control switch KS1 and the second output control switch KS2 to an external port.

[0058] For example, referring to Figure 3 The first input switch KN1, the second input switch KN2, the first output switch KO1, the third output switch KO3, the first selection switch KX1, and the third selection switch KX3 can all be configured as N-type switching transistors, and the first output control switch KS1, the second output control switch KS2, the second output switch KO2, the fourth output switch KO4, the second selection switch KX2, and the fourth selection switch KX4 can all be configured as P-type switching transistors. Of course, in actual applications, the first input switch KN1, the second input switch KN2, the first output switch KO1, the third output switch KO3, the first selection switch KX1, and the third selection switch KX3 can all be configured as P-type switching transistors, and the first output control switch KS1, the second output control switch KS2, the second output switch KO2, the fourth output switch KO4, the second selection switch KX2, and the fourth selection switch KX4 can all be configured as N-type switching transistors.

[0059] Continue to refer to Figure 3The first input terminal of the withstand voltage control circuit 20 is connected to the first withstand voltage control terminal NC1, the second input terminal is connected to the first signal output terminal VOUT1, the third input terminal is connected to the second signal output terminal VOUT2, the first output terminal is connected to the control electrode of the first output switch KO1, the second output terminal is connected to the control electrode of the second output switch KO2, the third output terminal is connected to the control electrode of the third output switch KO3, and the fourth output terminal is connected to the control electrode of the fourth output switch KO4. Therefore, by providing the withstand voltage control circuit 20, when the power supply voltage input to the second power supply terminal VDDH exceeds the upper limit of the withstand voltage range of a single switch in the input-output circuit 10, the withstand voltage control circuit 20 can adjust the voltage of the control electrodes of the first output switch KO1, the second output switch KO2, the third output switch KO3, and the fourth output switch KO4, so that the voltage difference between the control electrodes and the second electrodes of the first output switch KO1, the second output switch KO2, the third output switch KO3, and the fourth output switch KO4 is less than or equal to the upper limit of the withstand voltage range, thereby ensuring that the first output switch KO1, the second output switch KO2, the third output switch KO3, and the fourth output switch KO4 will not experience reliability degradation or failure.

[0060] Specifically, the withstand voltage control circuit 20 can output the voltage of the first withstand voltage control terminal NC1 or the first signal output terminal VOUT1 to the control electrode of the first output switch KO1, so as to adjust the voltage of the control electrode of the first output switch KO1 according to the voltage of the first withstand voltage control terminal NC1 or the first signal output terminal VOUT1, so that the voltage difference between the control electrode of the first output switch KO1 and the first signal output terminal VOUT1 is less than or equal to the upper limit of the withstand voltage range of the first output switch KO1, thereby avoiding reliability degradation or failure of the first output switch KO1.

[0061] The withstand voltage control circuit 20 can also output the voltage of the first withstand voltage control terminal NC1 or the first signal output terminal VOUT1 to the control electrode of the second output switch KO2, so as to adjust the voltage of the control electrode of the second output switch KO2 according to the voltage of the first withstand voltage control terminal NC1 or the first signal output terminal VOUT1, so that the voltage difference between the control electrode of the second output switch KO2 and the first signal output terminal VOUT1 is less than or equal to the upper limit of the withstand voltage range of the second output switch KO2, thereby avoiding reliability degradation or failure of the second output switch KO2.

[0062] The withstand voltage control circuit 20 can also output the voltage of the first withstand voltage control terminal NC1 or the second signal output terminal VOUT2 to the control electrode of the third output switch KO3, so as to adjust the voltage of the control electrode of the third output switch KO3 according to the voltage of the first withstand voltage control terminal NC1 or the second signal output terminal VOUT2, so that the voltage difference between the control electrode of the third output switch KO3 and the second signal output terminal VOUT2 is less than or equal to the upper limit of the withstand voltage range of the third output switch KO3, thereby avoiding reliability degradation or failure of the third output switch KO3.

[0063] The withstand voltage control circuit 20 can also output the voltage of the first withstand voltage control terminal NC1 or the second signal output terminal VOUT2 to the control electrode of the fourth output switch KO4, so as to adjust the voltage of the control electrode of the fourth output switch KO4 according to the voltage of the first withstand voltage control terminal NC1 or the second signal output terminal VOUT2, so that the voltage difference between the control electrode of the fourth output switch KO4 and the second signal output terminal VOUT2 is less than or equal to the upper limit of the withstand voltage range of the fourth output switch KO4, thereby avoiding reliability degradation or failure of the fourth output switch KO4.

[0064] It is understood that the voltage of the first withstand voltage control terminal NC1 is less than or equal to the upper limit of the withstand voltage range of a single switch in the input / output circuit 10. The voltage of the selection control terminal XC is less than or equal to the upper limit of the withstand voltage range of a single switch in the input / output circuit 10.

[0065] Figure 4 This is another circuit structure diagram of the level conversion circuit provided in the embodiment of the present application, referring to Figure 4 The withstand voltage control circuit 20 may include: a first withstand voltage control sub-circuit 21, a second withstand voltage control sub-circuit 22, a third withstand voltage control sub-circuit 23 and a fourth withstand voltage control sub-circuit 24. The first withstand voltage control sub-circuit 21, the second withstand voltage control sub-circuit 22, the third withstand voltage control sub-circuit 23 and the fourth withstand voltage control sub-circuit 24 can avoid reliability degradation or failure of the switch.

[0066] The first withstand voltage control sub-circuit 21 has a first input terminal connected to the first withstand voltage control terminal NC1, a second input terminal connected to the first signal output terminal VOUT1, and an output terminal connected to the gate electrode of the first output switch KO1. Furthermore, the first withstand voltage control sub-circuit 21 is configured to output the voltage at the first withstand voltage control terminal NC1 or the first signal output terminal VOUT1 to the gate electrode of the first output switch KO1 in response to the voltages at the first withstand voltage control terminal NC1 and the first signal output terminal VOUT1. With this configuration, the first withstand voltage control sub-circuit 21 can input the voltage at the first withstand voltage control terminal NC1 or the first signal output terminal VOUT1 to the gate electrode of the first output switch KO1 under the control of the voltage at one or both of the first withstand voltage control terminal NC1 and the first signal output terminal VOUT1, thereby adjusting the voltage at the gate electrode of the first output switch KO1. This can ensure that the voltage difference between the gate electrode of the first output switch KO1 and the first signal output terminal VOUT1 is less than or equal to the upper limit of the withstand voltage range of the first output switch KO1, thereby preventing reliability degradation or failure of the first output switch KO1.

[0067] The second withstand voltage control sub-circuit 22 has a first input terminal connected to the first withstand voltage control terminal NC1, a second input terminal connected to the first signal output terminal VOUT1, and an output terminal connected to the control electrode of the second output switch KO2. Furthermore, the second withstand voltage control sub-circuit 22 is configured to output the voltage of the first withstand voltage control terminal NC1 or the first signal output terminal VOUT1 to the control electrode of the second output switch KO2 in response to the voltages of the first withstand voltage control terminal NC1 and the first signal output terminal VOUT1. With this configuration, the second withstand voltage control sub-circuit 22 can input the voltage of the first withstand voltage control terminal NC1 or the first signal output terminal VOUT1 to the control electrode voltage of the second output switch KO2 under the control of the voltage of one or both of the first withstand voltage control terminal NC1 and the first signal output terminal VOUT1, thereby adjusting the voltage of the control electrode of the second output switch KO2 so that the voltage difference between the control electrode of the second output switch KO2 and the first signal output terminal VOUT1 is less than or equal to the upper limit of the withstand voltage range of the second output switch KO2, thereby preventing reliability degradation or failure of the second output switch KO2.

[0068] The third withstand voltage control subcircuit 23 has a first input terminal connected to the first withstand voltage control terminal NC1, a second input terminal connected to the second signal output terminal VOUT2, and an output terminal connected to the control electrode of the third output switch KO3. The third withstand voltage control subcircuit 23 is configured to output the voltage of the first withstand voltage control terminal NC1 or the second signal output terminal VOUT2 to the control electrode of the third output switch KO3 in response to the voltage of the first withstand voltage control terminal NC1 and the second signal output terminal VOUT2. With this arrangement, the third withstand voltage control subcircuit 23 can input the voltage of the first withstand voltage control terminal NC1 or the second signal output terminal VOUT2 to the control electrode of the third output switch KO3 under the control of the voltage of one or both of the first withstand voltage control terminal NC1 and the second signal output terminal VOUT2, thereby adjusting the voltage of the control electrode of the third output switch KO3 so that the voltage difference between the control electrode of the third output switch KO3 and the second signal output terminal VOUT2 is less than or equal to the upper limit of the withstand voltage range of the third output switch KO3, thereby preventing reliability degradation or failure of the third output switch KO3.

[0069] The fourth withstand voltage control subcircuit 24 has a first input terminal connected to the first withstand voltage control terminal NC1, a second input terminal connected to the second signal output terminal VOUT2, and an output terminal connected to the control electrode of the fourth output switch KO4. The fourth withstand voltage control subcircuit 24 is configured to output the voltage of the first withstand voltage control terminal NC1 or the second signal output terminal VOUT2 to the control electrode of the fourth output switch KO4 in response to the voltage of the first withstand voltage control terminal NC1 or the second signal output terminal VOUT2. With this configuration, the fourth withstand voltage control subcircuit 24 can input the voltage of the first withstand voltage control terminal NC1 or the second signal output terminal VOUT2 to the control electrode of the fourth output switch KO4 under the control of the voltage of one or both of the first withstand voltage control terminal NC1 and the second signal output terminal VOUT2, thereby adjusting the voltage of the control electrode of the fourth output switch KO4 so that the voltage difference between the control electrode of the fourth output switch KO4 and the second signal output terminal VOUT2 is less than or equal to the upper limit of the withstand voltage range of the fourth output switch KO4, thereby preventing reliability degradation or failure of the fourth output switch KO4.

[0070] In the embodiment of the present application, switches can be used to form the above-mentioned voltage-withstand control subcircuit.

[0071] Figure 5 A specific circuit structure diagram of the level conversion circuit provided in the embodiment of the present application is shown in FIG. Figure 5The first withstand voltage control subcircuit 21 may include a first control switch KC1 and a second control switch KC2. The control electrode of the first control switch KC1 is connected to the first withstand voltage control terminal NC1, the first electrode of the first control switch KC1 is connected to the first signal output terminal VOUT1, and the second electrode of the first control switch KC1 is connected to the control electrode of the first output switch KO1. Furthermore, the control electrode of the second control switch KC2 is connected to the first signal output terminal VOUT1, the first electrode of the second control switch KC2 is connected to the first withstand voltage control terminal NC1, and the second electrode of the second control switch KC2 is connected to the control electrode of the first output switch KO1. This configuration achieves a simple structure for the first withstand voltage control subcircuit 21, making it easier to use and reducing production costs. For example, the first control switch KC1 and the second control switch KC2 can be configured as P-type switching transistors. Of course, in actual applications, the first control switch KC1 and the second control switch KC2 can also be configured as N-type switching transistors.

[0072] The second withstand voltage control subcircuit 22 may include a third control switch KC3 and a fourth control switch KC4. The control electrode of the third control switch KC3 is connected to the first withstand voltage control terminal NC1, the first electrode of the third control switch KC3 is connected to the first signal output terminal VOUT1, and the second electrode of the third control switch KC3 is connected to the control electrode of the second output switch KO2. Furthermore, the control electrode of the fourth control switch KC4 is connected to the first signal output terminal VOUT1, the first electrode of the fourth control switch KC4 is connected to the first withstand voltage control terminal NC1, and the second electrode of the fourth control switch KC4 is connected to the control electrode of the second output switch KO2. This configuration achieves a simple structure for the second withstand voltage control subcircuit 22, making it easier to use and reducing production costs. For example, the third control switch KC3 and the fourth control switch KC4 can be configured as N-type switching transistors. Of course, in actual applications, the third control switch KC3 and the fourth control switch KC4 can also be configured as P-type switching transistors.

[0073] The third withstand voltage control subcircuit 23 may include a sixth control switch KC6 and a seventh control switch KC7. The control electrode of the sixth control switch KC6 is connected to the first withstand voltage control terminal NC1, the first electrode of the sixth control switch KC6 is connected to the second signal output terminal VOUT2, and the second electrode of the sixth control switch KC6 is connected to the control electrode of the third output switch KO3. Furthermore, the control electrode of the seventh control switch KC7 is connected to the second signal output terminal VOUT2, the first electrode of the seventh control switch KC7 is connected to the first withstand voltage control terminal NC1, and the second electrode of the seventh control switch KC7 is connected to the control electrode of the third output switch KO3. This configuration achieves a simple structure for the third withstand voltage control subcircuit 23, making it easier to implement and reducing production costs. For example, the sixth and seventh control switches KC6 and KC7 can be configured as P-type switching transistors. Of course, in actual applications, the sixth and seventh control switches KC6 and KC7 can also be configured as N-type switching transistors.

[0074] The fourth withstand voltage control subcircuit 24 may include an eighth control switch KC8 and a ninth control switch KC9. The control electrode of the eighth control switch KC8 is connected to the first withstand voltage control terminal NC1, the first electrode of the eighth control switch KC8 is connected to the second signal output terminal VOUT2, and the second electrode of the eighth control switch KC8 is connected to the control electrode of the fourth output switch KO4. Furthermore, the control electrode of the ninth control switch KC9 is connected to the second signal output terminal VOUT2, the first electrode of the ninth control switch KC9 is connected to the first withstand voltage control terminal NC1, and the second electrode of the ninth control switch KC9 is connected to the control electrode of the fourth output switch KO4. This configuration achieves a simple structure for the fourth withstand voltage control subcircuit 24, making it easier to implement and reducing production costs. This configuration achieves the functions of the fourth withstand voltage control subcircuit 24. For example, the eighth control switch KC8 and the ninth control switch KC9 may be configured as N-type switching transistors. Of course, in actual applications, the eighth control switch KC8 and the ninth control switch KC9 may also be configured as P-type switching transistors.

[0075] It is understandable that the above is only an example to illustrate the specific structure of the voltage-resistant control circuit 20 provided in the embodiment of the present application. In specific implementation, the specific structure of the voltage-resistant control circuit 20 is not limited to the above structure provided in the embodiment of the present application, and can also be other structures known to those skilled in the art, which is not limited here.

[0076] The level conversion circuit 212 in the present application can avoid reliability degradation or failure of each output switch when the voltage at the second power supply terminal VDDH is higher than the upper limit of the voltage resistance range of a single switch in the input-output circuit 10. Based on this, the voltage Vddl at the first voltage resistance control terminal NC1 can satisfy the following relationship: Vddh-Vddl≤Vmax, where Vmax represents the upper limit of the voltage resistance range of a single switch.

[0077] Below Figure 5 Taking the structure shown as an example, combined with the signal timing diagram, when the voltage at the second power supply terminal VDDH is higher than the upper limit of the withstand voltage range of a single switch in the input-output circuit 10, the working process of the level conversion circuit 212 provided in the embodiment of the present application is specifically described.

[0078] Figure 6 A signal timing diagram provided in an embodiment of the present application. Figure 6 Assume that the voltage of the second power supply terminal VDDH is 3.3V, the voltage of the first power supply terminal VSS is 0V, the upper limit of the voltage range of the single switch is 1.8V, the voltage of the first voltage-withstand control terminal NC1 is 1.8V or half of 3.3V, the voltage of the selection control terminal XC is 1.8V, and the signals input by the first signal input terminal VIN1 and the second signal input terminal VIN2 are voltages that alternate between 0V and 1.8V. Here, vin1 represents the signal of the first signal input terminal VIN1, vin2 represents the signal of the second signal input terminal VIN2, vko1 represents the signal of the control electrode of the first output switch KO1, vko2 represents the signal of the control electrode of the second output switch KO2, vko3 represents the signal of the control electrode of the third output switch KO3, vko4 represents the signal of the control electrode of the fourth output switch KO4, vout1 represents the signal of the first signal output terminal VOUT1, vout2 represents the signal of the second signal output terminal VOUT2, and xc represents the signal of the selection control terminal XC.

[0079] In stage t1, the first input switch KN1, the first output switch KO1, the second output switch KO2, the second output control switch KS2, the third output switch KO3, the fourth output switch KO4, the second control switch KC2, the third control switch KC3, the sixth control switch KC6 and the ninth control switch KC9 are all turned on, while the second input switch KN2, the first output control switch KS1, the first control switch KC1, the fourth control switch KC4, the seventh control switch KC7 and the eighth control switch KC8 are all turned off. Then, the voltage of the first power supply terminal VSS is input to the first signal output terminal VOUT1 through the first input switch KN1, the first selection switch KX1 and the first output switch KO1, pulling the first signal output terminal VOUT1 down to 0V, thereby ensuring that the first input switch KN1, the first selection switch KX1 and the first output switch KO1 will not experience reliability degradation or failure. The voltage of the second power supply terminal VDDH is input to the second signal output terminal VOUT2 through the first output control switch KS1, the second selection switch KX2, and the second output switch KO2, raising the second signal output terminal VOUT2 to 3.3V. This ensures that the first output control switch KS1, the second selection switch KX2, and the second output switch KO2 will not experience reliability degradation or failure. Furthermore, the voltage of the first withstand voltage control terminal NC1 is input to the control electrode of the first output switch KO1 and the control electrode of the fourth output switch KO4, respectively, ensuring that the voltage of the control electrode of the first output switch KO1 and the control electrode of the fourth output switch KO4 are both 1.8V. The self-protection circuit formed by the first control switch KC1 and the second control switch KC2 ensures that the voltage difference between the control electrode of the first output switch KO1 and the first signal output terminal VOUT1 is 1.8V, meeting the withstand voltage range of the first output switch KO1. The eighth control switch KC8 and the ninth control switch KC9 form a self-protection circuit, which can ensure that the voltage difference between the control electrode of the fourth output switch KO4 and the second signal output terminal VOUT2 is 1.5V, also meeting the withstand voltage range of the fourth output switch KO4. Furthermore, the third control switch KC3 and the fourth control switch KC4 form a self-protection circuit, which can ensure that the voltage at the first signal output terminal VOUT1 is input to the control electrode of the second output switch KO2. The voltage difference between the control electrode of the second output switch KO2 and the first signal output terminal VOUT1 is 0V, meeting the withstand voltage range of the second output switch KO2. The sixth control switch KC6 and the seventh control switch KC7 form a self-protection circuit, which can ensure that the voltage at the second signal output terminal VOUT2 is input to the control electrode of the third output switch KO3. The voltage difference between the control electrode of the third output switch KO3 and the second signal output terminal VOUT2 is 0V, meeting the withstand voltage range of the third output switch KO3.Therefore, it can be ensured that the first to fourth output switches KO1 to KO4 all meet their withstand voltage ranges, thereby preventing the first to fourth output switches KO1 to KO4 from experiencing reliability degradation or failure.

[0080] In stage t2, the second input switch KN2, the first output switch KO1, the second output switch KO2, the first output control switch KS1, the third output switch KO3, the fourth output switch KO4, the first control switch KC1, the fourth control switch KC4, the seventh control switch KC7 and the eighth control switch KC8 are all turned on, while the first input switch KN1, the second output control switch KS2, the second control switch KC2, the third control switch KC3, the sixth control switch KC6 and the ninth control switch KC9 are all turned off. Then, the voltage of the first power supply terminal VSS is input to the second signal output terminal VOUT2 through the second input switch KN2, the third selection switch KX3 and the third output switch KO3, pulling the second signal output terminal VOUT2 down to 0V, thereby ensuring that the second input switch KN2, the third selection switch KX3 and the third output switch KO3 will not experience reliability degradation or failure problems. The voltage of the second power supply terminal VDDH is input to the first signal output terminal VOUT1 through the second output control switch KS2, the fourth selection switch KX4, and the fourth output switch KO4, raising the first signal output terminal VOUT1 to 3.3V. This ensures that the second output control switch KS2, the fourth selection switch KX4, and the fourth output switch KO4 will not experience reliability degradation or failure. Furthermore, the voltage of the first withstand voltage control terminal NC1 is input to the control electrodes of the second output switch KO2 and the third output switch KO3, respectively, ensuring that the voltages of the control electrodes of the second output switch KO2 and the third output switch KO3 are both 1.8V. The self-protection circuit formed by the third control switch KC3 and the fourth control switch KC4 ensures that the voltage difference between the control electrode of the second output switch KO2 and the first signal output terminal VOUT1 is 1.5V, meeting the withstand voltage range of the second output switch KO2. The sixth control switch KC6 and the seventh control switch KC7 form a self-protection circuit, which can ensure that the voltage difference between the control electrode of the third output switch KO3 and the second signal output terminal VOUT2 is 1.8V, also meeting the withstand voltage range of the third output switch KO3. Furthermore, the first control switch KC1 and the second control switch KC2 form a self-protection circuit, which can ensure that the voltage at the first signal output terminal VOUT1 is input to the control electrode of the first output switch KO1. The voltage difference between the control electrode of the first output switch KO1 and the first signal output terminal VOUT1 is 0V, meeting the withstand voltage range of the first output switch KO1. The eighth control switch KC8 and the ninth control switch KC9 form a self-protection circuit, which can ensure that the voltage at the second signal output terminal VOUT2 is input to the control electrode of the fourth output switch KO4. The voltage difference between the control electrode of the fourth output switch KO4 and the second signal output terminal VOUT2 is 0V, meeting the withstand voltage range of the fourth output switch KO4.Therefore, it can be ensured that the first to fourth output switches KO1 to KO4 all meet their withstand voltage ranges, thereby preventing the first to fourth output switches KO1 to KO4 from experiencing reliability degradation or failure.

[0081] Afterwards, the operation process of the level conversion circuit 212 may repeat the operation in the t1 phase and the t2 phase, and details thereof will not be repeated here.

[0082] It can be seen from the above embodiments that when the voltage input to the second power supply terminal VDDH is greater than the upper limit of the voltage-withstand range of a single switch, the operation of each switch in the voltage-withstand control circuit 20 can enable each output switch to operate within the voltage-withstand range. Therefore, based on the application scenario where the voltage input to the second power supply terminal VDDH is greater than the upper limit of the voltage-withstand range of a single switch, the level conversion circuit 212 in the embodiment of the present application can be applied.

[0083] In some other application scenarios, if the voltage of the second power supply terminal VDDH input is greater than the upper limit of the voltage withstand range of a single switch during a period of time, for example, the voltage of the second power supply terminal VDDH input is 3.3V, the level shifter circuit 212 needs to be used in a 3.3V scenario. During another period of time, if the voltage of the second power supply terminal VDDH input is less than the upper limit of the voltage withstand range of a single switch, for example, the voltage of the second power supply terminal VDDH input is reduced to 1.8V, the level shifter circuit 212 needs to be used in a 1.8V scenario. In the prior art, in order to meet the requirements of these two scenarios, two different level shifter circuits 212 are usually provided, resulting in the level shifter circuit 212 occupying a large chip area and increasing costs. To this end, embodiments of the present application provide another level shifter circuit 212. Through a switching control process, the level shifter circuit 212 can be switched between a 3.3V scenario and a 1.8V scenario, thereby eliminating the need for additional level shifters 212, reducing the chip area occupied by the level shifter circuit 212 and reducing costs.

[0084] Figure 7 This is another circuit structure diagram of the level conversion circuit provided in the embodiment of the present application, referring to Figure 7 The withstand voltage control circuit 20 may include a first withstand voltage control sub-circuit 21, a second withstand voltage control sub-circuit 22, a third withstand voltage control sub-circuit 23 and a fourth withstand voltage control sub-circuit 24, and the specific structures of the first withstand voltage control sub-circuit 21, the second withstand voltage control sub-circuit 22, the third withstand voltage control sub-circuit 23 and the fourth withstand voltage control sub-circuit 24 may also refer to the contents in the above embodiments, and will not be elaborated here.

[0085] Furthermore, the second withstand voltage control subcircuit 22 includes not only the third control switch KC3 and the fourth control switch KC4, but also a fifth control switch KC5. The control electrode of the fifth control switch KC5 is connected to the second withstand voltage control terminal NC2, the first electrode of the fifth control switch KC5 is connected to the first withstand voltage control terminal NC1, and the second electrode of the fifth control switch KC5 is connected to the control electrode of the second output switch KO2. For example, the fifth control switch KC5 can be configured as an N-type switching transistor. Of course, in practical applications, the fifth control switch KC5 can also be configured as a P-type switching transistor.

[0086] Furthermore, the fourth withstand voltage control subcircuit 24 includes not only the eighth control switch KC8 and the ninth control switch KC9, but also the tenth control switch KC10. The control electrode of the tenth control switch KC10 is connected to the second withstand voltage control terminal NC2, the first electrode of the tenth control switch KC10 is connected to the first withstand voltage control terminal NC1, and the second electrode of the tenth control switch KC10 is connected to the control electrode of the fourth output switch KO4. For example, the tenth control switch KC10 can be configured as an N-type switch. Of course, in practical applications, the tenth control switch KC10 can also be configured as a P-type switch.

[0087] Reference Figure 7The level conversion circuit 212 may further include: a first conduction control circuit 31 and a second conduction control circuit 32. The input of the first conduction control circuit 31 is connected to the second electrode of the first input switch KN1, and the output of the first conduction control circuit 31 is connected to the control electrode of the first output switch KO1. The first conduction control circuit 31 is used to control the connection or disconnection between the second electrode of the first input switch KN1 and the control electrode of the first output switch KO1. Furthermore, the input of the second conduction control circuit 32 is connected to the second electrode of the second input switch KN2, and the output of the second conduction control circuit 32 is connected to the control electrode of the third output switch KO3. The second conduction control circuit 32 is used to control the connection or disconnection between the second electrode of the second input switch KN2 and the control electrode of the third output switch KO3. During operation, if the voltage at the second power supply terminal VDDH is greater than the upper limit of the withstand voltage range of the single switch, for example, if the voltage at the second power supply terminal VDDH is 3.3V, the first conduction control circuit 31 is controlled to disconnect the second electrode of the first input switch KN1 from the control electrode of the first output switch KO1, and the second conduction control circuit 32 is controlled to disconnect the second electrode of the second input switch KN2 from the control electrode of the third output switch KO3. If the voltage at the second power supply terminal VDDH is less than the upper limit of the withstand voltage range of the single switch, for example, if the voltage at the second power supply terminal VDDH drops to 1.8V, the first conduction control circuit 31 is controlled to connect the second electrode of the first input switch KN1 to the control electrode of the first output switch KO1, and the second conduction control circuit 32 is controlled to connect the second electrode of the second input switch KN2 to the control electrode of the third output switch KO3.

[0088] In the embodiment of the present application, switches may be used to form the first conduction control circuit 31 and the second conduction control circuit 32 .

[0089] Figure 8 This is another specific circuit structure diagram of the level conversion circuit provided in the embodiment of the present application, referring to Figure 8The first conduction control circuit 31 may include a first conduction control switch KD1 and a second conduction control switch KD2. The control electrode of the first conduction control switch KD1 is connected to the first conduction control terminal DT1, the first electrode of the first conduction control switch KD1 is connected to the second electrode of the first input switch KN1, and the second electrode of the first conduction control switch KD1 is connected to the first electrode of the second conduction control switch KD2. Furthermore, the control electrode of the second conduction control switch KD2 is connected to the second conduction control terminal DT2, and the second electrode of the second conduction control switch KD2 is connected to the control electrode of the first output switch KO1. This configuration achieves a simple structure for the first conduction control circuit 31, making it easier to use and reducing production costs. For example, the first conduction control switch KD1 and the second conduction control switch KD2 can be configured as N-type switching transistors. Of course, in actual applications, the first conduction control switch KD1 and the second conduction control switch KD2 can also be configured as P-type switching transistors.

[0090] The second conduction control circuit 32 may include a third conduction control switch KD3 and a fourth conduction control switch KD4. The control electrode of the third conduction control switch KD3 is connected to the first conduction control terminal DT1, the first electrode of the third conduction control switch KD3 is connected to the second electrode of the second input switch KN2, and the second electrode of the third conduction control switch KD3 is connected to the first electrode of the fourth conduction control switch KD4. Furthermore, the control electrode of the fourth conduction control switch KD4 is connected to the second conduction control terminal DT2, and the second electrode of the fourth conduction control switch KD4 is connected to the control electrode of the third output switch KO3. This configuration achieves a simple second conduction control circuit 32, making it easier to use and reducing production costs. For example, the third conduction control switch KD3 and the fourth conduction control switch KD4 can be configured as N-type switching transistors. Of course, in actual applications, the third conduction control switch KD3 and the fourth conduction control switch KD4 can also be configured as P-type switching transistors.

[0091] The level shifter circuit 212 of the present application can prevent reliability degradation or failure of each output switch when the voltage at the second power supply terminal VDDH is higher than the upper limit of the withstand voltage range of a single switch. To this end, the voltage at the second withstand voltage control terminal NC2 can be set to 0V, and the voltage at the first withstand voltage control terminal NC1, Vddl, can satisfy the following relationship: Vddh - Vddl ≤ Vmax, where Vmax represents the upper limit of the withstand voltage range of a single switch. When the voltage at the second power supply terminal VDDH is less than or equal to the upper limit of the withstand voltage range of a single switch, the voltage at the first withstand voltage control terminal NC1, Vddl, can be set to 0V, and the voltage at the second withstand voltage control terminal NC2 can be set to less than or equal to the upper limit of the withstand voltage range of the single switch. For example, the voltage at the second withstand voltage control terminal NC2 can be set to 1.8V.

[0092] Below Figure 8 Taking the structure shown as an example, combined with the signal timing diagram, when the voltage at the second power supply terminal VDDH is higher than the upper limit of the withstand voltage range of a single switch, the working process of the level conversion circuit 212 provided in the embodiment of the present application is specifically described.

[0093] Figure 9a Another signal timing diagram provided in the embodiment of the present application. Figure 9a For example, the voltage of the second power supply terminal VDDH is 3.3V, the voltage of the first power supply terminal VSS is 0V, the upper limit of the voltage range of the single switch is 1.8V, the voltage of the first voltage-withstand control terminal NC1 is 1.8V or half of 3.3V, the voltage of the second voltage-withstand control terminal NC2 is 0V, the voltage of the selection control terminal XC is 1.8V, and the signals input by the first signal input terminal VIN1 and the second signal input terminal VIN2 are voltages that alternate between 0V and 1.8V. Among them, vin1 represents the signal of the first signal input terminal VIN1, vin2 represents the signal of the second signal input terminal VIN2, vko1 represents the signal of the control electrode of the first output switch KO1, vko2 represents the signal of the control electrode of the second output switch KO2, vko3 represents the signal of the control electrode of the third output switch KO3, vko4 represents the signal of the control electrode of the fourth output switch KO4, vout1 represents the signal of the first signal output terminal VOUT1, vout2 represents the signal of the second signal output terminal VOUT2, xc represents the signal of the selection control terminal XC, da1 represents the signal of the first conduction control terminal DT1, and da2 represents the signal of the second conduction control terminal DT2.

[0094] In stage t1, the first input switch KN1, the first selection switch KX1, the first output switch KO1, the second output switch KO2, the second selection switch KX2, the second output control switch KS2, the fourth selection switch KX4, the third output switch KO3, the fourth output switch KO4, the third selection switch KX3, the second control switch KC2, the third control switch KC3, the sixth control switch KC6 and the ninth control switch KC9 are all turned on, while the second input switch KN2, the first output control switch KS1, the first control switch KC1, the fourth control switch KC4, the fifth control switch KC5, the seventh control switch KC7, the eighth control switch KC8 and the tenth control switch KC10 are all turned off. Then, the voltage of the first power supply terminal VSS is input to the first signal output terminal VOUT1, pulling the first signal output terminal VOUT1 down to 0V, and the voltage of the second power supply terminal VDDH is input to the second signal output terminal VOUT2, pulling the second signal output terminal VOUT2 up to 3.3V. Furthermore, the voltage of the first withstand voltage control terminal NC1 is input to the control electrodes of the first output switch KO1 and the fourth output switch KO4, respectively, so that the voltages of the control electrodes of the first output switch KO1 and the fourth output switch KO4 are both 1.8V. The first control switch KC1 and the second control switch KC2 form a self-protection circuit, which can reduce the voltage difference between the control electrode of the first output switch KO1 and the first signal output terminal VOUT1 to 1.8V, meeting the withstand voltage range of the first output switch KO1. The eighth control switch KC8, the ninth control switch KC9, and the tenth control switch KC10 form a self-protection circuit, which can reduce the voltage difference between the control electrode of the fourth output switch KO4 and the second signal output terminal VOUT2 to 1.5V, also meeting the withstand voltage range of the fourth output switch KO4. Furthermore, the third, fourth, and fifth control switches KC3, KC4, and KC5 form a self-protection circuit, allowing the voltage at the first signal output terminal VOUT1 to be input to the control electrode of the second output switch KO2. This results in a voltage difference of 0V between the control electrode of the second output switch KO2 and the first signal output terminal VOUT1, meeting the withstand voltage range of the second output switch KO2. The sixth and seventh control switches KC6 and KC7 form a self-protection circuit, allowing the voltage at the second signal output terminal VOUT2 to be input to the control electrode of the third output switch KO3. This results in a voltage difference of 0V between the control electrode of the third output switch KO3 and the second signal output terminal VOUT2, meeting the withstand voltage range of the third output switch KO3. This ensures that the first through fourth output switches KO1 through KO4 meet their withstand voltage ranges, preventing reliability degradation or failure of the first through fourth output switches KO1 through KO4. Furthermore, by pulling down the first signal output terminal VOUT1 through the first input switch KN1, the first selection switch KX1, and the first output switch KO1, the withstand voltage issues of each switch can be overcome.Furthermore, the second signal output terminal VOUT2 is pulled up by the second output control switch KS2 , the fourth selection switch KX4 , and the fourth output switch KO4 , thereby overcoming the voltage withstand problem of each switch.

[0095] In stage t2, the second input switch KN2, the first selection switch KX1, the first output switch KO1, the second output switch KO2, the second selection switch KX2, the first output control switch KS1, the fourth selection switch KX4, the third output switch KO3, the fourth output switch KO4, the third selection switch KX3, the first control switch KC1, the fourth control switch KC4, the seventh control switch KC7 and the eighth control switch KC8 are all turned on, while the first input switch KN1, the second output control switch KS2, the second control switch KC2, the third control switch KC3, the fifth control switch KC5, the sixth control switch KC6, the ninth control switch KC9 and the tenth control switch KC10 are all turned off. Then, the voltage of the first power supply terminal VSS is input to the second signal output terminal VOUT2, pulling the second signal output terminal VOUT2 down to 0V, and the voltage of the second power supply terminal VDDH is input to the first signal output terminal VOUT1, pulling the first signal output terminal VOUT1 up to 3.3V. Furthermore, the voltage of the first withstand voltage control terminal NC1 is input to the control electrodes of the second output switch KO2 and the third output switch KO3, respectively, so that the voltages of the control electrodes of the second output switch KO2 and the third output switch KO3 are both 1.8V. The third control switch KC3, the fourth control switch KC4, and the fifth control switch KC5 form a self-protection circuit, which can reduce the voltage difference between the control electrode of the second output switch KO2 and the first signal output terminal VOUT1 to 1.5V, meeting the withstand voltage range of the second output switch KO2. The sixth control switch KC6 and the seventh control switch KC7 form a self-protection circuit, which can reduce the voltage difference between the control electrode of the third output switch KO3 and the second signal output terminal VOUT2 to 1.8V, also meeting the withstand voltage range of the third output switch KO3. Furthermore, the self-protection circuit formed by the first control switch KC1 and the second control switch KC2 allows the voltage at the first signal output terminal VOUT1 to be input to the control electrode of the first output switch KO1. The voltage difference between the control electrode of the first output switch KO1 and the first signal output terminal VOUT1 is 0V, meeting the withstand voltage range of the first output switch KO1. The self-protection circuit formed by the eighth control switch KC8, the ninth control switch KC9, and the tenth control switch KC10 allows the voltage at the second signal output terminal VOUT2 to be input to the control electrode of the fourth output switch KO4. The voltage difference between the control electrode of the fourth output switch KO4 and the second signal output terminal VOUT2 is 0V, meeting the withstand voltage range of the fourth output switch KO4. This ensures that the first through fourth output switches KO1 through KO4 all meet their withstand voltage ranges, preventing reliability degradation or failure of the first through fourth output switches KO1 through KO4.The first output control switch KS1, the second selection switch KX2, and the second output switch KO2 are used to pull up the first signal output terminal VOUT1, thus overcoming the voltage withstand issues of each switch. Furthermore, the second input switch KN2, the third selection switch KX3, and the third output switch KO3 are used to pull down the second signal output terminal VOUT2, thus overcoming the voltage withstand issues of each switch.

[0096] Afterwards, the operation of the level shifter circuit 212 can repeat the operations of phases t1 and t2. The details are not further described here. Alternatively, the second conduction control switch KD2 and the fourth conduction control switch KD4 can both be turned on, while the first conduction control switch KD1 and the third conduction control switch KD3 can both be turned off. Alternatively, the first conduction control switch KD1, the second conduction control switch KD2, the third conduction control switch KD3, and the fourth conduction control switch KD4 can all be turned off.

[0097] It can be seen from the above embodiments that when the voltage input to the second power supply terminal VDDH is greater than the upper limit of the voltage-withstand range of a single switch, the operation of each switch in the voltage-withstand control circuit 20 can enable each output switch to operate within the voltage-withstand range. Therefore, based on the application scenario where the voltage input to the second power supply terminal VDDH is greater than the upper limit of the voltage-withstand range of a single switch, the level conversion circuit 212 in the embodiment of the present application can be applied.

[0098] Next, continue with Figure 8 Taking the structure shown as an example, combined with the signal timing diagram, when the voltage at the second power supply terminal VDDH is less than or equal to the upper limit of the withstand voltage range of a single switch, the working process of the level conversion circuit 212 provided in the embodiment of the present application is specifically described.

[0099] Figure 9b Another signal timing diagram provided in the embodiment of the present application. Figure 9b, take the voltage of the second power supply terminal VDDH as 1.8V, the voltage of the first power supply terminal VSS as 0V, the upper limit of the withstand voltage range of the single switch as 1.8V, the voltage of the first withstand voltage control terminal NC1 as 0V, the voltage of the second withstand voltage control terminal NC2 as 1.8V, the voltage of the selection control terminal XC as 0V, and the signals input by the first signal input terminal VIN1 and the second signal input terminal VIN2 as voltages alternating between 0V and 1.8V as an example. Among them, vin1 represents the signal of the first signal input terminal VIN1, vin2 represents the signal of the second signal input terminal VIN2, vko1 represents the signal of the control electrode of the first output switch KO1, vko2 represents the signal of the control electrode of the second output switch KO2, vko3 represents the signal of the control electrode of the third output switch KO3, vko4 represents the signal of the control electrode of the fourth output switch KO4, vout1 represents the signal of the first signal output terminal VOUT1, vout2 represents the signal of the second signal output terminal VOUT2, xc represents the signal of the selection control terminal XC, da1 represents the signal of the first conduction control terminal DT1, and da2 represents the signal of the second conduction control terminal DT2.

[0100] In the t1 phase, the first input switch KN1, the first conduction control switch KD1, the second conduction control switch KD2, the second output switch KO2, the second selection switch KX2, the second output control switch KS2, the fourth selection switch KX4, the third output switch KO3, the fourth output switch KO4, the third conduction control switch KD3, the fourth conduction control switch KD4, the first control switch KC1, the second control switch KC2, the fifth control switch KC5, the sixth control switch KC6, the ninth control switch KC9 and the tenth control switch KC10 are all turned on, and the second input When the switch KN2, the first selection switch KX1, the second selection switch KX2, the third selection switch KX3, the fourth selection switch KX4, the first output control switch KS1, the third control switch KC3, the fourth control switch KC4, the seventh control switch KC7, and the eighth control switch KC8 are all disconnected, the voltage of the first power supply terminal VSS is input to the first signal output terminal VOUT1, pulling the first signal output terminal VOUT1 down to 0 V, and the voltage of the second power supply terminal VDDH is input to the second signal output terminal VOUT2, pulling the second signal output terminal VOUT2 up to 1.8 V.

[0101] In the t2 phase, the second input switch KN2, the third conduction control switch KD3, the fourth conduction control switch KD4, the fourth output switch KO4, the fourth selection switch KX4, the first output control switch KS1, the second selection switch KX2, the second output switch KO2, the first output switch KO1, the first control switch KC1, the fourth control switch KC4, the fifth control switch KC5, the sixth control switch KC6, the seventh control switch KC7 and the tenth control switch KC10 are all turned on, while the first input switch KN1, the first selection switch KX1, the second selection switch KX2, the third selection switch KX3, the fourth selection switch KX4, the second output control switch KS2, the second control switch KC2, the third control switch KC3, the eighth control switch KC8 and the ninth control switch KC9 are all disconnected, the voltage of the first power supply terminal VSS is input to the second signal output terminal VOUT2, and the second signal output terminal VOUT2 is pulled down to 0V, and the voltage of the second power supply terminal VDDH is input to the first signal output terminal VOUT1, and the first signal output terminal VOUT1 is pulled up to 1.8V.

[0102] Afterwards, the operation process of the level conversion circuit 212 may repeat the operation in the t1 phase and the t2 phase, and details thereof will not be repeated here.

[0103] It can be seen from the above embodiments that when the voltage input to the second power supply terminal VDDH is less than or equal to the upper limit of the withstand voltage range of a single switch, the level conversion circuit 212 in the embodiment of the present application is applicable.

[0104] In order to reduce the number of external ports connected to the level conversion circuit 212 and reduce the wiring difficulty, in the embodiment of the present application, an inverter DN can also be set in the level conversion circuit 212 to reduce the number of input terminals through the inverter DN. Figure 10 , Figure 10 This is another specific circuit structure diagram of the level conversion circuit provided in an embodiment of the present application. The first signal input terminal VIN1 and the input terminal of the inverter DN can be connected to the same port, the second signal input terminal VIN2 is connected to the output terminal of the inverter DN, and the first signal output terminal VOUT1 and the second signal output terminal VOUT2 are used to connect to different ports. Figure 10 The working process of the level conversion circuit 212 shown can refer to the content of the above embodiment, and the details are not repeated here.

[0105] The above content is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, and they should all be covered by the protection scope of the present application.

Claims

1. A level conversion circuit, characterized in that: include: Input and output circuits and withstand voltage control circuits; The input-output circuit includes: a first input switch, a second input switch, a first output control switch, a second output control switch, a first output switch, a second output switch, a third output switch, a fourth output switch, a first selection switch, a second selection switch, a third selection switch, and a fourth selection switch; wherein, the control electrode of the first input switch is connected to the first signal input terminal, the first electrode of the first input switch is connected to the first power supply terminal, the second electrode of the first input switch is connected to the first electrode of the first selection switch, the second electrode of the first selection switch is connected to the first electrode of the first output switch, the control electrode of the first output control switch is used to receive a first output control signal, the first electrode of the first output control switch is connected to the second power supply terminal, the second electrode of the first output control switch is connected to the first electrode of the second selection switch, the second electrode of the second selection switch is connected to the first electrode of the second output switch, and the second electrode of the first output switch is connected to the second input terminal. the second electrodes of the output switches are connected to the first signal output terminal, the control electrode of the second input switch is connected to the second signal input terminal, the first electrode of the second input switch is connected to the first power supply terminal, the second electrode of the second input switch is connected to the first electrode of the third selection switch, the second electrode of the third selection switch is connected to the first electrode of the third output switch, the control electrode of the second output control switch is used to receive a second output control signal, the first electrode of the second output control switch is connected to the second power supply terminal, the second electrode of the second output control switch is connected to the first electrode of the fourth selection switch, the second electrode of the fourth selection switch is connected to the first electrode of the fourth output switch, the second electrode of the third output switch and the second electrode of the fourth output switch are both connected to the second signal output terminal, and the control electrodes of the first selection switch, the second selection switch, the third selection switch, and the fourth selection switch are all connected to the selection control terminal; The first input terminal of the withstand voltage control circuit is connected to the first withstand voltage control terminal, the second input terminal is connected to the first signal output terminal, the third input terminal is connected to the second signal output terminal, the first output terminal is connected to the control electrode of the first output switch, the second output terminal is connected to the control electrode of the second output switch, the third output terminal is connected to the control electrode of the third output switch, and the fourth output terminal is connected to the control electrode of the fourth output switch; The withstand voltage control circuit is used to output the voltage of the first withstand voltage control terminal or the first signal output terminal to the control electrode of the first output switch, output the voltage of the first withstand voltage control terminal or the first signal output terminal to the control electrode of the second output switch, output the voltage of the first withstand voltage control terminal or the second signal output terminal to the control electrode of the third output switch, and output the voltage of the first withstand voltage control terminal or the second signal output terminal to the control electrode of the fourth output switch.

2. The level conversion circuit according to claim 1, wherein: The withstand voltage control circuit includes: a first withstand voltage control sub-circuit, a second withstand voltage control sub-circuit, a third withstand voltage control sub-circuit and a fourth withstand voltage control sub-circuit; The first withstand voltage control subcircuit has a first input terminal connected to the first withstand voltage control terminal, a second input terminal connected to the first signal output terminal, and an output terminal connected to the control electrode of the first output switch. The first withstand voltage control subcircuit is configured to output the voltage of the first withstand voltage control terminal or the first signal output terminal to the control electrode of the first output switch in response to the voltage of the first withstand voltage control terminal and the first signal output terminal. The second withstand voltage control subcircuit has a first input terminal connected to the first withstand voltage control terminal, a second input terminal connected to the first signal output terminal, and an output terminal connected to the control electrode of the second output switch, and the second withstand voltage control subcircuit is configured to output the voltage of the first withstand voltage control terminal or the first signal output terminal to the control electrode of the second output switch in response to the voltage of the first withstand voltage control terminal and the first signal output terminal; The third withstand voltage control subcircuit has a first input terminal connected to the first withstand voltage control terminal, a second input terminal connected to the second signal output terminal, and an output terminal connected to the control electrode of the third output switch. The third withstand voltage control subcircuit is configured to output the voltage of the first withstand voltage control terminal or the second signal output terminal to the control electrode of the third output switch in response to the voltage of the first withstand voltage control terminal and the second signal output terminal. The first input terminal of the fourth withstand voltage control subcircuit is connected to the first withstand voltage control terminal, the second input terminal is connected to the second signal output terminal, and the output terminal is connected to the control electrode of the fourth output switch. The fourth withstand voltage control subcircuit is used to output the voltage of the first withstand voltage control terminal or the second signal output terminal to the control electrode of the fourth output switch in response to the voltage of the first withstand voltage control terminal and the second signal output terminal.

3. The level conversion circuit according to claim 2, wherein: The first withstand voltage control subcircuit includes: a first control switch and a second control switch; The control electrode of the first control switch is connected to the first withstand voltage control terminal, the first electrode of the first control switch is connected to the first signal output terminal, and the second electrode of the first control switch is connected to the control electrode of the first output switch; The control electrode of the second control switch is connected to the first signal output end, the first electrode of the second control switch is connected to the first withstand voltage control end, and the second electrode of the second control switch is connected to the control electrode of the first output switch.

4. The level conversion circuit according to claim 2 or 3, wherein: The second withstand voltage control subcircuit includes: a third control switch and a fourth control switch; The control electrode of the third control switch is connected to the first withstand voltage control terminal, the first electrode of the third control switch is connected to the first signal output terminal, and the second electrode of the third control switch is connected to the control electrode of the second output switch; The control electrode of the fourth control switch is connected to the first signal output end, the first electrode of the fourth control switch is connected to the first withstand voltage control end, and the second electrode of the fourth control switch is connected to the control electrode of the second output switch.

5. The level conversion circuit according to claim 4, wherein: The second withstand voltage control subcircuit further includes: a fifth control switch; The control electrode of the fifth control switch is connected to the second withstand voltage control terminal, the first electrode of the fifth control switch is connected to the first withstand voltage control terminal, and the second electrode of the fifth control switch is connected to the control electrode of the second output switch.

6. The level conversion circuit according to any one of claims 2 to 5, wherein: The third withstand voltage control subcircuit includes: a sixth control switch and a seventh control switch; The control electrode of the sixth control switch is connected to the first withstand voltage control terminal, the first electrode of the sixth control switch is connected to the second signal output terminal, and the second electrode of the sixth control switch is connected to the control electrode of the third output switch; The control electrode of the seventh control switch is connected to the second signal output end, the first electrode of the seventh control switch is connected to the first withstand voltage control end, and the second electrode of the seventh control switch is connected to the control electrode of the third output switch.

7. The level conversion circuit according to any one of claims 2 to 6, wherein: The fourth withstand voltage control subcircuit includes: an eighth control switch and a ninth control switch; The control electrode of the eighth control switch is connected to the first withstand voltage control terminal, the first electrode of the eighth control switch is connected to the second signal output terminal, and the second electrode of the eighth control switch is connected to the control electrode of the fourth output switch; The control electrode of the ninth control switch is connected to the second signal output terminal, the first electrode of the ninth control switch is connected to the first withstand voltage control terminal, and the second electrode of the ninth control switch is connected to the control electrode of the fourth output switch.

8. The level conversion circuit according to claim 7, wherein: The fourth withstand voltage control subcircuit further includes: a tenth control switch; The control electrode of the tenth control switch is connected to the second withstand voltage control terminal, the first electrode of the tenth control switch is connected to the first withstand voltage control terminal, and the second electrode of the tenth control switch is connected to the control electrode of the fourth output switch.

9. The level conversion circuit according to any one of claims 1 to 8, wherein: The level conversion circuit further includes: a first conduction control circuit and a second conduction control circuit; The input end of the first conduction control circuit is connected to the second electrode of the first input switch, and the output end of the first conduction control circuit is connected to the control electrode of the first output switch. The first conduction control circuit is used to control the connection or disconnection between the second electrode of the first input switch and the control electrode of the first output switch. The input end of the second conduction control circuit is connected to the second electrode of the second input switch, and the output end of the second conduction control circuit is connected to the control electrode of the third output switch. The second conduction control circuit is used to control the conduction or disconnection between the second electrode of the second input switch and the control electrode of the third output switch.

10. The level conversion circuit according to claim 9, wherein: The first conduction control circuit includes: a first conduction control switch and a second conduction control switch; The control electrode of the first conduction control switch is connected to the first conduction control terminal, the first electrode of the first conduction control switch is connected to the second electrode of the first input switch, and the second electrode of the first conduction control switch is connected to the first electrode of the second conduction control switch; The control electrode of the second conduction control switch is connected to the second conduction control terminal, and the second electrode of the second conduction control switch is connected to the control electrode of the first output switch.

11. The level conversion circuit according to claim 9 or 10, wherein: The second conduction control circuit includes: a third conduction control switch and a fourth conduction control switch; The control electrode of the third conduction control switch is connected to the first conduction control terminal, the first electrode of the third conduction control switch is connected to the second electrode of the second input switch, and the second electrode of the third conduction control switch is connected to the first electrode of the fourth conduction control switch; The control electrode of the fourth conduction control switch is connected to the second conduction control terminal, and the second electrode of the fourth conduction control switch is connected to the control electrode of the third output switch.

12. The level conversion circuit according to any one of claims 1 to 11, wherein: The control electrode of the first output control switch is connected to the control electrode of the third output switch, and the control electrode of the second output control switch is connected to the control electrode of the first output switch.

13. The level conversion circuit according to any one of claims 1 to 12, wherein: The first signal input terminal and the second signal input terminal are used to connect to different ports, and the first signal output terminal and the second signal output terminal are used to connect to different ports.

14. The level conversion circuit according to any one of claims 1 to 12, wherein: The level conversion circuit further includes an inverter, the first signal input end and the input end of the inverter are used to connect to the same port, and the second signal input end is connected to the output end of the inverter; The first signal output end and the second signal output end are used to connect to different ports.

15. A chip, characterized in that: include: An input circuit, an output circuit, and at least one level conversion circuit according to any one of claims 1 to 14; The input end of the level conversion circuit is connected to the input end circuit, and is used to receive an input voltage from the input end circuit; The output end of the level conversion circuit is connected to the output end circuit, and is used to send an output voltage to the output end circuit.

16. An electronic device, characterized in that: comprising a circuit board and the chip according to claim 15; The chip is arranged on the circuit board.

Images