Multi-channel high-speed low-power-consumption successive approximation analog-to-digital converter, system and method

Abstract

The invention discloses a multi-channel high-speed low-power-consumption successive approximation analog-to-digital converter, system and method, and relates to the technical field of analog integrated circuit design, the analog-to-digital converter comprises an M-bit auxiliary ADC, n N-bit main ADCs, a multiplexer and a digital error correction circuit, an M-bit non-binary digital code is obtained through quantization of the auxiliary ADC, and the N-bit non-binary digital code is obtained through quantization of the N-bit main ADCs. A group of N-M-bit non-binary digital codes are obtained through quantization of multiple paths of main ADCs respectively, then combination and binary conversion are carried out on M-bit non-binary digital codes and each group of N-M-bit non-binary digital codes through a digital error correction circuit, n groups of binary digital codes are obtained and output, and multi-channel sampling, quantization, conversion and output are achieved. The device has the characteristics of low power consumption, high conversion speed and high precision, and the conversion speed and precision can be improved while the characteristic of low power consumption is maintained.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog integrated circuit design, in particular to a multi-channel high-speed low-power successive approximation analog-to-digital converter, system and method. BACKGROUND

[0002] In the process of modern electronic system digitization, successive approximation analog-to-digital converter (SARADC) has become a key component in the conversion of analog signals and digital signals due to its unique technical advantages. SARADC is characterized by medium accuracy, moderate conversion speed and extremely low power consumption. Its simple architecture design not only reduces the complexity of the chip, but also greatly reduces the energy consumption cost, and occupies an important position in the fields of portable devices, Internet of Things sensors, industrial automation monitoring, etc. With the rapid development of 5G communication, artificial intelligence and big data technology, information processing systems have put forward unprecedented challenges to the real-time performance, accuracy and energy efficiency of data acquisition, prompting the research of high-speed low-power analog-to-digital converters (ADCs) to become the focus of attention of academia and industry.

[0003] The traditional SARADC is based on the architecture design of a binary capacitor array. Although it can theoretically achieve accurate analog-to-digital conversion, it exposes many technical bottlenecks that are difficult to overcome in practice. The core defect of this architecture is that the maximum capacitance value of the capacitor digital-to-analog converter (CDAC) array has an exponential growth relationship with the conversion accuracy N. Taking 16-bit accuracy as an example, the capacitor array needs to accommodate 65536 unit capacitors. The large capacitance scale not only leads to a dramatic increase in chip area, but also causes a series of performance problems: the high accuracy requirement forces the capacitance value to increase, which exacerbates the mismatch between capacitors, resulting in errors in the conversion result; at the same time, the large-capacity capacitor array significantly prolongs the charging and discharging process, reduces the conversion rate, and increases the system power consumption. This contradiction makes it difficult for traditional SARADC to achieve low-power design in high-precision, high-speed application scenarios, limiting its application expansion in high-end fields.

[0004] To alleviate the problem caused by the size of the capacitor array, a conventional binary segmented structure digital-to-analog converter (DAC) emerges as the times require. The structure attempts to reduce the total number of capacitors while ensuring accuracy by introducing a bridge capacitor. However, this solution has inherent deficiencies: the fractional ratio relationship between the bridge capacitor and the unit capacitor makes it difficult to accurately implement capacitor matching in actual layout design, and it is extremely sensitive to parasitic capacitance, and even a small parasitic effect can seriously affect the conversion accuracy. To solve the matching problem, the unit capacitor is often used to replace the bridge capacitor in engineering practice, but this substitution changes the binary characteristics of the capacitor weight and introduces a fixed gain error. In addition, reducing the size of the unit capacitor can control the chip area, but it will further amplify the negative effects of parasitic capacitance, leading to a decline in ADC performance; while increasing the unit capacitor value can improve accuracy, it is contrary to the design goal of low power consumption and small area, forming a technical contradiction that is difficult to reconcile.

[0005] In addition to capacitor matching and parasitic effects, the size problem of the most significant bit (MSB) capacitor in the conventional architecture cannot be ignored. Since the MSB capacitor accounts for a large proportion of the total capacitor, the settling time of its charging and discharging process directly determines the overall conversion speed of the ADC. This natural contradiction between accuracy and speed makes high-precision SAR ADCs often have low-speed characteristics. Although the DAC with a non-binary structure optimizes the settling time by introducing redundancy, the size of the highest several capacitors is still large, and large-size switching circuits are needed to ensure accurate establishment. Non-ideal effects such as charge injection and clock feedthrough generated during the high-speed quantization process further worsen the performance of the ADC.

[0006] In summary, how to provide a multi-channel high-speed low-power successive approximation ADC that effectively improves the conversion speed and accuracy while maintaining the low-power characteristics of the ADC, thereby achieving the dual goals of reducing chip area and improving economic benefits, has become a technical problem that needs to be solved in the field. SUMMARY

[0007] The purpose of the present application is to provide a multi-channel high-speed low-power successive approximation ADC, system and method, which has the characteristics of low power consumption, high conversion speed and high accuracy, and can improve the conversion speed and accuracy while maintaining low power consumption.

[0008] To achieve the above-mentioned purpose, the present application provides the following solutions.

[0009] In a first aspect, the present application provides a multi-channel high-speed low-power successive approximation ADC, which comprises: 1 auxiliary ADC of M bits, n main ADCs of N bits, a multiplexer and a digital error correction circuit, wherein M, n and N are positive integers, and N≥n·M.

[0010] The auxiliary ADC comprises a first gate voltage bootstrap circuit, a first non-binary DAC capacitor array, a first comparator and a first successive approximation logic module.

[0011] Each of the main ADCs comprises a second gate voltage bootstrap circuit, a second non-binary DAC capacitor array, a second comparator and a second successive approximation logic module.

[0012] An input end of the first non-binary DAC capacitor array is connected to the first gate voltage bootstrap circuit, an output end of the first non-binary DAC capacitor array is connected to an input end of the first comparator, an output end of the first comparator is connected to an input end of the first successive approximation logic module, and an output end of the first successive approximation logic module is connected to each of the second successive approximation logic modules and the digital error correction circuit.

[0013] An input end of each of the second non-binary DAC capacitor arrays is connected to the corresponding second gate voltage bootstrap circuit, an output end of each of the second non-binary DAC capacitor arrays is connected to an input end of the corresponding second comparator, an output end of each of the second comparators is connected to an input end of the corresponding second successive approximation logic module, and an output end of each of the second successive approximation logic modules is connected to an input end of the multiplexer, and an output end of the multiplexer is connected to the digital error correction circuit.

[0014] The first gate voltage bootstrap circuit and the second gate voltage bootstrap circuit are configured to receive an externally input analog signal and transmit the analog signal to the corresponding first non-binary DAC capacitor array and the second non-binary DAC capacitor array.

[0015] The first non-binary DAC capacitor array and the second non-binary DAC capacitor array are configured to sample the analog signal and obtain a first upper plate voltage pair and a second upper plate voltage pair, respectively, and transmit the first upper plate voltage pair and the second upper plate voltage pair to the corresponding first comparator and the corresponding second comparator, respectively.

[0016] The first comparator and the second comparator are configured to compare the received upper plate voltage pair, obtain a first comparison result and a second comparison result, and send the first comparison result and the second comparison result to the corresponding first successive approximation logic module and the corresponding second successive approximation logic module, respectively.

[0017] The first successive approximation logic module is configured to perform successive approximation quantization according to the first comparison result, obtain an M-bit non-binary digital code, and send the M-bit non-binary digital code to each of the second successive approximation logic modules and the digital error correction circuit.

[0018] Each of the second successive approximation logic modules is configured to perform successive approximation quantization based on the M-bit non-binary digital code according to the corresponding second comparison result to obtain an N-M-bit non-binary digital code and send the N-M-bit non-binary digital code to the multiplexer.

[0019] The multiplexer is configured to select the N-M-bit non-binary digital code obtained by the current main ADC quantization after the main ADC quantization is completed and send the N-M-bit non-binary digital code to the digital error correction circuit.

[0020] The digital error correction circuit is configured to combine the M-bit non-binary digital code and each of the N-M-bit non-binary digital codes and perform binary conversion to obtain n groups of binary digital codes and output the n groups of binary digital codes.

[0021] In a second aspect, the present application provides a working method of the multi-channel high-speed low-power successive approximation ADC, and the working method comprises the following steps.

[0022] A1: sampling stage.

[0023] Based on the auxiliary ADC and one main ADC, the first gate voltage bootstrap circuit and the second gate voltage bootstrap circuit are used to simultaneously receive an analog signal of the same external input, and the first non-binary DAC capacitor array and the second non-binary DAC capacitor array are used to sample and store sampling charges of the analog signal, respectively, to obtain a first upper plate voltage pair and a second upper plate voltage pair.

[0024] A2: quantization stage.

[0025] The first M-bit capacitors of the first non-binary DAC capacitor array and the second non-binary DAC capacitor array are sequentially subjected to quantization operations, and after each quantization, a first comparator is used to compare the first upper plate voltage pair to obtain a first comparison result, and a first successive approximation logic module is used to perform successive approximation quantization based on the first comparison result to obtain an M-bit non-binary digital code.

[0026] Based on the first M-bit code value, the remaining N-M-bit capacitors of the second non-binary DAC capacitor array are sequentially subjected to quantization operations, and after each quantization, a second comparator is used to compare the second upper plate voltage pair to obtain a second comparison result, and a second successive approximation logic module is used to perform successive approximation quantization based on the M-bit non-binary digital code according to the second comparison result to obtain an N-M-bit non-binary digital code.

[0027] A3: digital error correction stage.

[0028] The M-bit non-binary digital code and the N-M-bit non-binary digital code are combined and binary converted by a digital error correction circuit to obtain a binary digital code.

[0029] A4: repeating steps A1 to A3 n times to obtain n groups of the binary digital code and outputting.

[0030] A4: repeating steps A1 to A3 n times to obtain n groups of the binary digital code and outputting.

[0031] An analog signal inputted from outside is acquired.

[0032] The analog signal is sampled respectively to determine a first upper plate voltage pair and a second upper plate voltage pair.

[0033] The first upper plate voltage pair is compared to obtain a first comparison result, and the second upper plate voltage pair is compared to obtain a second comparison result.

[0034] The first comparison result is used for successive approximation quantization to obtain an M-bit non-binary digital code.

[0035] The second comparison result is used for successive approximation quantization based on the M-bit non-binary digital code to obtain an N-M-bit non-binary digital code.

[0036] The M-bit non-binary digital code and the N-M-bit non-binary digital code are combined and binary converted to obtain a group of binary digital codes.

[0037] Returning to the step of sampling the analog signal respectively to determine a first upper plate voltage pair and a second upper plate voltage pair, n groups of the binary digital code are obtained and outputted.

[0038] A fourth aspect of the present application provides a multi-channel high-speed low-power successive approximation type analog-to-digital conversion system, which applies the multi-channel high-speed low-power successive approximation type analog-to-digital conversion method as described in the third aspect, and comprises the following functional modules.

[0039] An analog signal acquisition module is configured to acquire an analog signal inputted from outside.

[0040] A sampling module is configured to sample the analog signal respectively to determine a first upper plate voltage pair and a second upper plate voltage pair.

[0041] A comparison module is configured to compare the first upper plate voltage pair to obtain a first comparison result, and compare the second upper plate voltage pair to obtain a second comparison result.

[0042] A first quantization module is configured to perform successive approximation quantization according to the first comparison result to obtain M-bit non-binary digital codes.

[0043] A second quantization module is configured to perform successive approximation quantization according to the second comparison result based on the M-bit non-binary digital codes to obtain N-M-bit non-binary digital codes.

[0044] A conversion module is configured to combine and convert the M-bit non-binary digital codes and the N-M-bit non-binary digital codes into binary digital codes.

[0045] A multi-channel resampling quantization conversion output module is configured to drive the sampling module, the comparison module, the first quantization module, the second quantization module and the conversion module to work in a loop to realize the process of multi-channel resampling, quantization, conversion and output, and obtain n groups of the binary digital codes and output.

[0046] According to the embodiments provided in the present application, the present application has the following technical effects:

[0047] The application provides a multi-channel high-speed low-power successive approximation type analog-to-digital converter, a system and a method, the analog-to-digital converter comprising an M-bit auxiliary ADC, n N-bit main ADCs, a multiplexer and a digital error correction circuit, the auxiliary ADC comprising a first gate voltage bootstrap circuit, a first non-binary DAC capacitor array, a first comparator and a first successive approximation logic module; each main ADC comprising a second gate voltage bootstrap circuit, a second non-binary DAC capacitor array, a second comparator and a second successive approximation logic module. Through the cooperation between the auxiliary ADC (the first gate voltage bootstrap circuit, the first non-binary DAC capacitor array, the first comparator and the first successive approximation logic module), the main ADC (the second gate voltage bootstrap circuit, the second non-binary DAC capacitor array, the second comparator and the second successive approximation logic module) and the multiplexer and the digital error correction circuit, multi-channel analog signal sampling, successive approximation quantization and digital error correction can be realized, and ultimately n (n is the number of main ADCs) groups of N-bit binary digital codes can be output. Since the analog-to-digital converter adopts the structure of multiple main ADCs and one auxiliary ADC, through the multi-channel design of the multiple main ADCs and the shunt selection effect of the multiplexer, multi-channel sampling, quantization, conversion and output can be realized, high-M-bit quantization is directly performed by the auxiliary ADC, the switching and quantization process of the high-bit capacitors of the second non-binary DAC capacitor array of the main ADC is omitted, thereby the energy consumption of the second non-binary DAC capacitor array of the main ADC is reduced, and the overall conversion speed and precision are improved. Moreover, the main ADC and the auxiliary ADC both use non-binary DAC capacitor arrays, the non-binary DAC capacitor array does not need to use a large number of capacitors, thereby the power consumption can be reduced, and in combination with the successive approximation quantization effect of the first successive approximation logic module and the second successive approximation logic module and the digital error correction effect of the digital error correction circuit, the conversion speed and precision can be improved while the low-power characteristic is maintained, which is beneficial to realizing the dual goals of chip area reduction and economic benefit improvement, and solves the problem that the traditional SARADC cannot simultaneously have high precision and reduce the number of DAC capacitors and power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0049] Figure 1 The circuit structure schematic diagram of the multi-channel high-speed low-power successive approximation type analog-to-digital converter provided by an embodiment of the present application.

[0050] Figure 2The working timing diagram of the multi-channel high-speed low-power successive approximation analog-to-digital converter provided by an embodiment of the present application is shown.

[0051] Figure 3 The flowchart of the working method of the multi-channel high-speed low-power successive approximation analog-to-digital converter provided by an embodiment of the present application is shown.

[0052] Figure 4 The flowchart of the multi-channel high-speed low-power successive approximation analog-to-digital conversion method provided by an embodiment of the present application is shown.

[0053] Figure 5 The structural diagram of the multi-channel high-speed low-power successive approximation analog-to-digital conversion system provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0055] The present application aims to provide a multi-channel high-speed low-power successive approximation analog-to-digital converter, system and method, which adopts a super-high-speed and low-power analog-to-digital converter architecture, can experimentally work at a GHz level, and is used to solve the problem that the traditional SARADC cannot simultaneously consider high precision and reduce the number of DAC capacitors and power consumption.

[0056] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0057] As shown in Figure 1 The present embodiment provides a multi-channel high-speed low-power successive approximation analog-to-digital converter, which comprises one M-bit auxiliary ADC, n N-bit main ADCs, a multiplexer (MUX) and a digital error correction circuit (DEC), wherein M, n and N are positive integers, and N≥n·M.

[0058] In the present embodiment, the auxiliary ADC comprises a first gate voltage bootstrap circuit, a first non-binary DAC capacitor array, a first comparator and a first successive approximation logic (SAR Logic) module.

[0059] In the present embodiment, each main ADC comprises a second gate voltage bootstrap circuit, a second non-binary DAC capacitor array, a second comparator and a second successive approximation logic module.

[0060] In the embodiment, the input end of the first non-binary DAC capacitor array is connected to the first gate voltage bootstrap circuit, the output end of the first non-binary DAC capacitor array is connected to the input end of the first comparator, the output end of the first comparator is connected to the input end of the first successive approximation logic module, and the output end of the first successive approximation logic module is connected to each of the second successive approximation logic modules and the digital error correction circuit.

[0061] In the embodiment, the input end of each of the second non-binary DAC capacitor arrays is connected to the corresponding second gate voltage bootstrap circuit, the output end of each of the second non-binary DAC capacitor arrays is connected to the input end of the corresponding second comparator, the output end of each of the second comparators is connected to the input end of the corresponding second successive approximation logic module, the output end of each of the second successive approximation logic modules is connected to the input end of the multiplexer, and the output end of the multiplexer is connected to the digital error correction circuit.

[0062] In the embodiment, the first gate voltage bootstrap circuit and the second gate voltage bootstrap circuit are used to receive an externally input analog signal and transmit it to the corresponding first non-binary DAC capacitor array and the second non-binary DAC capacitor array.

[0063] In the embodiment, the first non-binary DAC capacitor array and the second non-binary DAC capacitor array are used to sample the analog signal, and a first upper plate voltage pair and a second upper plate voltage pair are obtained respectively and transmitted to the corresponding first comparator and second comparator.

[0064] In the embodiment, the first comparator and the second comparator are used to compare the received upper plate voltage pairs, obtain a first comparison result and a second comparison result, and send them to the corresponding first successive approximation logic module and second successive approximation logic module.

[0065] In the embodiment, the first successive approximation logic module is used to perform successive approximation quantization according to the first comparison result, obtain M-bit non-binary digital codes, and send them to each of the second successive approximation logic modules and the digital error correction circuit.

[0066] In the embodiment, each of the second successive approximation logic modules is used to perform successive approximation quantization according to the corresponding second comparison result based on the M-bit non-binary digital codes, obtain N-M-bit non-binary digital codes, and send them to the multiplexer.

[0067] In the embodiment, the multiplexer is configured to select the N-M bit non-binary digital code obtained by the current main ADC quantization and send the N-M bit non-binary digital code to the digital error correction circuit after the quantization of each main ADC is completed.

[0068] In the embodiment, the digital error correction circuit is configured to combine the M bit non-binary digital code and each N-M bit non-binary digital code and perform binary conversion to obtain n groups of binary digital codes and output the n groups of binary digital codes.

[0069] In the embodiment, the multi-channel high-speed low-power SAR ADC further comprises a timing and logic circuit. The timing and logic circuit is connected to the first gate voltage bootstrap circuit, each second gate voltage bootstrap circuit, the first SAR logic module, each second SAR logic module, and the multiplexer. The timing and logic circuit is configured to provide a clock signal and specifically configured to generate a control signal for a timing circuit and a multiplexer for controlling the operation of the ADC.

[0070] In the embodiment, the first non-binary DAC capacitor array and the second non-binary DAC capacitor array both adopt a non-binary capacitor arrangement structure.

[0071] In the embodiment, the second non-binary DAC capacitor array adopts a two-level reference level.

[0072] In the embodiment, the working period of the auxiliary ADC is n times of the working period of the main ADC, the working clock interval of n main ADCs is one working period of the auxiliary ADC. Taking four main ADCs as an example, the number of main ADCs is four, and the working period of the auxiliary ADC is four times of the working period of the main ADC. The working clock interval of the four main ADCs is one working period of the auxiliary ADC.

[0073] In the embodiment, the capacitor weight ratio of the first non-binary DAC capacitor array is 23:16:25, and the capacitor weight ratio of the second non-binary DAC capacitor array is 184:128:64:64:32:16:8:8:4:2:1:1.

[0074] In the embodiment, four main ADCs (i.e., n = 4) are taken as an example. As shown in FIG. 4, the capacitor weight ratio of the first non-binary DAC capacitor array is 23:16:25, and the capacitor weight ratio of the second non-binary DAC capacitor array is 184:128:64:64:32:16:8:8:4:2:1:1. Figure 1As shown, the 4-way main ADC adopts 4 groups of interleaving, the multi-channel high-speed low-power successive approximation analog-to-digital converter includes an M-bit auxiliary ADC and four N-bit main ADCs (i.e., main ADC1, main ADC2, main ADC3, and main ADC4) of the same structure, and N≥4M. The auxiliary ADC and the main ADC are connected through respective comparators (i.e., first comparator and second comparator) and successive approximation logic modules (i.e., first successive approximation logic module and second successive approximation logic module); the externally input analog signal Vin and Vip are connected to the first non-binary DAC capacitor array and the second non-binary DAC capacitor array of the auxiliary ADC and the main ADC, respectively; and the non-binary digital code converted by the first successive approximation logic module and the second successive approximation logic module is converted into a binary digital code by a digital error correction circuit and output.

[0075] In the embodiment, the main ADC includes a second non-binary DAC capacitor array, a second comparator, and a second successive approximation logic module. After the first non-binary DAC capacitor array of the auxiliary ADC and the second non-binary DAC capacitor array of the main ADC sample the input analog signal, the two upper plate voltages of the first non-binary DAC capacitor array and the second non-binary DAC capacitor array are input to the first comparator and the second comparator, respectively; the first successive approximation logic module of the auxiliary ADC obtains a digital code value through the comparison result of the first comparator and outputs the digital code value to the highest bit switch of the main ADC through a code value output module; the lower plate switch of the second non-binary DAC capacitor array is controlled to switch through a switch control module, then a new DAC upper plate voltage is established through the principle of charge redistribution, the first non-binary DAC capacitor array is input to the first comparator for next comparison, so as to realize the function of SAR.

[0076] In this embodiment, the M bits of the auxiliary ADC are loaded onto the corresponding bits of the main ADC after each quantization. The DAC switch circuit of the main ADC is controlled by receiving the M-bit code value of the auxiliary ADC after quantization, so that the plate voltage on the second non-binary DAC capacitor array is re-established; finally, the remaining N-M bits are quantized by the re-established voltage on the plate of the second non-binary DAC capacitor array, and the N-bit non-binary digital code value is obtained. Moreover, the working period of the auxiliary ADC is 4 times that of the main ADC, and the working process of the auxiliary ADC is uninterrupted with the working clock of the auxiliary ADC. The working clock interval time of the four main ADCs is one working period of the auxiliary ADC. The M-bit code value of the auxiliary ADC after quantization for 4 cycles is loaded onto the high M bits of the four second non-binary DAC capacitor arrays, respectively, to control the re-establishment of the plate voltage on the high M-bit capacitor array of the four main ADCs. The four groups of N-M-bit non-binary digital codes after quantization of the four main ADCs are controlled by a multiplexer, combined with the four groups of M-bit code values of the auxiliary ADC, to obtain four groups of high-speed parallel output. Finally, the four groups of non-binary digital codes are decoded into binary digital codes by a digital error correction circuit and output.

[0077] In this embodiment, the multiplexer is controlled by the four groups of decoded signals output by the timing and logic circuit to complete the correct quantization output of the four-channel high-speed low-power SAR ADC.

[0078] In this embodiment, the first non-binary DAC capacitor array of the auxiliary ADC and the second non-binary DAC capacitor array of the main ADC adopt a non-binary capacitor arrangement structure. The second non-binary DAC capacitor array uses two reference levels to reduce the total capacitance of the second non-binary DAC capacitor array.

[0079] In this embodiment, since the main ADC is provided with four main ADCs, namely main ADC1, main ADC2, main ADC3 and main ADC4, the corresponding second non-binary DAC capacitor arrays (F1-F4) are DACF1, DACF2, DACF3 and DACF4, respectively.

[0080] The specific working process of the multi-channel high-speed low-power successive approximation analog-to-digital converter proposed in this embodiment is as follows.

[0081] (1) In the first sampling stage, the auxiliary ADC and the first main ADC1 sample the same input signal.

[0082] After sampling, first for M-bit auxiliary ADC quantization stage, M-bit auxiliary ADC quantization code value will be loaded to the highest M-bit capacitor of the first group of DAC F1 after each bit of the auxiliary ADC is quantized, so that the lower plate of the high M-bit capacitor of the first group of DAC F1 is switched, the first group of DAC F1 performs charge redistribution to establish a new DAC upper plate voltage; then according to the voltage re-established by the upper plate of the first group of DAC F1, continue to quantize the lower bit, until all bits of the non-binary digital code value are generated.

[0083] After the first group of main ADC 1 quantization, the multi-channel selector selects and outputs the N-M-bit non-binary digital code of the first group of main ADC 1, and the digital error correction circuit encodes the non-binary non-binary digital code of the N-bit auxiliary ADC and the first group of main ADC 1 into binary, and finally outputs the first group of binary digital code value.

[0084] (2) In the second sampling stage, the auxiliary ADC and the second main ADC 2 sample the same input signal.

[0085] After sampling, first for M-bit auxiliary ADC quantization stage, M-bit auxiliary ADC quantization code value will be loaded to the highest M-bit capacitor of the first group of DAC F1 after each bit of the auxiliary ADC is quantized, so that the lower plate of the high M-bit capacitor of the first group of DAC F1 is switched, the first group of DAC F1 performs charge redistribution to establish a new DAC upper plate voltage; then according to the voltage re-established by the upper plate of the first group of DAC F1, continue to quantize the lower bit, until all bits of the non-binary digital code value are generated.

[0086] After the second group of main ADC 2 quantization, the multi-channel selector selects and outputs the N-M-bit non-binary digital code of the second group of main ADC 2, and the digital error correction circuit encodes the non-binary non-binary digital code of the N-bit auxiliary ADC and the second group of main ADC 2 into binary, and finally outputs the second group of binary digital code value.

[0087] (3) In the third sampling stage, the auxiliary ADC and the third main ADC 3 sample the same input signal.

[0088] After sampling, first for M-bit auxiliary ADC quantization stage, M-bit auxiliary ADC quantization code value will be loaded to the highest M-bit capacitor of the first group of DAC F1 after each bit of the auxiliary ADC is quantized, so that the lower plate of the high M-bit capacitor of the first group of DAC F1 is switched, the first group of DAC F1 performs charge redistribution to establish a new DAC upper plate voltage; then according to the voltage re-established by the upper plate of the first group of DAC F1, continue to quantize the lower bit, until all bits of the non-binary digital code value are generated.

[0089] After the quantization of the third group of main ADC 3 is completed, the multiplexer selects and outputs the N-M bit non-binary digital code of the third group of main ADC 3, and the digital error correction circuit performs binary coding on the N bit non-binary digital code of the auxiliary ADC and the third group of main ADC 3, and finally outputs the third group of binary digital code values.

[0090] (4) In the fourth sampling stage, the auxiliary ADC and the fourth group of main ADC 4 sample the same input signal.

[0091] After sampling, first for the quantization stage of the M-bit auxiliary ADC, the M-bit auxiliary ADC quantization code value will be loaded onto the highest M-bit capacitor of the fourth group of DAC 4 after each bit of the auxiliary ADC is quantized, so that the high M-bit capacitor of the fourth group of DAC 4 switches the lower plate, the fourth group of DACF 4 performs charge redistribution, and a new DAC upper plate voltage is established; Then, according to the voltage re-established by the upper plate of the fourth group of DACF 4, continue to quantize the lower bit, until all bit non-binary digital code values are generated.

[0092] After the quantization of the fourth group of main ADC 4 is completed, the multiplexer selects and outputs the N-M bit non-binary digital code of the fourth group of main ADC 4, and the digital error correction circuit performs binary coding on the N bit non-binary digital code of the auxiliary ADC and the fourth group of main ADC 4, and finally outputs the fourth group of binary digital code values.

[0093] (5) The first four groups of quantization are completed and the decoded four groups of binary digital code values are output, completing a complete working cycle of the multi-channel high-speed low-power SAR ADC.

[0094] Figure 1The overall architecture diagram of the multi-channel high-speed low-power successive approximation analog-to-digital converter proposed in the application includes the gate voltage bootstrap circuit (i.e. the first gate voltage bootstrap circuit and the second gate voltage bootstrap circuit) of the auxiliary ADC and the main ADC, further includes an auxiliary ADC and a second non-binary DAC capacitor array with four same structures, and further includes a timing and logic circuit, a multiplexer and a digital error correction circuit. The auxiliary ADC and the four main ADCs are composed of a non-binary DAC capacitor array (i.e. the first non-binary DAC capacitor array and the second non-binary DAC capacitor array), a comparator (i.e. the first comparator and the second comparator) and a successive approximation logic module (i.e. the first successive approximation logic module and the second successive approximation logic module). The first non-binary DAC capacitor array in the auxiliary ADC is composed of three groups of differential capacitors, and the capacitor weight ratio of the three groups of differential capacitors is 23:16:25. The second non-binary DAC capacitor array in the four main ADCs with the same structure is composed of 12 groups of differential capacitors, and the capacitor weight ratio is 184:128:64:64:32:16:8:8:4:2:1:1. The auxiliary ADC and the four main ADCs have the same structure and different dynamic comparators, and the structure and speed of the second comparators of the four main ADCs are completely the same. The auxiliary ADC and the four main ADCs both have the successive approximation logic module, and the first successive approximation logic module of the auxiliary ADC has 3-bit control logic, while the second successive approximation logic module of the main ADC has 9-bit control logic.

[0095] In the embodiment, the auxiliary ADC contains two groups of first gate voltage bootstrap circuits in differential form, the first gate voltage bootstrap circuit and the common mode voltage Vcm switch are controlled by the clock CLKC, the input ends of the first gate voltage bootstrap circuit are connected with the input signals Vin and Vip respectively, the output ends of the first gate voltage bootstrap circuit are connected with the three groups of sampling switches of the first non-binary DAC capacitor array, the three groups of sampling switches in differential form are connected with the lower plates of the three groups of differential capacitors with the capacitor weight ratio of 23:16:25 respectively, and the upper plates of the three groups of differential capacitors with the capacitor weight ratio of 23:16:25 are connected with the differential input + / - ports of the first comparator CMPC1 and the output end of the common mode voltage Vcm switch. The differential output end of the first comparator CMPC1 is connected to the first successive approximation logic module C1 circuit, and the output of the first successive approximation logic module is regulated according to the first comparison result of the first comparator CMPC1 in the auxiliary ADC, and finally controls the high 3-bit differential control switch of the first non-binary DAC capacitor array (DAC1) and the four second non-binary DAC capacitor arrays (DACF1-DACF4) to perform the charge and discharge operation of the DAC capacitor.

[0096] In this embodiment, the four main ADCs share a set of two second gate voltage bootstrap circuits in differential form, and the second gate voltage bootstrap circuits and common mode voltage Vcm switch are controlled by the four clock signals CLKF<1:4>. The input terminals of the second gate voltage bootstrap circuits are connected to the input signals Vin and Vip, respectively. The output terminals of the second gate voltage bootstrap circuits are connected to 12 sets of sampling switches of the second non-binary DAC capacitor array, respectively. The 12 sets of sampling switches in differential form are connected to 12 sets of differential capacitors with weight ratios of 184:128:64:64:32:16:8:8:4:2:1:1, respectively. The upper plates of the 12 sets of differential capacitors are connected to the differential input + / - ports of the second comparators and the output terminals of the common mode voltage Vcm switch. The output terminals of the second comparators (CMPF1-4, corresponding to the four main ADCs) are connected to the second successive approximation logic modules F1-4 of the second comparators. The output of the second successive approximation logic modules is regulated according to the second comparison results of the respective second comparators in the main ADCs 1-4, and finally controls the differential control switches of the DACs F1-4 except for the top three bits to perform the charging and discharging operation of the DAC capacitors.

[0097] In this embodiment, the input terminal of the timing and logic circuit inputs a high-frequency clock signal CLKS with a duty cycle of 50% as shown in Figure 2 The output signal CLKC of the timing and logic circuit is connected to the first gate voltage bootstrap circuit and the common mode voltage switch of the auxiliary ADC. The output signals CLKF<1:4> of the timing and logic circuit are connected to the input terminals, output port 1, and common mode voltage switch of the second gate voltage bootstrap circuits of the four main ADCs, respectively. The output signals CLKCT<1:2> of the timing and logic circuit are connected to the multiplexer. The input terminals of the multiplexer are connected to the last nine-bit output of the four main ADCs and the control signal CLKCT<1:2> output by the timing and logic circuit, respectively. The output terminal of the multiplexer is connected to the digital error correction circuit. The input terminals of the digital error correction circuit are connected to the first successive approximation logic module C1 of the auxiliary ADC and the multiplexer.

[0098] Figure 2The application discloses a timing diagram of a multi-channel high-speed low-power successive approximation analog-digital converter. The timing diagram comprises the working clock CLKS of a timing and logic circuit, the working clock CLKC and CLKF<1:4> of an auxiliary ADC and four main ADCs, the control signal CLKCT<1:2> of a multiplexer, wherein the clock CLKC and CLKF<1:4> are obtained by frequency division processing of the clock CLKS, and the duty cycles of the clocks are all 25%, the period of the clock CLKF<1:4> is four times of the period of the clock CLKC, and the period of the clock CLKF<1:4> is eight times of the period of the clock CLKS; the control signal CLKCT<1:2> is the control signal of the multiplexer, four groups of control signals 0001, 0010, 0100 and 1000 are generated by decoding in a period, and the correct splicing of the 9-bit output signals of the four main ADCs and the 3-bit output signals of the auxiliary ADC is completed. One complete working process of the multi-channel high-speed low-power successive approximation analog-digital converter comprises four sampling stages and quantization stages, and the stages are as follows.

[0099] In the first sampling stage, Figure 2 When the clock CLKS and CLKF<1> are high, the switch of the common-mode voltage Vcm and the sampling switch composed of a gate voltage bootstrap circuit are closed under the driving of the high clock CLKS and CLKF<1>, the lower plates of DAC1 and DACF1 start sampling, at this moment, the upper plates are connected with the common-mode voltage Vcm, and the lower plates of the two groups of non-binary DAC capacitor arrays of the differential circuit are connected with the input signals Vin and Vip respectively. When the clock CLKS and CLKF<1> are low, the switch of the common-mode voltage Vcm and the sampling switch are disconnected under the driving of the low clock CLKS and CLKF<1>, and the first sampling of the input analog signal is completed.

[0100] In the first quantization stage, the timing and logic circuit starts quantization operation on the highest bits 23C and 184C of DAC1 and DACF1 under the driving of the timing signal. After the quantization is completed, the first comparator CMPC1 starts comparing the voltage of the positive (+) input end and the negative (-) input end, and outputs the first digital code value B<11>.

[0101] According to the first comparison result, the second high bits 16C and 128C of DAC1 and DACF1 are quantized. After the quantization is completed, the first comparator CMPC1 of the auxiliary ADC starts comparing the voltage of the positive (+) input end and the negative (-) input end, and outputs the second digital code value B<10>.

[0102] According to the second comparison result, the third bits 25C and 64C of DAC1 and DACF1 are quantized. After the quantization is completed, the first comparator CMPC1 of the auxiliary ADC starts comparing the voltage of the positive (+) input end and the negative (-) input end, and outputs the third digital code value B<9>.

[0103] According to the result of the 4th comparison, the 5th capacitor 32C of the DACF1 is quantized. After the quantization is completed, the comparator CMPF1 of the main ADC1 starts comparing the size of the voltage of the positive (+) input terminal and the negative (-) input terminal, and outputs the 5th digital code value BF1<7>.

[0104] According to the result of the 4th comparison, the 5th capacitor 32C of the DACF1 is quantized. After the quantization is completed, the comparator CMPF1 of the main ADC1 starts comparing the size of the voltage of the positive (+) input terminal and the negative (-) input terminal, and outputs the 5th digital code value BF1<7>.

[0105] According to the result of the 5th comparison, the 6th capacitor 16C of the DACF1 is quantized. After the quantization is completed, the comparator CMPF1 of the main ADC1 starts comparing the size of the voltage of the positive (+) input terminal and the negative (-) input terminal, and outputs the 6th digital code value BF1<6>.

[0106] According to the result of the 6th comparison, the 7th capacitor 8C of the DACF1 is quantized. After the quantization is completed, the comparator CMPF1 of the main ADC1 starts comparing the size of the voltage of the positive (+) input terminal and the negative (-) input terminal, and outputs the 7th digital code value BF1<5>.

[0107] According to the result of the 7th comparison, the 8th capacitor 8C of the DACF1 is quantized. After the quantization is completed, the comparator CMPF1 of the main ADC1 starts comparing the size of the voltage of the positive (+) input terminal and the negative (-) input terminal, and outputs the 8th digital code value BF1<4>.

[0108] According to the result of the 8th comparison, the 9th capacitor 4C of the DACF1 is quantized. After the quantization is completed, the comparator CMPF1 of the main ADC1 starts comparing the size of the voltage of the positive (+) input terminal and the negative (-) input terminal, and outputs the 9th digital code value BF1<3>.

[0109] According to the result of the 9th comparison, the 10th capacitor 2C of the DACF1 is quantized. After the quantization is completed, the comparator CMPF1 of the main ADC1 starts comparing the size of the voltage of the positive (+) input terminal and the negative (-) input terminal, and outputs the 10th digital code value BF1<2>.

[0110] According to the result of the 10th comparison, the 11th capacitor 1C of the DACF1 is quantized. After the quantization is completed, the comparator CMPF1 of the main ADC1 starts comparing the size of the voltage of the positive (+) input terminal and the negative (-) input terminal, and outputs the 11th digital code value BF1<1>.

[0111] According to the 11th comparison result, the 12th capacitor 1C of DACF1 is quantized. After quantization, the comparator CMPF1 of the main ADC1 starts to compare the voltage of the positive (+) input end and the negative (-) input end, and outputs the 12th digital code value BF1<0>.

[0112] When the 2nd sampling stage is performed, as Figure 2 When CLK S and CLKF<2> are high, the auxiliary ADC and the main ADC2 are connected to the common mode voltage Vcm switch and the sampling switch composed of the gate voltage bootstrap circuit, which are closed under the driving of CLK S and CLKF<2> high level. The lower plate of DAC1 and DACF2 starts to sample, at this time, the upper plate is connected to the common mode voltage Vcm, and the lower plate of the two groups of non-binary DAC capacitor arrays of the differential circuit is connected to the input signal Vin and Vip respectively. When CLK S and CLKF<2> are low, the common mode voltage Vcm switch and the sampling switch are disconnected under the driving of CLK S and CLKF<2> low level, and the 2nd sampling of the input signal is completed.

[0113] The 2nd quantization stage is started, and the timing and logic circuit starts to quantize the highest bit 23C and 184C of DAC1 and DACF2 under the driving of the timing signal. After quantization, the first comparator CMPC1 starts to compare the voltage of the positive (+) input end and the negative (-) input end, and outputs the 1st digital code value B<11>.

[0114] According to the 1st comparison result, the 2nd highest bit 16C and 128C of DAC1 and DACF2 are quantized. After quantization, the first comparator CMPC1 of the auxiliary ADC starts to compare the voltage of the positive (+) input end and the negative (-) input end, and outputs the 2nd digital code value B<10>.

[0115] According to the 2nd comparison result, the 3rd capacitor 25C and 64C of DAC1 and DACF2 are quantized. After quantization, the first comparator CMPC1 of the auxiliary ADC starts to compare the voltage of the positive (+) input end and the negative (-) input end, and outputs the 3rd digital code value B<9>.

[0116] According to the 3rd comparison result, the 4th capacitor 64C of DACF2 is quantized. After quantization, the second comparator CMPF2 of the main ADC2 starts to compare the voltage of the positive (+) input end and the negative (-) input end, and outputs the 4th digital code value BF2<8>.

[0117] According to the result of the 4th comparison, the 5th capacitor 32C of DACF2 is quantized. After the quantization, the second comparator CMPF2 of main ADC2 starts to compare the voltage of the positive (+) input terminal and the negative (-) input terminal, and outputs the 5th digital code value BF2<7>.

[0118] According to the result of the 5th comparison, the 6th capacitor 16C of DACF2 is quantized. After the quantization, the second comparator CMPF2 of main ADC2 starts to compare the voltage of the positive (+) input terminal and the negative (-) input terminal, and outputs the 6th digital code value BF2<6>.

[0119] According to the result of the 6th comparison, the 7th capacitor 8C of DACF2 is quantized. After the quantization, the second comparator CMPF2 of main ADC2 starts to compare the voltage of the positive (+) input terminal and the negative (-) input terminal, and outputs the 7th digital code value BF2<5>.

[0120] According to the result of the 7th comparison, the 8th capacitor 8C of DACF2 is quantized. After the quantization, the second comparator CMPF2 of main ADC2 starts to compare the voltage of the positive (+) input terminal and the negative (-) input terminal, and outputs the 8th digital code value BF2<4>.

[0121] According to the result of the 8th comparison, the 9th capacitor 4C of DACF2 is quantized. After the quantization, the second comparator CMPF2 of main ADC2 starts to compare the voltage of the positive (+) input terminal and the negative (-) input terminal, and outputs the 9th digital code value BF2<3>.

[0122] According to the result of the 9th comparison, the 10th capacitor 2C of DACF2 is quantized. After the quantization, the second comparator CMPF2 of main ADC2 starts to compare the voltage of the positive (+) input terminal and the negative (-) input terminal, and outputs the 10th digital code value BF2<2>.

[0123] According to the result of the 10th comparison, the 11th capacitor 1C of DACF2 is quantized. After the quantization, the second comparator CMPF2 of main ADC2 starts to compare the voltage of the positive (+) input terminal and the negative (-) input terminal, and outputs the 11th digital code value BF2<1>.

[0124] According to the result of the 11th comparison, the 12th capacitor 1C of DACF2 is quantized. After the quantization, the second comparator CMPF2 of main ADC2 starts to compare the voltage of the positive (+) input terminal and the negative (-) input terminal, and outputs the 12th digital code value BF2<0>.

[0125] In the 3rd sampling stage, as shown in Fig. 6, the voltage of the positive (+) input terminal and the negative (-) input terminal is compared, and the 5th digital code value BF2<7> is outputted. Figure 2When CLK S and CLK F<3> are high, the auxiliary ADC and the main ADC 3 connect the switch of common mode voltage Vcm and the sampling switch composed of the gate voltage bootstrap circuit are closed under the driving of CLK S and CLK F<3> high level, the lower plate of DAC1 and DAC F3 starts sampling, at this time the upper plate is connected to the common mode voltage Vcm, the lower plate of the two groups of non-binary DAC capacitor arrays of the differential circuit is connected to the input signal Vin and Vip respectively. When CLK S and CLK F<3> are low, the switch of common mode voltage Vcm and the sampling switch are disconnected under the driving of CLK S and CLK F<2> low level, the third sampling of the input signal is completed.

[0126] The third quantization stage is started, and the timing and logic circuit starts quantizing the highest bit 23C and 184C of DAC1 and DAC F3 under the driving of the timing signal. After quantization, the first comparator CMPC1 starts comparing the size of the positive (+) input end and the negative (-) input end voltage. And output the first digital code value B<11>.

[0127] According to the first comparison result, the next highest bit 16C and 128C of DAC1 and DAC F3 are quantized. After quantization, the first comparator CMPC1 of the auxiliary ADC starts comparing the size of the positive (+) input end and the negative (-) input end voltage. And output the second digital code value B<10>.

[0128] According to the second comparison result, the third capacitor 25C and 64C of DAC1 and DAC F3 are quantized. After quantization, the first comparator CMPC1 of the auxiliary ADC starts comparing the size of the positive (+) input end and the negative (-) input end voltage. And output the third digital code value B<9>.

[0129] According to the third comparison result, the fourth capacitor 64C of DAC F3 is quantized. After quantization, the second comparator CMPF3 of the main ADC 3 starts comparing the size of the positive (+) input end and the negative (-) input end voltage. And output the fourth digital code value BF3<8>.

[0130] According to the fourth comparison result, the fifth capacitor 32C of DAC F3 is quantized. After quantization, the second comparator CMPF3 of the main ADC 3 starts comparing the size of the positive (+) input end and the negative (-) input end voltage. And output the fifth digital code value BF3<7>.

[0131] According to the fifth comparison result, the sixth capacitor 16C of DAC F3 is quantized. After quantization, the second comparator CMPF3 of the main ADC 3 starts comparing the size of the positive (+) input end and the negative (-) input end voltage. And output the sixth digital code value BF3<6>.

[0132] Based on the result of the 6th comparison, the 7th bit capacitor 8C of DACF3 is quantized. After quantization, the second comparator CMPF3 of the main ADC3 begins comparing the voltages at the positive (+) and negative (-) input terminals, and outputs the 7th bit digital code value BF3. <5> .

[0133] Based on the result of the 7th comparison, the 8th capacitor 8C of DACF3 is quantized. After quantization, the second comparator CMPF3 of the main ADC3 begins comparing the voltages at the positive (+) and negative (-) input terminals, and outputs the 8th digital code value BF3. <4> .

[0134] Based on the result of the 8th comparison, the 9th bit capacitor 4C of DACF3 is quantized. After quantization, the second comparator CMPF3 of the main ADC3 begins comparing the voltages at the positive (+) and negative (-) input terminals, and outputs the 9th bit digital code value BF3. <3> .

[0135] Based on the result of the 9th comparison, the 10th bit capacitor 2C of DACF3 is quantized. After quantization, the second comparator CMPF3 of the main ADC3 begins comparing the voltages at the positive (+) and negative (-) input terminals, and outputs the 10th bit digital code value BF3. <2> .

[0136] Based on the result of the 10th comparison, the 11th bit capacitor 1C of DACF3 is quantized. After quantization, the second comparator CMPF3 of the main ADC3 begins comparing the voltages at the positive (+) and negative (-) input terminals, and outputs the 11th bit digital code value BF3. <1> .

[0137] Based on the result of the 11th comparison, the 12th bit capacitor 1C of DACF3 is quantized. After quantization, the second comparator CMPF3 of the main ADC3 begins comparing the voltages at the positive (+) and negative (-) input terminals, and outputs the 12th bit digital code value BF3. <0> .

[0138] During the fourth sampling phase, such as Figure 2 CLKS and CLKF <4> When the level is high, the auxiliary ADC and main ADC4 are connected to the common-mode voltage Vcm switch and the sampling switch composed of the gate voltage bootstrap circuit at CLKS and CLKF. <4> When driven by a high level, the lower plates of DAC1 and DACF4 begin sampling. At this time, the upper plates are first connected to the common-mode voltage Vcm. The lower plates of the two sets of non-binary DAC capacitor arrays in the differential circuit are connected to the input signals Vin and Vip, respectively. CLKS and CLKF <4> When the level is low, the switching and sampling switches for the common-mode voltage Vcm are at CLKS and CLKF. <4> Disconnect when driven by a low level, completing the fourth sampling of the input signal.

[0139] The 4th quantization stage is started, the timing and logic circuit is driven by the timing signal to start quantizing the highest bits 23C and 184C of DAC1 and DACF4. After the quantization, the first comparator CMPC1 starts comparing the voltage of the positive (+) input and the negative (-) input, and outputs the 1st digital code value B<11>.

[0140] According to the 1st comparison result, the next highest bits 16C and 128C of DAC1 and DACF4 are quantized. After the quantization, the first comparator CMPC1 of the auxiliary ADC starts comparing the voltage of the positive (+) input and the negative (-) input, and outputs the 2nd digital code value B<10>.

[0141] According to the 2nd comparison result, the 3rd bits 25C and 64C of DAC1 and DACF4 are quantized. After the quantization, the first comparator CMPC1 of the auxiliary ADC starts comparing the voltage of the positive (+) input and the negative (-) input, and outputs the 3rd digital code value B<9>.

[0142] According to the 3rd comparison result, the 4th bit 64C of DACF4 is quantized. After the quantization, the second comparator CMPF4 of the main ADC4 starts comparing the voltage of the positive (+) input and the negative (-) input, and outputs the 4th digital code value BF4<8>.

[0143] According to the 4th comparison result, the 5th bit 64C of DACF4 is quantized. After the quantization, the second comparator CMPF4 of the main ADC4 starts comparing the voltage of the positive (+) input and the negative (-) input, and outputs the 5th digital code value BF4<7>.

[0144] According to the 5th comparison result, the 6th bit 32C of DACF4 is quantized. After the quantization, the second comparator CMPF4 of the main ADC4 starts comparing the voltage of the positive (+) input and the negative (-) input, and outputs the 6th digital code value BF4<6>.

[0145] According to the 6th comparison result, the 7th bit 16C of DACF4 is quantized. After the quantization, the second comparator CMPF4 of the main ADC4 starts comparing the voltage of the positive (+) input and the negative (-) input, and outputs the 7th digital code value BF4<5>.

[0146] According to the 7th comparison result, the 8th bit 8C of DACF4 is quantized. After the quantization, the second comparator CMPF4 of the main ADC4 starts comparing the voltage of the positive (+) input and the negative (-) input, and outputs the 8th digital code value BF4<4>.

[0147] According to the 9th comparison result, the 10th capacitor 2C of the DACF4 is quantized. After quantization, the second comparator CMPF4 of the main ADC4 starts to compare the size of the positive (+) input terminal and the negative (-) input terminal voltage, and outputs the 10th digital code value BF4<2>.

[0148] According to the 9th comparison result, the 10th capacitor 2C of the DACF4 is quantized. After quantization, the second comparator CMPF4 of the main ADC4 starts to compare the size of the positive (+) input terminal and the negative (-) input terminal voltage, and outputs the 10th digital code value BF4<2>.

[0149] According to the 9th comparison result, the 10th capacitor 2C of the DACF4 is quantized. After quantization, the second comparator CMPF4 of the main ADC4 starts to compare the size of the positive (+) input terminal and the negative (-) input terminal voltage, and outputs the 10th digital code value BF4<2>.

[0150] According to the 9th comparison result, the 10th capacitor 2C of the DACF4 is quantized. After quantization, the second comparator CMPF4 of the main ADC4 starts to compare the size of the positive (+) input terminal and the negative (-) input terminal voltage, and outputs the 10th digital code value BF4<2>.

[0151] At the 2nd sampling of the main ADC1, the 9-bit output result BF1<8:0> after the 1st sampling and quantization of the main ADC1 and the 3-bit output result B<11:9> after the 1st sampling and quantization of the auxiliary ADC are selected by the control signal CLKCT<1:2> of the timing and logic circuit to splice, and then output after decoding by the digital error correction circuit. The 3-bit non-binary digital code B<11:9> of the auxiliary ADC and the 9-bit non-binary digital code BF1<8:0> of the main ADC1 are converted into 10-bit binary digital code.

[0152] At the 2nd sampling of the main ADC2, the 9-bit output result BF2<8:0> after the 1st sampling and quantization of the main ADC2 and the 3-bit output result B<11:9> after the 2nd sampling and quantization of the auxiliary ADC are selected by the control signal CLKCT<1:2> of the timing and logic circuit to splice, and then output after decoding by the digital error correction circuit. The 3-bit non-binary digital code B<11:9> of the auxiliary ADC and the 9-bit non-binary digital code BF2<8:0> of the main ADC2 are converted into 10-bit binary digital code.

[0153] At the 2nd sampling of the main ADC 3, the 1st sampling and quantized 8-bit output result BF3<8:0> of the main ADC 3 and the 3rd sampling and quantized 3-bit output result B<11:9> of the auxiliary ADC are selected to be spliced by the control signal CLKCT<1:2> of the timing and logic circuit, and the spliced result is decoded and output by the digital error correction circuit. The 3-bit non-binary digital code B<11:9> of the auxiliary ADC and the 9-bit non-binary digital code BF3<8:0> of the main ADC 3 are converted into a 10-bit binary digital code.

[0154] At the 2nd sampling of the main ADC 4, the 1st sampling and quantized 9-bit output result BF4<8:0> of the main ADC 4 and the 4th sampling and quantized 3-bit output result B<11:9> of the auxiliary ADC are selected to be spliced by the control signal CLKCT<1:2> of the timing and logic circuit, and the spliced result is decoded and output by the digital error correction circuit. The 3-bit non-binary digital code B<11:9> of the auxiliary ADC and the 9-bit non-binary digital code BF4<8:0> of the main ADC 4 are converted into a 10-bit binary digital code.

[0155] The first four groups of quantization are completed, and the decoded four groups of binary digital code values are output, and a complete working cycle of the multi-channel high-speed low-power SAR ADC is completed.

[0156] In the architecture of the multi-channel high-speed low-power successive approximation analog-to-digital converter proposed in the application, the main ADC has high precision, the high-bit capacitor is large, and the setup time is relatively long when the high-bit is switched. Direct quantization of the high-M-bit by the auxiliary ADC saves the switching and quantization process of the high-bit capacitor of the second non-binary DAC capacitor array of the main ADC, and directly loads the code value of the auxiliary ADC to the corresponding weight bit of the main ADC. On the other hand, the auxiliary SAR ADC with low precision requires a small capacitor area and a shorter setup time, and a shorter quantization period allocated to the ADC can achieve a faster conversion speed, effectively improving the overall working speed, thereby improving the sampling rate. In addition, the second non-binary DAC capacitor array of the main ADC applies a two-level reference level structure, which reduces the number of unit capacitors from N to N / 2+1, greatly reduces the number of capacitors used, and significantly reduces the power consumption. In addition, the four main ADCs adopt a four-group interleaving mode, which fully utilizes the auxiliary ADC and further improves the working speed of the overall circuit.

[0157] In one exemplary embodiment, as shown in Figure 3 A working method of the multi-channel high-speed low-power successive approximation analog-to-digital converter is provided, and the working method of the multi-channel high-speed low-power successive approximation analog-to-digital converter includes the following steps.

[0158] A1: Sampling stage. Based on an auxiliary ADC and a main ADC, a first gate voltage bootstrap circuit and a second gate voltage bootstrap circuit are used to simultaneously receive an analog signal of the same external input, and a first non-binary DAC capacitor array and a second non-binary DAC capacitor array are used to sample and store the sampling charges of the analog signal, respectively, to obtain a first upper plate voltage pair and a second upper plate voltage pair.

[0159] A2: Quantization stage. The first M bits of the first non-binary DAC capacitor array and the second non-binary DAC capacitor array are sequentially quantized. After each quantization, a first comparator is used to compare the first upper plate voltage pair to obtain a first comparison result, and a first successive approximation logic module is used to perform successive approximation quantization based on the first comparison result to obtain an M-bit non-binary digital code. Based on the first M-bit code value, the remaining N-M bits of the second non-binary DAC capacitor array are sequentially quantized. After each quantization, a second comparator is used to compare the second upper plate voltage pair to obtain a second comparison result, and a second successive approximation logic module is used to perform successive approximation quantization based on the M-bit non-binary digital code and the second comparison result to obtain an N-M-bit non-binary digital code.

[0160] A3: Digital error correction stage. A digital error correction circuit is used to combine and binary-convert the M-bit non-binary digital code and the N-M-bit non-binary digital code to obtain a binary digital code.

[0161] A4: Repeat steps A1 to A3 n times to obtain n sets of binary digital codes and output.

[0162] In one exemplary embodiment, as shown in Figure 4 a multi-channel high-speed low-power successive approximation analog-to-digital conversion method based on the multi-channel high-speed low-power successive approximation analog-to-digital converter is provided, which includes the following steps.

[0163] B1: Obtain an analog signal of an external input.

[0164] B2: Sample the analog signal to determine a first upper plate voltage pair and a second upper plate voltage pair.

[0165] B3: Compare the first upper plate voltage pair to obtain a first comparison result, and simultaneously compare the second upper plate voltage pair to obtain a second comparison result.

[0166] B4: Perform successive approximation quantization based on the first comparison result to obtain an M-bit non-binary digital code.

[0167] B5: based on the M-bit non-binary digital code, according to the second comparison result, successive approximation quantization is performed to obtain an N-M-bit non-binary digital code.

[0168] B6: the M-bit non-binary digital code and the N-M-bit non-binary digital code are combined and binary converted to obtain a group of binary digital codes.

[0169] B7: return to the step of "sampling the analog signal respectively, determining the first upper plate voltage pair and the second upper plate voltage pair", to obtain n groups of binary digital codes and output.

[0170] In an exemplary embodiment, as shown in Figure 5 A multi-channel high-speed low-power successive approximation analog-to-digital conversion system is provided, which applies the multi-channel high-speed low-power successive approximation analog-to-digital conversion method as described, and comprises the following functional modules.

[0171] An analog signal acquisition module is configured to acquire an externally input analog signal.

[0172] A sampling module is configured to sample the analog signal respectively, and determine a first upper plate voltage pair and a second upper plate voltage pair.

[0173] A comparison module is configured to compare the first upper plate voltage pair to obtain a first comparison result, and compare the second upper plate voltage pair to obtain a second comparison result.

[0174] A first quantization module is configured to perform successive approximation quantization according to the first comparison result to obtain an M-bit non-binary digital code.

[0175] A second quantization module is configured to perform successive approximation quantization according to the second comparison result based on the M-bit non-binary digital code to obtain an N-M-bit non-binary digital code.

[0176] A conversion module is configured to combine and binary convert the M-bit non-binary digital code and the N-M-bit non-binary digital code to obtain a group of binary digital codes.

[0177] A multi-channel resampling quantization conversion output module is configured to drive the sampling module, the comparison module, the first quantization module, the second quantization module, and the conversion module to work in a loop, to realize the process of multi-channel resampling, quantization, conversion, and output, to obtain n groups of binary digital codes and output.

[0178] In this embodiment, the first non-binary DAC capacitor array and the second non-binary DAC capacitor array both adopt a binary redundant reorganization structure, which can introduce redundancy in the quantization process, reduce the overall quantization time, and improve the quantization speed. In terms of speed, compared with the main ADC, the accuracy of the auxiliary ADC is slightly lower, and the low-precision auxiliary ADC requires less capacitor area and shorter setup time, which can achieve faster conversion speed. The high 3 bits of the main ADC do not need to be quickly established, but are directly loaded with the code value of the auxiliary ADC, thereby effectively improving the working speed of the overall ADC and increasing the sampling rate. The high-precision main ADC determines the accuracy of the final ADC, and requires longer setup time. Compared with the auxiliary ADC, the main ADC can allocate 4 times the quantization time through the frequency divider, and the main ADC allocates 4 times the working time per cycle, so that the DAC quantization time is more sufficient, ensuring accurate conversion of the ADC. In terms of power consumption, since the auxiliary ADC quantizes earlier than the main ADC, the switching frequency of the large capacitors in the highest 3 bits of the main ADC is effectively reduced, and the power consumption waste caused by unnecessary capacitor switching is reduced. In terms of linearity, since a two-level reference level is introduced in the lowest bit of the main ADC, the total capacitor quantity can be reduced by half, and the unit capacitor can be made larger while the total capacitor quantity is reduced by a factor of two, thereby reducing the nonlinearity problem caused by capacitor mismatch. Moreover, the four main ADCs adopt a four-group interleaving manner, which fully utilizes the high-speed advantage of the auxiliary ADC, and can greatly improve the overall sampling speed of the ADC. By using the binary redundant reorganization, auxiliary ADC, four-channel main ADC, and two-level reference level non-binary DAC capacitor array, the quantization time is accelerated, the quantization rate is further improved, the conversion rate and accuracy of the analog-to-digital converter can be significantly improved, the circuit power consumption and area are reduced, and these advantages not only improve the working speed but also reduce the overall power consumption, so that the performance of the ADC architecture of the present application is higher than that of other SAR ADCs.

[0179] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not contradict, they should be considered within the scope of the present disclosure.

[0180] The principles and implementation modes of the present application are described by using specific examples, and the above embodiments are only used to help understand the method and core idea of the present application. For those skilled in the art, according to the idea of the present application, the specific implementation mode and application range can be changed. In summary, the content of the present application should not be understood as a limitation.

Claims

1. A multi-channel high-speed, low-power successive approximation analog-to-digital converter, characterized in that, The multi-channel high-speed low-power successive approximation analog-to-digital converter includes: one M-bit auxiliary ADC, n N-bit main ADCs, a multiplexer, and a digital error correction circuit, wherein M, n, and N are all positive integers, and N ≥ n·M; The auxiliary ADC includes: a first gate voltage bootstrap circuit, a first non-binary DAC capacitor array, a first comparator, and a first successive approximation logic module; Each of the main ADCs includes: a second gate voltage bootstrap circuit, a second non-binary DAC capacitor array, a second comparator, and a second successive approximation logic module; The input terminal of the first non-binary DAC capacitor array is connected to the first gate voltage bootstrap circuit, the output terminal of the first non-binary DAC capacitor array is connected to the input terminal of the first comparator, the output terminal of the first comparator is connected to the input terminal of the first successive approximation logic module, and the output terminal of the first successive approximation logic module is connected to each of the second successive approximation logic modules and the digital error correction circuit respectively. The input terminal of each of the second non-binary DAC capacitor arrays is connected to the corresponding second gate voltage bootstrap circuit, the output terminal of each of the second non-binary DAC capacitor arrays is connected to the input terminal of the corresponding second comparator, the output terminal of each of the second comparators is connected to the input terminal of the corresponding second successive approximation logic module, the output terminal of each of the second successive approximation logic modules is connected to the input terminal of the multiplexer, and the output terminal of the multiplexer is connected to the digital error correction circuit. The first gate voltage bootstrap circuit and the second gate voltage bootstrap circuit are used to receive externally input analog signals and transmit them to their respective first non-binary DAC capacitor array and second non-binary DAC capacitor array; The first non-binary DAC capacitor array and the second non-binary DAC capacitor array are used to sample the analog signal, respectively obtaining the first upper plate voltage pair and the second upper plate voltage pair, and respectively transmitting them to their respective first comparators and second comparators; The first comparator and the second comparator are used to compare the upper plate voltage pairs they receive respectively, and obtain the first comparison result and the second comparison result respectively, and send them to the first successive approximation logic module and the second successive approximation logic module respectively. The first successive approximation logic module is used to perform successive approximation quantization based on the first comparison result, obtain an M-bit non-binary digital code, and send it to each of the second successive approximation logic modules and the digital error correction circuit respectively. Each of the second successive approximation logic modules is used to perform successive approximation quantization based on the M-bit non-binary digital code and according to the corresponding second comparison result to obtain an NM-bit non-binary digital code and send it to the multiplexer. The multiplexer is used to select the NM-bit non-binary digital code obtained by the current main ADC quantization after each main ADC quantization is completed and send it to the digital error correction circuit. The digital error correction circuit is used to combine and convert the M-bit non-binary digital code and each of the NM-bit non-binary digital codes into binary codes to obtain n sets of binary digital codes and output them.

2. The multi-channel high-speed, low-power successive approximation analog-to-digital converter according to claim 1, characterized in that, The multi-channel high-speed low-power successive approximation analog-to-digital converter also includes: timing and logic circuitry; The timing and logic circuits are respectively connected to the first gate voltage bootstrap circuit, each of the second gate voltage bootstrap circuits, the first successive approximation logic module, each of the second successive approximation logic modules, and the multiplexer; The timing and logic circuitry is used to provide clock signals.

3. The multi-channel high-speed, low-power successive approximation analog-to-digital converter according to claim 1, characterized in that, Both the first non-binary DAC capacitor array and the second non-binary DAC capacitor array adopt a non-binary capacitor arrangement structure.

4. The multi-channel high-speed, low-power successive approximation analog-to-digital converter according to claim 1, characterized in that, The second non-binary DAC capacitor array uses a two-level reference level.

5. The multi-channel high-speed, low-power successive approximation analog-to-digital converter according to claim 1, characterized in that, The number of main ADCs is 4.

6. The multi-channel high-speed, low-power successive approximation analog-to-digital converter according to claim 5, characterized in that, The duty cycle of the auxiliary ADC is four times that of the main ADC, and the clock interval of four main ADCs is one duty cycle of the auxiliary ADC.

7. The multi-channel high-speed, low-power successive approximation analog-to-digital converter according to claim 1, characterized in that, The capacitor weight ratio of the first non-binary DAC capacitor array is 23:16:25; the capacitor weight ratio of the second non-binary DAC capacitor array is 184:128:64:64:32:16:8:8:4:2:1:

1.

8. A method for operating a multi-channel high-speed, low-power successive approximation analog-to-digital converter as described in any one of claims 1-7, characterized in that, The operating method of the multi-channel high-speed low-power successive approximation analog-to-digital converter includes: A1: Sampling Phase Based on an auxiliary ADC and a main ADC, the first gate voltage bootstrap circuit and the second gate voltage bootstrap circuit simultaneously receive the same external input analog signal, and the first non-binary DAC capacitor array and the second non-binary DAC capacitor array respectively sample the analog signal and store the sampled charge to obtain the first upper plate voltage pair and the second upper plate voltage pair respectively. A2: Quantification Phase The first M-bit capacitors of the first non-binary DAC capacitor array and the second non-binary DAC capacitor array are sequentially quantized. After each quantization, the voltage of the first upper plate is compared with the voltage of the first plate using the first comparator to obtain the first comparison result. The first successive approximation logic module is then used to perform successive approximation quantization based on the first comparison result to obtain the M-bit non-binary digital code. Based on the first M bits of code value, the remaining NM bits of the capacitors in the second non-binary DAC capacitor array are sequentially quantized. After each quantization, the voltage of the second upper plate is compared with the second comparator to obtain the second comparison result. The second successive approximation logic module is then used to perform successive approximation quantization based on the M bits of non-binary digital code and the second comparison result to obtain the NM bits of non-binary digital code. A3: Digital Error Correction Stage: Using a digital error correction circuit, the M-bit non-binary digital code and the NM-bit non-binary digital code are combined and converted into binary to obtain a binary digital code. A4: Repeat steps A1 to A3 n times to obtain n sets of binary digital codes and output them.

9. A method for multi-channel high-speed, low-power successive approximation analog-to-digital conversion based on any one of claims 1-7, characterized in that, The multi-channel high-speed, low-power successive approximation analog-to-digital conversion method includes: Acquire externally input analog signals; The analog signals are sampled respectively to determine the first upper plate voltage pair and the second upper plate voltage pair; The voltage pairs of the first upper plate are compared to obtain a first comparison result; at the same time, the voltage pairs of the second upper plate are compared to obtain a second comparison result. Based on the first comparison result, successive approximation quantization is performed to obtain an M-bit non-binary digital code. Based on the M-bit non-binary digital code, successive approximation quantization is performed according to the second comparison result to obtain an NM-bit non-binary digital code. The M-bit non-binary digital code and the NM-bit non-binary digital code are combined and converted into binary to obtain a set of binary digital codes. Returning to the step of "sampling the analog signals respectively to determine the first upper plate voltage pair and the second upper plate voltage pair", n sets of binary digital codes are obtained and output.

10. A multi-channel, high-speed, low-power successive approximation analog-to-digital converter system, characterized in that, The multi-channel high-speed, low-power successive approximation analog-to-digital converter system uses the multi-channel high-speed, low-power successive approximation analog-to-digital converter method as described in claim 9. The multi-channel high-speed, low-power successive approximation analog-to-digital converter system includes: Analog signal acquisition module, used to acquire externally input analog signals; The sampling module is used to sample the analog signals respectively to determine the first upper plate voltage pair and the second upper plate voltage pair; The comparison module is used to compare the voltage pairs of the first upper plate to obtain a first comparison result; and simultaneously compare the voltage pairs of the second upper plate to obtain a second comparison result. The first quantization module is used to perform successive approximation quantization based on the first comparison result to obtain an M-bit non-binary digital code. The second quantization module is used to perform successive approximation quantization based on the M-bit non-binary digital code and according to the second comparison result to obtain an NM-bit non-binary digital code. The conversion module is used to combine and convert the M-bit non-binary digital code and the NM-bit non-binary digital code into binary code to obtain a set of binary digital codes. The multi-channel resampling quantization conversion output module is used to drive the sampling module, comparison module, first quantization module, second quantization module and conversion module to work in a loop, realize the process of multi-channel resampling, quantization, conversion and output, and obtain n sets of binary digital codes and output them.

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