Wafer aging test system and method with dynamic gate bias and reverse bias test function

Abstract

The invention relates to the technical field of wafer testing, and discloses a wafer aging test system and method with a dynamic gate bias and reverse bias test function, and the system comprises a main control board, an industrial control computer, a high-voltage source, a source meter, a high-voltage switching board, a test switching board, and a needle card board. Dynamic high-temperature reverse bias and dynamic high-temperature gate bias tests can be added on the basis of static high-temperature reverse bias and reverse bias tests, higher requirements for SiC power device reliability testing equipment in the industry are met, stress borne by a chip under the actual working condition can be simulated, and the reliability of the SiC power device is improved. And the threshold voltage is monitored on line in real time while the pulse voltage is implemented, so that the reliability of the chip can be better evaluated.

Description

Technical Field

[0001] This invention relates to the field of wafer testing technology, and in particular to a wafer aging test system and method with dynamic gate bias and reverse bias testing functions. Background Technology

[0002] After silicon carbide (SiC) power devices are manufactured from wafers, they still need to be diced. Before being diced into individual chips, a series of routine tests are required, including high-temperature reverse bias, high-temperature gate bias, and threshold voltage (VTH) tests, to ensure that each chip meets the expected specifications and performance standards. However, these test conditions are insufficient to ensure that defects in SiC power devices can be quickly detected. A test is needed to apply stress to the device to simulate the operating conditions of actual production applications. Therefore, dynamic reverse bias and gate bias tests are essential. The principle is to simulate the aging process of the chip by rapidly charging and discharging the gate or drain at high dV / dt.

[0003] A wafer aging test system is disclosed in the related technology. It is only for high temperature reverse bias or gate bias test in static state. It cannot determine the threshold voltage drift caused by long-term dynamic switching process, which brings the risk of shoot-through failure or thermal failure of the system. Summary of the Invention

[0004] In view of this, the present invention provides a wafer aging test system and method with dynamic gate bias and reverse bias test functions, so as to solve or partially solve the technical problem that related solutions do not have dynamic high temperature reverse bias and dynamic high temperature gate bias test functions.

[0005] The technical solution proposed in this invention is as follows:

[0006] In a first aspect, the present invention provides a wafer aging test system with dynamic gate bias and reverse bias testing functions, comprising: a main control board, an industrial computer, a high-voltage source, a source meter, a high-voltage switching board, a test switching board, and a pin card board. The main control board is equipped with a main control unit, the high-voltage switching board is equipped with a high-voltage switching circuit, and the test switching board is equipped with a test switching circuit. The pin card board is used to assemble the wafer under test. The output terminal of the high-voltage source is connected to the input terminal of the high-voltage switching circuit, and the output terminal of the high-voltage switching circuit is connected to the test switching circuit. The main control unit controls the voltage output to the test switching circuit through the high-voltage switching circuit. The test switching circuit is connected to the source meter. The main control unit controls the test switching circuit to select the output voltage of the high-voltage switching circuit to output to different electrodes of the wafer under test, and selects whether to output the bipolar high-frequency pulse signal generated by the source meter to the gate of the wafer under test. The source meter measures the gate voltage and source voltage of the wafer under test. The industrial computer is connected to the main control unit, the high-voltage source, and the source meter respectively, and is used to control the operation of the main control unit, the high-voltage source, and the source meter.

[0007] In some alternative implementations, the high-voltage switching circuit includes a first IGBT device, a second IGBT device, a first IGBT driver, a second IGBT driver, a first resistor, and a second resistor;

[0008] The drain of the first IGBT device is connected to the output terminal of the high voltage source. The gate of the first IGBT device is connected to the output terminal of the first IGBT driver through the first resistor. The source of the first IGBT device is connected to the test switching circuit and the drain of the second IGBT device. The gate of the second IGBT device is connected to the output terminal of the second IGBT driver through the second resistor. The source of the second IGBT device is grounded.

[0009] In some alternative embodiments, the resistance values ​​of both the first resistor and the second resistor are 1.1KΩ to 1.3KΩ.

[0010] In some alternative implementations, the test switching circuit includes a first relay, a second relay, a third relay, a fourth relay, a fifth relay, a sixth relay, a third resistor, and a fourth resistor;

[0011] The output of the high-voltage switching circuit is connected to the gate of the wafer under test via the first relay. The output of the high-voltage switching circuit is connected to the source of the wafer under test via the second relay. The gate of the wafer under test is connected to the first interface of the source meter via the third relay, to the first end of the third resistor via the fourth relay, to the first end of the second resistor via the fifth relay, to the second end of the source meter via the second resistor, to the second end of the third resistor, to ground via the second end of the fourth resistor, and the source of the wafer under test is connected to the first end of the second resistor and to the third interface of the source meter via the sixth relay.

[0012] In some alternative implementations, the wafer aging test system with dynamic gate bias and reverse bias testing capabilities also includes a precision meter for measuring the gate voltage and source voltage of the wafer under test.

[0013] In some alternative implementations, the wafer aging test system with dynamic gate bias and reverse bias testing functions also includes a pin card adapter board, which is used to connect the test switching board and the wafer under test on the pin card board.

[0014] In some alternative implementations, the wafer aging test system with dynamic gate bias and reverse bias testing functions also includes an electrical control board, which is used to control the on and off of the first, second, third, fourth, fifth and sixth relays via I / O modules.

[0015] In some alternative implementations, the wafer to be tested is a silicon carbide wafer.

[0016] Secondly, the present invention provides a wafer aging test method with dynamic gate bias and reverse bias test functions, applied to a wafer aging test system with dynamic gate bias and reverse bias test functions as described in any of the first aspects of the present invention, comprising: performing dynamic high-temperature reverse bias test and dynamic high-temperature gate bias test by controlling the on and off intervals of a first IGBT device, a second IGBT device, a first relay, a second relay, a third relay, a fourth relay, a fifth relay, and a sixth relay; performing a threshold voltage test during the interval between the dynamic high-temperature reverse bias test and the dynamic high-temperature gate bias test, wherein the interval between the dynamic high-temperature reverse bias test and the dynamic high-temperature gate bias test is less than 1 minute.

[0017] In some optional implementations, during dynamic high-temperature reverse bias testing, the fourth and sixth relays are turned on, the second and third relays are turned off, the fifth relay is turned off before testing, and the fifth relay is turned on during aging. The first and second IGBT devices are controlled to switch intermittently between a first state and a second state, wherein the first state is when the first IGBT device is turned on and the second IGBT device is turned off, and the second state is when the first IGBT device is turned off and the second IGBT device is turned on. During dynamic high-temperature gate bias testing, the third and sixth relays are turned on, the second and fifth relays are turned off, the fourth relay is turned off before testing, and the fourth relay is turned on during aging. The source meter outputs a bipolar pulse signal. During threshold voltage testing, the third and sixth relays are turned on, the fourth and fifth relays are turned off, the second relay is turned on first, then turned off, and then the first relay is turned on to test the threshold voltage.

[0018] The present invention has the following beneficial effects:

[0019] The wafer aging test system of the present invention with dynamic gate bias and reverse bias test functions, through the coordinated use of main control board, industrial control computer, high voltage source, source meter, high voltage switching board, test switching board and pin card board, can add dynamic high temperature reverse bias and dynamic high temperature gate bias tests on the basis of static high temperature reverse bias and reverse bias tests, meet the higher requirements of the industry for SiC power device reliability test equipment, and can simulate the stress that the chip is subjected to under actual working conditions, while applying pulse voltage and monitoring the threshold voltage online in real time, thereby better evaluating the reliability of the chip. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the wafer aging test system with dynamic gate bias and reverse bias test functions in an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of the high-voltage switching circuit in an embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of the test switching circuit in an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of the signal output of the IGBT driver during the DHTRB test in an embodiment of the present invention;

[0025] Figure 5 This is a circuit topology diagram for performing threshold voltage VTH testing in an embodiment of the present invention;

[0026] Figure 6 This is a schematic diagram of the source meter's operation during threshold voltage VTH testing in an embodiment of the present invention;

[0027] Figure 7 This is a flowchart of dynamic testing for three test modes in an embodiment of the present invention.

[0028] Explanation of reference numerals in the attached figures:

[0029] R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; Q1, first IGBT device; Q2, second IGBT device; KGD, first relay; KDS, second relay; KG, third relay; KVG, fourth relay; KGS, fifth relay; KS, sixth relay. Detailed Implementation

[0030] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] In the description of this invention, it should be noted that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0032] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0033] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0034] A wafer aging test system is disclosed in the related technology, which is only for high temperature reverse bias or gate bias test in static state. It cannot determine the threshold voltage drift caused by long-term dynamic switching process, thus bringing the risk of shoot-through failure or thermal failure of the system. In addition, the threshold voltage test in the related technology is affected by the gate dynamic voltage and cannot be monitored in real time. The threshold voltage drift will recover at an exponential rate after the stress ends.

[0035] Therefore, this invention proposes a wafer aging test system with dynamic high temperature reverse bias (DHTRB) and dynamic high temperature gate bias (DHTGB) testing functions, which can monitor the threshold voltage in real time during the aging process. This not only solves the above problems well, but also saves the testing cost of the wafer aging test system.

[0036] like Figure 1As shown, the wafer aging test system with dynamic gate bias and reverse bias testing functions according to an embodiment of the present invention includes: a main control board, an industrial computer, a high-voltage source, a source meter, a high-voltage switching board, a test switching board, and a pin card board. The main control board is equipped with a main control unit, the high-voltage switching board is equipped with a high-voltage switching circuit, and the test switching board is equipped with a test switching circuit. The pin card board is used to assemble the wafer under test. The output terminal of the high-voltage source is connected to the input terminal of the high-voltage switching circuit, and the output terminal of the high-voltage switching circuit is connected to the test switching circuit. The main control unit controls the voltage output to the test switching circuit through the high-voltage switching circuit. The test switching circuit is connected to the source meter. The main control unit controls the test switching circuit to select the output voltage of the high-voltage switching circuit to output to different electrodes of the wafer under test, and selects whether to output the bipolar high-frequency pulse signal generated by the source meter to the gate of the wafer under test. The source meter measures the gate voltage and source voltage of the wafer under test. The industrial computer is connected to the main control unit, the high-voltage source, and the source meter respectively, and is used to control the operation of the main control unit, the high-voltage source, and the source meter.

[0037] Specifically, the wafer under test is a silicon carbide wafer, and each wafer under test has three electrodes: gate, source, and drain.

[0038] The main control unit uses a microcontroller unit (MCU), specifically the STM32MP series. It features an I / O bus supporting the IIC protocol. The test switching board selects the voltage applied to the wafer under test (DUT) via multiple relays. The relays and the main control unit transmit data via the IIC protocol. The test switching board includes I / O expansion chips, which can expand the I / O after IIC signal input and allocate it to the DUT channels on the pincard board, thus achieving the purpose of I / O expansion.

[0039] The operating voltage of the main control board, high voltage switching board and test switching board is provided by a switching power supply with 12V DC output, and the gate negative voltage is output through an isolated power supply and a low-dropout regulator (LDO).

[0040] The microcontroller unit (MCU) interacts with the industrial computer via Ethernet through a switch and connects to the high-voltage switching board and the test switching board via an IDE connector. The high-voltage switching board and the test switching board can be integrated on a single circuit board or set up separately.

[0041] The industrial control computer is a common industrial control computer on the market, with functions such as calculation, programming, and chart editing. The industrial control computer is connected to the main control unit, high voltage source and source meter via Ethernet to exchange data.

[0042] Furthermore, the wafer aging test system with dynamic gate bias and reverse bias testing functions also includes a pin card adapter board. The test switching circuit is electrically connected to the pin card adapter board via a backplane. The test switching board and the pin card adapter board are connected via a 200-pin connector, and the pin card adapter board and the pin card board are electrically connected under automatic control. The pin card board is equipped with wafer pin cards, which are led out to the left and right connection areas through gate and source pads. The pin card adapter board transmits electrical signals through test probes contacting the wafer pin cards. The test switching board connects the source meter or high voltage source signal to the wafer inside the pin card board through this connection. The wafer pin card contains the wafer under test, and the gate and source signals of the wafer under test are led out internally, and after being depressurized, they are electrically connected to the pin card adapter board. The measured data is also transmitted back to the source meter through this connection.

[0043] In some embodiments, the wafer aging test system with dynamic gate bias and reverse bias testing functions further includes a precision meter and a data acquisition board. The precision meter is used to measure the gate voltage and source voltage of the wafer under test. The measured data can be selectively transmitted back to either the source meter or the precision meter. The precision meter has high-precision measurement capabilities, enabling more accurate measurement of the wafer's voltage parameters and improving the reliability of the test results. The data acquisition board is electrically connected to the main control board. The data obtained from the source meter and the precision meter is transmitted to the main control board through the data acquisition board, and then transmitted to the industrial control computer through the main control board.

[0044] The source meter and precision meter also communicate with the industrial control computer via an Ethernet connection switch. The industrial control computer is electrically connected to the precision meter, source meter, and high voltage source via Ethernet. The high voltage source is electrically connected to the high voltage switching circuit. The pin card adapter board is used to connect the test switching board and the wafer under test on the pin card board.

[0045] The high-voltage source is used to generate high-speed, high-frequency pulses, and is used in conjunction with a high-voltage switching circuit. The frequency is 0kHz-100kHz, and the amplitude is adjustable from 0V to 2000V. The high-voltage source provides a dynamic reverse bias voltage to the corresponding channel of the wafer under test. Combined with an IGBT half-bridge topology, dynamic reverse bias is achieved in passive mode. Dynamic reverse bias testing is implemented through passive mode. The voltage output from the high-voltage source is converted by the high-voltage switching circuit into a source voltage (Vd) that applies the drain-source voltage to the corresponding channel of the wafer under test. The high-voltage switching circuit switches the high-voltage source output between high and low voltage levels.

[0046] The source meter is used to generate a bipolar high-frequency pulse signal, providing gate bias and cutoff voltage, with a frequency of 0kHz-100kHz and an adjustable amplitude of ±200V. Under different test functions, the source meter can provide a high-frequency pulse signal, gate bias, and cutoff voltage to the wafer under test, and measure the voltage or current data of the wafer.

[0047] In some embodiments, such as Figure 2As shown, the high-voltage switching circuit includes a first IGBT device Q1, a second IGBT device Q2, a first IGBT driver, a second IGBT driver, a first resistor R1, and a second resistor R2.

[0048] The drain of the first IGBT device Q1 is connected to the output terminal of the high voltage source. The gate of the first IGBT device Q1 is connected to the output terminal of the first IGBT driver through the first resistor R1. The source of the first IGBT device Q1 is connected to the test switching circuit and the drain of the second IGBT device Q2. The gate of the second IGBT device Q2 is connected to the output terminal of the second IGBT driver through the second resistor R2. The source of the second IGBT device Q2 is grounded.

[0049] Specifically, an Insulated Gate Bipolar Transistor (IGBT) is a composite fully controllable voltage-driven power semiconductor device composed of a bipolar transistor and an insulated gate field-effect transistor. As a switching device, IGBT can withstand high voltage and high current, and is suitable for switching control of high voltage sources, ensuring the stability and reliability of high voltage output.

[0050] The first and second IGBT drivers are controlled by the main control unit. The tester sets the drive commands via an industrial control computer and controls the signals output by the first and second IGBT drivers through the main control unit. When the signal output by either the first or second IGBT driver is high (VGE), the driver... on When the corresponding first IGBT device Q1 or second IGBT device Q2 is turned on, and the signal output by the first IGBT driver or the second IGBT driver is low level VGE, then the signal is turned on. off When the time is right, the corresponding first IGBT device Q1 or the second IGBT device Q2 is turned on.

[0051] Control the first IGBT driver to output a high level VGE on The second IGBT driver outputs a low level VGE. off Then the upper bridge of the high-voltage switching circuit is turned on, and the high-voltage source outputs voltage to the drain of the wafer under test, maintaining it for a certain period of time before switching the output of the first IGBT driver to a low level VGE. off The second IGBT driver outputs a high level VGE. on The lower bridge conducts discharge.

[0052] IGBTs have fast switching characteristics, enabling them to switch high-voltage sources in a short time, meeting the requirements of dynamic testing for rapid response.

[0053] Furthermore, regarding the selection of the resistance values ​​of the first resistor R1 and the second resistor R2, while a small resistance will result in a larger drive current and a shorter IGBT turn-on and turn-off time, an excessively small resistance value will cause high-voltage oscillation at the input, while an excessively large resistance value cannot guarantee that the IGBT will be fully turned on or off. Therefore, when the resistance values ​​of the first resistor R1 and the second resistor R2 are between 1.1KΩ and 1.3KΩ, for example, when the resistance values ​​of both the first resistor R1 and the second resistor R2 are 1.2KΩ, it will not cause high-voltage oscillation at the input and can guarantee that the IGBT will be fully turned on and off.

[0054] In some embodiments, such as Figure 3 As shown, the test switching circuit includes a first relay KGD, a second relay KDS, a third relay KG, a fourth relay KVG, a fifth relay KGS, a sixth relay KS, a third resistor R3, and a fourth resistor R4.

[0055] The output of the high-voltage switching circuit is connected to the gate of the wafer under test through the first relay KGD. The output of the high-voltage switching circuit is connected to the source of the wafer under test through the second relay KDS. The gate of the wafer under test is connected to the first interface of the source meter through the third relay KG, the first end of the third resistor R3 through the fourth relay KVG, the first end of the second resistor R2 through the fifth relay, the second end of the third resistor R3 and the second interface of the source meter, the second end of the fourth resistor R4 and grounded. The source of the wafer under test is connected to the first end of the second resistor R2 and the third interface of the source meter through the sixth relay KS.

[0056] Specifically, the enable terminals of the first relay KGD, the second relay KDS, the third relay KG, the fourth relay KVG, the fifth relay KGS, and the sixth relay KS are connected to the main control unit. The main control unit controls the on and off of the first relay KGD, the second relay KDS, the third relay KG, the fourth relay KVG, the fifth relay KGS, and the sixth relay KS through corresponding output signals.

[0057] Alternatively, a separate electrical control board can be installed. This board controls the on / off states of the first relay KGD, second relay KDS, third relay KG, fourth relay KVG, fifth relay KGS, and sixth relay KS via I / O modules. Using an electrical control board to independently control relays, solenoid valves, and other devices simplifies the control logic and improves system controllability by centrally controlling the states of multiple relays.

[0058] The source meter can output voltage or measure voltage data through the first interface, the second interface, and the third interface.

[0059] The wafer aging test system with dynamic gate bias and reverse bias test functions in this embodiment of the invention can perform a variety of tests, including DHTRB and DHTGB test modes, and intersperse threshold voltage real-time monitoring in the above modes.

[0060] In one embodiment, the third relay KG, the fourth relay KVG, the fifth relay KGS, and the sixth relay KS are all reed relays, corresponding to the relays present in each channel of the wafer aging test. The first relay KGD and the second relay KDS are common relays. The specific test logic for different test modes is shown in Table 1.

[0061] Test mode KG KVG KGS KS KDS KGD DHTRB 0 1 0 / 1 1 0 0 DHTGB 1 0 / 1 0 1 1 0 VTH Test 1 0 0 1 0 / 1 0 / 1 Protect 0 0 0 0 0 0

[0062] Table 1 Test Mode Switching Logic Table

[0063] In the above specific embodiments:

[0064] When performing dynamic high temperature reverse bias test, i.e. DHTRB mode: the fourth relay KVG and the sixth relay KS are in the closed conducting state. Before the test, the fifth relay KGS is disconnected. During aging, the fifth relay KGS is closed. The second relay KDS and the third relay KG are both in the open state.

[0065] When performing dynamic high temperature grid bias test, i.e. DHTGB mode: the third relay KG and the sixth relay KS are in the closed conducting state. Before the test, the fourth relay KVG is disconnected. In aging mode, the fourth relay KVG is closed, and the second relay KDS and the fifth relay KGS are both in the open state.

[0066] When performing the threshold voltage VTH test: the third relay KG and the sixth relay KS are in the closed conducting state, the fourth relay KVG and the fifth relay KGS are both in the open state, the second relay KDS closes first to give the gate pulse, and then closes the first relay KGD after opening, so that the test current is given from the gate to test the threshold voltage;

[0067] When in protection mode, all of the above relays are in the off state.

[0068] The above three test modes can be freely combined in the industrial control computer design and testing process. In particular, for the threshold voltage test, since the higher the gate oxide electric field, the more fully the problems of the device itself can be exposed, a short-term high-temperature reverse bias or high-temperature gate bias pulse is used to repeatedly power on the wafer for testing. The switching frequency and duty cycle are set, and the threshold voltage VTH is tested once every hour, and the threshold voltage is tested once at the beginning and end to check the degradation of the device. The VTH test time is less than 1 minute.

[0069] A dynamic high voltage is applied to the drain and source terminals using an IGBT half-bridge topology, while a reverse bias voltage is applied to the gate and source terminals to achieve dynamic reverse bias aging in passive mode. Vd is the source for applying the drain-source voltage to the corresponding channel of the wafer under test. In passive mode, the industrial control computer controls the first and second IGBT drivers, and the drain-source voltage is repeatedly turned on and off through the IGBT half-bridge circuit. The switching frequency and duty cycle can be set according to conditions, while the gate voltage remains constant through the source table. The specific implementation method of dynamic high-temperature reverse bias test is as follows:

[0070] 1. Set the wafer aging system test mode to DHTRB test mode. Set the switching frequency and duty cycle of the first IGBT device Q1 and the second IGBT device Q2 on the industrial computer and output high voltage to the drain of the wafer under test.

[0071] 2. For example Figure 4 As shown, at t0-t1, the main control unit controls the IGBT driver to output a signal, causing the IGBT to turn on or off. Specifically, the signal output from the first IGBT driver to the first IGBT device Q1 is high, and the signal output from the second IGBT driver to the second IGBT device Q2 is low. At this time, the upper bridge is turned on, and the high voltage source outputs voltage to the drain. After maintaining this voltage for a certain period of time, the first IGBT device Q1 returns to a low level, and the second IGBT device Q2 switches back to a high level, causing the lower bridge to turn on and discharge. t1-t2 is the dead time, which prevents the half-bridge from being mistakenly turned on due to untimely switching between high and low levels.

[0072] By repeatedly charging and discharging the drain and source, the actual working state of the device can be simulated, the threshold voltage VTH can be monitored, and the drift of the threshold voltage can be found by comparing the before and after, which helps the wafer fab to further evaluate the device.

[0073] The specific implementation method of dynamic high-temperature gate bias test is as follows:

[0074] 1. Unlike the dynamic high temperature reverse bias test, the dynamic high temperature grid bias test is mainly achieved through the bipolar pulse function of the source meter. The source meter provides aging voltage and grid bias voltage to achieve dynamic grid bias.

[0075] 2. The source meter performs an infinite loop scan based on the set voltage list, sets the step trigger source and step trigger time interval, and outputs bipolar pulse signals +20V and -5V.

[0076] The specific implementation method of threshold voltage VTH test is as follows: Figure 5 and Figure 6 As shown:

[0077] 1. The drain and source of the wafer channel are shorted, that is, the second relay KDS is closed, and the industrial control computer controls the source meter to be set to pulse output mode, so as to output t_con (t_con<100ms) pulse to the gate of the corresponding channel;

[0078] 2. Industrial computer control delay t_float (t_float<50ms);

[0079] 3. Set the industrial control computer's control source meter to constant current source mode, output a fixed current, and test the VGS voltage, i.e., the threshold voltage time is t_VT (t_VT<100ms).

[0080] Furthermore, such as Figure 7 As shown, DHTGB and DHTRB can be used to apply stress to SiC MOSFETs. VTH is measured at a fixed current before and after the aging test. The VTH value during DHTGB and DHTRB test overshoot is monitored in real time, and VTH at high temperature is read every hour. When comparing the threshold voltage, the test data is compared with the VTH values ​​before and after at room temperature.

[0081] By adopting the above scheme, DHTGB and DHTRB tests were performed on SiC MOSFETs. Threshold tests were added during the test process, which allowed for online monitoring of VTH offset and further rapid identification of device defects, providing strong support for reliability testing of third-generation semiconductors.

[0082] The embodiments of this invention can achieve autonomous and arbitrary switching between DHTGB and DHTRB by writing test procedures through an industrial control computer. DHTRB adopts an IGBT half-bridge topology to achieve dynamic high voltage applied to the drain and source, while a reverse bias voltage is applied to the gate and source to achieve dynamic reverse bias aging in passive mode. DHTGB uses a source meter to provide dynamic voltage applied to the gate and source to achieve dynamic gate bias aging. The threshold voltage test can monitor the Vth drift of the corresponding channel of the wafer under test online.

[0083] Compared to traditional wafer aging systems, this invention has the advantages of diverse testing functions and good temperature control. Some reliability tests of traditional wafer aging equipment cannot adapt to the new mode of high-voltage operation and fast switching, as well as dynamic gate bias testing faced by SiC MOSFETs. Based on this, this invention developed DHTGB and DHTRB tests to make up for the deficiencies of reliability testing in traditional wafer aging systems.

[0084] This invention provides a wafer aging test method with dynamic gate bias and reverse bias testing functions, applied to a wafer aging test system with dynamic gate bias and reverse bias testing functions as described in any of the above embodiments of this invention. The method includes: performing dynamic high-temperature reverse bias testing and dynamic high-temperature gate bias testing by controlling the on and off intervals of a first IGBT device Q1, a second IGBT device Q2, a first relay KGD, a second relay KDS, a third relay KG, a fourth relay KVG, a fifth relay KGS, and a sixth relay KS; and performing a threshold voltage test during the interval between the dynamic high-temperature reverse bias test and the dynamic high-temperature gate bias test, wherein the interval between the dynamic high-temperature reverse bias test and the dynamic high-temperature gate bias test is less than 1 minute.

[0085] Specifically, during dynamic high-temperature reverse bias testing, the fourth relay KVG and the sixth relay KS are turned on, while the second relay KDS and the third relay KG are turned off. Before testing, the fifth relay KGS is turned off, and during aging, the fifth relay KGS is turned on. This controls the first IGBT device Q1 and the second IGBT device Q2 to switch intermittently between a first state and a second state. The first state is when the first IGBT device Q1 is on and the second IGBT device Q2 is off, and the second state is when the first IGBT device Q1 is off and the second IGBT device Q2 is on. During the high-temperature grid bias test, the third relay KG and the sixth relay KS are turned on, while the second relay KDS and the fifth relay KGS are turned off. Before the test, the fourth relay KVG is turned off, and during aging, the fourth relay KVG is turned on, controlling the source meter to output a bipolar pulse signal. When performing the threshold voltage test, the third relay KG and the sixth relay KS are turned on, while the fourth relay KVG and the fifth relay KGS are turned off. First, the second relay KDS is turned on, then the second relay KDS is turned off, and then the first relay KGD is turned on to test the threshold voltage.

[0086] While exemplary embodiments and their advantages have been described in detail, those skilled in the art can make various changes, substitutions and modifications to these embodiments without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined herein.

Claims

1. A wafer burn-in test system with dynamic gate bias and reverse bias test functions, comprising: The utility model relates to a kind of high voltage test system, including: Master board, industrial computer, high voltage source, source table, high voltage switching board, test switching board and needle card board, the master board is equipped with main control unit, the high voltage switching board is equipped with high voltage switching circuit, the test switching board is equipped with test switching circuit; The needle card board is used to assemble wafer to be measured; The output end of the high voltage source is connected with the input end of the high voltage switching circuit, the output end of the high voltage switching circuit is connected with the test switching circuit, and the main control unit controls the voltage output to the test switching circuit through the high voltage switching circuit; The test switching circuit is connected with the source table, and the main control unit selects the voltage output by the high voltage switching circuit to different electrodes of the wafer to be measured by controlling the test switching circuit, and selects whether the bipolar high-frequency pulse signal generated by the source table is output to the gate electrode of the wafer to be measured, and measures the gate voltage and source voltage of the wafer to be measured through the source table; The industrial computer is connected with the main control unit, the high voltage source and the source table respectively, and is used to control the main control unit, the high voltage source and the source table to operate.

2. The wafer burn-in test system with dynamic gate bias and reverse bias test function according to claim 1, wherein, The high voltage switching circuit includes a first IGBT device, a second IGBT device, a first IGBT driver, a second IGBT driver, a first resistor and a second resistor. The drain electrode of the first IGBT device is connected with the output end of the high voltage source, the gate electrode of the first IGBT device is connected with the output end of the first IGBT driver through the first resistor, the source electrode of the first IGBT device is connected with the test switching circuit and the drain electrode of the second IGBT device, the gate electrode of the second IGBT device is connected with the output end of the second IGBT driver through the second resistor, and the source electrode of the second IGBT device is grounded.

3. The wafer burn-in test system with dynamic gate bias and reverse bias test function according to claim 2, wherein, The resistance values of the first resistor and the second resistor are both 1.1KΩ to 1.3KΩ.

4. The wafer burn-in test system with dynamic gate bias and reverse bias test function of claim 1, wherein, The test switching circuit includes a first relay, a second relay, a third relay, a fourth relay, a fifth relay, a sixth relay, a third resistor and a fourth resistor. The output end of the high voltage switching circuit is connected with the gate electrode of the wafer to be measured through the first relay, and the output end of the high voltage switching circuit is connected with the source electrode of the wafer to be measured through the second relay, the gate electrode of the wafer to be measured is connected with the first interface of the source table through the third relay, connected with the first end of the third resistor through the fourth relay, connected with the first end of the second resistor through the fifth relay, the second end of the third resistor is connected with the source table and the second interface, the second end of the fourth resistor is grounded, the source electrode of the wafer to be measured is connected with the first end of the second resistor, and connected with the third interface of the source table through the sixth relay.

5. The wafer burn-in test system with dynamic gate bias and reverse bias test function according to claim 4, wherein, Further including a precision meter, the precision meter is used to measure the gate voltage and source voltage of the wafer to be measured.

6. The wafer burn-in test system with dynamic gate bias and reverse bias test function according to claim 1, wherein, Further including a needle card adapter board, the needle card adapter board is used to connect the wafer to be measured on the test switching board and the needle card board.

7. The wafer burn-in test system with dynamic gate bias and reverse bias test function according to claim 4, wherein, The electrical control board is used for controlling the turn-on and turn-off of the first, second, third, fourth, fifth and sixth relays through the IO module.

8. The wafer burn-in test system with dynamic gate bias and reverse bias test function according to claim 1, wherein, The wafer to be tested is a silicon carbide wafer.

9. A wafer burn-in test method with dynamic gate bias and reverse bias test function, applied to the wafer burn-in test system with dynamic gate bias and reverse bias test function as claimed in any one of claims 1 to 8, characterized in that, The method comprises the following steps: The dynamic high-temperature reverse bias test and the dynamic high-temperature gate bias test are performed by controlling the turn-on and turn-off intervals of the first IGBT device, the second IGBT device, the first relay, the second relay, the third relay, the fourth relay, the fifth relay and the sixth relay. The threshold voltage test is performed at intervals of the dynamic high-temperature reverse bias test and the dynamic high-temperature gate bias test, and the interval of the dynamic high-temperature reverse bias test and the dynamic high-temperature gate bias test is less than 1 minute.

10. The wafer burn-in test method with dynamic gate bias and reverse bias test function according to claim 9, wherein, During the dynamic high-temperature reverse bias test, the fourth relay and the sixth relay are controlled to be turned on, the second relay and the third relay are controlled to be turned off, the fifth relay is turned off before the test, the fifth relay is turned on during the aging, the first IGBT device and the second IGBT device are controlled to be switched between the first state and the second state, wherein the first state is that the first IGBT device is turned on and the second IGBT device is turned off, and the second state is that the first IGBT device is turned off and the second IGBT device is turned on. During the dynamic high-temperature gate bias test, the third relay and the sixth relay are controlled to be turned on, the second relay and the fifth relay are controlled to be turned off, the fourth relay is turned off before the test, the fourth relay is turned on during the aging, and the source table outputs a bipolar pulse signal. During the threshold voltage test, the third relay and the sixth relay are controlled to be turned on, the fourth relay and the fifth relay are controlled to be turned off, the second relay is controlled to be turned on first, then the second relay is controlled to be turned off, and then the first relay is controlled to be turned on, and the threshold voltage is tested.

Images