Digital predistortion of RF transmitters using digital power supply modulation

Abstract

In some embodiments, a digital predistorter (DPD) in an RF transceiver system having a radio frequency (RF) amplifier includes: pre-processing blocks collectively configured to receive an input signal and output a pre-processed signal; and a non-linear combiner. The input signal includes a transmit signal and a control signal. The pre-processed signal includes a first pre-processed signal and a second pre-processed signal, the second pre-processed signal being at least partially derived from the control signal. The pre-processing block includes a delay block configured to provide a first pre-processed signal corresponding to a delayed or advanced version of the transmit signal with respect to itself. The non-linear combiner is configured to combine the first and pre-processed signals to provide a pre-distorted version of the transmit signal for transmission via the RF amplifier.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Patent Application No. 18 / 735,618, filed June 6, 2024, which claims the benefit of U.S. Provisional Patent Application No. 63 / 509,341, filed June 21, 2023, pursuant to 35 USC §119. This application also claims the benefit of U.S. Provisional Patent Application No. 63 / 509,341, filed June 21, 2023. Each of the stated priority applications is incorporated herein by reference in its entirety. Background Technology

[0003] Discrete power supply modulation methods and systems improve PA efficiency by switching between a set of discrete power amplifier (PA) supply voltages according to the desired IQ (in-phase and quadrature) amplitudes. High PA supply voltage levels are required to support high IQ amplitudes (corresponding to high RF output power), while lower PA supply voltage levels can be applied at low IQ amplitudes to conserve PA power and improve efficiency. Signal processing algorithms are used in discrete power supply modulation systems to determine the appropriate supply voltage level for each IQ sample in the desired transmitted signal.

[0004] It is known that transmitters distort RF signals. Systems and methods exist to predistort the input signal to a power amplifier (PA) so that the PA's output is the desired signal, thereby improving the PA's linearity. Such predistortion can be achieved through analog or digital means. Digital predistortion (DPD) systems process digital baseband signal samples of the PA's input waveform to create a predistorted baseband signal. Existing DPD methods can employ high-order nonlinear basis functions, deep memory, neural networks, or machine learning to accurately model complex PA distortions.

[0005] Discrete PA power supply modulation produces additional types of PA distortion caused by sudden changes in PA power supply voltage. Existing systems and methods use polynomial coefficients or lookup table coefficients indexed to the PA power supply voltage level, making the coefficients suitable for the power supply voltage level in use. Summary of the Invention

[0006] According to one aspect of this disclosure, a digital predistorter (DPD) in an RF transceiver system with a radio frequency (RF) amplifier includes: one or more preprocessing blocks configured collectively to receive a plurality of input signals and output a plurality of preprocessed signals, wherein: the plurality of input signals include at least a transmit signal corresponding to a signal to be transmitted or a modified version of the signal, and a control signal corresponding to a signal for controlling a power supply voltage level of the RF amplifier or a converted version of the signal for controlling a power supply voltage level of the RF amplifier; the plurality of preprocessed signals include at least a first preprocessed signal and a second preprocessed signal, the second preprocessed signal being at least partially derived from the control signal; and the one or more preprocessing blocks include at least one or more delay blocks configured to provide a first preprocessed signal corresponding to a delayed or advanced version of the transmit signal relative to itself; and a nonlinear combiner configured to combine at least the first preprocessed signal and the second preprocessed signal to provide a predistorted version of the transmit signal for transmission via the RF amplifier.

[0007] In some embodiments, the control signal is a level selection signal for discrete power supply modulation of the RF amplifier. In some embodiments, a nonlinear combiner is configured to algebraically combine the transmitted signal with the control signal. In some embodiments, one or more delay blocks are configured to delay or advance a signal representing the amplitude of the transmitted signal relative to the transmitted signal. In some embodiments, a DPD is configured to use at least one or more delay blocks to model the memory effect of the transmit chain. In some embodiments, due to the one or more delay blocks, a predistorted version of the transmitted signal depends at least in part on both the current value and the delay value of the transmitted signal. In some embodiments, one or more preprocessing blocks include at least one preprocessing block having real-valued inputs and real-valued outputs. In some embodiments, one or more preprocessing blocks include at least one filter configured to receive the control signal.

[0008] In some embodiments, one or more preprocessing blocks include at least one preprocessing block having real-valued inputs and real-valued outputs. In some embodiments, the control signal is real-valued. In some embodiments, at least one filter is a low-pass filter. In some embodiments, at least one filter is at least partially implemented as a finite impulse response (FIR) filter with three or more taps. In some embodiments, one or more preprocessing blocks include at least one filter. In some embodiments, one or more preprocessing blocks include at least one preprocessing block having real-valued inputs and real-valued outputs. In some embodiments, at least one filter is a high-pass filter. In some embodiments, at least one filter is at least partially implemented as a finite impulse response (FIR) filter with three or more taps. In some embodiments, at least one filter is configured to receive the transmitted signal or a modified version of the transmitted signal and provide a filtered version of the transmitted signal. In some embodiments, at least one filter is configured to receive a real-valued representation of the transmitted signal and provide a filtered version of the transmitted signal.

[0009] In some embodiments, one or more preprocessing blocks include at least a first preprocessing block having an output connected to an input of a second processing block. In some embodiments, one or more preprocessing blocks include at least a first preprocessing block, a second preprocessing block, and a third preprocessing block, the third preprocessing block being configured to combine the outputs of the first preprocessing block and the second preprocessing block. In some embodiments, the third preprocessing block is a summing element. In some embodiments, the summing element provides at least one of the plurality of preprocessed signals output by the one or more preprocessing blocks. In some embodiments, a delay is applied to the inputs or outputs of the first preprocessing block and / or the second preprocessing block before combination. In some embodiments, the first preprocessing block and / or the second preprocessing block includes a filter. In some embodiments, the signal output from the first preprocessing block is delayed relative to the signal output from the second preprocessing block before being combined by the third preprocessing block.

[0010] In some embodiments, the input signals to the first preprocessing block and / or the second preprocessing block are real-valued signals derived at least partially from a signal representing the amplitude of the transmitted signal. In some embodiments, the DPD is configured to receive a plurality of coefficients and apply the plurality of coefficients to the one or more preprocessing blocks. In some embodiments, the one or more preprocessing blocks include a filter, and the DPD is configured to apply at least one of the plurality of coefficients to the filter. In some embodiments, one or more of the plurality of coefficients respond to the state of the power management circuitry of the RF transceiver system. In some embodiments, one or more of the plurality of coefficients respond to the state of the RF amplifier. In some embodiments, one or more of the plurality of coefficients respond to the configuration of the power management circuitry of the RF transceiver system.

[0011] In some embodiments, one or more preprocessing blocks include a lookup table (LUT) configured to receive the power supply voltage level or a preprocessed version of the power supply voltage level. In some embodiments, the DPD is configured to receive one or more coefficients based on the behavior of the power management circuitry of the RF transceiver system and apply the one or more coefficients to the LUT. In some embodiments, one or more delay blocks include delay blocks that can be configured in a programmable manner. In some embodiments, delay blocks that can be configured in a programmable manner can be configured at least in part based on filter coefficients and / or the sampling rate of the transmitted signal. In some embodiments, one or more preprocessing blocks include a resampler configured to adjust a first rate of at least one signal in the DPD to a second rate different from that of at least one other signal in the DPD. In some embodiments, one or more preprocessing blocks include a resampler configured to adjust the rate of a signal.

[0012] In some implementations, the signal corresponds to one of the plurality of input signals. In some implementations, the signal corresponds to the output of another preprocessing block among the plurality of preprocessing blocks. In some implementations, the resampler is configured to adjust the rate of the signal to a fixed rate independent of the sampling rate of the transmitted signal. In some implementations, one or more preprocessing blocks include filters having inputs coupled to the output of the resampler, the filters being configured to operate at the fixed rate. In some implementations, the resampler is configured to adjust the rate of the signal to be equal to the sampling rate of the transmitted signal. In some implementations, one or more preprocessing blocks include a first resampler configured to adjust the signal from an original rate to an adjusted rate, and a second resampler configured to adjust the signal from the adjusted rate back to the original rate.

[0013] In some embodiments, the original rate is greater than the adjusted rate. In some embodiments, the nonlinear combiner is configured to generate at least one cross-term basis function by combining the transmitted signal with another signal. In some embodiments, the other signal is one of the plurality of preprocessed signals. In some embodiments, the nonlinear combiner is configured to generate at least one basis function by exponentializing the signal. In some embodiments, the signal is one of the plurality of preprocessed signals.

[0014] According to another aspect of this disclosure, a method in an RF transceiver system having a radio frequency (RF) amplifier includes: receiving a plurality of input signals via one or more preprocessing blocks of a digital predistorter (DPD), the plurality of input signals including at least a transmit signal corresponding to a signal to be transmitted or a modified version of the signal, and a control signal corresponding to a signal for controlling a power supply voltage level of the RF amplifier or a converted version of the signal for controlling a power supply voltage level of the RF amplifier; generating a plurality of preprocessed signals via one or more preprocessing blocks of the DPD, each preprocessed signal including at least a first preprocessed signal and a second preprocessed signal, the second preprocessed signal being at least partially derived from the control signal, wherein the generation includes delaying or advancing the transmit signal relative to itself via one or more delay blocks of the one or more preprocessing blocks to provide the first preprocessed signal; and combining at least the first preprocessed signal and the second preprocessed signal via a nonlinear combiner of the DPD to provide a predistorted version of the transmit signal for transmission via the RF amplifier.

[0015] In some embodiments, the control signal is a level selection signal for discrete power supply modulation of the RF amplifier. In some embodiments, the method further includes algebraically combining the transmitted signal with the control signal via the nonlinear combiner. In some embodiments, the method also uses the one or more delay blocks to delay or advance a signal representing the amplitude of the transmitted signal relative to the transmitted signal. In some embodiments, the method also uses at least the one or more delay blocks to model the memory effect of the transmit chain.

[0016] In some embodiments, due to the one or more delay blocks, the predistorted version of the transmitted signal depends at least in part on both the current value and the delay value of the transmitted signal. In some embodiments, one or more preprocessing blocks include at least one preprocessing block having real-valued inputs and real-valued outputs. In some embodiments, one or more preprocessing blocks include at least one filter configured to receive the control signal. In some embodiments, one or more preprocessing blocks include at least one preprocessing block having real-valued inputs and real-valued outputs. In some embodiments, the control signal is real-valued. In some embodiments, at least one filter is a low-pass filter. In some embodiments, at least one filter is at least partially implemented as a finite impulse response (FIR) filter with three or more taps. In some embodiments, one or more preprocessing blocks include at least one filter. In some embodiments, one or more preprocessing blocks include at least one preprocessing block having real-valued inputs and real-valued outputs. In some embodiments, at least one filter is a high-pass filter. In some embodiments, at least one filter is at least partially implemented as a finite impulse response (FIR) filter with three or more taps.

[0017] In some embodiments, the method further includes receiving the transmitted signal or a modified version of the transmitted signal through the at least one filter and providing a filtered version of the transmitted signal. In some embodiments, the method further includes receiving a real-valued representation of the transmitted signal through the at least one filter and providing a filtered version of the transmitted signal. In some embodiments, one or more preprocessing blocks include at least a first preprocessing block having an output connected to an input of a second processing block. In some embodiments, one or more preprocessing blocks include at least a first preprocessing block, a second preprocessing block, and a third preprocessing block, and the method further includes combining the output of the first preprocessing block and the output of the second preprocessing block. In some embodiments, the third preprocessing block is a summing element.

[0018] In some embodiments, the method further includes providing at least one of the plurality of preprocessed signals output by the summing element. In some embodiments, the method further includes applying a delay to the input or output of the first preprocessing block and / or the second preprocessing block before combination. In some embodiments, the first preprocessing block and / or the second preprocessing block includes a filter. In some embodiments, the method further includes delaying the signal output from the first preprocessing block relative to the signal output from the second preprocessing block before combination by the third preprocessing block. In some embodiments, the input signals of the first preprocessing block and / or the second preprocessing block are real-valued signals derived at least partially from a signal representing the amplitude of the transmitted signal.

[0019] In some embodiments, the method further includes receiving a plurality of coefficients and applying the plurality of coefficients to the one or more preprocessing blocks. In some embodiments, the method further includes applying at least one of the plurality of coefficients to a filter of the one or more preprocessing blocks. In some embodiments, one or more of the plurality of coefficients are responsive to the state of the power management circuitry of the RF transceiver system. In some embodiments, one or more of the plurality of coefficients are responsive to the state of the RF amplifier. In some embodiments, one or more of the plurality of coefficients are responsive to the configuration of the power management circuitry of the RF transceiver system.

[0020] In some embodiments, the method further includes receiving the power supply voltage level or a preprocessed version of the power supply voltage level via a lookup table (LUT) of the one or more preprocessing blocks. In some embodiments, the method further includes receiving one or more coefficients based on the behavior of the power management circuitry of the RF transceiver system and applying the one or more coefficients to the LUT. In some embodiments, the one or more delay blocks include delay blocks that can be configured in a programmable manner. In some embodiments, the programmable delay blocks can be configured at least in part based on the coefficients of the filter and / or the sampling rate of the transmitted signal.

[0021] In some embodiments, the method further includes adjusting a first rate of at least one signal in the DPD to a second rate different from at least one other signal in the DPD via a resampler of the one or more preprocessing blocks. In some embodiments, the method further includes adjusting the rate of a signal via a resampler of the one or more preprocessing blocks. This signal corresponds to one of the plurality of input signals. In some embodiments, this signal corresponds to the output of another preprocessing block among the plurality of preprocessing blocks. In some embodiments, the method further includes adjusting the rate of the signal to a fixed rate independent of the sampling rate of the transmitted signal via the resampler. In some embodiments, one or more preprocessing blocks include filters having inputs coupled to the output of the resampler, and the method further includes operating the filters at the fixed rate. In some embodiments, the method further includes adjusting the rate of the signal to be equal to the sampling rate of the transmitted signal via the resampler. In some embodiments, the method further includes: adjusting the signal from an original rate to an adjusted rate via a first resampler of the one or more preprocessing blocks; and adjusting the signal from the adjusted rate back to the original rate via a second resampler of the one or more preprocessing blocks. In some implementations, the original rate is greater than the adjusted rate.

[0022] In some embodiments, the method further includes generating at least one cross-term basis function by combining the transmitted signal with another signal using the nonlinear combiner. In some embodiments, the other signal is one of the plurality of preprocessed signals. In some embodiments, the method further includes generating at least one basis function by exponentializing the signal using the nonlinear combiner. In some embodiments, the signal is one of the plurality of preprocessed signals.

[0023] According to another aspect of this disclosure, a digital predistorter (DPD) in an RF transceiver system with a radio frequency (RF) amplifier includes: one or more preprocessing blocks configured to receive a plurality of input signals and output a plurality of preprocessed signals, wherein: the plurality of input signals include at least a transmit signal corresponding to a signal to be transmitted or a modified version of the signal, and a control signal corresponding to a signal for controlling a power supply voltage level of the RF amplifier or a converted version of the signal for controlling a power supply voltage level of the RF amplifier; the preprocessed signals include at least a first preprocessed signal derived at least partially from the transmit signal and a second preprocessed signal derived at least partially from the control signal; and the one or more preprocessing blocks include at least one filter that is at least partially a finite impulse response (FIR) filter; and a nonlinear combiner configured to combine at least the first preprocessed signal and the second preprocessed signal to provide a predistorted version of the transmit signal for transmission via the RF amplifier.

[0024] In some embodiments, at least one of the first preprocessed signal and the second preprocessed signal is the output of the FIR filter, or is at least partially derived from the output of the FIR filter. In some embodiments, the control signal is a level selection signal for discrete power supply modulation of the RF amplifier. In some embodiments, a nonlinear combiner is configured to algebraically combine the transmit signal with the control signal. In some embodiments, a DPD is configured to model the memory effect of the transmit chain using the at least one filter.

[0025] In some embodiments, one or more preprocessing blocks further include one or more delay blocks arranged to delay or advance one of the preprocessed signals relative to the transmitted signal. In some embodiments, one or more delay blocks are arranged to delay or advance a signal representing the amplitude of the transmitted signal relative to the transmitted signal. In some embodiments, one or more delay blocks are arranged to delay or advance a modified version of the level selection signal or the control signal relative to the transmitted signal.

[0026] In some embodiments, one or more preprocessing blocks include at least one preprocessing block having real-valued inputs and real-valued outputs. In some embodiments, at least one filter is configured to receive the control signal. In some embodiments, at least one filter has real-valued inputs and real-valued outputs. In some embodiments, at least one filter is a low-pass filter. In some embodiments, the filter operates on a signal having a sampling rate different from that of the transmitted signal. In some embodiments, at least one filter is at least partially implemented as an FIR filter having three or more taps. In some embodiments, at least one filter is configured to receive the transmitted signal or a signal at least partially derived from the transmitted signal and provide a filtered version of the transmitted signal.

[0027] In some embodiments, one or more preprocessing blocks include at least one preprocessing block having real-valued inputs and real-valued outputs. In some embodiments, at least one filter is a high-pass filter. In some embodiments, at least one filter is at least partially implemented as a finite impulse response (FIR) filter with three or more taps. In some embodiments, one or more preprocessing blocks include at least a first preprocessing block having an output connected to an input of a second processing block. In some embodiments, one or more preprocessing blocks include at least a first preprocessing block, a second preprocessing block, and a third preprocessing block, the third preprocessing block being configured to combine the outputs of the first preprocessing block and the second preprocessing block. In some embodiments, the third preprocessing block is a summing element. In some embodiments, the summing element provides at least one of the plurality of preprocessed signals output by the one or more preprocessing blocks.

[0028] In some embodiments, a delay is applied to the inputs or outputs of the first preprocessing block and / or the second preprocessing block before combination. In some embodiments, the input signals of the first preprocessing block and / or the second preprocessing block are real-valued signals derived at least partially from a signal representing the amplitude of the transmitted signal. In some embodiments, the DPD is configured to receive a plurality of coefficients and apply the plurality of coefficients to the one or more preprocessing blocks. In some embodiments, the DPD is configured to apply at least one of the plurality of coefficients to the filter. In some embodiments, one or more of the plurality of coefficients are responsive to the state of the RF amplifier. In some embodiments, one or more of the plurality of coefficients are responsive to the configuration of the power management circuitry of the RF transceiver system.

[0029] In some embodiments, one or more preprocessing blocks include a lookup table (LUT) configured to receive the power supply voltage level or a preprocessed version of the power supply voltage level. In some embodiments, the DPD is configured to receive one or more coefficients based on the behavior of the power management circuitry of the RF transceiver system and apply the one or more coefficients to the LUT. In some embodiments, a nonlinear combiner is configured to generate at least one cross-term basis function by combining the transmitted signal with another signal. In some embodiments, the other signal is one of the plurality of preprocessed signals. In some embodiments, the nonlinear combiner is configured to generate at least one basis function by exponentializing the signal. In some embodiments, the signal is one of the plurality of preprocessed signals.

[0030] According to another aspect of this disclosure, a method in an RF transceiver system having a radio frequency (RF) amplifier includes: receiving a plurality of input signals via one or more preprocessing blocks of a digital predistorter (DPD), the plurality of input signals including at least a transmit signal corresponding to a signal to be transmitted or a modified version of the signal and a control signal corresponding to a signal for controlling a power supply voltage level of the RF amplifier or a converted version of the signal for controlling a power supply voltage level of the RF amplifier; generating a plurality of preprocessed signals via one or more preprocessing blocks of the DPD, the plurality of preprocessed signals including at least a first preprocessed signal derived at least partially from the transmit signal and a second preprocessed signal derived at least partially from the control signal, wherein the generation includes filtering at least one signal through at least one filter of the one or more preprocessing blocks, wherein the filter is at least partially a finite impulse response (FIR) filter; and combining at least the first preprocessed signal and the second preprocessed signal via a nonlinear combiner of the DPD to provide a predistorted version of the transmit signal for transmission via the RF amplifier.

[0031] In some embodiments, at least one of the first preprocessed signal and the second preprocessed signal is the output of the FIR filter, or is at least partially derived from the output of the FIR filter. In some embodiments, the control signal is a level selection signal for discrete power supply modulation of the RF amplifier. In some embodiments, the method further includes algebraically combining the transmitted signal with the control signal via the nonlinear combiner. In some embodiments, the method further includes modeling the memory effect of the transmit chain via the at least one filter. In some embodiments, the method further includes delaying or advancing one of the preprocessed signals relative to the transmitted signal via one or more delay blocks of the one or more preprocessing blocks. In some embodiments, the method further includes delaying or advancing a signal representing the amplitude of the transmitted signal relative to the transmitted signal via the one or more delay blocks.

[0032] In some embodiments, the method further includes delaying or advancing a modified version of the level selection signal or the control signal relative to the transmitted signal via the one or more delay blocks. In some embodiments, the one or more preprocessing blocks include at least one preprocessing block having real-valued inputs and real-valued outputs. In some embodiments, the method further includes receiving the control signal through the at least one filter. In some embodiments, the at least one filter has real-valued inputs and real-valued outputs. In some embodiments, the at least one filter is a low-pass filter. In some embodiments, the method further includes operating the filter on a signal having a sampling rate different from that of the transmitted signal. In some embodiments, the at least one filter is at least partially implemented as an FIR filter having three or more taps.

[0033] In some embodiments, the method further includes receiving the transmitted signal or a signal at least partially derived from the transmitted signal through the at least one filter, and providing a filtered version of the transmitted signal. In some embodiments, one or more preprocessing blocks include at least one preprocessing block having real-valued inputs and real-valued outputs. In some embodiments, the at least one filter is a high-pass filter. In some embodiments, the at least one filter is at least partially implemented as a finite impulse response (FIR) filter with three or more taps. In some embodiments, one or more preprocessing blocks include at least a first preprocessing block having an output connected to an input of a second processing block. In some embodiments, one or more preprocessing blocks include at least a first preprocessing block, a second preprocessing block, and a third preprocessing block, the third preprocessing block being configured to combine the outputs of the first preprocessing block and the second preprocessing block.

[0034] In some embodiments, the third preprocessing block is a summing element. In some embodiments, the method further includes providing at least one of the plurality of preprocessed signals output by the one or more preprocessing blocks via the summing element. In some embodiments, the method further includes applying a delay to the input or output of the first preprocessing block and / or the second preprocessing block before combination. In some embodiments, the input signals of the first preprocessing block and / or the second preprocessing block are real-valued signals derived at least partially from a signal representing the amplitude of the transmitted signal. In some embodiments, the method further includes receiving a plurality of coefficients and applying the plurality of coefficients to the one or more preprocessing blocks. In some embodiments, the method further includes applying at least one of the plurality of coefficients to the filter.

[0035] In some embodiments, one or more of the multiple coefficients respond to the state of the RF amplifier. In some embodiments, one or more of the multiple coefficients respond to the configuration of the power management circuitry of the RF transceiver system. In some embodiments, the method further includes receiving the power supply voltage level or a preprocessed version of the power supply voltage level via a lookup table (LUT) of the one or more preprocessing blocks. In some embodiments, the method further includes receiving one or more coefficients based on the behavior of the power management circuitry of the RF transceiver system and applying the one or more coefficients to the LUT. In some embodiments, the method further includes generating at least one cross-term basis function by combining the transmitted signal with another signal via the nonlinear combiner. In some embodiments, the other signal is one of the multiple preprocessed signals. In some embodiments, the method further includes generating at least one basis function by exponentializing the signal via the nonlinear combiner. In some embodiments, the signal is one of the multiple preprocessed signals.

[0036] According to another aspect of this disclosure, a digital predistorter (DPD) in an RF transceiver system having a radio frequency (RF) amplifier includes: means for receiving a plurality of input signals and providing a plurality of preprocessed signals, wherein: the plurality of input signals include at least a transmit signal corresponding to a signal to be transmitted or a modified version of the signal and a control signal corresponding to a signal for controlling a power supply voltage level of the RF amplifier or a converted version of a signal for controlling a power supply voltage level of the RF amplifier, the plurality of preprocessed signals include at least a first preprocessed signal and a second preprocessed signal, the second preprocessed signal being at least partially derived from the control signal; and means for combining the preprocessed signals with the transmit signal to provide a predistorted version of the transmit signal for transmission via the RF amplifier. Attached Figure Description

[0037] The foregoing and other objects, features, and advantages will become apparent from the following more detailed description of the embodiments and the appended claims, as illustrated in the accompanying drawings, in which the same reference numerals refer to the same parts throughout the detailed description. Reference numerals introduced in the drawings may be repeated in one or more subsequent drawings without further description in the specific embodiments to provide context for other features of the described embodiments.

[0038] Figure 1 This is a block diagram illustrating an example of a radio frequency (RF) transmitter according to some embodiments of the present disclosure, the RF transmitter being configured to digitally predistort an input signal representing a modulated RF signal to be transmitted.

[0039] Figure 2A This is a block diagram illustrating an example of an RF transmitter according to some embodiments, the RF transmitter being configured to digitally predistort an input signal in part based on control signals that are also used to actuate the system state of the transmitter.

[0040] Figure 2B It is a timing diagram of the control signals and transceiver component responses corresponding to the transition from the first system state to the second system state.

[0041] Figure 3 This is a block diagram illustrating an example of an RF transmitter according to some embodiments, the RF transmitter being configured to digitally predistort an input signal in part based on a level selection signal for changing the power supply voltage level of a power amplifier (PA).

[0042] Figures 4A to 4D This is a block diagram illustrating an example of a digital predistorter (DPD) that can be provided within an RF transceiver according to some implementations.

[0043] Figure 5 An example of a processing block that can be provided within a DPD according to some implementations is shown.

[0044] Figures 6 to 8 An example of a nonlinear combiner that can be provided within a DPD according to some implementations is shown.

[0045] Figure 9 This is a block diagram illustrating another example of a DPD that can be provided within an RF transceiver including additional inputs for control signals and external signals, according to some implementations.

[0046] Figure 10 This is a block diagram illustrating an example of a power-modulated RF transmitter according to some embodiments.

[0047] Figure 11 This is a block diagram illustrating an example of a gate-biased modulated RF transmitter according to some embodiments.

[0048] Figure 12A An example of a load-modulated RF transmitter according to some implementations is shown.

[0049] Figure 12B This is a block diagram illustrating an example of a reconfigurable matching network (RMN) that can be used for load modulation according to some implementations.

[0050] Figure 12C An example of a multiplexer for generating control signals to actuate the RMN, according to some embodiments, is shown.

[0051] Figure 12D Reconfigurable elements that can be provided within an RMN according to some implementations are shown.

[0052] Figure 12E An example of a concatenated RMN is shown.

[0053] Figure 12F This is a block diagram illustrating an example of a switch output matching network.

[0054] Figure 13A This is a block diagram illustrating an example of a multi-PA RF transmitter according to some implementations.

[0055] Figure 13B This is a block diagram showing a multiplexer used to generate the PA enable signal.

[0056] Figure 13C This is a block diagram illustrating an example of a multi-PA RF transmitter according to some implementations.

[0057] Figure 13D This is a block diagram showing a multiplexer used to generate amplitude and phase control signals.

[0058] Figure 14A This is a block diagram showing an example transceiver including a beamformer and an antenna array.

[0059] Figure 14B This is a block diagram showing the front PA beamformer.

[0060] Figure 14C This is a block diagram showing the post-PA beamformer.

[0061] Figure 14D This is a block diagram showing a multiplexer used to generate beamformer control signals.

[0062] The accompanying drawings are not necessarily drawn to scale or include all components of the system, but usually focus on illustrating the concepts, structures and techniques for which protection is sought herein. Detailed Implementation

[0063] In this article, a signal may be referred to as "corresponding to" a certain value or information, such as temperature, voltage standing wave ratio (VSWR), battery voltage, scan angle, etc. It should be understood that this means the signal encodes that value / information, responds to that value / information, or otherwise conveys that value / information.

[0064] As those skilled in the art will understand, the terminals of a given amplifying transistor are specified depending on the type of transistor being implemented. For example, a field-effect transistor (FET) has a gate terminal, a drain terminal, and a source terminal. In another example, a bipolar junction transistor (BJT) has a base terminal, an emitter terminal, and a collector terminal. The term "bias" is generally used to describe a change in the voltage or current at the gate or base terminal of an amplifying transistor.

[0065] As used herein, the terms “power supply” and “bias” are distinct. The term “bias” refers to an input condition, such as a change in the voltage or current at the gate or base terminal of an amplifying transistor. In both examples, base current bias or gate voltage bias sets the quiescent collector current or quiescent drain current, respectively. Regardless of transistor type or terminal name, the term “bias” refers to an input condition that affects the efficiency, linearity, or other performance characteristics of the amplifying transistor. The term “power supply” refers to the voltage applied to the output side of the amplifying transistor (and the current supplied to the output side of the amplifying transistor). For example, in the case of a common-source FET, the power supply may be applied to the drain terminal. In another example, in the case of a common-emitter BJT, the power supply may be applied to the collector terminal. As used herein, “power supply voltage” refers to the voltage applied to the output side of the amplifying transistor (i.e., the drain or emitter terminal in the examples above). Those skilled in the art will understand that while these terms may vary across transistor types, the appended methods and techniques are contemplated for use agnostically across all transistor types.

[0066] Figure 1An example of a transmitter 100 configured to digitally predistort an input signal representing an RF signal to be transmitted, according to some embodiments of this disclosure, is shown. The input signal 120 is also referred to herein as the “signal to be transmitted,” the “desired transmission signal,” or simply the “transmit signal.” The illustrative transmitter 100 includes a digital predistorter (DPD) 102, a decoder 104, a digital-to-RF converter 106, a power amplifier (PA) 108, a tuner 110, an RF antenna 112, and an RF-to-digital converter 114, which are components that can be coupled together and / or arranged as shown. PA 108 may include one or more transistors (or “amplifying transistors”).

[0067] Transmitter 100 may be provided as part of an RF transceiver, and the general concepts, structures, and techniques sought to be protected herein may be implemented or otherwise provided within a wide range of systems and devices for transmitting and / or receiving data. For example, transmitter 100 may be located in a mobile handheld device or other type of mobile device, a base station, a customer premises equipment (CPE), an IoT sensor / device, a gaming device, an access point, a network device, etc.

[0068] DPD 102 can be configured to receive input signal 120 (denoted as r), which corresponds to a digital baseband signal representing the RF signal to be transmitted. The real-valued RF signal can be represented using baseband "IQ" notation, where the in-phase and quadrature components of the signal comprise complex numbers describing the amplitude and phase of the RF signal. The baseband IQ signal can be converted into an equivalent RF modulated signal by modulation of the in-phase and quadrature components (or equivalently, amplitude and phase) of an RF sine wave at the desired RF center frequency. Similarly, "amplitude / phase" notation can be used, where the amplitude and phase components of input signal 120 represent the amplitude and phase of an RF sine wave at the desired RF center frequency. The baseband signal can be represented as a sampled digital signal in the transceiver. Therefore, in some cases, the input signal 120 can be a digital baseband signal with a representation (e.g., IQ or amplitude / phase), precision (e.g., 14 bits), and sampling rate (e.g., 491.52 MSps), wherein the sampling rate and precision of the input signal 120 can be selected such that the input signal 120 approximates a continuous-time signal.

[0069] For example, input signal 120 can be received from a modem (not shown), which generates an ideal baseband signal encoded with the data to be transmitted. Several stages of processing in the modem and / or transceiver (e.g., upsampling, crest factor reduction, amplification, filtering, etc.) can generate input signal 120.

[0070] For ease of illustration, the signals and their propagation paths are shown in the accompanying drawings and described herein using common reference numerals. For example, reference numeral 120 is used to indicate both the input signal to DPD 102 and the signal path coupled to the input of DPD 102.

[0071] DPD 102 and resolver 104 can be configured to correct non-ideals throughout the signal path from input signal 120 to antenna 112. DPD 102 and resolver 104 can be implemented by various means, including as part of a transmitter modem, radio frequency integrated circuit (RFIC) and / or as a separate circuit system, digital signal processing (DSP) engine, firmware and / or software.

[0072] More specifically, DPD 102 can be configured to perform real-time processing (e.g., computation) on in-phase and quadrature (IQ) samples of the input signal 120 to generate a predistorted signal 122, denoted as x. The predistorted signal 122 can be provided at the input of the digital-to-RF converter 106. In response to receiving the (digital) predistorted signal 122, the digital-to-RF converter 106 can generate or otherwise provide a corresponding RF signal 124 (X) at its output. RF It is understood that a practical implementation of a digital-to-RF converter may include components comprising a digital resampler, digital and analog filters, a digital-to-analog converter, an amplifier, an attenuator, a mixer, and an IQ modulator. In some embodiments, the resulting RF signal 124 is coupled to the RF input of PA 108. PA 108 amplifies the RF signal 124 to provide an amplified RF output signal 126 (Y). RF ).

[0073] The RF output signal 126 can propagate, for example, through the RF antenna 112. The RF antenna 112 can be an active or passive antenna and can include one or more antenna elements forming an antenna array. It should be understood that practical implementations of the transceiver system may include RF filters, RF duplexers, RF switches, and other RF components. For example, the RF antenna 112 can be coupled to an antenna tuner such as tuner 110, which is configured to match the antenna impedance to the RF signal (e.g., the received signal).

[0074] A portion of the RF output signal 126 may be coupled (e.g., via an RF coupler) or otherwise provided to the input of the RF-to-digital converter 114. The RF-to-digital converter 114 receives the RF signal provided thereto and generates a feedback signal 128(y) in response, which is provided to the input of the solver 104.

[0075] In addition to feedback signal 128, solver 104 can also be coupled to receive input signal 120 and predistortion signal 122 as inputs. It is worth noting that signals 120, 122, and 128 all correspond to baseband signal representations (e.g., sampled digital IQ signals). Solver 104 can utilize one or more techniques described below to determine one or more coefficients 130 provided to DPD 102 for generating predistortion signal 122. Coefficients 130 are determined by the solver to effectively transform input signal 120 into predistortion signal 122, which will produce a transmit RF output signal 126 that conforms to a “desired” output signal, meaning an output signal that matches (and ideally is equal to) an amplified and RF modulated version of input signal 120. The techniques employed by solver 104 can utilize a portion or all of the baseband signal provided to it to determine and / or generate coefficients 130 or otherwise provide coefficients 130 to DPD 102. In some cases, the solver 104 can utilize input signals other than baseband signals 120, 122, and 128.

[0076] In some embodiments, the solver 104 or a portion thereof may be implemented as part of a device in which other components of the transmitter 100 are implemented. For example, a portion of the solver 104 may be implemented in modem firmware, in the transmitter RFIC or other circuitry of the device, in a DSP engine, and / or in software running on the processor of the transmitter device. In other embodiments, a portion or all of the solver 104 may be separable from the transmitter device. For example, one or more of the coefficients 130 may be determined a priori (i.e., prior to operation of the transmitter) using an external computing device or other remote processing unit.

[0077] In some cases, the techniques implemented as part of the solver 104 can use one or more of the baseband signals 120, 122, and 128, as well as linear least squares methods such as ordinary least squares (OLS), to determine the coefficients 130 in an optimal or near-optimal manner. The solver techniques can be described as "direct" and "indirect." In the "indirect" approach, OLS is used to determine the coefficients that model the behavior of the PA (e.g., to achieve the transformation from signal 124 to signal 126), and then the model is inverted to achieve the DPD response. In the "direct" approach, the predistortion signal 122 required to generate the desired RF output signal 126 is first determined, and then OLS is used to determine the coefficients that model the DPD behavior (e.g., to achieve the transformation from signal 120 to signal 122).

[0078] The techniques utilized by solver 104 can be executed by any suitable processing device and / or controller on a device (not shown) in which signal processing elements can be implemented. The processor and / or controller can be any device capable of executing one or more instructions (e.g., algorithm instructions) and capable of receiving baseband signals 120, 122, and / or 128 via one or more signal or communication paths between structures of the signal processing elements. Solver 104 can operate in real-time (processing the sample stream as it is provided) or offline (processing the sample set after it has been collected). In some embodiments, one or more of the solver computation blocks and / or algorithms described herein can be provided as an RTL structure on a custom ASIC or executed in software by a general-purpose processor.

[0079] Go to Figure 2A ,exist Figure 2A The same reference numerals are used to illustrate Figure 1 Using the same components, RF transmitter 200 can be configured to digitally predistort input signal 120 based at least in part on control signal 220, which is also used to actuate system state. As used herein, “system state” can refer to the state of transmitter 200 itself, the state of a transceiver to which transmitter 200 is part, the state of a part of a transceiver, and / or the state of the device / system providing said transmitter / transceiver. Illustrative transmitter 200 includes DPD 102, state actuation control unit 202, state actuation circuitry 204, resolver 104, and PA 108. PA provides an RF output signal 126 (Y) that can be propagated, for example, via RF antenna 112. RF ).

[0080] Control unit 202 can be configured to command changes in system state. For example, control unit 202 can be a digital control for actuating one or more of the following: PA power supply voltage, PA bias voltage or current, reconfigurable load or other matching network, and / or other transmitter component behavior (e.g., IQ modulator gain / offset / quadrature, amplifier gain or filter bandwidth).

[0081] Control unit 202 is configured to receive input signal 120 and / or a modified version of input signal 120. For example, in the case of discrete power modulation (sometimes referred to as "digital power modulation") and in other cases, the modified version of input signal 120 may correspond to the amplitude (also referred to as envelope or magnitude) of input signal 120 (which may be a complex baseband signal as described above). Control unit 202 is configured to generate control signal 220 (denoted as z) for state actuation circuit 204, and may also provide control signal 220 to DPD 102 and / or solver 104. DPD 102 may be configured to utilize control signal 220 at least in part to generate predistortion signal 122.

[0082] Control unit 202 can be configured to receive one or more control parameters 222, which are denoted herein as K = {k1, k2, ..., k m} where m is an integer greater than or equal to 1. For example, control parameters 222 can be received from the modem and / or transceiver based on desired performance trade-offs. Control parameters 222 can be determined based on the operating conditions and / or system state of the transceiver system. For example, control parameters 222 can be determined based on the system state associated with the transceiver and transmitted to the control unit 202. In another example, control parameters 222 can be determined based on operating conditions commanded by the modem and transmitted to the control unit 202.

[0083] State actuation circuitry 204 may include any circuitry of transmitter 200 configured to be adjusted by control unit 202 to achieve some change in system state to achieve some performance benefit or trade-off (e.g., linearity versus efficiency). For example, state actuation circuitry 204 may be circuitry configured to actuate one or more of the following in response to control signal 220 from control unit 202: tuning network impedance or aperture, beamformer scan angle, amplifier bias voltage and / or current, amplifier supply voltage, or circuit behavior (e.g., IQ modulator quadrature / offset / gain, variable gain amplifier gain or attenuator attenuation, phase shifter angle), reconfigurable matching network, and any other type of circuitry that can actuate system state. Adjusting these circuits in part in response to input signal 120 can result in improvements in transceiver linearity, efficiency, and / or other performance metrics. As will be appreciated by those skilled in the art, state actuation circuitry 204 may be connected to any component of a circuit designed to achieve a change in its state. For example, as... Figure 2AAs shown, the state actuation circuit 204 can realize state changes of any component shown in block 240, including the digital-to-RF converter 106, PA 108, tuner 110, and RF-to-digital converter 114. The state actuation circuit 204 can be implemented separately from or together with the components shown in block 240.

[0084] The digital-to-RF converter 106, PA 108, tuner 110, and antenna 112 can be collectively referred to as the "transmit chain". In practice, the transmit chain may include additional components.

[0085] Compared to existing technologies, the digital predistortion technique for DPD 102 disclosed herein can provide enhanced predistortion to the input signal 120 by digitally modeling the analog response of the transceiver components caused by the operation of the state actuation circuit 204 when modulated by the control signal 220. For example, Figure 2B A control signal 220 is shown that jumps from value n to value n+1, causing the state actuation circuit 204 to transition between states L and L+1. However, as shown by dashed line 221, the state actuation circuit can transition with some non-instantaneous response. Therefore, the control signal 220 behaves differently from that implemented by the state actuation circuit 204 and may not be directly used for predistortion. For example, in the case of discrete power supply modulation: in response to the output voltage level control signal 322 (s, in Figure 3 The power management circuit (PMC) 304 shown in the diagram and also referred to as the "level selection signal" (in...) Figure 3 As shown in the figure, corresponding to Figure 2A The state-actuated circuit 204 will need to charge a certain amount of the output capacitor through some parasitic inductance and using a limited input current. Therefore, the actual response 221 will occupy a non-zero time period and have a different shape than the control signal 220, such as... Figure 2B As shown by the dashed lines in the diagram. It is worth noting that... Figure 2B The aim is to illustrate the relationship between the control signal z and the ideal response, and for this purpose, some voltages are not necessarily plotted to scale.

[0086] Providing signals related to the simulated behavior (i.e., modeling the behavior) also yields solutions with lower complexity than existing predistortion techniques. For example, existing techniques that compensate for the aforementioned variations can be achieved through predistortion, applying average corrections to transitions, applying predetermined multiplicative or additive corrections to samples after each transition (e.g., impulse cancellation), or highly complex Volterra-based solutions with deep memory, which become impractical to implement.

[0087] The coefficients of the signal processing elements used to model the hardware can be adjusted according to the system's state. For example, if the analog behavior of a state-actuated circuit is modified by adjusting the state-actuated circuit, the coefficients can be similarly modified to correspond to that behavior.

[0088] Now refer to Figure 3 ,exist Figure 3 The same reference numerals are used to illustrate Figure 1 Using the same components as in Figure 2, another example of an RF transmitter with digital predistortion according to some embodiments is shown. The illustrative transmitter 300, which may be referred to as a power modulation transmitter, implements discrete power modulation using a level selector 302 and a PMC 304. Referring to Figure 2 and... Figure 3 Level selection 302 is an example of state actuation control unit 202, and PMC 304 is an example of state actuation circuit 204.

[0089] The transmitter 300 also includes an absolute value block 306 configured to transform the input signal 120 into a signal 320, denoted as 'a', which corresponds to the amplitude component (also called amplitude) of the input signal 120. In some cases, the absolute value block 306 may be implemented using or corresponding to CORDIC ("coordinate rotating digital computer") or semi-CORDIC. Other means of obtaining the amplitude component of the input signal may be used.

[0090] Level selector 302 receives amplitude signal 320 as input and processes it, or otherwise, to generate level select signal 322 represented as s. In other embodiments, level selector 302 may directly receive and process input signal 120 (i.e., in some cases, absolute value block 306 may be omitted). Level select signal 322 may be provided to PMC 304, DPD 102, and solver 104. The transmission of level select signal 322 to PMC 304 enables PMC 304 to provide power supply voltage 324 (V) to PA 108 (or more generally, to one or more PAs). PA The power supply voltage 324 can be selected / determined to have the following voltage levels: (a) the voltage level is high enough to allow PA 108 to amplify the RF signal for transmission, and (b) the voltage level is low enough to allow PA 108 to operate substantially close to its gain compression region, in which PA efficiency can be maximized.

[0091] In some implementations, to indicate the appropriate PMC 304 output voltage, the level selection signal 322 may represent an index (or "level value") indicating the desired supply voltage level. For example, the index may be an integer value in the range [1, n], where n corresponds to the highest voltage level that the PMC 304 can provide. The level selection 302 may implement an algorithm and / or lookup table (LUT) to determine the level value for each sample of the amplitude signal 320.

[0092] The level selection algorithm implemented by level selector 302 is a so-called "controller" for the power supply voltage level of PA 108. Controllers for PA power supply voltage levels and other digital system inputs are considered in this disclosure.

[0093] To control the operation of the PMC 304, the level selection signal 322 can be provided to the PMC 304 as control signals along with other possible control signals. In some embodiments, these control signals can be transmitted using a Digital Control Level (DCL) interface, where the bit sequence in the digital signal commands the associated PMC 304 voltage output level and possible other system states. Encoding or mapping schemes can be used to efficiently transmit voltage levels and / or other control information from the level selection 302 to the PMC 304 (e.g., using a DCL interface).

[0094] Level selection 302 can be configured to receive and utilize one or more control parameters 222(K) from a modem and / or transceiver. In some transmission scenarios (e.g., RF band, RF output power, desired signal bandwidth, desired peak-to-average power ratio, etc.), level selection 302 can be configured by the modem and / or transceiver using control parameters 222 to generate a control signal 322 that closely follows the shape (or “envelope”) of the amplitude signal derived from the input signal 120 to increase the efficiency of PA108 (e.g., at the expense of linearity). The following... Figure 3 Examples of such amplitude signals are shown and described in the context of [the relevant context]. In some cases, one or more control parameters 222 may cause the control unit 202 to generate a control signal 322 that commands a constant supply voltage level above a desired minimum to increase PA linearity (e.g., at the expense of efficiency). Typically, control parameters 222 give the transmitter 300 the flexibility to trade efficiency for linearity and spectral emission as needed to meet operational requirements in different scenarios. Control parameters 222 may be determined during the operation of the transmitter 200 based on the transmission scenario and / or predetermined based on the characteristics of the modem and / or transceiver (before transmitter operation). Control parameters 222 may also be determined in real time during the operation of the transmitter 300 based on operating conditions and / or predetermined based on early characterization of the transceiver.

[0095] DPD 102 can modify the input signal 120 to compensate for amplitude (AM-AM) distortion and phase (AM-PM) distortion. Amplitude distortion refers to the static (time-invariant) change in the PA 108 gain relative to the input power characteristic. Phase distortion refers to the static change in the PA 108's inserted phase relative to the input power characteristic. In the case of static distortion, the distortion characteristics depend only on the current value of the input signal 120.

[0096] In addition to the static distortion compensation described above, the techniques used in DPD 102 can also correct for dynamic variations in the amplitude (AM-AM) and phase (AM-PM) distortion characteristics of PA 108. Dynamic distortion varies depending on other system states and conditions (e.g., temperature, supply voltage, RF operating frequency) and can be termed a memory effect, which can include baseband memory effect (or long-time constant memory) and RF memory effect (or short-time constant memory). Dynamic distortion characteristics depend on system conditions or inputs, rather than the instantaneous value of the baseband input signal. Some disturbances or conditions that cause memory may be partially or completely related to the input signal 120, such as temperature due to self-heating, previous values ​​of the input and output signals, or, in the case of a power-modulated transmitter, the supply voltage. Other conditions that cause dynamic distortion (e.g., memory) may be unrelated to the input signal and are independent of it, such as antenna mismatch, RF operating frequency, ambient temperature, etc. Such system conditions and disturbances are referred to herein as “exogenous”. In some implementations, DPD 102 may receive one or more inputs or signals in response to exogenous conditions. Such inputs are referred to herein as “exogenous inputs” or “exogenous signals”.

[0097] Baseband memory effects can be caused by phenomena with a slowly varying time constant similar to the bandwidth of the baseband input signal, such as memory based on the absolute value of the baseband signal. These can include variations in the nonlinearity of the PA 108 transistor due to temperature changes or bias line voltage variations. For example, the gain and phase of the PA 108 can change in response to one or more temperature and / or voltage variations. Intentional power supply voltage modulation is a major source of baseband memory effects in discrete power supply modulated transmitters.

[0098] Dynamic changes in the digital control of the transceiver (such as variations in the PA power supply voltage 324 provided by the level selection command 302 from the PMC 304) can cause variations in the static nonlinearity of the transceiver because the PA is forced to operate at different power supply voltages. DPD systems used in systems with digital control must compensate for these variations in distortion characteristics in each state of such digital control.

[0099] When a command from the control unit immediately changes the control signal, the state-actuated circuit implements an analog change in the transceiver circuit system within a non-zero time interval. For example, in situations such as... Figure 3 In the discrete power supply modulation system shown, the level selection 302 commands a change in the output voltage level immediately, but the PMC 304 can implement a change in the voltage at the PA power supply terminal over a non-zero time period. The PA distortion characteristics depend on the actual voltage at the PA 108 power supply terminal and therefore change over this non-zero time period. Therefore, effective pre-distortion of power supply voltage changes (or other system states) commanded by the control unit may require converting digital control signals (e.g., level selection signal 322) into a digital representation of the analog response at the transmitter component (e.g., PA power supply voltage 324). According to embodiments of this disclosure, such conversion is provided by one or more processing blocks, as described below.

[0100] In this document, the term "processing block" refers to a preprocessing block (e.g., a block configured to provide a preprocessed version of a signal to a nonlinear combiner) or a postprocessing block (e.g., a block configured to receive the output of a nonlinear combiner or a converted version thereof).

[0101] In addition to the described static nonlinearity and memory effect distortion, DPD 102 can be configured to address non-idealities from other sources. For example, digital-to-RF converter 106 may apply the in-phase and quadrature components of the predistorted signal 122 to an RF carrier signal with imperfect quadrature (not exactly 90 degrees out of phase), and / or may allow for smaller average (DC) offset or scaling errors in the in-phase and quadrature components. In another example, the baseband and / or RF signal paths may have some imperfect frequency response, resulting in non-idealities in the output signal 126. These types of errors, typically introduced by transceivers and RF front-ends, can be compensated for using one or more digital predistortion techniques described herein.

[0102] According to some implementations, a single set of receive coefficients 130 can be used to describe the behavior of DPD 102 for all power supply voltage levels used in transmission by PMC 304, and more generally, to compensate for variations in PA linearity caused by actuation of other digital system states and variations in transmitter conditions such as temperature or mismatch, as further described below. In addition to receive coefficients 130 as input, DPD 102 can also receive amplitude signal 320 and level selection signal 322. DPD 102 can utilize these various inputs to generate predistortion signal 122 using the structures and techniques described below.

[0103] Go to Figure 4A ,exist Figure 4A The same reference numerals are used to illustrate Figures 1 to 3 Using the same components, a DPD 400 is shown, configured to digitally predistort the RF signal to be transmitted. For example, the DPD 400 can be used with... Figures 1 to 3 The DPD 400 is the same as or similar to the DPD 102. The DPD 400 can convert the input signal 120 (e.g., a digital baseband signal using IQ notation) into a predistorted signal 122. The DPD 400 can also receive an amplitude signal 320 corresponding to the amplitude component of the input signal 120, a control signal 220(z), and signals generated by a solver (e.g., Figure 3 The solver 104) provides one or more coefficients 130 as input. The control signal 220 can correspond to, for example... Figure 3 The level selection signal 322 or any other signal used to control or actuate the system state within the transceiver, such as Figure 2A The control signal 220(z) is used. In some cases, control signal 220 may correspond to a converted version of the control signal. For example, a preprocessing block outside the DPD 400 may be used to convert the control signal (e.g., signal 220 of FIG. 2) before it is input to the DPD (e.g., by converting it from a discrete voltage level to a transient analog signal). Signals 120, 320, and 220 are collectively referred to herein as DPD input signals. In other embodiments, the DPD may receive different types and numbers of input signals.

[0104] The DPD 400 may include one or more preprocessing blocks 402 and a nonlinear combiner 404. The preprocessing blocks 402 may include a variety of numbers and types of preprocessing blocks arranged in various topologies according to their intended application. Typically, the preprocessing blocks 402 may include at least one block for receiving a corresponding one of the DPD input signals. The outputs (or combinations of the outputs) of the preprocessing blocks 402 may be provided to the nonlinear combiner 404, which in turn combines those outputs in various ways to generate a predistorted signal 122. Specific examples of preprocessing blocks and nonlinear combiners are disclosed herein. More generally, a group of preprocessing blocks 402 may collectively receive one or more input signals and operate on these signals to provide one or more preprocessed signals.

[0105] exist Figure 4AIn the example, processing block 402 is shown as including: a first filter 408, a second filter 412, and a delay 414. Typically, a DPD preprocessing block can include any type of digital element, component, or block configured to operate on signals, including but not limited to LUTs, algorithms, polynomials, filters, nonlinear transforms, mathematical operators (e.g., summation, multiplication, inversion), multiplexers (and / or other combinational logic), resamplers, interpolators, decimators, comparators, and / or delays. In other embodiments, each preprocessing block 402 shown herein, having a single input and a single output, may have one or more inputs and / or outputs. A preprocessing block may receive the output of another preprocessing block as an input. As those skilled in the art will understand, two or more preprocessing blocks may be arranged and / or combined into series and / or parallel configurations, such as those required for preprocessing inputs, transformed versions of inputs, and / or other signals for further processing by the nonlinear combiner 404. For example, in a parallel configuration, the outputs of two separate preprocessing blocks having the same or separate inputs may be combined (e.g., by summation or multiplication). In another example of a parallel configuration, two separate preprocessing blocks can operate on a common input signal and produce two separate output signals.

[0106] In this embodiment, the input signal 120 is directly applied to the nonlinear combiner 404, and a delay 414 is added to the input signal 120 to generate a delayed input signal 415 (r) corresponding to a delayed version of the input signal 120. D In some implementations, delay 414 may be zero or virtually zero. Those skilled in the art will recognize that a Volterra derived model (e.g., a memory polynomial) can be constructed using the described nonlinear combiner having input 120 and one or more delayed versions of input 120 (e.g., delayed input signal 415). Such a model is used in the art to model memory emitter effects. Additional nonlinear combiner inputs (each with a different preprocessing delay) are used to extend memory depth, but also have drawbacks including additional implementation complexity, additional coefficient counting, and additional multipliers (corresponding to additional requirements for physical size and power consumption). In this approach, both the described delay and other preprocessing blocks (e.g., filters, and specifically FIR-implemented filters) can be applied to any input (e.g., Figure 4A The signal 220(z) (which may correspond to the level selection signal 322(s) in power modulation), signal a 320, input signal 120(r), and any additional inputs such as additional control signals and external signals) are used to expand the memory depth with lower complexity, coefficient counting and multipliers.

[0107] The delay preprocessing element has the effect of delaying a first signal relative to other signals. The delay can be configured to delay the first signal by an integer number of samples or a fraction of samples. Fractional sampling delay can be implemented using any known technique known in the art (e.g., filtering using an FIR filter with an all-pass amplitude response and a linear phase response). It should be understood that the first signal can be delayed relative to all other signals, or a delay block can be applied to all other signals to achieve timing advance of the first signal. As an example, see [reference]. Figure 4A The delay element 414 can generate a delayed input signal 415(r) corresponding to a delayed version of the input signal 120(r). D The first filter 412 can generate a first filtered signal 424(A) corresponding to a filtered version of the amplitude signal 320; and the second filter 408 can generate a second filtered signal 424(Z) corresponding to a filtered version of the control signal 220. It should be understood that delaying the input signal 415 effectively advances the timing of the input signal 120. By adding the dependence of the current output on the previous input, the delay or advance of the timing of one signal relative to other signals has proven useful in modeling memory behavior (e.g., memory effects). The delay element in the preprocessing block 402 can be implemented as a programmable delay, which is programmed, for example, as a predistortion coefficient, fixed to a static value, adjusted based on a group delay of the filter response produced by selected coefficients of an FIR or similar filter, or adjusted based on the digital sampling rate of the preprocessing block. In the example shown, delaying the input signal 415(r D The signal is shown as being delayed relative to the input signal 120(r), but as those skilled in the art will understand, the delay can be applied relative to the input signal 120 to any signal. For example, the delay can be applied relative to the input signal 120 to the control signal z.

[0108] Resampling elements alter the time period between samples of a digital signal while minimizing the loss or corruption of signal information. Upsamplers and downsamplers are resampling elements used to increase or decrease the sampling frequency, respectively. The former can be implemented, for example, by interpolation to increase the number of samples representing the signal within a given time period, while the latter can be implemented by decimation followed by filtering to decrease the number of samples representing the signal within a given time period. Efficient digital signal processing techniques for resampling are well known in the art (e.g., interpolation, or decimation followed by filtering).

[0109] Those skilled in the art will understand that preprocessing a signal at a reduced rate or at a fixed rate (e.g., a fixed rate independent of the transmitted signal sampling rate) can be useful for various preprocessing blocks. For example, a signal known to have finite signal bandwidth content can be downsampled, processed at a lower sampling rate, and then upsampled back to the original rate for use with other signals. Some possible benefits of processing at a lower rate include reduced power consumption of digital logic, reduced size required to implement the preprocessing algorithm in digital logic, and reduced latency through the preprocessing block. In another example, consider a system in which the input signal r can be provided at different sampling rates. Some preprocessing blocks will produce different responses depending on the sampling rate; for example, a single set of FIR filter coefficients will produce different frequency responses depending on the signal sampling rate. A fixed frequency response can be achieved using a set of FIR filter coefficients if an appropriate resampler is used before the FIR filter to convert the input signal to a fixed rate, and a second resampler is used at the output of the FIR filter to achieve the original sampling rate. In such a configuration, the FIR filter will always operate on data at the set sampling rate, and the FIR filter will always produce the same frequency response.

[0110] Although Figure 4A The implementation shown illustrates a single delay 414 for operating on the input signal 120(r), but it should be understood that the general concept and structure sought to be protected herein are not limited to this arrangement. For example, in other implementations, delays may be additionally or alternatively provided for operating on the control signal 220(z) and / or the amplitude signal 320.

[0111] Filters 408 and 412 can be configured to achieve any desired frequency response, such as low-pass, high-pass, or all-pass filters. Furthermore, such filters can be implemented using various methods, such as finite impulse response (FIR) filters, infinite impulse response (IIR) filters, and filters that are at least partially FIR filters (e.g., combinations or "hybrid" structures / filters of FIR and IIR). IIR structures offer the advantages of reproducing very long step responses with a small number of coefficients and accurately modeling analog filters. However, IIRs can be practically challenging due to timing requirements for digital implementation on the feedback path, sensitivity to quantization noise requiring complex fixed-point implementations, and reduced numerical stability. In contrast, FIR structures can synthesize arbitrary frequency responses and are unconditionally stable. Fixed-point implementation is also simpler because FIR structures lack any feedback path and are less sensitive to quantization noise. Hybrid structures, including cascaded low-order FIRs and low-order IIRs, can be an ideal trade-off between synthesizing a more diverse range of frequency responses, increased step response lengths, and moderate design complexity.

[0112] Although Figure 4A The illustrated implementation shows three (3) preprocessing blocks, but the general concept, structure, and techniques sought to be protected herein are not limited to any number or arrangement of preprocessing blocks. In some implementations, additional processing blocks may be included. For example, preprocessing blocks may be arranged in parallel or cascaded depending on their intended application. Furthermore, in some implementations, these preprocessing blocks and / or one or more of the preprocessing block examples may be combined, provided together with one or more of the nonlinear combiner 404 and DPD 400, and / or provided separately from one or more of the nonlinear combiner 404 and DPD 400.

[0113] Preprocessing block 402 can take any form of input-to-output transformation, including linear or nonlinear functions, time-varying or time-invariant functions, lookup tables, state machines, delays, filters, or other algorithms. Preprocessing block 402 can incorporate inputs from real-valued or complex-valued signals, including digital control signals (e.g., discrete power supply modulation control signals commanding discrete voltage levels from the PMC), digital representations of analog control signals (e.g., continuously variable gate bias control signals), or baseband signals, etc. In some cases, preprocessing block 402 can use feedback signals (e.g., Figure 2A The feedback signal 128 or the predistortion signal 122 is used as input. The output of the preprocessing block can be in the form of a real-valued or complex-valued signal, and can represent a digital control signal, a digital representation of an analog control signal, or a baseband signal.

[0114] As previously mentioned, the Volterra model can represent memory and nonlinearity, but at the cost of increased complexity, coefficients, and multipliers. Consider a scenario where the value of the input control signal 220(z) is correlated with its effect on the PA nonlinearity via the sigmoid function. Incorporating higher-order nonlinear Volterra terms into the predistorted signal 122(x) adds complexity, coefficients, and multipliers to the solution. Preprocessing block 402 can be used to transform the control signal 220(z) into a nonlinear combiner input Z 424 that is more linearly correlated with its effect on PA behavior, thereby reducing the nonlinear order required by the nonlinear combiner 404 compared to a Volterra model with equivalent performance. Such a preprocessing block can be implemented using mathematical functions (e.g., polynomials, sigmoid, etc.) or as a LUT for approximating a nonlinear transformation.

[0115] The overall response of a cascade of preprocessing blocks (or blocks) with a nonlinear combiner can be combined into a single block or expression. As an example, consider the following cascade of an FIR filter and a nonlinearity:

[0116] Equation 1: FIR Filter

[0117] Equation 2 Nonlinear:

[0118] Equation 3: FIR+ nonlinear cascade:

[0119] In this discussion, preprocessing blocks, nonlinear combiners, and postprocessing blocks provide a framework for describing and understanding specific signal processing techniques used for digital predistortion. This framework is used in a descriptive rather than restrictive manner. For example, a preprocessing block cascaded with a nonlinearity (e.g., Equation 2) (e.g., Equation 1) can be equivalently represented as a single expression (e.g., Equation 3). Those skilled in the art will understand that the same underlying signal processing can be reconstructed in different forms for clarity or improved implementation. In this case, a framework (e.g., the connection of preprocessing blocks, nonlinear combiners, and postprocessing blocks) is used for clarity; however, those skilled in the art will understand that the signal processing mathematics and techniques for predistortion discussed herein can also be described in any mathematically equivalent alternative form.

[0120] Control signal 220(z) enters DPD 102 and is input to one or more preprocessing blocks 402. It will be understood that the functions of such preprocessing blocks (e.g., scaling, filtering, etc.) may be performed in different functional blocks prior to entering the DPD. In this discussion, preprocessing block 402 and nonlinear combiner 404 are grouped together within DPD 400 for clarity and not limitation. Those skilled in the art will understand that the preprocessing blocks may be implemented separately from DPD 400, or described as separate blocks from DPD 400. For example, an alternative block diagram could depict filter 408 implemented within level selection 302, such that signal Z 424 enters the DPD directly from control unit 202. Such cases demonstrate that the same underlying signal processing can be reclassified for clarity or improved implementation, while still utilizing the concepts described herein.

[0121] As previously stated, coefficients 130 can be derived by the solver. Different coefficients in coefficients 130 can be provided to, or utilized by, different preprocessing blocks and / or nonlinear combiners 404 in preprocessing block 402 (for clarity in the figures, coefficients 130 are simply shown as inputs to the DPD 400 itself). For example, a first filter 408 can utilize one or more of coefficients 130, a second filter 412 can utilize other coefficients in coefficients 130, and so on. In the case of filters, the number of coefficients can be determined based on the length of the filter. The number of coefficients provided to the nonlinear combiner 404 can be determined based on the degree of the polynomial basis functions (e.g., second-order polynomial basis functions, third-order polynomial basis functions, etc.) implemented by the combiner. Each of the coefficients 130 (including those provided to preprocessing block 402 and those provided to nonlinear combiner 404) can be individually addressable and modifiable to achieve proper predistortion of the input signal 120.

[0122] The coefficients of the filter preprocessing block can include each tap applied to the finite impulse response filter (e.g., Figure 5 The weights of tap 504 in the DPD 400 are used. The coefficients of the NLT block can include coefficients of polynomials or other nonlinear equations. The coefficients of the delay preprocessing block can include the time the signal should be delayed (e.g., the number of clock cycles). The coefficients of the LUT can include values ​​that define the input-output mapping of the block. In all cases, the correlation coefficients 130 used for the preprocessing block 525 and the nonlinear combiner 404 can be derived by the solver and loaded into the DPD 400. In some cases, one or more coefficients can be predetermined by the solver and stored and loaded into the DPD 400 during operation.

[0123] The predistortion networks described in this paper can benefit from the sequential application of various specialized solver techniques (such as combining...). Figure 1The steps discussed here sequentially determine the required coefficients for each block. Some or all of these steps can be used for different types of calibration, including: “characterization,” which calculates a common set of coefficients for all transceivers with identical hardware using a single transceiver in a laboratory setting; “factory” calibration, which calculates a customized set or subset of coefficients for each unique transceiver during production; and “real-time” adaptation, which updates the set or subset of coefficients during transceiver operation. Real-time adaptation can occur continuously at preset time intervals when operating conditions (e.g., temperature, voltage VSWR) change beyond a given threshold, when transmit conditions are adjusted (e.g., operating band / channel, desired signal characteristics such as bandwidth or peak-to-average power ratio), or when the device is powered on. In some cases, the solver can generate one or more coefficients in response to the configuration of the RF transceiver system's PMC. In one example, coefficients can be adjusted when different voltages are assigned to the PMC power level by changing the configuration of the multi-output power generator voltage target. In another example, the coefficient can be adjusted when the output impedance of the PMC is adjusted by changing the configuration of the pulse shaping network switch or by changing the configuration of the multi-output power generator control loop bandwidth or switching frequency.

[0124] The nonlinear combiner 404 can receive the input signal 120(r) and one or more preprocessed signals generated by the preprocessing block 402 as inputs. The nonlinear combiner 404 can use various structures and techniques described below to combine these various inputs to form a predistorted signal 122(x).

[0125] Figure 4B (exist Figure 4B The same reference numerals are used to illustrate Figures 1 to 4A The same components (shown in the diagram) illustrate a DPD 400 configured to digitally predistort the RF signal to be transmitted. For example, the DPD 400 can be used with... Figures 1 to 4A The DPD102 and DPD400 are identical or similar. In some embodiments, DPD400 may include one or more post-processing blocks 450 coupled to the output of the nonlinear combiner 404. The post-processing block 450 may have the same form as any pre-processing block mentioned herein. The post-processing block 450 may acquire any input signal that the pre-processing block can acquire. The post-processing block 450 may be configured to receive one or more of the following: input signal 120 or its derivatives (e.g., amplitude signal a 320 and delay signal r). D426), external signal 428 (e.g., a temperature signal such as described in more detail below), control signal 220 (e.g., level selection signal 322), outputs of other post-processing blocks 450, and / or outputs of pre-processing blocks 402 (e.g., signal Z 424 and the shown intermediate signal 427(x') corresponding to the output of the nonlinear combiner 404). For example, in some embodiments, DPD 400 may include a temperature pre-processing block, and its output may be received by post-processing block 450. In some embodiments, post-processing block 450 compensates for RF components that may distort the input signal before the RF transmission component. For example, if the configuration of the beamformer, filter, or other circuitry before PA is adjusted and undesirable byproducts also attenuate the pre-distortion signal 122, post-processing block 450 may modify the pre-distortion signal 122 accordingly to compensate for attenuation. Note that post-processing block 450 may also include one or more additional signals (e.g., 428), which may correspond to external signals from control signals from additional state actuation control blocks and / or other types of signals described above.

[0126] Go to Figure 4C ,exist Figure 4C The same reference numerals are used to illustrate the same elements, illustrating an embodiment of the DPD 400 including two or more control signals (control signal 220, z and level selection signal 322, s) as inputs. As those skilled in the art will understand, the disclosure herein can be applied to n control signal inputs, where n is an integer greater than 1. As stated above regarding... Figure 3 As shown and described, control signal 220(z) can be a level selection signal 322. In other embodiments, there may be more than one control signal 220. For example, in Figure 4C In the illustrated embodiment, there are two control signals: one corresponding to the level selection signal 322(s) and the other corresponding to the control signal 220. Control signal 220 can be provided by any of the control blocks described herein. Each control signal can be provided as an input to preprocessing block 402. The outputs of preprocessing block 402 (e.g., preprocessing signals S, Z, A, and rD) can be combined and / or otherwise provided to nonlinear combiner 404 for generating predistortion signal 122(x).

[0127] Go to Figure 4D ,exist Figure 4D The same reference numerals are used to illustrate Figures 1 to 4C The same components, Figure 4D A DPD 400 configured to digitally predistort an RF signal to be transmitted is shown. For example, the DPD 400 can be used with... Figures 1 to 4CThe DPD 102 and DPD 400 are the same or similar. DPD 400 can convert an input signal 120 (e.g., a digital baseband signal using IQ notation) into a predistorted signal 122. DPD 400 can also receive an amplitude signal 320 corresponding to the amplitude component of the input signal 120, a control signal 220, and signals generated by a solver (e.g., ...). Figure 3 The solver 104) provides one or more coefficients 130 as input. The control signal 220 can correspond to, for example... Figure 3 The level selection signal 322 or any other signal used to control or actuate the system state within the transceiver, such as Figure 2A Control signal 220. Similar to other embodiments, in some cases, control signal 220 may correspond to a converted version of the control signal. For example, a preprocessing block outside the DPD 400 may be used to convert the control signal (e.g., signal 220 of FIG. 2) before it is input to the DPD (e.g., by converting it from a discrete voltage level to a transient analog signal). Signals 120, 320, and 220 are collectively referred to herein as DPD input signals. In other embodiments, the DPD may receive different types and numbers of input signals.

[0128] The DPD 400 may include one or more preprocessing blocks 402 and a nonlinear combiner 404. The preprocessing blocks 402 may include a variety of numbers and types of preprocessing blocks arranged in various topologies according to their intended application. Typically, the preprocessing blocks 402 may include at least one block for receiving a corresponding one of the DPD input signals. The outputs (or combinations of the outputs) of the preprocessing blocks 402 may be provided to the nonlinear combiner 404, which in turn combines those outputs in various ways to generate a predistorted signal 122. Specific examples of preprocessing blocks and nonlinear combiners are disclosed herein. More generally, a group of preprocessing blocks 402 may collectively receive one or more input signals and operate on these signals to provide one or more preprocessed signals.

[0129] exist Figure 4DIn the example shown, processing block 402 includes: a first filter 408, a second filter 412, a lookup table (LUT) 406, a nonlinear transform (NLT) 410, and a delay 414. Typically, a DPD preprocessing block can include any type of digital element, component, or block configured to operate on signals, including but not limited to LUTs, algorithms, polynomials, filters, nonlinear transforms, mathematical operators (e.g., summation, multiplication, inversion), multiplexers (and / or other combinational logic), resamplers, interpolators, decimators, and / or delays. In other embodiments, the preprocessing block 402 shown here, each with a single input and a single output, may have one or more inputs and / or one or more outputs. A preprocessing block may receive the output from another preprocessing block as an input. As those skilled in the art will understand, two or more preprocessing blocks can be arranged and / or combined in series and / or parallel configurations as may be required for preprocessing input signals for further processing by the nonlinear combiner 404. For example, in Figure 4D In the illustrated embodiment, LUT 406 and the first filter 408 are shown in a series (sometimes referred to as cascaded) arrangement with a combined output V1. Similarly, NLT 410 and the second filter 412 are shown in a series (sometimes referred to as cascaded) arrangement with a combined output V2. Signals s' and a' represent the respective outputs of LUT 406 and NLT 410, which are illustrated as intermediate signals between preprocessing blocks. However, it should be understood that in some embodiments, these preprocessing blocks, illustrated as separate blocks, can be directly combined without intermediate signals. Outputs V1 and V2 are shown as being combined together by a summing preprocessing block 413 (and thus in a parallel configuration), where the outputs of two separate preprocessing blocks having the same or separate inputs are shown as being combined into a single output.

[0130] Delay block 414 is shown as outputting signal 415 (r), which is a delayed version of the input signal 120. D The nonlinear combiner 404 weights and combines the delayed and undelayed versions of the input signal to create a predistorted signal x that depends on the current value (undelayed) and the historical value (delayed) of the input. Similarly, any input to the nonlinear combiner (i.e., Z 424) can be delayed as a means of incorporating memory into the DPD model. A model is said to have memory when the output depends on both the current and historical values ​​of the input. Therefore, one way to incorporate memory into the DPD model is to provide a delayed version of the input signal as input.

[0131] Figure 5An example of a filter-type processing block that can be provided within a DPD according to some embodiments is shown. An illustrative filter 500, which can be described as a finite impulse response filter, includes multiple unit delays 502a, 502b, 502c, ..., 502m (collectively referred to as 502), multiple taps 504a, 504b, 504c, 504d, ..., 504n (collectively referred to as 504), and multiple summing elements 506a, 506b, 506c, ..., 506o (collectively referred to as 506). In the example shown, m = o = n-1. Filter 500 can be used by a solver (e.g., ... Figure 3 The solver 104 provides one or more coefficients. More specifically, tap 504 can be configured using coefficients b0 to bn provided by the solver. In this example, filter 500 may correspond to the first filter 408 of FIG4, receiving control signal 220 (which may correspond to any control signal, including but not limited to level selection signal 322(s) in the case of power modulation) as input and providing preprocessed signal Z 424 as output. The preprocessed signal Z 424 may be provided directly to nonlinear combiner 404, as input to one or more additional preprocessing blocks 402, and / or otherwise provided for combination with other signals (summation and / or multiplication).

[0132] Figure 6 Examples of nonlinear combiners that can be provided within a DPD according to some implementations are shown. For example, illustrative nonlinear combiner 600 can be used with... Figure 4A and Figure 4B The nonlinear combiner 404 is the same as or similar to it.

[0133] The nonlinear combiner 600 includes an absolute value block 602 denoted as ABS(), operators 604a to 604b, multiplication elements (or “multipliers”) 606a to 606b and 608a to 608b, and a summing element 610. The various elements 602 to 610 can be arranged and connected to apply a third-order polynomial to the input signal 120, thereby generating a predistorted signal 122.

[0134] The input signal 120(r) is provided as input to the absolute value block 602 to generate the amplitude signal 320(a). In some embodiments, the absolute value block 602 may be, for example, a CORDIC or a semi-CORDIC. In other embodiments, the transmitter may include a CORDIC external to the DPD, and therefore, the amplitude signal 320 may be provided as input to the DPD and its nonlinear combiner (such as...). Figure 3(As shown in the diagram). Therefore, in some cases, the absolute value block 602 can be omitted from the nonlinear combiner 600. Furthermore, an alternative block implementing similar functionality to CORDIC and / or semi-CORDIC can be used to generate the amplitude signal 320 from the input signal 120.

[0135] like Figure 6 As shown, one or more basis functions can be created from the input signal 120. To provide a first basis function, a first operator 604a (λ1) creates a signal 620a (a1) by exponentializing the amplitude signal 320 (a), which is then multiplied by the input signal 120 via a first multiplier 606a. To provide a second basis function, a second operator 604b (λ2) creates a signal 620b (a2) by exponentializing the amplitude signal 320 (a), which is then multiplied by the input signal 120 via a second multiplier 606b. For example, different powers can be used to perform two exponentiation operations. Other operators can be used to create basis functions, such as an exponentiator for creating polynomial basis functions. A third basis function can correspond to the input signal 120. Multipliers 608a, 608b, and 608c apply coefficients k1, k2, and k3 to three basis functions, respectively, where coefficients k1, k2, and k3 can be determined and provided by a solver (e.g., solver 104 in Figure 2). The three basis functions, weighted by the corresponding coefficients k1, k2, and k3, can then be combined by summing element 610 to generate a predistorted signal 122(x).

[0136] Although Figure 6 A nonlinear combiner with three (3) basis functions created from a single input signal is shown, but other numbers of input signals and / or basis functions can be used.

[0137] Figure 6 A method or technique known as a static nonlinear sub-model is shown, which can be used within a nonlinear combiner to compensate for the static nonlinearity of the transceiver. Although Figure 6 The implementations shown (e.g., third-order static nonlinearity) are discussed as methods for compensating PA distortion; however, the techniques described herein can be applied to compensate for distortions associated with components throughout the transceiver system. Static nonlinearity compensation may include compensation for variations in gain relative to input amplitude (AM / AM) and phase relative to input amplitude (AM / PM). In the PA example, these characteristics vary with the supply voltage, therefore the static linearization characteristics of the DPD must be adjusted independently for each supply voltage level. Figure 6 The static nonlinear sub-model can assume that the power supply voltage (and therefore the compensated AM / AM and AM / PM characteristics) is constant.

[0138] In some implementations, the subset of coefficients provided by the solver may include polynomial coefficients k1...k n These coefficients can vary with the power supply voltage level because they are indexed to that level. For example, if the power supply voltage level changes, a different set of polynomial coefficients might be needed. Changing the polynomial coefficients with the power supply voltage level helps ensure that the coefficients used are appropriate for a given power supply voltage level.

[0139] Although Figure 6 An example of a nonlinear combiner employing a static nonlinear submodel is shown, but the general concepts, structures, and techniques that this paper seeks to protect are not limited to any particular type of nonlinear combiner design or implementation.

[0140] Go to Figure 7 ,exist Figure 7 The same reference numerals are used to illustrate Figure 6 The same components, Figure 7 Another example of a nonlinear combiner 700 that can be provided within a DPD is shown. Figure 7 The methods or techniques shown can be used to compensate for changes in PA gain and phase given a modified input signal.

[0141] In this example, there are two combined static nonlinear sub-models to consider two input signals: input signal 120(r), which can be a complex baseband signal as described above, and a preprocessed input signal 424(Z), which can be real-valued. The preprocessed input signal 424 can be generated using one or more preprocessing blocks 402 and provided to the nonlinear combiner 700, such as... Figures 4A to 4C As shown in the image. Figure 7 The method can be with Figure 6 The method forms a contrast, in Figure 6 The method only compensates for changes caused by the (complex) input signal 120.

[0142] like Figure 6 The first sub-model, comprising elements 604a to 604b, 606a to 606b, and 608a to 608c, provides basis functions based on the input signal 120. These basis functions generate term 640 (“r-term”), which is provided as input to the summing element 610.

[0143] The second sub-model, including operators 612a to 612c and multipliers 614a to 614c, provides basis functions based on the second input (in this case, the preprocessed input signal 424). These basis functions produce term 642 (“Z-term”), which is also provided as input to summing element 610. Similar to the r-term 640, the Z-term 642 can be weighted by coefficients provided by the solver (shown here as coefficients k4, k5, and k6), and the weighted term can be provided as additional input to summing element 610.

[0144] Additional term 644 (“cross term”) can be created by combining basis functions of different inputs, for example by multiplying the outputs of operators 604a to 604b with the output of operator 612 using multipliers 616a to 616c, as shown. Cross term 644 can also be weighted by coefficients provided by the solver (shown here as coefficients k7, k8, and k9), and the weighted term can be provided as additional input to summing element 610. Cross term 644 can be used to compensate for distortions that are interdependent with the two input signals.

[0145] It should be understood that the exemplary nonlinear combiner structure is only one implementation of a nonlinear combiner. A nonlinear combiner can be implemented using any mechanism that combines and transforms input signals (e.g., signals 120 and 424) to produce an output signal (e.g., predistorted signal 122). In other implementations, the nonlinear combiner can be implemented as an n-dimensional lookup table.

[0146] As discussed earlier, knowing the level selection signal 322 ( Figure 3 In the case of ), the preprocessed input signal 424(Z) provided as input to the static nonlinear sub-model can use at least one preprocessing block outside the sub-model (e.g., Figures 4A to 4C The preprocessing block 402 is used to generate it.

[0147] In existing methods of digital power modulation predistortion, the preprocessed input signal 424 can be used as an index for selection from a set of DPD102 coefficients 130. In the example of digital power modulation, the command voltage level s 322 will be used as an index for selecting a set of DPD coefficients specific to a given power supply voltage level.

[0148] In contrast, in this method, the command voltage level s 322 is preprocessed within DPD 102, and the output is partially used to form an intermediate signal representing the PA power supply voltage 324. The intermediate signal derived from the control signal 322 is algebraically (or mathematically, e.g., by addition or multiplication) combined with other signals to form a predistortion signal 122, and is not used as an index for selecting appropriate DPD coefficients.

[0149] One or more preprocessing blocks can estimate the behavior of the preprocessed input signal 424 during transitions from one voltage level to another. Other behaviors of the preprocessed input signal 424 can also be modeled to provide even better estimates of the gain and phase compensation required to produce a linear output from the PA. For example, in the case of power supply modulation, the PMC output voltage error, depending on the PA input current, the bandwidth of the input signal 120, or the system operating temperature, can be modeled and included in the preprocessed input signal 424. This technique of estimating the time-varying preprocessed input signal 424 based on digital control signals (e.g., level selection) and external inputs (e.g., signal bandwidth or operating temperature) and applying that estimate to the DPD for accurate compensation can be applied to all types of digital transceiver control. Several examples are provided in this paper.

[0150] In the case of PA power supply modulation, the nonlinear combiner 700 can use the preprocessed input signal 424' (S, such as...) Figure 4C (As shown) to correct the amplitude (AM / AM) and phase (AM / PM) distortion of PA 108 by creating a predistortion signal 122, which will cause PA to produce a desired RF output signal (Y) equivalent to an amplified version of the input signal 120. RF ).

[0151] Figure 7 A nonlinear combiner 700 combines two inputs (i.e., signal 120 and preprocessed input signal 424) in a nonlinear manner to produce a predistorted signal 122. When used in a transmitter (e.g., transmitter 200 of FIG. 2), the nonlinear combiner 700 can help reduce non-idealities in the RF output signal (e.g., signal 126 of FIG. 2). The number of input types for the nonlinear combiner 700 is not intended to be limiting. For example, in other embodiments, the nonlinear combiner may receive signals corresponding to other actuation system states and conditions as inputs, which will be described in more detail below. Furthermore, the general approach described herein is not limited to power supply modulation but can be implemented for a variety of actuation system states.

[0152] Although Figure 7 Nine (9) basis functions and their corresponding coefficients k1 to k9 are shown, but it should be understood that any number of basis functions can be constructed based on additional inputs and the cross terms between basis functions created from those inputs. Furthermore, any mathematical operator or combination of operators can be used to construct them. Figure 7 The basis functions are not shown in the polynomial example.

[0153] Figure 8The diagram illustrates how the above-described techniques and methods, according to some embodiments, can be used to provide a generalized nonlinear combiner 800 having any number of inputs 802a, 802b, 802c, etc. (collectively, 802). At least one of the inputs 802 may correspond to a transmitter input signal (e.g., Figure 7 The input signal 120). In some cases, another input in 802 may correspond to a preprocessed input signal (e.g., Figure 7 Signal 424). In some cases, another input in 802 may correspond to an additional preprocessed input signal (e.g., Figure 4C (Signal 424'). Therefore, it can be envisioned that the DPD 400 can receive any number of input control signals, and that nonlinear inputs can be combined with any number of input control signals.

[0154] For each input 802, one or more basis functions 804 can be applied to produce one or more terms. For example, basis function 804a can be applied to input 802a to produce n1 terms, basis function 804b can be applied to input 802b to produce n2 terms, basis function 804c can be applied to input 802c to produce n3 terms, and so on. These various terms can be weighted using a corresponding number of coefficients provided by the solver. For example, weighting 806a can use n1 coefficients to weight the n1 terms produced for input 802a, weighting 806b can use n2 coefficients to weight the n2 terms produced for input 802b, and weighting 806c can use n3 coefficients to weight the n3 terms produced for input 802c, and so on. Examples of such methods can be used. Figure 6 and Figure 7 The multiplier shown implements the weighted 806.

[0155] Additional terms can be generated by cross-referencing the terms produced for different inputs in input 802. For example, n can be generated by cross-referencing (box 808a) the terms for inputs 802a and 802b. 12 There are several additional terms, and n can be generated by crossing (box 808b) the terms of inputs 802b and 802c. 23 Additional terms, and so on. Typically, any (or all) pairs or combinations of input terms can be interleaved to produce additional terms (e.g., in another example, inputs 802a and 802c can be interleaved). Additional terms can also be weighted. For example, weighted 810a can utilize n... 12 The coefficients are generated by box 808a. 12 The additional items are weighted, and the weighted 810b can be used with n. 23 The coefficients are generated by box 808b. 23 Weighting the items, etc.

[0156] As shown in the figure, various weighted terms can be combined using the summing element 820 to generate the predistortion signal 122.

[0157] It should be understood that this general technique can be used to incorporate n input signals, including transmitter input signals and / or other signals estimated by a preprocessing function. According to this disclosure, any such signal described herein can be provided as input to a nonlinear combiner for digital predistortion.

[0158] The transfer function derived from Volterra can be implemented through a combination of appropriate preprocessing blocks and nonlinear combiners. For example, consider a nonlinear combiner with three inputs: an input signal 120(r), an input signal 120(r) delayed by a single-sample preprocessing block, and an input signal 120(r) delayed by a double-sample preprocessing block. It should be understood in this paper that such a DPD can be configured to implement a full Volterra series with a memory depth of three samples and a nonlinear order selected according to the basis functions of the nonlinear combiner (e.g., operators 604a to 604b).

[0159] Go to Figure 9 ,exist Figure 9 The same reference numerals are used to illustrate the same elements in Figure 4, showing an example of a DPD 900 configured to correct for external interference. In addition to the transmitter input signal 120, the DPD 900 can receive an input amplitude signal 320, one or more control signals 220(z) (e.g., signals for controlling or actuating the transceiver system state, such as a level selection signal 322), and one or more external signals or inputs 906a, 906b, 906c, 906d, etc. (collectively, 906). The external signals 906 can respond to external system conditions that produce distortion and non-idealities.

[0160] The illustrative DPD 900 includes a preprocessing block 902, which may include, for example, blocks 408 and 414 previously discussed. Additionally, preprocessing block 902 may include one or more blocks 904a, 904b, 904c, 904d, etc. (collectively referred to as 904) for preprocessing corresponding external inputs 906a, 906b, 906c, 906d, etc. The nonlinear combiner 404 can use such preprocessed inputs to enhance the predistortion signal 122.

[0161] Typically, one or more preprocessing blocks may be provided for each external input 906, wherein these blocks are arranged in series and / or parallel configurations and configured to generate (or contribute to generating) interference-related signals, thereby compensating for interference and enhancing predistortion. Preprocessing block 904 may include the above-described... Figures 4A to 4CAny type of preprocessing block described in the context, such as LUTs, filters, NLTs, delays, etc., is configured to model the corresponding external system conditions or disturbances. Variations in the external input 906 can be used to continuously adjust the predistortion signal 122 of the DPD 900 to compensate for external disturbances in the same way that the supply voltage is continuously modeled and used to compensate for the effects of discrete supply modulation.

[0162] In the example shown, the preprocessing block 902 may further include a block 904a for receiving a temperature input 906a, a block 904b for receiving a voltage standing wave ratio (VSWR) input 906b, and a block 904b for receiving a battery voltage (V... 电池 Block 904c is the input to 906c, and block 904d is the input to 906d for receiving the scanning angle (i.e., the angle of the highest directivity of the beamforming array). Each of these non-limiting examples of external inputs is discussed in more detail below.

[0163] Temperature input 906a can be a signal or value in response to instantaneous system temperature changes due to environmental factors, adjacent components, etc. Temperature changes may affect the transceiver distortion response, and DPD 900 can be configured to reflect updated distortion characteristics. Temperature information can be used directly by nonlinear combiner 404 and / or processed by preprocessing block 904a (as shown) to create an input to nonlinear combiner 404 to correct for such external time-varying interference. Temperature can be measured using circuitry configured to measure temperature (e.g., a silicon bandgap temperature sensor or other types of temperature sensing circuitry known in the art), implemented near and / or as part of the transmit chain.

[0164] The VSWR input 906b can be a signal or value that responds to the VSWR angle and amplitude caused by environmental or other factors, which presents different loads to the PA RF output (e.g., RF output signal 126 in Figure 2) and affects AM / AM and AM / PM characteristics. The nonlinear combiner 404 can use this signal / value, or a version modified by the preprocessing block 904b, to correct for such external time-varying interference. The VSWR can be measured at the antenna (e.g., antenna 112 in Figure 2) or transmitted from an external device to the transmitter.

[0165] The battery voltage input 906c can be a signal or value in response to the voltage of the system battery or other transceiver power source (in some cases referred to as the power delivery network). Battery discharge or connection to a battery charger can affect the transceiver's behavior (e.g., PMC input and output voltage levels). The nonlinear combiner 404 can use this signal / value, or a version modified by the preprocessing block 904c, to correct for such external time-varying disturbances. Battery voltage changes can be measured at the battery or otherwise transmitted from within and / or as part of the transmission chain.

[0166] The scan angle input 906d can be a signal or value responding to the scan angle of the transceiver antenna (e.g., a beamforming array antenna), where relative phase adjustments of adjacent elements cause variations in the load presented to the PA RF output and affect AM / AM and AM / PM characteristics. The nonlinear combiner 404 can use the scan angle input 906d or a version modified by the preprocessing block 904d to correct for such external time-varying interference. In some cases, the beamformer scan angle can be controlled by a modem, and such beamformer control information can be transmitted to the DPD as the scan angle input 906d. As mentioned earlier in this disclosure, the DPD can also compensate for undesired variations in beamformer characteristics when adjusting the scan angle. For example, a post-processing block (such as...) can be used... Figure 4B (as shown in the figure) to increase or decrease the attenuation of the predistortion signal x in response to the scan angle input signal 906d.

[0167] In some implementations, one or more external input signals in response to system conditions are values ​​(not shown) representing the instantaneous or average output signal variation of other transmitters or antennas (not shown) that may or may not be connected to the same PMC. When other amplifiers are connected to the same PMC, the output power level (e.g., average output power) of these other amplifiers may cause deviations from the expected average or instantaneous supply voltage at the PMC's output level. When other transmitters operate very close together (e.g., with antennas within 20 cm of each other), the transmissions of these other amplifiers may cause reverse intermodulation distortion (RIMD). Therefore, for example, the external signal may be based at least in part on the power level of another transmitter chain configured to operate simultaneously with the transmitter chain of this subject. In some cases, the two transmitter chains may be managed by a common PMC. In some cases, the two transmitter chains may be provided as part of a common facility (e.g., on the same mobile device, base station, etc.). The nonlinear combiner 404 may use the instantaneous and / or average output power from other power amplifiers to correct for external time-varying interference such as deviations from the expected voltage level in the PMC, or to correct for RIMD.

[0168] Figure 10It shows Figure 2A Further details of the embodiment of the power modulation transmitter shown are in Figure 10 The same reference numerals are used to illustrate Figure 2A The same components. For example, the PMC 304 connected to PA 40 can correspond to... Figure 2A The state-actuated circuit 204 mentioned above. The PMC 304 is represented by n voltage sources 703 and a multiplexer (called a power modulator) 702, which selects the voltages to be directed to the output V. out One of the voltage levels of the 704. The level selection signal 322 determines which voltage level should be connected to the output. In some implementations, the information of the level selection signal 322(s) is encoded and transmitted from the transceiver to the PMC 304 over a custom physical interconnect to optimize interface power, clock rate, or the number of physical wires connecting the transceiver level selection 302 to the PMC 304. A decoding block 1000 can be provided to decode and recover the information of the level selection signal 322(s) from the DCL 701. The pulse shaping network (PSN 705) is used for the discrete output voltage V out The step voltage in the middle is shaped to generate a PA power supply voltage of 324 (V). PA The electrical network of the PA transistor. As those skilled in the art will understand, depending on the type of PA transistor technology used for the amplifying transistor, the term supply voltage as used herein may refer to Vdd or Vcc, and is intended to refer to a PA supply voltage of 324 (V). PA ).

[0169] Figure 10 PA 40 is shown in this embodiment as having signal 65 (X) RF ) as its input and signal 75 (Y) RF A scaled-up version of the transistor 720a is used as a two-stage RF amplifier for its output. The first-stage transistor 720a, together with the input impedance matching network (IMN) 722 and the interstage impedance matching network (ISMN) 723, is designed for the desired RF performance (e.g., gain, phase and / or efficiency behavior, behavior relative to V). PA (Changes, etc.). The gate bias network (GBN) 725 provides DC bias V to the gate of transistor 720a. gg1 730. The drain power network (DSN) 727 provides the PA supply voltage 324 (V) to the drain of transistor 720a. PA The second-stage transistor 720b, along with GBN 726, DSN 728, OMN 724, and ISMN 723, can be arranged in a similar manner to implement the second RF stage, as shown in the figure.

[0170] The behavior of the two-stage RF PA 40 depends on the gate bias voltage V.gg1 and V gg2 ; IMN, ISMN, and OMN; and PA power supply voltage 324 (V) PA Under discrete power supply modulation, the PMC 304 output voltage level V out 704 is commanded by signal DCL 701 to adjust the PA power supply voltage 324 (V) PA ). Reference Figures 10 to 2A The PMC 304 acts as the state actuation circuit 204 under the influence of the control signal 220 (in this case, the level selection signal 322) determined by the state actuation control unit 202 (in this case, the level selection 302). This applies to any aspect of the PA (e.g., V). gg1 V gg2 IMN, ISMN, OMN, V PA Adjustments to the PA linearity (instantaneous PA gain and PA phase) can affect PA performance and performance tradeoffs (e.g., efficiency versus linearity). Without compensation, variations in PA linearity will lead to changes in the output signal 75 (Y). RF The distortion described in this paper is due to adjustments made to the PA (Pattern Indicator).

[0171] Those skilled in the art will understand that Figure 10 The simplified block diagram can be extended to more complex implementations of PA 40 and PMC 140, but the discrete power supply modulation behavior described in this paper is essentially similar.

[0172] It should be understood that, as described above, different types of transistors can be biased by applying current or voltage to specific terminals. For example, a bipolar junction transistor (BJT) can be biased by applying current to its base terminal, and a field-effect transistor (FET) can be biased by applying voltage to its gate terminal. Therefore, although certain implementations are described herein with respect to “gate” bias modulation, the general structures and techniques described herein are applicable to all transistor technologies. For example, this method can be applied to BJT transistors by adjusting the bias current at the base terminal.

[0173] like Figure 11 As shown, in Figure 11 The same reference numerals are used to illustrate Figure 2A The same components, in some embodiments, Figure 2A The state actuation control unit 202 may include gate bias modulation control (or “gate bias modulation circuitry”) for changing the gate bias of one or more PAs. For example, the transceiver may include gate bias modulation circuitry 1100 (corresponding to state actuation circuitry 204) configured to modulate the observed gate bias of the PA during operation to improve the performance characteristics of the PA. Figure 11 An implementation of PA 40 utilizing stacked transistors 721a, 721b, and 721c is shown. This approach can facilitate the generation of large RF voltage swings (and thus large RF output power) using transistors with desired RF characteristics but low rated voltages. However, the gate bias voltages 731a to 731c (V) must be controlled. ggA To V ggC (collectively referred to as 731) to measure the voltage difference (V) between the gate and source of each transistor 721a to 721c. gs ) and the voltage difference between the gate and drain (V gd It must be kept within a useful and safe operating range. If the voltage becomes too high, the transistor may be damaged or destroyed. If the voltage deviates from the design target voltage, RF performance (e.g., linearity, efficiency, saturation power, etc.) will deteriorate.

[0174] For example, it might be desirable for gate bias modulation control to actively adjust the gate voltage bias (or base current bias) during transmission, which actively determines the bias point of the PA. Adjustment of the bias can alter the PA's nonlinear characteristics, efficiency, and / or maximum output power (saturation power or P). sat Adjusting the bias point can be beneficial or critical for maintaining each PA under safe operating conditions (e.g., the voltage across the two terminals or the current flowing into the terminals) and preventing damage. At a PA supply voltage of 324V... PA The gate voltage 731 of the stacked transistors under power supply modulation may be particularly important.

[0175] Adjustments to the gate voltage bias (or base current bias) can be performed as a continuous analog or discrete adjustment of the bias voltage (similar to the discrete PA power supply modulation discussed earlier). The adjustment of the gate voltage bias can be coordinated with the RF input signal (e.g., power, bandwidth, frequency, etc.), other system controls (e.g., modulating the power supply voltage, etc.), and / or system states (e.g., temperature, VSWR, etc.). For example, in some implementations, control can be adjusted with changes in the drain or collector power supply voltage to enhance RF performance (e.g., efficiency, linearity, or P). satIn some implementations, temperature can be used to adjust control to enhance RF performance. In some implementations, control of one or more transistors in a transistor stack can be adjusted to maintain each of the gate-to-source and gate-to-drain voltages at a safe level. Active adjustment of the individual gate-to-source and gate-to-drain voltages can be particularly important for stacked PAs under power supply modulation. In some implementations, control can be adjusted for each component of a multi-amplifier PA topology. For example, in some implementations, this could include the carrier stage and peak stage of a Doherty amplifier system. In other implementations, the gate of each input of the combiner in a non-inverting amplifier system can be adjusted individually.

[0176] The output of the gate bias modulation control (control signal 220(z)) is transmitted as input or otherwise provided to the gate bias modulation circuit 1100 and the preprocessing block of DPD 102 (e.g., Figure 4A and Figure 4B The preprocessing element 402 outputs an output signal related to the variation in PA behavior to be compensated. Depending on the implementation of the gate bias modulation circuit 1100 and the desired behavior, the control signal 220(z) can take the form of an n-bit sampled signal representing a continuously varying (continuous-time) analog signal, or it can take the form of a digital index signal representing one of many discrete states (as in the case of power supply modulation). The nonlinear combiner 404 can combine the output of the preprocessing block into the predistorted signal provided to the transmitter.

[0177] Figure 11 The gate bias modulation circuit 1100 can be implemented in various ways to provide control over discrete or continuous variations of any number of gate bias voltages 731. In some embodiments, the various gate bias voltages can be correlated by a fixed ratio, such as by utilizing a network of resistor dividers. In other embodiments, the various gate bias voltages can be generated independently using an active circuit system. In other embodiments, the gate bias voltages of one or more transistors can be modified in response to system conditions (e.g., temperature).

[0178] In some embodiments, the gate bias modulation circuit 1100 may be implemented independently, co-implemented with the PMC 140 on the same integrated circuit (IC) or in the same package, or co-implemented with the PA 40 on the same IC or in the same package. The gate bias modulation circuit 1100 has a control signal 220(z) as an input, which can be transmitted from the gate bias control block using an analog or digital interface. In some embodiments, the interface may be similar to the DCL interface previously described in the context of discrete power supply modulation. In some embodiments with discrete power supply modulation, the input control signal 220 may be derived from a power supply modulation control signal (e.g., level selection signal 322,s) used by the PMC 304, or decoded from the DCL signal 701 used by the PMC 304.

[0179] Go to Figures 12A to 12F ,exist Figures 12A to 12F The same reference numerals are used to illustrate Figure 2A Using the same components, in some embodiments, the state actuation control unit 202 may correspond to load modulation control for changing the load of one or more PAs by altering the load actuation circuitry. For example, it may be desirable for the load modulation control to actively adjust the output matching network (OMN, corresponding to the state actuation circuit 204) that at least partially determines the PA load line. The adjustment of the control alters the nonlinear characteristics, efficiency, and / or maximum output power (saturation power or P) of the PA. sat Adjustments to the controls may be beneficial or critical for keeping each PA in a safe operating range and preventing damage (e.g., under PA power modulation or the effects of antenna mismatch).

[0180] Figure 12A One implementation of a simple PA 40 including an OMN 724 is shown. As illustrated, in one example, the OMN 724' can be implemented by incorporating two series capacitors 741 and a shunt inductor 742 in parallel. This example is provided by way of illustration and not limitation; prior art demonstrates techniques for implementing output matching networks, and some examples of these are provided herein.

[0181] Figure 12B An embodiment of a reconfigurable matching network (RMN) 740 according to some implementations is shown, which can be provided to replace the fixed OMN 724. The RMN has an RF input Y connected to the drain of a transistor. RF '65' and connected to output signal 75 (Y) RF RF output Y RF And control signal 220 (z). For example, Figure 12B The RMN 740 can be provided as Figure 12AThe OMN 724. In some implementations, the RMN can be the output matching network (OMN), interstage matching network (ISMN), and / or input matching network (IMN) of the power amplifier.

[0182] Figure 12C An illustrative embodiment is shown, wherein control signal 220(z) can generate control signals 760b to 760d by means of multiplexer 743 to actuate reconfigurable matching elements in the RMN. Those skilled in the art will understand that other means (e.g., combinational logic, state machines, etc.) can be used to decode control signal 220 to generate control signals for the reconfigurable matching elements. In this embodiment, control signals 760b to 760d effectively actuate exemplary reconfigurable elements in the shunt RMN 750 (e.g., Figure 12D (as shown in 745, 746, 747). In some embodiments, Figure 12C and Figure 12D The general structure and technology can be implemented as Figure 12B Part of the RMN 740.

[0183] exist Figure 12E The diagram illustrates a reconfigurable matching network 751 comprising elements 753 and 754 connected in series. Different OMN adjustment methods are known in the art. For example, this can be achieved by adding elements connected in series with another matching network element (such as...). Figure 12D (as shown) or connected in parallel with another matching network element (such as Figure 12E The impedance of the network (as shown in the diagram) is used to adjust the network impedance transformation. The network can be tuned to discrete states by adding or removing components from the circuit using discrete switching techniques. In some implementations, the RMN can be configured to change abruptly from one state to another (e.g., within less than 1 microsecond, less than 500 nanoseconds, less than 250 nanoseconds, or less than 100 nanoseconds).

[0184] Microelectromechanical systems (MEMS) switch 742b, PIN diode 742c, and solid-state switch 742d are included in the RMN 750 to illustrate some reconfigured elements known in the art. Passive element 742a is shown as an inductor connected to ground. Figure 12E The diagram shows a reconfigurable matching network 751 consisting of elements 753 and 754 connected in series. It can be reconfigured by adding elements connected in series with another matching network element (e.g., such as...). Figure 12D (as shown) or connected in parallel with another matching network element (e.g., as shown) Figure 12E The impedance of the RMN impedance transformer is adjusted by using the impedance shown. The network can be tuned to a discrete state by adding or removing components from the circuit using discrete switching techniques. In other implementations, the RF signal can be switched to, for example... Figure 12FThe alternative matching network path within the switch output matching network 752 shown.

[0185] In a discrete power supply modulation implementation, the control signal 220 changes abruptly and effectively at the next sample, but the effect of the control signal 220 on the reconfigurable output matching network may not be instantaneous due to the actual time constant of the analog and RF circuitry.

[0186] Other impedance-tuning elements also provide continuously variable impedance control, such as variable capacitor diodes (or "varactor diodes"), where the reactance of the element can be adjusted by varying the DC voltage applied to the tuning element. In this case, the load modulation control signal can be provided as an analog continuous-time signal to the corresponding load modulation actuation circuit and as an n-bit sampled signal representing the continuous-time analog signal to the corresponding preprocessing block. The change in PA behavior may not be linearly related to the control signal 220.

[0187] Continuous or discrete variations in the RMN can affect PA performance (e.g., linearity, efficiency). Uncompensated variations in PA gain and phase result in changes in the output signal 75 (Y). RF Distortion of the signal. In such cases, it may be beneficial to provide the load modulation control signal 220 to the preprocessing block 402 of the DPD 102. The preprocessing block 402 converts the control signal 220 into a signal related to the change in PA behavior caused by the control signal. In some embodiments, the preprocessing block may include a lookup table and / or nonlinearity to convert the control signal into a signal closely related to PA behavior. In discrete load modulation embodiments, a preprocessing filter may be additionally applied to create a nonlinear combiner input signal with a response that is the same as or at least related to the RMN response. The nonlinear combiner 404 can combine the output of the preprocessing block into the predistorted signal provided to the transmitter and effectively improve the linearity of the load modulation transmitter system.

[0188] The benefits of load modulation can include improved performance or robustness (ensuring transistors remain in safe operating regions, avoiding electrical overstress). Adjustment of the RMN can be coordinated with RF input signal characteristics (e.g., average power, bandwidth, RF center frequency), instantaneous RF input or desired signal amplitude (or envelope), other system controls (e.g., modulated supply voltage, bias voltage), or system conditions (e.g., temperature, VSWR). In some implementations, the RMN can be adjusted with changes in the drain or collector supply voltage to improve efficiency, linearity, or P. sat In some implementations, temperature-adjusted RMN can be used to improve efficiency or linearity. In some implementations, RMN can be adjusted to adjust the load line to dynamically increase P at peak instantaneous power. satFurthermore, it increases efficiency when instantaneous power is reduced.

[0189] Compensation for anticipated changes in PA characteristics can be achieved by providing control signals to the preprocessing block of DPD (for RMN adjustment of desired and beneficial effects, e.g., increasing P). sat DPD can also be used to compensate for unintended changes (or changes that are not directly beneficial, such as increased losses and reduced gains in RMN elements).

[0190] In some examples, DPD processing blocks (e.g., filters) can be provided and configured to model changes in the gain and phase of the emitter chain due to the reconfiguration of the RMN.

[0191] Load modulation control techniques can be more generally considered as techniques for adjusting the impedance of any matching network. Other matching networks (e.g., IMN, ISMN, etc.) can also be implemented as RMNs to achieve various additional performance trade-offs. For example, adjusting the IMN can affect the PA gain; adjusting the ISMN can affect the PA gain and the change in PA phase relative to the supply voltage (the so-called "gain dispersion"). Therefore, all of the above techniques can be applied to input matching networks, inter-stage matching networks, or output matching networks in a similar manner.

[0192] Reference Figures 13A to 13B ,exist Figures 13A to 13B The same reference numerals are used to illustrate Figure 2A The same components exist, and combinations of various RF PA units (in) Figure 13AMethods (shown as 770a to 770c) for generating increased output power, improving efficiency, or achieving other RF performance benefits are described. An input RF signal can be split into n paths using an RF splitter 771 and a combiner 773. Such components are known in the art and can take the form of a Wilkinson combiner, a 90-degree hybrid combiner, a transformer, or other combiner structures. The combiner 773 can be implemented using various components known in the art, including lumped circuit elements, transmission lines, resonators, waveguides, or combinations thereof. In some embodiments, the plurality of PA units 770a to 770c may include at least a first PA unit and a second PA unit, the first PA unit being configured to receive a first RF signal from one or more RF signals as input, and the second PA unit being configured to receive a second RF signal from one or more RF signals as input. In some embodiments, depending on the design, the first RF signal and the second RF signal may be the same and / or different signals. A multi-PA controller can be configured to independently control the first PA unit and the second PA unit. In some implementations, the transmit chain includes a splitter configured to receive an input RF signal and provide multiple RF signals as amplitude-adjusted and / or phase-adjusted versions of the input RF signal.

[0193] In another example of a multi-PA transmitter, the so-called digital PA is coupled to a common output node to generate an RF output signal 75 (Y). RF The PA power stage consists of n PA power stage units 770a to 770c. PA power stage units 770a to 770c (collectively referred to as 770) are shown as having single-ended inputs and differential outputs, although either the input or output needs to be differential or single-ended. The output of stage 770 can be combined using many devices, such as... Figure 13A The n:1 transformer 773 shown. Figure 13A The diagram also shows a balun 774 used to convert the differential output of transformer 773 to a single-ended output YRF 775. Each power stage unit 770 can be enabled by PA signals a1 to a2. n Activate or deactivate (e.g., switch in / out, turn on / off, or otherwise activate / deactivate). For example, a given power state unit 770 can be enabled by closing an RF switch, adjusting an RF matching network, adjusting a PA bias, or adjusting a PA supply voltage. Figure 13A It is shown in an illustrative rather than restrictive manner. Although Figure 13A Three (3) power stage units 770 are shown, but other numbers of power stage units may be provided.

[0194] Figure 13B The diagram illustrates the generation of PA enable signals a1 to a2 from digital control signal 220. nThe implementation of the multiplexer 743. The digital control signal 220 can, for example, be derived from... Figure 2A The state-actuated control 202 is generated. As mentioned above, the PA enable signal a1 to a... n Each of the one or more power stage units 770 to be combined can be fully and / or partially enabled and / or disabled.

[0195] When only one power stage unit 770 is enabled, a baseline level RF power is observed at the output. For example, when only power stage 770c is enabled, a baseline RF power of 0 dB will be observed at the output. The effect of enabling additional power stage units depends on the amplitude and phase relationship of the input / output signals between the power stage units. In one example, when two power stage units 770c and 770b are enabled, the RF output power level increases by 3 dB from the baseline. In another example, as those skilled in the art will understand, when four power stage units are enabled, the output power increases by 6 dB from the baseline; and so on. Changes in the enable signal are accompanied by changes in the nonlinear characteristics (e.g., gain and phase) of the entire power stage.

[0196] The configuration of the enabled PA power stage unit 770 can be changed by the discrete digital control signal 220 (e.g., by...). Figure 2A The state actuation control unit 202 generates a command, which is simultaneously provided to the actuation circuit 204 and the appropriate preprocessing unit 402 (e.g., Figure 4B One of those shown). The preprocessing block transforms the digital control signal 220 into a signal that is supplied to the nonlinear combiner (e.g., Figure 4B The input signal of the nonlinear combiner 404 is used to compensate for the change in nonlinear characteristics caused by enabling the additional PA unit.

[0197] The splitter 711 and combiner 773 can be designed to provide a given amplitude and phase relationship between two or more PA input terminals, and a given phase relationship between two or more PA output terminals. It should be understood herein that adjusting the amplitude and phase of the input / output signals supplied to one of the multiple combined PAs can adjust the overall RF performance. In one example, out-of-phase techniques use the phase relationship between two combined PA paths as a method to control the signal amplitude at the combiner output while maintaining PA compression and thus high efficiency. In another example, the Doherty amplifier uses input phase offsets and output phase offsets (along with unique bias control) for multiple combined PAs to dynamically adjust the load impedance at each of the PA output stage transistors and maintain high efficiency under reduced instantaneous output power.

[0198] The amplitude and phase relationship can be fixed or reconfigurable. Reconfiguration of the amplitude or phase of a given input or output path can be achieved using a reconfigurable matching element under the influence of a control signal (e.g., control signal 220) as described herein. Figure 13C An embodiment of a multi-PA unit system 762 with amplitude and phase control is shown. The multi-PA system includes amplitude shifters 781a to 781c and phase shifters 780a to 780c for amplitude and phase adjustment of the input signal. Figure 13D At least one multi-PA controller 743d and 743e for implementing amplitude and phase control are shown. The at least one multi-PA controller 743d and 743e generate multiple amplitude adjustment signals 762a to 762n and multiple phase adjustment signals 763a to 763n from control signal 220. At least one multi-PA controller 743b and 743c are configured to adjust the amplitude and / or phase of one or more RF signals received as input by multiple PA units. In some embodiments, splitter 771 may be configured to receive input RF signals and provide multiple RF signals as amplitude-adjusted and / or phase-adjusted versions of the input RF signals. As will be appreciated by those skilled in the art, some embodiments may include enable signals a1 to a2. n Amplitude shifters 781a to 781c and / or phase shifters 780a to 780c.

[0199] One or more state actuation circuits 204 of one or more PA power stage units 770 (e.g., circuitry for adjusting supply voltage, gate bias, RMN) can have coordinated adjustments to achieve desired RF performance (e.g., linearity, efficiency, robustness). In the case of multiple PA transmitters, the adjustment of the state actuation circuitry of each PA unit can be coordinated with enabling or disabling the PA unit. Adjustment of each PA element can be performed using a shared or unique control signal (e.g., control signal 220). Each control signal can be generated by a shared or unique state actuation control unit (e.g., control unit 202). Each control signal can be provided to a shared or unique preprocessing block 420 in the DPD 400 for incorporation into a predistortion signal 122 to be provided to the PA or PA unit. In the presence of adjustments performed by the actuation circuitry, the DPD is used to linearize the RF output signal 75 (Y). RF ).

[0200] like Figures 14A to 14D As shown, in some embodiments, the state actuation control unit (e.g., Figure 2AThe control unit 202 can be configured to generate control signals 220(z) for manipulating the beamforming array of the radiating elements. For example, the transceiver may include a beamformer 783 and one or more antenna array elements 782a to 782c (collectively referred to as 782). The beamformer 783 may partially include RF phase shifters 780a to 780c, RF amplitude attenuators 781a to 781c, and / or an RF variable gain amplifier (not shown). For example, the control signal 220 can be used to adjust the relative phase and amplitude of adjacent radiating elements, thereby causing increased radiation directivity in one or more directions. That is, one or more “beams” of radiated energy can be “formed” and one or more beams can be “manipulated” in a given direction. Figure 14A The image also shows the DPD 20 and the digital-to-RF converter 35.

[0201] In some implementations, in such Figure 14B In the “front PA” beamformer configuration 786 shown, beamformer elements 780a to 780c, 781a to 781c, etc., can be located in the DPD (e.g., Figure 2A The DPD 102) is located between one or more PAs 770a to 770c. In other embodiments, beamforming elements 780a to 780c, 781a to 781c, etc., may be located between at least one PA 770a and one or more antenna elements 112 in the "post-PA" beamforming configuration 788, such as... Figure 14C As shown. Either of beamforming configurations 786 and 788 can correspond to... Figure 14A Beamformer 783. As shown in Figure 14, an RF splitter 771 can be provided to split a single input RF signal 65 onto multiple paths respectively routed to different phase shift adjustment elements 780a to 780c and amplitude adjustment elements 781a to 781c. State actuation circuit (e.g., Figure 2A The circuit 204 can be connected to the beamformer 783 and configured to modulate the direction of one or more beams. In this case, the state actuation circuit can be referred to as a beamforming array controller or simply a beamformer controller.

[0202] Modulating the beam direction can introduce distortion into the transmitted signal. For example, non-idealities in beamformers (e.g., nonlinear effects of phase shifters implemented by switches) can occur up to the PA stage ( Figure 14B (Pre-PA configuration) or after PA level ( Figure 14CThe “post-PA” configuration introduces nonlinearity. In either case, the beamformer may increase distortion (e.g., due to nonlinear variations caused by phase shifter angle adjustments or attenuator attenuation adjustments, RF splitter frequency response, etc.). The distortion introduced by the beamformer can vary depending on the selected beam direction or angle.

[0203] Modulating the beam direction can also affect the insertion loss (e.g., attenuation or gain independent of envelope amplitude) and / or insertion phase (e.g., phase contribution independent of envelope amplitude) of beamformer components. When the beam direction is modulated, variations in insertion loss and / or phase can lead to discontinuities in the transmitted waveform. In some implementations, Figure 14A The beamformer and radiating array themselves can be subarrays within a larger array. Similar to a single array, the larger array uses the relative amplitude and / or phase relationships between the subarrays to further enhance the directivity of one or more beams. Variations in insertion loss and / or phase when the subarray beams are manipulated can affect the performance of the larger array.

[0204] In addition to the nonlinearities introduced in the transmission path by the beamformer elements (e.g., the nonlinear characteristics of individual PAs connected to an antenna radiating close to the ground), these nonlinearities can also be altered by modulation of the beam direction. The RF signal of one antenna array element (e.g., element 782c) is coupled to another antenna array element (e.g., element 782b) with a certain phase and amplitude relationship, thereby creating impedance mismatch at each PA. Variations in PA impedance partially account for the changes in the nonlinear characteristics of each PA.

[0205] Go to Figure 14D The diagram illustrates a first example of a beamformer controller, wherein beamformer control signal 220(z) is input to one or more multiplexers (e.g., multiplexers 743b, 743c), LUTs, or other combinational logic to generate a beamformer control signal for use with the beamformer controller. Figure 14A Beamformer 783 and / or Figure 14B The beamformer configuration 786 includes phase shift control signals 784a to 784c, amplitude control signals 785a to 785c (as shown), and / or other beamformer element adjustments (not shown). In some examples, the phase shift control signals 784a to 784c can be provided as inputs. Figure 14B and / or Figure 14C The RF phase shifters 780a to 780c and / or RF amplitude attenuators 781a to 781c, and in some embodiments, can jointly manipulate at least one beam radiated from the beamforming array.

[0206] In some implementations, the beamformer control signal 220(z) may be connected to or otherwise provided to Figure 14A One or more preprocessing and / or postprocessing blocks of the DPD 20 are used to predistort the behavior of at least one of the following, all of which may change with beam modulation: nonlinearity or frequency response of beamformer elements, beamformer insertion gain and / or insertion phase, and / or PA nonlinearity due to coupling of radiating elements. Figure 9 An external input scan angle 906d is also shown as entering the preprocessing block 904d of the DPD 900. The scan angle 906d can be commanded by a modem and indicates the desired beamforming direction, generating a beamformer control signal 220. The input scan angle 906d and control signal 220 can be substantially the same, or one can be an abstract modem command while the control signal 220 is a hardware control signal. The DPD 900 can preprocess and use any command or signal related to changes in beamformer behavior as input. The preprocessing block 904d can receive the scan angle 906d or a converted version thereof, and in some embodiments is a LUT configured to convert the scan angle into a digital representation of the beamformer's analog response. The preprocessing block 904d is then configured to provide the preprocessed signal to a nonlinear combiner 404 for combination with at least one of the other input signals to generate a predistortion signal 122(x).

[0207] In some embodiments, the beamformer may include a circuit arrangement that splits an RF input signal into one input for each element of an antenna element array, and then performs phase and / or amplitude adjustment on the RF signal for each element. In some embodiments, the beamforming array may include an array of beamformers and one or more antenna elements. In some embodiments, the beamformer controller may include a control block that determines what phase and / or phase adjustment to apply to the RF input signal of each element based on a desired scan angle. As used herein, the scan angle may refer to the configuration of the beamformer's phase and / or amplitude adjustment that determines the direction of one or more beams propagating from the beamforming array.

[0208] It should be noted that digital-to-RF converters (e.g., Figure 2A Converter 106 and / or Figure 14A The nonlinear effect of the converter 35 in the middle can also be at least partially transmitted through Figure 4B The post-processing block 450 shown is used for compensation.

[0209] Although the electronic circuits shown in the accompanying drawings may be illustrated in the form of analog or digital blocks, it will be understood that analog blocks may be replaced by digital blocks performing the same or similar functions, and digital blocks may be replaced by analog blocks performing the same or similar functions. Analog-to-digital or digital-to-analog conversion may not be explicitly shown in the drawings, but should be understood.

[0210] The subject matter described herein can be implemented as a digital electronic circuit system, or as computer software, firmware, or hardware (including the structural devices disclosed herein and their structural equivalents), or a combination thereof. The subject matter described herein can be implemented as one or more computer program products, for example, tangibly implemented in an information carrier (e.g., in a machine-readable storage device) or in a propagating signal, for execution by or to control the operation of a data processing device (e.g., a programmable processor, computer, or multiple computers). Computer programs (also referred to as programs, software, software applications, or code) can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file. A program can be stored as a portion of a file containing other programs or data, a program can be stored in a single file dedicated to the program under discussion, or a program can be stored in multiple coordinating files (e.g., a file storing portions of one or more modules, subroutines, or code). Computer programs can be deployed to run on one computer or multiple computers at one site, or they can be distributed across multiple sites and interconnected through a communication network.

[0211] The processing and logic flows described in this disclosure (including the method steps of the subject matter described herein) can be executed by one or more programmable processors that execute one or more computer programs to perform the functions of the subject matter described herein by manipulating input data and generating outputs. The processing and logic flows can also be executed by a special-purpose logic circuit system (e.g., an FPGA (Field-Programmable Gate Array) or an ASIC (Application-Specific Integrated Circuit)), and the apparatus of the subject matter described herein can be implemented as a special-purpose logic circuit system (e.g., an FPGA or an ASIC).

[0212] For example, processors suitable for executing computer programs include general-purpose and special-purpose microprocessors, as well as any one or more processors in any type of digital computer. Typically, the processor receives instructions and data from read-only memory or random access memory, or both. The basic components of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or operatively coupled to receive data from or transfer data to said mass storage devices, or both. Information carriers suitable for embodying computer program instructions and data include all forms of non-volatile memory, such as semiconductor memory devices like EPROMs, EEPROMs, flash memory devices, or magnetic disks. The processor and memory may be supplemented by or incorporated into a dedicated logic circuit system.

[0213] Computer programs can be stored / distributed on suitable media such as optical storage media or solid-state media, provided together with or as part of other hardware, but can also be distributed in other forms such as via the Internet or other wired or wireless telecommunications systems.

[0214] The use of ordinal terms such as “first,” “second,” and “third” to modify a claim element does not imply any priority, precedence, or order of one claim element relative to another, or any temporal order of the actions of the method of execution. Rather, it serves only as a label to distinguish one claim element with a specific name from another element with the same name (but for the purpose of using ordinal terms) to differentiate claim elements.

[0215] In some embodiments, the terms "approximately" and "about" may be used to indicate values ​​within ±20% of the target value, within ±10% of the target value, within ±5% of the target value, and within ±2% of the target value. The terms "approximately" and "about" may include the target value. The term "substantially equal" may be used to refer to values ​​that are within ±20% of each other in some embodiments, within ±10% of each other in some embodiments, within ±5% of each other in some embodiments, and within ±2% of each other in some embodiments.

[0216] The term "substantially" can be used to refer to a value within ±20% of the comparative measure in some embodiments, within ±10% in some embodiments, within ±5% in some embodiments, and within ±2% in some embodiments. For example, "substantially" referring to a first direction perpendicular to the second direction can refer to a first direction within ±20% of the second direction at a 90° angle in some embodiments, within ±10% of the second direction at a 90° angle in some embodiments, within ±5% of the second direction at a 90° angle in some embodiments, and within ±2% of the second direction at a 90° angle in some embodiments.

[0217] It should be understood that the various elements of the different embodiments and / or figures described herein can be combined to form other embodiments not specifically described above. The various elements described in the context of a single embodiment or figure may also be provided individually or in any suitable sub-combination. It should also be understood that other embodiments not specifically described herein are also within the scope of the appended claims.

[0218] In the foregoing detailed description, various features have been combined in one or more individual embodiments for the purpose of simplifying this disclosure. This approach of the disclosure should not be construed as reflecting an intention that each claim requires more features than those expressly listed herein. Rather, the inventive aspect may lie in fewer than all features of each disclosed embodiment.

[0219] References to "one embodiment," "implementation," "some embodiments," or variations thereof in this disclosure indicate that the described embodiment may include a particular feature, structure, or characteristic; however, each embodiment may include a particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in conjunction with the knowledge of those skilled in the art, whether explicitly described or not, it will affect such feature, structure, or characteristic in conjunction with other embodiments.

[0220] The disclosed subject matter is not limited in its application to the details of construction and is not limited to the arrangement of components set forth in the following description or shown in the accompanying drawings. The disclosed subject matter is capable of other embodiments and can be practiced and performed in various ways. Therefore, those skilled in the art will understand that the concepts upon which this disclosure is based can readily be used as the basis for designing other structures, methods, and systems for achieving several objectives of the disclosed subject matter. Therefore, the claims should be considered to include such equivalent constructions, provided they do not depart from the spirit and scope of the disclosed subject matter.

[0221] Although the disclosed subject matter has been described and illustrated in the foregoing exemplary embodiments, it should be understood that this disclosure is by way of example only, and many changes may be made to the implementation details of the disclosed subject matter without departing from the spirit and scope of the disclosed subject matter.

[0222] All publications and references cited in this article are explicitly incorporated in their entirety through citation.

Claims

1. A digital pre-distorter (DPD) in a radio frequency (RF) transceiver system having an RF amplifier, comprising: one or more pre-processing blocks collectively configured to receive a plurality of input signals and output a plurality of pre-processed signals, wherein: the plurality of input signals includes at least a transmit signal corresponding to a signal expected to be transmitted or a modified version of the signal and a control signal corresponding to a signal for controlling a power supply voltage level of the RF amplifier or a transformed version of a signal for controlling a power supply voltage level of the RF amplifier, the plurality of pre-processed signals includes at least a first pre-processed signal and a second pre-processed signal, the second pre-processed signal derived at least in part from the control signal, and the one or more pre-processing blocks include at least one or more delay blocks configured to provide the first pre-processed signal corresponding to a delayed or advanced version of the transmit signal relative to itself; and a non-linear combiner configured to combine at least the first pre-processed signal and the second pre-processed signal to provide a pre-distorted version of the transmit signal for transmission via the RF amplifier.

2. The DPD of claim 1, wherein, the control signal is a level selection signal for discrete power supply modulation of the RF amplifier.

3. The DPD of claim 1, wherein, the non-linear combiner is configured to combine the transmit signal and the control signal in a product.

4. The DPD of claim 1, wherein, the one or more delay blocks are configured to delay or advance a signal representing an amplitude of the transmit signal relative to the transmit signal.

5. The DPD of claim 1, the DPD configured to model a memory effect of a transmit chain using at least the one or more delay blocks.

6. The DPD of claim 1, wherein, the pre-distorted version of the transmit signal depends at least in part on both a current value and a delayed value of the transmit signal due to the one or more delay blocks.

7. The DPD of claim 1, wherein, the one or more pre-processing blocks include at least one pre-processing block having a real-valued input and a real-valued output.

8. The DPD of claim 1, wherein, the one or more pre-processing blocks include at least one filter configured to receive the control signal.

9. The DPD of claim 8, wherein, the one or more pre-processing blocks include at least one pre-processing block having a real-valued input and a real-valued output.

10. The DPD of claim 8, wherein, the control signal is real-valued.

11. The DPD of claim 8, wherein, the at least one filter is a low-pass filter.

12. The DPD of claim 8, wherein, the at least one filter is at least partially implemented as a finite impulse response (FIR) filter having three or more taps.

13. The DPD of claim 1, wherein, the one or more pre-processing blocks include at least one filter.

14. The DPD of claim 13, wherein, the one or more pre-processing blocks include at least one pre-processing block having a real-valued input and a real-valued output.

15. The DPD of claim 13, wherein, the at least one filter is a high-pass filter.

16. The DPD of claim 13, wherein, the at least one filter is at least partially implemented as a finite impulse response (FIR) filter having three or more taps.

17. The DPD of claim 13, wherein, the at least one filter is configured to receive the transmit signal or a modified version of the transmit signal and provide a filtered version of the transmit signal.

18. The DPD of claim 13, wherein, the at least one filter is configured to receive a real-valued representation of the transmit signal and provide a filtered version of the transmit signal.

19. The DPD of claim 1, wherein, The one or more pre-processing blocks include at least a first pre-processing block having an output connected to an input of a second processing block.

20. The DPD of claim 1, wherein, The one or more pre-processing blocks include at least a first pre-processing block, a second pre-processing block, and a third pre-processing block configured to combine an output of the first pre-processing block and an output of the second pre-processing block.

21. The DPD of claim 20, wherein, The third pre-processing block is a summing element.

22. The DPD of claim 21, wherein, The summing element provides at least one of the plurality of pre-processed signals output by the one or more pre-processing blocks.

23. The DPD of claim 20, wherein, A delay is imposed on an input or output of the first pre-processing block and / or the second pre-processing block prior to combination.

24. The DPD of claim 20, wherein, The first pre-processing block and / or the second pre-processing block includes a filter.

25. The DPD of claim 20, wherein, A signal output from the first pre-processing block is delayed relative to a signal output from the second pre-processing block prior to combination by the third pre-processing block.

26. The DPD of claim 25, wherein, An input signal of the first pre-processing block and / or the second pre-processing block is a real-valued signal derived at least in part from a signal representing an amplitude of the transmit signal.

27. The DPD of claim 1, configured to receive a plurality of coefficients and apply the plurality of coefficients to the one or more pre-processing blocks.

28. The DPD of claim 27, wherein, The one or more pre-processing blocks include a filter, and the DPD is configured to apply at least one of the plurality of coefficients to the filter.

29. The DPD of claim 27, wherein, One or more of the plurality of coefficients is responsive to a state of a power management circuit of the RF transceiver system.

30. The DPD of claim 27, wherein, One or more of the plurality of coefficients is responsive to a state of the RF amplifier.

31. The DPD of claim 30, wherein, One or more of the plurality of coefficients is responsive to a configuration of a power management circuit of the RF transceiver system.

32. The DPD of claim 1, wherein, The one or more pre-processing blocks include a look-up table (LUT) configured to receive the supply voltage level or a pre-processed version of the supply voltage level.

33. The DPD of claim 32, configured to receive one or more coefficients based on a behavior of a power management circuit of the RF transceiver system and apply the one or more coefficients to the LUT.

34. The DPD of claim 1, wherein, The one or more delay blocks include programmably configurable delay blocks.

35. The DPD of claim 34, wherein, The programmably configurable delay blocks are configurable based at least in part on coefficients of a filter and / or a sampling rate of the transmit signal.

36. The DPD of claim 1, wherein, The one or more pre-processing blocks include a resampler configured to adjust a first rate of at least one signal in the DPD to a second rate different from at least one other signal in the DPD.

37. The DPD of claim 1, wherein, The one or more pre-processing blocks include a resampler configured to adjust a rate of a signal.

38. The DPD of claim 37, wherein, The signal corresponds to one of the plurality of input signals.

39. The DPD of claim 37, wherein, The signal corresponds to an output of another pre-processing block of the plurality of pre-processing blocks.

40. The DPD of claim 37, wherein, The resampler is configured to adjust the rate of the signal to a fixed rate independent of a sampling rate of the transmit signal.

41. The DPD of claim 40, wherein, The one or more pre-processing blocks include a filter having an input coupled to an output of the resampler, the filter configured to operate at the fixed rate.

42. The DPD of claim 37, wherein, The resampler is configured to adjust a rate of the signal to be equal to a sampling rate of the transmit signal.

43. The DPD of claim 1, wherein, The one or more pre-processing blocks include a first resampler configured to adjust a signal from an original rate to an adjusted rate, and a second resampler configured to adjust the signal from the adjusted rate back to the original rate.

44. The DPD of claim 43, wherein, The original rate is greater than the adjusted rate.

45. The DPD of claim 1, wherein, The non-linear combiner is configured to generate at least one cross-term basis function by combining the transmit signal with another signal.

46. The DPD of claim 45, wherein, The other signal is one of the plurality of pre-processed signals.

47. The DPD of claim 1, wherein, The non-linear combiner is configured to generate at least one basis function by exponentiating a signal.

48. The DPD of claim 47, wherein, The signal is one of the plurality of pre-processed signals.

49. A method in a radio frequency (RF) transceiver system having an RF amplifier, comprising: receiving, collectively by one or more pre-processing blocks of a digital pre-distorter (DPD), a plurality of input signals including at least a transmit signal corresponding to a signal expected to be transmitted or a modified version of that signal, and a control signal corresponding to a signal or a transformed version of a signal for controlling a power supply voltage level of the RF amplifier; generating, by the one or more pre-processing blocks of the DPD, a plurality of pre-processed signals including at least a first pre-processed signal and a second pre-processed signal derived at least in part from the control signal, wherein the generating includes delaying or advancing, by one or more delay blocks of the one or more pre-processing blocks, the transmit signal relative to itself to provide the first pre-processed signal; and combining, by a non-linear combiner of the DPD, at least the first pre-processed signal and the second pre-processed signal to provide a pre-distorted version of the transmit signal for transmission via the RF amplifier.

50. The method of claim 49, wherein, The control signal is a level selection signal for discrete power supply modulation of the RF amplifier.

51. The method of claim 49, further comprising combining, by the non-linear combiner, the transmit signal with the control signal.

52. The method of claim 49, further comprising delaying or advancing, by the one or more delay blocks, a signal representative of an amplitude of the transmit signal relative to the transmit signal.

53. The method of claim 49, further comprising modeling, using at least the one or more delay blocks, a memory effect of a transmit chain.

54. The method of claim 49, wherein, The pre-distorted version of the transmit signal depends at least in part on both a current value and a delayed value of the transmit signal due to the one or more delay blocks.

55. The method of claim 49, wherein, The one or more pre-processing blocks include at least one pre-processing block having real-valued inputs and real-valued outputs.

56. The method of claim 49, wherein, The one or more pre-processing blocks include at least one filter configured to receive the control signal.

57. The method of claim 56, wherein, The one or more pre-processing blocks include at least one pre-processing block having a real-valued input and a real-valued output.

58. The method of claim 56, wherein, The control signal is real-valued.

59. The method of claim 56, wherein, The at least one filter is a low-pass filter.

60. The method of claim 56, wherein, The at least one filter is implemented at least in part as a finite impulse response (FIR) filter having three or more taps.

61. The method of claim 49, wherein, The one or more pre-processing blocks include at least one filter.

62. The method of claim 61, wherein, The one or more pre-processing blocks include at least one pre-processing block having a real-valued input and a real-valued output.

63. The method of claim 61, wherein, The at least one filter is a high-pass filter.

64. The method of claim 61, wherein, The at least one filter is implemented at least in part as a finite impulse response (FIR) filter having three or more taps.

65. The method of claim 61, further comprising receiving, by the at least one filter, the transmit signal or a modified version of the transmit signal and providing a filtered version of the transmit signal.

66. The method of claim 61, further comprising receiving, by the at least one filter, a real-valued representation of the transmit signal and providing a filtered version of the transmit signal.

67. The method of claim 49, wherein, The one or more pre-processing blocks include at least a first pre-processing block having an output connected to an input of a second processing block.

68. The method of claim 49, wherein, The one or more pre-processing blocks include at least a first pre-processing block, a second pre-processing block, and a third pre-processing block, the method further comprising combining an output of the first pre-processing block and an output of the second pre-processing block.

69. The method of claim 68, wherein, The third pre-processing block is a summing element.

70. The method of claim 69, further comprising providing, by the summing element, at least one of the plurality of pre-processed signals output by the one or more pre-processing blocks.

71. The method of claim 68, further comprising imposing a delay on an input or output of the first pre-processing block and / or the second pre-processing block prior to combining.

72. The method of claim 68, wherein, The first pre-processing block and / or the second pre-processing block includes a filter.

73. The method of claim 68, further comprising delaying a signal output from the first pre-processing block relative to a signal output from the second pre-processing block prior to combining by the third pre-processing block.

74. The method of claim 73, wherein, An input signal of the first pre-processing block and / or the second pre-processing block is a real-valued signal derived at least in part from a signal representing an amplitude of the transmit signal.

75. The method of claim 49, further comprising receiving a plurality of coefficients and applying the plurality of coefficients to the one or more pre-processing blocks.

76. The method of claim 75, further comprising applying at least one of the plurality of coefficients to a filter of the one or more pre-processing blocks.

77. The method of claim 75, wherein, One or more of the plurality of coefficients is responsive to a state of a power management circuit of the RF transceiver system.

78. The method of claim 75, wherein, One or more of the plurality of coefficients is responsive to a state of the RF amplifier.

79. The method of claim 78, wherein, One or more of the plurality of coefficients is responsive to a configuration of a power management circuit of the RF transceiver system.

80. The method of claim 49, further comprising receiving the supply voltage level or a pre-processed version of the supply voltage level through a look-up table (LUT) of the one or more pre-processing blocks.

81. The method of claim 80, further comprising receiving one or more coefficients based on behavior of a power management circuit of the RF transceiver system and applying the one or more coefficients to the LUT.

82. The method of claim 49, wherein, The one or more delay blocks comprise programmably configurable delay blocks.

83. The method of claim 82, wherein, The programmably configurable delay blocks are configurable based at least in part on coefficients of a filter and / or a sampling rate of the transmit signal.

84. The method of claim 49, further comprising adjusting a first rate of at least one signal in the DPD to a second rate different from at least one other signal in the DPD through a resampler of the one or more pre-processing blocks.

85. The method of claim 49, further comprising adjusting a rate of a signal through a resampler of the one or more pre-processing blocks.

86. The method of claim 85, wherein, The signal corresponds to one of the plurality of input signals.

87. The method of claim 85, wherein, The signal corresponds to an output of another pre-processing block of the plurality of pre-processing blocks.

88. The method of claim 85, further comprising adjusting the rate of the signal to a fixed rate independent of a sampling rate of the transmit signal through the resampler.

89. The method of claim 88, wherein, The one or more pre-processing blocks comprise a filter having an input coupled to an output of the resampler, the method further comprising operating the filter at the fixed rate.

90. The method of claim 85, further comprising adjusting the rate of the signal to equal a sampling rate of the transmit signal through the resampler.

91. The method of claim 49, further comprising: adjusting a signal from an original rate to an adjusted rate through a first resampler of the one or more pre-processing blocks; and adjusting the signal from the adjusted rate back to the original rate through a second resampler of the one or more pre-processing blocks. The original rate is greater than the adjusted rate.

92. The method of claim 91, wherein, 93. The method of claim 49, further comprising generating at least one cross-term basis function through the non-linear combiner by combining the transmit signal with another signal. The other signal is one of the plurality of pre-processed signals.

94. The method of claim 93, wherein, 95. The method of claim 49, further comprising generating at least one basis function through the non-linear combiner by exponentiating a signal. The signal is one of the plurality of pre-processed signals.

96. The method of claim 95, wherein, 97. A digital pre-distorter (DPD) in a radio frequency (RF) transceiver system having an RF amplifier, comprising: one or more pre-processing blocks collectively configured to receive a plurality of input signals and output a plurality of pre-processed signals, wherein: ​ The plurality of input signals comprises at least a transmit signal corresponding to a signal expected to be transmitted or a modified version of the signal and a control signal corresponding to a signal for controlling a power supply voltage level of the RF amplifier or a transformed version of the signal for controlling a power supply voltage level of the RF amplifier, The pre-processing signals comprise at least a first pre-processing signal derived at least in part from the transmit signal and a second pre-processing signal derived at least in part from the control signal, and The one or more pre-processing blocks comprise at least one filter that is at least in part a Finite Impulse Response (FIR) filter; and a non-linear combiner configured to combine at least the first pre-processing signal and the second pre-processing signal to provide a pre-distorted version of the transmit signal for transmission via the RF amplifier.

98. The DPD of claim 97, wherein, At least one of the first pre-processing signal and the second pre-processing signal is an output of, or derived at least in part from, the FIR filter.

99. The DPD of claim 97, wherein, The control signal is a level selection signal for discrete power supply modulation of the RF amplifier.

100. The DPD of claim 97, wherein, The non-linear combiner is configured to combine the transmit signal and the control signal in antiphase.

101. The DPD of claim 97, the DPD configured to model memory effects of a transmit chain using the at least one filter.

102. The DPD of claim 97, wherein, The one or more pre-processing blocks further comprise one or more delay blocks arranged to delay or advance one of the pre-processing signals relative to the transmit signal.

103. The DPD of claim 102, wherein, The one or more delay blocks are arranged to delay or advance a signal representative of an amplitude of the transmit signal relative to the transmit signal.

104. The DPD of claim 102, wherein, The one or more delay blocks are arranged to delay or advance the level selection signal or a modified version of the control signal relative to the transmit signal.

105. The DPD of claim 97, wherein, The one or more pre-processing blocks comprise at least one pre-processing block having real-valued inputs and real-valued outputs.

106. The DPD of claim 97, wherein, The at least one filter is configured to receive the control signal.

107. The DPD of claim 106, wherein, The at least one filter has real-valued inputs and real-valued outputs.

108. The DPD of claim 106, wherein, The at least one filter is a low-pass filter.

109. The DPD of claim 106, wherein, The filter operates on a signal having a sampling rate different from a sampling rate of the transmit signal.

110. The DPD of claim 106, wherein, The at least one filter is at least in part implemented as a Finite Impulse Response (FIR) filter having three or more taps.

111. The DPD of claim 97, wherein, The at least one filter is configured to receive the transmit signal or a signal derived at least in part from the transmit signal and provide a filtered version of the transmit signal.

112. The DPD of claim 111, wherein, The one or more pre-processing blocks comprise at least one pre-processing block having real-valued inputs and real-valued outputs.

113. The DPD of claim 111, wherein, The at least one filter is a high-pass filter.

114. The DPD of claim 111, wherein, The at least one filter is at least in part implemented as a Finite Impulse Response (FIR) filter having three or more taps.

115. The DPD of claim 97, wherein, The one or more pre-processing blocks comprise at least a first pre-processing block having an output connected to an input of a second processing block.

116. The DPD of claim 97, wherein, The one or more preprocessing blocks comprise at least a first preprocessing block, a second preprocessing block, and a third preprocessing block, the third preprocessing block being configured to combine an output of the first preprocessing block and an output of the second preprocessing block.

117. The DPD of claim 116, wherein, The third preprocessing block is a summing element.

118. The DPD of claim 117, wherein, The summing element provides at least one of the plurality of preprocessing signals output by the one or more preprocessing blocks.

119. The DPD of claim 117, wherein, A delay is imposed on an input or an output of the first preprocessing block and / or the second preprocessing block prior to the combining.

120. The DPD of claim 117, wherein, An input signal of the first preprocessing block and / or the second preprocessing block is a real-valued signal derived at least in part from a signal representative of an amplitude of the transmit signal.

121. The DPD of claim 117, the DPD being configured to receive a plurality of coefficients and apply the plurality of coefficients to the one or more preprocessing blocks.

122. The DPD of claim 121, the DPD being configured to apply at least one of the plurality of coefficients to the filter.

123. The DPD of claim 121, wherein, One or more of the plurality of coefficients are responsive to a state of the RF amplifier.

124. The DPD of claim 121, wherein, One or more of the plurality of coefficients are responsive to a configuration of a power management circuit of the RF transceiver system.

125. The DPD of claim 121, wherein, The one or more preprocessing blocks comprise a look-up table (LUT) configured to receive the supply voltage level or a preprocessed version of the supply voltage level.

126. The DPD of claim 125, the DPD being configured to receive one or more coefficients based on a behavior of a power management circuit of the RF transceiver system and apply the one or more coefficients to the LUT.

127. The DPD of claim 97, wherein, The nonlinear combiner is configured to generate at least one cross-term basis function by combining the transmit signal with another signal.

128. The DPD of claim 127, wherein, The other signal is one of the plurality of preprocessing signals.

129. The DPD of claim 97, wherein, The nonlinear combiner is configured to generate at least one basis function by exponentiating a signal.

130. The DPD of claim 129, wherein, The signal is one of the plurality of preprocessing signals.

131. A method in a radio frequency (RF) transceiver system having an RF amplifier, comprising: receiving, by one or more preprocessing blocks of a digital pre-distorter (DPD), a plurality of input signals, the plurality of input signals comprising at least a transmit signal corresponding to a signal expected to be transmitted or a modified version of the signal and a control signal corresponding to a signal for controlling a supply voltage level of the RF amplifier or a transformed version of a signal for controlling a supply voltage level of the RF amplifier; generating, by the one or more preprocessing blocks of the DPD, a plurality of preprocessing signals, the plurality of preprocessing signals comprising at least a first preprocessing signal derived at least in part from the transmit signal and a second preprocessing signal derived at least in part from the control signal, wherein the generating comprises filtering at least one signal by at least one filter of the one or more preprocessing blocks, wherein the filter is at least in part a finite impulse response (FIR) filter; and combining, by a nonlinear combiner of the DPD, at least the first preprocessed signal and the second preprocessed signal to provide a predistorted version of the transmit signal for transmission via the RF amplifier.

132. The method of claim 131, wherein, At least one of the first preprocessed signal and the second preprocessed signal is an output of, or is derived at least in part from an output of, the FIR filter.

133. The method of claim 131, wherein, The control signal is a level selection signal for discrete power modulation of the RF amplifier.

134. The method of claim 131, further comprising combining, by the nonlinear combiner, the transmit signal with the control signal.

135. The method of claim 131, further comprising modeling, by the at least one filter, a memory effect of a transmit chain.

136. The method of claim 131, further comprising delaying or advancing, by one or more delay blocks of the one or more pre-processing blocks, one of the pre-processed signals relative to the transmit signal.

137. The method of claim 136, further comprising delaying or advancing, by the one or more delay blocks, a signal representative of an amplitude of the transmit signal relative to the transmit signal.

138. The method of claim 136, further comprising delaying or advancing, by the one or more delay blocks, a modified version of the level selection signal or the control signal relative to the transmit signal.

139. The method of claim 131, wherein, The one or more pre-processing blocks include at least one pre-processing block having real-valued inputs and real-valued outputs.

140. The method of claim 131, further comprising receiving, by the at least one filter, the control signal.

141. The method of claim 140, wherein, The at least one filter has real-valued inputs and real-valued outputs.

142. The method of claim 140, wherein, The at least one filter is a low-pass filter.

143. The method of claim 140, further comprising operating, by the filter, on a signal having a sampling rate different from a sampling rate of the transmit signal.

144. The method of claim 140, wherein, The at least one filter is implemented at least in part as a finite impulse response (FIR) filter having three or more taps.

145. The method of claim 131, further comprising receiving, by the at least one filter, the transmit signal or a signal derived at least in part from the transmit signal, and providing a filtered version of the transmit signal.

146. The method of claim 145, wherein, The one or more pre-processing blocks include at least one pre-processing block having real-valued inputs and real-valued outputs.

147. The method of claim 145, wherein, The at least one filter is a high-pass filter.

148. The method of claim 145, wherein, The at least one filter is implemented at least in part as a finite impulse response (FIR) filter having three or more taps.

149. The method of claim 131, wherein, The one or more pre-processing blocks include at least a first pre-processing block having an output connected to an input of a second processing block.

150. The method of claim 131, wherein, The one or more pre-processing blocks include at least a first pre-processing block, a second pre-processing block, and a third pre-processing block configured to combine an output of the first pre-processing block and an output of the second pre-processing block.

151. The method of claim 150, wherein, The third pre-processing block is a summing element.

152. The method of claim 151, further comprising providing, by the summing element, at least one of the plurality of pre-processing signals output by the one or more pre-processing blocks.

153. The method of claim 151, further comprising imposing a delay on an input or output of the first pre-processing block and / or the second pre-processing block prior to combining.

154. The method of claim 151, wherein, The input signal of the first pre-processing block and / or the second pre-processing block is a real-valued signal derived at least in part from a signal representing an amplitude of the transmit signal.

155. The method of claim 151, further comprising receiving a plurality of coefficients and applying the plurality of coefficients to the one or more pre-processing blocks.

156. The method of claim 155, further comprising applying at least one of the plurality of coefficients to the filter.

157. The method of claim 155, wherein, One or more of the plurality of coefficients is responsive to a state of the RF amplifier.

158. The method of claim 155, wherein, One or more of the plurality of coefficients is responsive to a configuration of a power management circuit of the RF transceiver system.

159. The method of claim 155, further comprising receiving, by a look-up table (LUT) of the one or more pre-processing blocks, the supply voltage level or a pre-processed version of the supply voltage level.

160. The method of claim 159, further comprising receiving one or more coefficients based on a behavior of a power management circuit of the RF transceiver system and applying the one or more coefficients to the LUT.

161. The method of claim 131, further comprising generating, by the non-linear combiner, at least one cross-term basis function by combining the transmit signal with another signal.

162. The method of claim 161, wherein, The other signal is one of the plurality of pre-processed signals.

163. The method of claim 131, further comprising generating, by the non-linear combiner, at least one basis function by exponentiating a signal.

164. The method of claim 163, wherein, The signal is one of the plurality of pre-processed signals.

165. A digital pre-distorter (DPD) for a radio frequency (RF) transceiver system having an RF amplifier, comprising: means for receiving a plurality of input signals and providing a plurality of pre-processed signals, wherein: the plurality of input signals includes at least a transmit signal corresponding to a signal expected to be transmitted or a modified version of the signal and a control signal corresponding to a signal for controlling a supply voltage level of the RF amplifier or a transformed version of the signal for controlling a supply voltage level of the RF amplifier, the plurality of pre-processed signals includes at least a first pre-processed signal and a second pre-processed signal, the second pre-processed signal being derived at least in part from the control signal, and means for combining the pre-processed signals with the transmit signal to provide a pre-distorted version of the transmit signal for transmission via the RF amplifier.

166. The DPD of claim 165, wherein: the first pre-processed signal is derived at least in part from a signal representing an amplitude of the transmit signal, and the second pre-processed signal is derived at least in part from a signal representing a phase of the transmit signal.

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