Ternary logic four-state gate circuit

Abstract

The application provides a ternary logic four-state gate circuit. The ternary logic four-state gate circuit comprises an output module and a control module, the output module comprises a first resistor and a second resistor connected in series, a first switch component arranged between the first resistor and a power supply voltage, and a second switch component arranged between the second resistor and the ground, and the control module generates control signals of the first switch component and the second switch component according to a ternary input signal and a ternary enable signal, so that the same logic value as the ternary input signal is obtained at the circuit output end when the logic value of the ternary enable signal is 2, and the first switch component and the second switch component are disconnected when the logic value of the ternary enable signal is 0 or 1, so that a high resistance state is formed at the circuit output end, that is, the ternary input four-state output is realized, which is helpful to improve the system integration and information transmission efficiency.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a ternary logic four-state gate circuit. Background Technology

[0002] As the scale of digital integrated circuits continues to expand and semiconductor processes approach their physical limits, traditional CMOS integrated circuit architectures based on binary logic face challenges in improving performance.

[0003] Multivalued logic uses three or more states to represent and process data, which can improve information density and expressive power, and is an important technological direction for expanding information processing capabilities. Taking ternary logic as an example, compared with traditional binary logic, where two input signals can only represent four different cases in binary logic, ternary logic can represent nine different cases, significantly improving the information transmission capability of the circuit. It can achieve lower interconnection costs, higher information density, and stronger information processing and transmission capabilities, and can be applied to database systems, digital circuits and computer hardware, as well as artificial intelligence and other fields.

[0004] Current research on ternary logic mainly focuses on the design of basic gate circuits, i.e. the implementation of ternary signals. However, the functional construction of ternary logic (such as solving the selection and isolation of devices in a bus structure) is still incomplete, which is not conducive to improving system integration and information transmission efficiency. Summary of the Invention

[0005] This application provides a ternary logic four-state gate circuit, which can use an enable signal to output the logic value of a ternary input signal or output a high-impedance state, thereby realizing ternary input four-state output, which helps to improve system integration and information transmission efficiency.

[0006] The ternary logic four-state gate circuit of this application includes an output module and a control module. The output module includes a first resistor and a second resistor connected in series, a first switching component disposed between the first resistor and the power supply voltage, and a second switching component disposed between the second resistor and ground. The connection point of the first resistor and the second resistor is the circuit output terminal. The control module is configured to receive a ternary input signal and a ternary enable signal and output a first control signal for controlling the on / off state of the first switching component and a second control signal for controlling the on / off state of the second switching component. Furthermore, the logic value of the first control signal is equivalent to the maximum value of the first logic value formed by the ternary enable signal through a first ternary inversion transformation and the second logic value formed by the ternary input signal through a second ternary inversion transformation. The logic value of the second control signal is equivalent to the logic value formed by the maximum value of the three-valued input signal and the first logic value through the second three-valued inverse transformation; wherein, the first three-valued inverse transformation converts logic values ​​0, 1, and 2 into logic values ​​2, 2, and 0 respectively, and the second three-valued inverse transformation converts logic values ​​0, 1, and 2 into logic values ​​2, 1, and 0 respectively, the first switch component is turned on when the logic value of the first control signal is 0 and 1 and turned off when it is 2, and the second switch component is turned on when the logic value of the second control signal is 1 and 2 and turned off when it is 0.

[0007] Optionally, the control module includes a first processing unit, the first processing unit comprising:

[0008] The first inverter has the ternary enable signal connected to its input terminal and is configured to perform the first ternary inversion transformation on the ternary enable signal.

[0009] The second inverter is connected to the three-valued input signal at its input terminal and is configured to perform the second three-valued inversion transformation on the three-valued input signal;

[0010] A first NOR gate, whose two inputs are respectively connected to the outputs of the first inverter and the second inverter, is configured to perform a ternary logic NOR operation on the input signals; and

[0011] The third inverter has its input connected to the output of the first NOR gate and is configured to perform the second ternary inversion transformation on the input signal to form the first control signal.

[0012] Optionally, the first inverter includes a first transistor and a third resistor; wherein the source of the first transistor is connected to the power supply voltage, the drain is grounded through the third resistor, the gate is connected to the three-value enable signal, and the connection point of the first transistor and the third resistor is the output terminal of the first inverter.

[0013] Optionally, the second inverter includes a second transistor, a fourth resistor, a fifth resistor, and a third transistor connected in series. The source of the second transistor is connected to the power supply voltage, and the source of the third transistor is grounded. Furthermore, the gates of the second transistor and the third transistor are both connected to the three-valued input signal, and the connection point of the fourth resistor and the fifth resistor is the output terminal of the second inverter.

[0014] Optionally, the first NOR gate includes a fourth transistor, a fifth transistor, a sixth resistor, and a seventh resistor connected in series, and also includes a sixth transistor and a seventh transistor connected in parallel. The source of the fourth transistor is connected to the power supply voltage, and the drains of the sixth and seventh transistors are connected to the seventh resistor, with their sources grounded. Furthermore, the gates of the fourth and seventh transistors are both connected to the output of the first inverter, the gates of the fifth and sixth transistors are both connected to the output of the second inverter, and the connection point of the sixth and seventh resistors is the output of the first NOR gate.

[0015] Optionally, the third inverter includes an eighth transistor, an eighth resistor, a ninth resistor, and a ninth transistor connected in series. The source of the eighth transistor is connected to the power supply voltage, and the source of the ninth transistor is grounded. The gates of the eighth transistor and the ninth transistor are the input terminals of the third inverter, and the connection point of the eighth resistor and the ninth resistor is the output terminal of the third inverter.

[0016] Optionally, the first switching component, the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the eighth transistor are all PMOS transistors with the same threshold voltage; and / or, the second switching component, the third transistor, the sixth transistor, the seventh transistor, and the ninth transistor are all NMOS transistors with the same threshold voltage.

[0017] Optionally, the control module includes a second processing unit, the second processing unit comprising:

[0018] The second NOR gate has two input terminals connected to the output terminal of the first inverter and the three-valued input signal, respectively, and is configured to perform a three-valued logic NOR operation on the input signal to form the second control signal.

[0019] Optionally, the second NOR gate includes a tenth transistor, an eleventh transistor, a tenth resistor, and an eleventh resistor connected in series, and also includes a twelfth transistor and a thirteenth transistor connected in parallel. The source of the tenth transistor is connected to the power supply voltage, and the drains of the twelfth and thirteenth transistors are connected to the eleventh resistor and their sources are grounded. Furthermore, the gates of the tenth and thirteenth transistors are both connected to the output of the first inverter, and the gates of the eleventh and twelfth transistors are both connected to the three-valued input signal. The connection point of the tenth and eleventh resistors is the output of the second NOR gate.

[0020] Optionally, the first switching component, the tenth transistor, and the eleventh transistor are all PMOS transistors with the same threshold voltage; and / or, the second switching component, the twelfth transistor, and the thirteenth transistor are all NMOS transistors with the same threshold voltage.

[0021] In the ternary logic four-state gate circuit provided in this application, the control module is configured to receive a ternary input signal and a ternary enable signal, and output a first control signal for controlling the on / off state of the first switching component and a second control signal for controlling the on / off state of the second switching component. The first control signal and the second control signal enable the circuit to output the same logic value as the ternary input signal when the logic value of the ternary enable signal is 2. When the logic value of the ternary enable signal is 0 or 1, the first and second switching components are disconnected, thereby forming a high-impedance state at the circuit output. This achieves ternary input and four-state output, which helps improve system integration and information transmission efficiency. Furthermore, the ternary logic four-state gate circuit can be fabricated using CMOS technology and does not require multiple transistors with different threshold voltages to achieve different output states. The threshold voltage of each transistor is uniform, which helps simplify the circuit process and reduce manufacturing costs. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a three-valued logic four-state gate circuit according to an embodiment of this application.

[0023] Figure 2 This is a logic diagram of a three-valued logic four-state gate circuit according to an embodiment of this application.

[0024] Figure 3 This is a circuit diagram of a ternary logic four-state gate circuit according to an embodiment of this application. Detailed Implementation

[0025] The following detailed description of the ternary logic four-state gate circuit of this application, in conjunction with the accompanying drawings and specific embodiments, provides further clarity. It should be understood that the accompanying drawings are in a very simplified form and use non-precise scales, intended only to facilitate clear explanation of the embodiments of this application. Terms such as "first," "second," etc., used in the specification are used to distinguish between similar elements and are not necessarily intended to describe a specific order or chronological sequence. It should be understood that these terms can be replaced where appropriate.

[0026] To achieve a ternary logic four-state output, the ternary logic four-state gate circuit in this embodiment has a resistor voltage divider structure disposed between the power supply and ground. A switching component is disposed between the resistor voltage divider structure and the power supply and ground respectively. By controlling the on / off state of the switching components, the connection between the resistor voltage divider structure and the power supply and ground is adjusted, thus forming four output states. Detailed explanation follows.

[0027] Reference Figure 1 According to one embodiment of this application, a ternary logic quad-state gate circuit includes an output module 10 and a control module 20. The output module 10 includes a first resistor R1 and a second resistor R2 connected in series, and a control module disposed between the first resistor R1 and the power supply voltage V. DD The first switching component Q1 and the second switching component Q2 are located between the second resistor R2 and ground (GND). The connection point of the first resistor R1 and the second resistor R2 is the circuit output terminal Y of the three-valued logic four-state gate circuit.

[0028] The first resistor R1 and the second resistor R2 are used to form a resistive voltage divider structure. Both the first resistor R1 and the second resistor R2 may include one or more resistive elements. In some embodiments, the voltage at the circuit output terminal Y when both the first switching component Q1 and the second switching component Q2 are turned on is the power supply voltage V. DD Half of the resistance of the first switching component Q1 is equal to the sum of the resistances of the first resistor R1 and the second resistor R2. In some embodiments, the on-resistances of the first switching component Q1 and the second switching component Q2 are very small and can be ignored when calculating the voltage divider. Furthermore, the resistances of the first resistor R1 and the second resistor R2 are set to be equal, for example, both equal to 100kΩ, so that the voltage at the circuit output terminal Y when both the first switching component Q1 and the second switching component Q2 are on is equal to the power supply voltage V. DD 1 / 2. In the ternary logic four-state gate circuit of this application embodiment, the logic states include logic values ​​0, 1, and 2, and each corresponds to a different voltage value, such as a voltage value of 0V (i.e., ground (GND)), V DD / 2 and V DDThese represent logic values ​​0, 1, and 2, respectively. The logic states in the ternary logic four-state gate circuit also include a high-impedance state, denoted by Z.

[0029] The control module 20 is configured to receive a three-valued input signal A and a three-valued enable signal EN, and output a first control signal V for controlling the on / off state of the first switching component Q1. G1 and a second control signal V for controlling the on / off state of the second switching assembly Q2. G2 The first switching component Q1 is activated by the first control signal V. G1 The logic values ​​are 0 and 1 (corresponding to voltage values ​​of 0V and V respectively). DD / 2) When the first control signal V is turned on, it is activated. G1 When the logic value is 2, it is disconnected; the second switch component Q2 is activated by the second control signal V. G2 The logic values ​​are 1 and 2 (corresponding to voltage values ​​V respectively). DD / 2 and V DD When the second control signal V is activated, it is turned on. G2 When the logic value is 0, the circuit is disconnected, and the settings of the first switching component Q1 and the second switching component Q2 satisfy this requirement. The first switching component Q1 and the second switching component Q2 may include at least one of the switching elements such as MOSFET, transistor, JFET, IGBT, and Darlington transistor.

[0030] like Figure 1 As shown, as an example, the first switching component Q1 uses a PMOS transistor, and the source of the PMOS transistor is connected to the power supply voltage V. DD Furthermore, the drain is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to one end of the second resistor R2. This PMOS transistor satisfies the condition of the first control signal V. G1 The threshold voltage at which the circuit is turned on when the logic value is 0 or 1 and turned off when the logic value is 2 is, for example, a threshold voltage of -0.3V; the second switching component Q2 uses an NMOS transistor with its drain connected to the other end of the second resistor R2 and its source grounded (GND). This NMOS transistor has a condition that satisfies the second control signal V G2 The threshold voltage is the voltage at which the circuit is turned on when the logic value is 1 or 2 and turned off when the logic value is 0, for example, a threshold voltage of 0.3V. It should be noted that the configuration of the first switching component Q1 and the second switching component Q2 is not limited to this. For example, in some other embodiments, at least one of the first switching component Q1 and the second switching component Q2 includes more than one transistor.

[0031] The first control signal V generated by the control module 20 G1 Second control signal V G2 The following conditions must be met: First control signal V G1The logic value is equivalent to the maximum value between the first logic value formed by the first ternary inversion transformation of the ternary enable signal EN and the second logic value formed by the second ternary inversion transformation of the ternary input signal A; the second control signal V G2 The logic value is equivalent to the logic value of the three-valued input signal A and the maximum value of the first logic value, which are then transformed by a second three-valued inverse transformation; wherein, the first three-valued inverse transformation converts logic values ​​0, 1, and 2 into logic values ​​2, 2, and 0 respectively, and the second three-valued inverse transformation converts logic values ​​0, 1, and 2 into logic values ​​2, 1, and 0 respectively. The control module 20 may include circuits capable of satisfying this condition.

[0032] Reference Figure 2 In some embodiments, the control module 20 includes a function for generating a first control signal V. G1 The first processing unit 21 may include a first inverter INV1, a second inverter INV2, a first NOR gate U1, and a third inverter INV3.

[0033] The input of the first inverter INV1 is connected to a ternary enable signal EN and configured to perform the aforementioned first ternary inversion transformation on the ternary enable signal EN, thereby outputting the aforementioned first logic value. The first inverter INV1 is, for example, a polarity-controlled ternary inverter (PTI). (See reference...) Figure 3 As an example, the first inverter INV1 includes a first transistor T1 and a third resistor R3; wherein the source of the first transistor T1 is connected to the power supply voltage V. DD The drain is grounded through the third resistor R3, and the gate is connected to the three-value enable signal EN. The connection point between the first transistor T1 and the third resistor R3 is the output terminal of the first inverter INV1.

[0034] The second inverter INV2 is connected to a ternary input signal A and configured to perform the aforementioned second ternary inversion transformation on the ternary input signal A, thereby outputting the aforementioned second logic value. The second inverter INV2 is, for example, a standard ternary inverter (STI). (See reference...) Figure 3 As an example, the second inverter INV2 includes a second transistor T2, a fourth resistor R4, a fifth resistor R5, and a third transistor T3 connected in series. The source of the second transistor T2 is connected to the power supply voltage V. DD The source of the third transistor T3 is grounded; and the gates of the second transistor T2 and the third transistor T3 are both connected to the three-value input signal A. The connection point of the fourth resistor R4 and the fifth resistor R5 is the output terminal of the second inverter INV2.

[0035] The two inputs of the first NOR gate U1 are connected to the outputs of the first inverter INV1 and the second inverter INV2, respectively, and are configured to perform a ternary NOR operation on the signals at these two inputs. The first NOR gate U1 is a ternary NOR gate (TNOR). The output of the ternary NOR operation is equivalent to the output of the result of the OR operation after the second ternary inversion transformation described above. That is, after the ternary NOR operation on two logic values ​​(such as the first logic value output by the first inverter INV1 and the second logic value output by the second inverter INV2), the output logic value is equivalent to the logic value formed by the maximum value of the two logic values ​​after the second ternary inversion transformation (converting logic values ​​0, 1, and 2 into logic values ​​2, 1, and 0, respectively).

[0036] Reference Figure 3 As an example, the first NOR gate U1 includes a fourth transistor T4, a fifth transistor T5, a sixth resistor R6, and a seventh resistor R7 connected in series, and also includes a sixth transistor T6 and a seventh transistor T7 connected in parallel. The source of the fourth transistor T4 is connected to the power supply voltage V. DD The drains of the sixth transistor T6 and the seventh transistor T7 are connected to the seventh resistor R7 and their sources are grounded; and the gates of the fourth transistor T4 and the seventh transistor T7 are both connected to the output of the first inverter INV1, the gates of the fifth transistor T5 and the sixth transistor T6 are both connected to the output of the second inverter INV2, and the connection point of the sixth resistor R6 and the seventh resistor R7 is the output of the first NOR gate U1.

[0037] The input of the third inverter INV3 is connected to the output of the first NOR gate U1 and configured to perform the aforementioned second ternary inversion transformation on its input signal to form the first control signal V. G1 The output of the third inverter INV3 is connected, for example, to the gate of the first switching assembly Q1. (See reference...) Figure 3 As an example, the third inverter INV3 includes an eighth transistor T8, an eighth resistor R8, a ninth resistor R9, and a ninth transistor T9 connected in series. The source of the eighth transistor T8 is connected to the power supply voltage V. DD The source of the ninth transistor T9 is grounded; the gates of the eighth transistor T8 and the ninth transistor T9 are the input terminals of the third inverter INV3, and the connection point of the eighth resistor R8 and the ninth resistor R9 is the output terminal of the third inverter INV3, which is used to output the first control signal V. G1 .

[0038] In some embodiments, the first switching component Q1, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are all PMOS transistors with the same threshold voltage, and / or the second switching component Q2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are all NMOS transistors with the same threshold voltage. Furthermore, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, and the ninth resistor R9 are, for example, equal.

[0039] Reference Figure 2 In some embodiments, the control module 20 includes a function for generating a second control signal V. G2 The second processing unit 22 may include a second NOR gate U2. The two input terminals of the second NOR gate U2 are respectively connected to the output terminal of the first inverter INV1 and the ternary input signal A, and are configured to perform a ternary logic NOR operation on the signals at the two input terminals to form a second control signal V. G2 The logic value output by the second NOR gate U2 is equivalent to the logic value formed by the maximum value of the first logic value output by the first inverter INV1 and the logic value of the three-value input signal A after the above-mentioned second three-value inversion transformation.

[0040] Reference Figure 3 As an example, the second NOR gate U2 includes a tenth transistor T connected in series. 10 11th transistor T 11 The tenth resistor R 10 And the eleventh resistor R 11 It also includes a twelfth transistor T connected in parallel. 12 and the thirteenth transistor T 13 The tenth transistor T 10 The source is connected to the power supply voltage V. DD Twelfth transistor T 12 and the thirteenth transistor T 13 The drain is connected to the eleventh resistor R. 11 And the source is grounded; and, the tenth transistor T 10 The gate of the thirteenth transistor T 13 The gates of all transistors are connected to the output of the first inverter INV1, and the eleventh transistor T... 11 The gate and the twelfth transistor T 12 The gates of all three resistors are connected to a three-value input signal A, and the tenth resistor R 10 and the eleventh resistor R 11 The connection point is the output terminal of the second NOR gate U2, which is used to output the second control signal V. G2 .

[0041] In some embodiments, the first switching component Q1 and the tenth transistor T 10 and the eleventh transistor T 11 All are PMOS transistors with the same threshold voltage, and / or, the second switching component Q2 and the twelfth transistor T 12 and the thirteenth transistor T 13 All are NMOS transistors with the same threshold voltage. Additionally, the first resistor R1, the second resistor R2, and the tenth resistor R... 10 And the eleventh resistor R 11 The resistance values ​​are, for example, equal.

[0042] Table 1 shows the truth table of the ternary logic four-state gate circuit of the present application embodiment. It can be seen that for different combinations of ternary input signal A and ternary enable signal EN, four logic states can be obtained at the circuit output terminal Y: logic value 0, 1, 2 and high impedance state (Z).

[0043] Table 1

[0044] EN A Y 0 0 Z 0 1 Z 0 2 Z 1 0 Z 1 1 Z 1 2 Z 2 0 0 2 1 1 2 2 2

[0045] Reference Figure 2 , Figure 3 As shown in Table 1, in some embodiments, the operation of the ternary logic quad-state gate circuit is as follows.

[0046] When the logic values ​​of the ternary enable signal EN and the ternary input signal A are both 0 (EN=0 and A=0), the output voltages of the first inverter INV1 and the second inverter INV2 are both the power supply voltage V. DD Corresponding to logic value 2, the first inverter INV1 performs the first three-value inversion transformation, and the second inverter INV2 performs the second three-value inversion transformation. After the two logic values ​​2 are input to the first NOR gate U1, the output terminal of the first NOR gate U1 is grounded (GND), corresponding to logic value 0; simultaneously, after the output signal of the first inverter INV1 and the three-value input signal A are input to the second NOR gate U2, the output terminal of the second NOR gate U2 is grounded (GND), corresponding to logic value 0. After the output signal of the first NOR gate U1 is input to the third inverter INV3, the output voltage of the third inverter INV3 is V. DD This corresponds to logic value 2, meaning the third inverter INV3 completes the second ternary inversion. At this time, both the first switch component Q1 and the second switch component Q2 are in the off state, and the circuit output terminal Y is in a high-impedance state.

[0047] When the logic value of the ternary enable signal EN is 0 and the logic value of the ternary input signal A is 1 (EN=0 and A=1), the output voltage of the first inverter INV1 is the power supply voltage V. DDThe voltage at the output of the second inverter INV2 is VDD / 2, corresponding to logic value 2, and the voltage at the output of the second inverter INV2 is VDD / 2, corresponding to logic value 1. Logic values ​​2 and 1 are input to the first NOR gate U1, causing its output to be grounded (GND), corresponding to logic value 0. Simultaneously, the output signal of the first inverter INV1 and the ternary input signal A are input to the second NOR gate U2, causing its output to be grounded (GND), corresponding to logic value 0. The output signal of the first NOR gate U1 is then processed by the third inverter INV3 to output VDD / 2. DD This corresponds to the logic value 2. At this time, both the first switch component Q1 and the second switch component Q2 are in the off state, and the circuit output terminal Y is in a high impedance state.

[0048] When the ternary enable signal EN=0 and the ternary input signal A=2, the output voltages of the first inverter INV1 and the second inverter INV2 are respectively the power supply voltage V. DD 0V and 0V (i.e., ground (GND)) correspond to logic values ​​2 and 0, respectively. Logic values ​​2 and 0 are input to the first NOR gate U1, causing its output to be grounded (GND), corresponding to logic value 0. Simultaneously, the output signal of the first inverter INV1 and the ternary input signal A are input to the second NOR gate U2, causing its output to be grounded (GND), corresponding to logic value 0. The output signal of the first NOR gate U1 is then processed by the third inverter INV3 to output V. DD This corresponds to the logic value 2. At this time, both the first switch component Q1 and the second switch component Q2 are in the off state, and the circuit output terminal Y is in a high impedance state.

[0049] When the ternary enable signal EN=1 and the ternary input signal A=0, the output voltages of the first inverter INV1 and the second inverter INV2 are both V. DD This corresponds to the logic value 2. After two logic values ​​of 2 are input to the first NOR gate U1, the output of the first NOR gate U1 is grounded (GND), corresponding to the logic value 0. Simultaneously, after the output signal of the first inverter INV1 and the three-valued input signal A are input to the second NOR gate U2, the output of the second NOR gate U2 is grounded (GND), corresponding to the logic value 0. The output signal of the first NOR gate U1 is then processed by the third inverter INV3 to output V. DD This corresponds to the logic value 2. At this time, both the first switch component Q1 and the second switch component Q2 are in the off state, and the circuit output terminal Y is in a high impedance state.

[0050] When the ternary enable signal EN=1 and the ternary input signal A=1, the output voltages of the first inverter INV1 and the second inverter INV2 are respectively V DD and V DD / 2 corresponds to logic values ​​2 and 1, respectively. After logic values ​​2 and 1 are input to the first NOR gate U1, its output is grounded (GND). Simultaneously, the output signal of the first inverter INV1 and the ternary input signal A are input to the second NOR gate U2, whose output is also grounded (GND), corresponding to logic value 0. The output signal of the first NOR gate U1 is then processed by the third inverter INV3 to output V. DD This corresponds to the logic value 2. At this time, both the first switch component Q1 and the second switch component Q2 are in the off state, and the circuit output terminal Y is in a high impedance state.

[0051] When the ternary enable signal EN=1 and the ternary input signal A=2, the output voltages of the first inverter INV1 and the second inverter INV2 are respectively V DD 0V and 0V (i.e., ground (GND)) correspond to logic values ​​2 and 0, respectively. After logic values ​​2 and 0 are input to the first NOR gate U1, the output of the first NOR gate U1 is grounded (GND). Simultaneously, the output signal of the first inverter INV1 and the ternary input signal A are input to the second NOR gate U2, and the output of the second NOR gate U2 is grounded (GND), corresponding to the logic value 0. The output signal of the first NOR gate U1 is then processed by the third inverter INV3 to output V. DD This corresponds to the logic value 2. At this time, both the first switch component Q1 and the second switch component Q2 are in the off state, and the circuit output terminal Y is in a high impedance state.

[0052] When the ternary enable signal EN=2 and the ternary input signal A=0, the output voltages of the first inverter INV1 and the second inverter INV2 are 0V (i.e., ground (GND)) and V, respectively. DD These correspond to logic values ​​0 and 2, respectively. After logic values ​​0 and 2 are input to the first NOR gate U1, the output of the first NOR gate U1 is grounded (GND). Simultaneously, after the output signal of the first inverter INV1 and the ternary input signal A are input to the second NOR gate U2, the output voltage of the second NOR gate U2 is V. DD This corresponds to the logic value 2. The output signal of the first NOR gate U1 is then processed by the third inverter INV3 to output V. DD This corresponds to the logic value 2. At this time, the first switch component Q1 is in the off state, the second switch component Q2 is in the on state, and the circuit output terminal Y is grounded (GND), corresponding to the logic value 0.

[0053] When the ternary enable signal EN=2 and the ternary input signal A=1, the output voltages of the first inverter INV1 and the second inverter INV2 are 0V (i.e., ground (GND)) and V, respectively. DD / 2 corresponds to logic values ​​0 and 1, respectively. After logic values ​​0 and 1 are input to the first NOR gate U1, the output voltage of the first NOR gate U1 is V.DD / 2 corresponds to the logic value 1; simultaneously, after the output signal of the first inverter INV1 and the ternary input signal A are input to the second NOR gate U2, the output voltage of the second NOR gate U2 is V. DD / 2 corresponds to the logic value 1. The output signal of the first NOR gate U1 is then processed by the third inverter INV3 to output V. DD / 2 corresponds to the logic value 1. At this time, both the first switch component Q1 and the second switch component Q2 are in the ON state. Through the voltage divider between the first resistor R1 and the second resistor R2, the voltage at the circuit output terminal Y is V. DD / 2 corresponds to the logical value 1.

[0054] When the ternary enable signal EN=2 and the ternary input signal A=2, the output voltages of both the first inverter INV1 and the second inverter INV2 are 0V (i.e., grounded (GND)), corresponding to the logic value 0. After two logic values ​​of 0 are input to the first NOR gate U1, the output voltage of the first NOR gate U1 is V. DD This corresponds to a logic value of 2. Simultaneously, after the output signal of the first inverter INV1 and the ternary input signal A are input to the second NOR gate U2, the output voltage of the second NOR gate U2 is 0V (i.e., grounded (GND)), corresponding to a logic value of 0. The output signal of the first NOR gate U1 is then processed by the third inverter INV3 and outputs 0V (i.e., grounded (GND)), corresponding to a logic value of 0. At this time, the first switching component Q1 is in the on state, the second switching component Q2 is in the off state, and the voltage at the circuit output terminal Y is V. DD This corresponds to the logical value 2.

[0055] The ternary logic four-state gate circuits described in the above embodiments can be used in systems corresponding to ternary logic, such as microcontrollers, FPGA GPIOs, or dedicated bus interfaces, to realize multi-device bus sharing (i.e., bus arbitration) and solve the selection and isolation problems of devices on the bus. For example, it can be configured to allow one device to drive the bus by outputting a logic value of 0, 1, or 2 at any time, while other devices disconnect from the bus by outputting a high-impedance state (Z); or, it can be configured to allow one device to drive the bus by outputting a logic value of 0 or 1 at any time, while other devices disconnect from the bus by outputting a high-impedance state (Z), and the master device can be used for wake-up or addressing by outputting a logic value of 2. However, it is not limited to this, and the ternary logic four-state gate circuits can also be applied to other occasions as needed.

[0056] The ternary logic quad-state gate circuit described in the above embodiments can obtain a logic value corresponding to the ternary input signal A at the circuit output terminal Y when the ternary enable signal EN is a logic value of 2. When the ternary enable signal EN is a logic value of 0 or 1, the first switching component and the second switching component are disconnected, thereby obtaining a high-impedance state at the circuit output terminal Y, thus realizing a ternary input quad-state output. Compared with a ternary input tri-state output, this helps to improve system integration. The quad-state output also helps to improve the transmission bandwidth within and between chips, thereby improving information transmission efficiency. In addition, the ternary logic quad-state gate circuit can be formed using CMOS technology and does not require multiple transistors with different threshold voltages to achieve different output states. The threshold voltage of each transistor is uniform, which helps to simplify the circuit process and reduce the circuit manufacturing cost.

[0057] The above description is merely a description of preferred embodiments of this application and is not intended to limit the scope of the claims of this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A ternary logic four-state gate circuit, characterized in that, include: The output module includes a first resistor and a second resistor connected in series, a first switching component disposed between the first resistor and the power supply voltage, and a second switching component disposed between the second resistor and ground. The connection point of the first resistor and the second resistor is the circuit output terminal. as well as The control module is configured to receive a ternary input signal and a ternary enable signal, and output a first control signal for controlling the on / off state of the first switch component and a second control signal for controlling the on / off state of the second switch component. The logic value of the first control signal is equivalent to the maximum value of the first logic value formed by the ternary enable signal through a first ternary inverse transformation and the second logic value formed by the ternary input signal through a second ternary inverse transformation. The logic value of the second control signal is equivalent to the logic value formed by the maximum value of the ternary input signal and the first logic value through a second ternary inverse transformation. Specifically, the first ternary inverting transformer converts logic values ​​0, 1, and 2 into logic values ​​2, 2, and 0, respectively; the second ternary inverting transformer converts logic values ​​0, 1, and 2 into logic values ​​2, 1, and 0, respectively; the first switching component is turned on when the logic value of the first control signal is 0 or 1, and turned off when it is 2; the second switching component is turned on when the logic value of the second control signal is 1 or 2, and turned off when it is 0; when the ternary enable signal is logic value 2, the circuit output terminal obtains the same logic value as the ternary input signal; when the ternary enable signal is logic value 0 or 1, either the first or second switching component is turned off, and the circuit output terminal is in a high-impedance state.

2. The ternary logic four-state gate circuit as described in claim 1, characterized in that, The control module includes a first processing unit, the first processing unit comprising: The first inverter has the ternary enable signal connected to its input terminal and is configured to perform the first ternary inversion transformation on the ternary enable signal. The second inverter is connected to the three-valued input signal at its input terminal and is configured to perform the second three-valued inversion transformation on the three-valued input signal; A first NOR gate, whose two inputs are respectively connected to the outputs of the first inverter and the second inverter, is configured to perform a ternary logic NOR operation on the signals at the two inputs; and The third inverter has its input connected to the output of the first NOR gate and is configured to perform the second ternary inversion transformation on the input signal to form the first control signal.

3. The ternary logic four-state gate circuit as described in claim 2, characterized in that, The first inverter includes a first transistor and a third resistor; wherein the source of the first transistor is connected to the power supply voltage, the drain is grounded through the third resistor, the gate is connected to the three-value enable signal, and the connection point of the first transistor and the third resistor is the output terminal of the first inverter.

4. The ternary logic four-state gate circuit as described in claim 3, characterized in that, The second inverter includes a second transistor, a fourth resistor, a fifth resistor, and a third transistor connected in series. The source of the second transistor is connected to the power supply voltage, and the source of the third transistor is grounded. Furthermore, the gates of the second transistor and the third transistor are both connected to the three-value input signal. The connection point of the fourth resistor and the fifth resistor is the output terminal of the second inverter.

5. The ternary logic four-state gate circuit as described in claim 4, characterized in that, The first NOR gate includes a fourth transistor, a fifth transistor, a sixth resistor, and a seventh resistor connected in series, and also includes a sixth transistor and a seventh transistor connected in parallel. The source of the fourth transistor is connected to the power supply voltage, and the drains of the sixth and seventh transistors are connected to the seventh resistor, with their sources grounded. Furthermore, the gates of the fourth and seventh transistors are both connected to the output of the first inverter, the gates of the fifth and sixth transistors are both connected to the output of the second inverter, and the connection point of the sixth and seventh resistors is the output of the first NOR gate.

6. The ternary logic four-state gate circuit as described in claim 5, characterized in that, The third inverter includes an eighth transistor, an eighth resistor, a ninth resistor, and a ninth transistor connected in series. The source of the eighth transistor is connected to the power supply voltage, and the source of the ninth transistor is grounded. The gates of the eighth transistor and the ninth transistor are the input terminals of the third inverter, and the connection point of the eighth resistor and the ninth resistor is the output terminal of the third inverter.

7. The ternary logic four-state gate circuit as described in claim 6, characterized in that, The first switching assembly, the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the eighth transistor are all PMOS transistors with the same threshold voltage; and / or, the second switching assembly, the third transistor, the sixth transistor, the seventh transistor, and the ninth transistor are all NMOS transistors with the same threshold voltage.

8. The ternary logic four-state gate circuit as described in claim 2, characterized in that, The control module includes a second processing unit, the second processing unit comprising: The second NOR gate has two input terminals connected to the output terminal of the first inverter and the three-valued input signal, respectively, and is configured to perform a three-valued logic NOR operation on the signals at the two input terminals to form the second control signal.

9. The ternary logic four-state gate circuit as described in claim 8, characterized in that, The second NOR gate includes a tenth transistor, an eleventh transistor, a tenth resistor, and an eleventh resistor connected in series, and a twelfth transistor and a thirteenth transistor connected in parallel. The source of the tenth transistor is connected to the power supply voltage, and the drains of the twelfth and thirteenth transistors are connected to the eleventh resistor, with their sources grounded. Furthermore, the gates of the tenth and thirteenth transistors are both connected to the output of the first inverter, and the gates of the eleventh and twelfth transistors are both connected to the three-valued input signal. The connection point of the tenth and eleventh resistors is the output of the second NOR gate.

10. The ternary logic four-state gate circuit as described in claim 9, characterized in that, The first switching component, the tenth transistor, and the eleventh transistor are all PMOS transistors with the same threshold voltage; and / or, the second switching component, the twelfth transistor, and the thirteenth transistor are all NMOS transistors with the same threshold voltage.

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