PWM wave optimization method and system based on VIENNA rectifier single-cycle control

Abstract

The invention provides a PWM wave optimization method and system based on VIENNA rectifier single-period control. The PWM wave optimization method comprises the steps that three-phase input current is sampled; determining the position of the corresponding PWM wave high level in the switching period according to the current direction of each phase; the method specifically comprises the following steps: for each PWM output channel, according to a phase current symbol associated with the PWM output channel, selecting to place a high level at two ends or in the middle of a switching period; and based on the determined PWM high level position and the calculated duty ratio, generating and outputting a PWM driving signal used for controlling a VIENNA rectifier switch tube. According to the method, PWM generation logic is redesigned, a non-optimal voltage vector combination used in traditional synthesis is abandoned, and three vectors (namely vectors corresponding to three vertexes of a small triangle where a target vector is located) closest to the target voltage vector are adopted for synthesis; according to the optimization, on the premise that the switching frequency is not increased and extra hardware cost is not increased, output current harmonics are remarkably reduced.

Description

A PWM waveform optimization method and system based on single-cycle control of VIENNA rectifier Technical Field

[0001] This application belongs to the field of power electronic conversion and control technology, and relates to a PWM wave optimization method and system based on single-cycle control of VIENNA rectifier. Background Technology

[0002] VIENNA rectifiers, as a three-phase three-level power factor correction topology with advantages such as high power factor and low current harmonics, have been widely used in industrial power supplies, new energy power generation systems, and charging piles. One of its core control objectives is to achieve low harmonics and high power factor operation of the grid-side current.

[0003] In traditional single-cycle control methods, a seven-segment PWM (Pulse Width Modulation) modulation strategy is typically employed. This involves synthesizing the target voltage vector within one carrier cycle using a symmetrically arranged sequence of switches. Taking Figure 3 as an example, when the desired output voltage vector is Vg, the traditional method uses four voltage vectors (including a zero vector 111) for synthesis. Since the zero vector 111 is far from the target voltage vector Vg, its participation in the synthesis leads to increased instantaneous fluctuations in the output voltage, which in turn increases the switching ripple of the output current, degrading the system's harmonic performance. Similarly, in another operating state shown in Figure 6, the traditional method uses vectors 000, 010, 110, and 111 (where 111 is the zero vector) to synthesize Vh, and suffers from similar problems.

[0004] In existing technologies, methods such as adding filters, increasing switching frequency, or optimizing modulation strategies are commonly used to reduce harmonics. However, adding filters increases system cost and size, while increasing switching frequency increases switching losses and affects system efficiency. Moreover, simulations and experiments show that traditional single-cycle control methods, under typical operating conditions, have high harmonic content in the output current, affecting overall system energy efficiency and causing harmonic pollution to the power grid.

[0005] Therefore, how to effectively reduce output current harmonics under the existing single-cycle control framework by optimizing the PWM generation mechanism without increasing the switching frequency or adding extra hardware costs has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] This application provides a PWM waveform optimization method and system based on VIENNA rectifier single-cycle control, which solves the technical problems in traditional single-cycle control, such as large output current harmonics, reduced system energy efficiency, and aggravated grid harmonic pollution caused by the use of non-optimal voltage vectors (especially long-distance zero vectors) to synthesize the target voltage vector.

[0007] In a first aspect, this application provides a PWM wave optimization method based on single-cycle control of a VIENNA rectifier. The method includes: acquiring three-phase input current; determining the direction of the three-phase input current based on the three-phase input current; determining the position of the corresponding PWM wave high level within the switching cycle according to the direction of the three-phase input current; including: for each PWM output channel, selecting to place the high level at the two ends or in the middle of the switching cycle according to the associated phase current sign; calculating the duty cycle based on the position of the PWM wave high level within the switching cycle; and generating a PWM drive signal for controlling the switching transistors of the VIENNA rectifier based on the position of the PWM wave high level within the switching cycle and the duty cycle.

[0008] This application achieves dynamic identification of the target voltage vector's position in the spatial vector diagram and synthesizes only the three closest voltage vectors, completely avoiding output voltage fluctuations caused by the introduction of distant zero vectors in traditional methods. This method minimizes errors at the source of synthesis, thereby significantly reducing the harmonic content of the input current (simulation shows a reduction of approximately 50.8%), effectively improving the system's power quality, overall energy efficiency, and grid compatibility, without requiring additional hardware or increased switching frequency.

[0009] In one implementation of the first aspect, determining the position of the corresponding PWM wave high level within the switching cycle based on the direction of the three-phase input current includes:

[0010] When the phase current associated with the PWM1 channel is greater than or equal to 0, the high level of the PWM1 waveform is configured at both ends of the switching cycle; when the phase current associated with the PWM1 channel is less than 0, the high level of the PWM1 waveform is configured in the middle of the switching cycle.

[0011] When the phase current associated with the PWM2 channel is greater than or equal to 0, the high level of the PWM2 waveform is configured at both ends of the switching cycle; when the phase current associated with the PWM2 channel is less than 0, the high level of the PWM2 waveform is configured in the middle of the switching cycle.

[0012] When the phase current associated with the PWM3 channel is greater than or equal to 0, the high level of the PWM3 waveform is configured at both ends of the switching cycle; when the phase current associated with the PWM3 channel is less than 0, the high level of the PWM3 waveform is configured in the middle of the switching cycle.

[0013] In one implementation of the first aspect, the method further includes: calculating the duty cycle of the three-phase PWM wave based on the output value of the voltage loop PI regulator and the current sampling value.

[0014] In one implementation of the first aspect, calculating the duty cycle based on the position of the PWM wave high level within the switching cycle includes: acquiring an input current signal; obtaining a bus voltage signal; performing voltage closed-loop calculation based on the bus voltage signal to obtain a voltage adjustment command; the voltage closed-loop calculation includes comparing the bus voltage signal with a target voltage and generating the voltage adjustment command through a regulator; calculating the duty cycle based on the voltage adjustment command and generating a PWM control signal.

[0015] In one implementation of the first aspect, the switching vector sequence corresponding to the PWM drive signal has a seven-segment symmetrical structure within a single switching cycle and is composed of four different basic voltage vectors.

[0016] In one implementation of the first aspect, the selection of the four basic voltage vectors is such that the output voltage synthesis vector is synthesized from the vectors of the three nearest vertices in the spatial vector diagram in which it resides.

[0017] In one implementation of the first aspect, the switching cycle corresponds to a switching frequency of 50kHz, and a double-sampling double-update control mode is adopted within one PWM cycle.

[0018] Secondly, this application provides a PWM waveform optimization system based on single-cycle control of a VIENNA rectifier, comprising:

[0019] The data acquisition module is used to acquire the three-phase input current and determine the direction of the three-phase input current based on the three-phase input current.

[0020] The position information determination module is used to determine the position of the corresponding PWM wave high level within the switching cycle based on the direction of the three-phase input current; including: for each PWM output channel, selecting to place the high level at the two ends or in the middle of the switching cycle according to the sign of its associated phase current;

[0021] The duty cycle calculation module is used to calculate the duty cycle based on the position of the PWM wave high level within the switching cycle.

[0022] The drive signal output module is used to generate a PWM drive signal for controlling the switching transistors of the VIENNA rectifier, based on the position of the PWM wave high level within the switching cycle and the duty cycle.

[0023] In this application, the system can implement the above-mentioned optimization algorithm in a digital controller (such as a DSP or FPGA) to achieve optimal vector selection and PWM wave generation in real time and with high accuracy. The system has a simple structure and is easy to integrate into existing control architectures. It is not only suitable for ideal power grid conditions, but its vector nearest neighbor selection principle also enables it to maintain excellent low harmonic performance under various operating conditions such as light load, heavy load, and power grid imbalance, demonstrating good robustness and engineering practicality.

[0024] Thirdly, this application provides a PWM waveform optimization device based on single-cycle control of a VIENNA rectifier, comprising: a current sampling circuit, a controller, and a drive circuit; wherein,

[0025] The current sampling circuit is used to collect the three-phase input current;

[0026] The controller is configured to: determine the direction of each phase based on the sampled current, determine the high-level position of the PWM, calculate the duty cycle, and generate an optimized PWM waveform;

[0027] The drive circuit is used to amplify the PWM signal generated by the controller to drive the power switching transistors of the VIENNA rectifier.

[0028] Fourthly, this application provides an electronic device, including: a processor and a memory; the memory is used to store a computer program; the processor is connected to the memory and is used to execute the computer program stored in the memory, so that the PWM wave optimization device based on VIENNA rectifier single-cycle control performs the PWM wave optimization method based on VIENNA rectifier single-cycle control.

[0029] As described above, the PWM waveform optimization method and system based on single-cycle control of the VIENNA rectifier described in this application have the following beneficial effects:

[0030] (1) The PWM waveform optimization method based on single-cycle control of VIENNA rectifier provided in this application can dynamically identify the position of the target voltage vector in the spatial vector diagram and select only the three closest voltage vectors for synthesis, thus completely avoiding the output voltage fluctuation caused by the introduction of long-distance zero vectors in the traditional method. The method of this application can minimize the error from the source of synthesis, thereby significantly reducing the harmonic content of the input current (as shown in the simulation, it can be reduced by about 50.8%), effectively improving the power quality, overall energy efficiency and compatibility with the power grid of the system, and without the need for additional hardware or increasing the switching frequency.

[0031] (2) The PWM wave optimization system based on single-cycle control of VIENNA rectifier provided in this application can complete the optimal vector selection and PWM wave generation in real time and accurately by implementing the above optimization algorithm in a digital controller (such as DSP or FPGA). The system provided in this application has a simple structure and is easy to integrate into the existing control architecture. It is not only suitable for ideal power grid conditions, but its vector nearest neighbor selection principle also enables it to maintain excellent low harmonic performance under various operating conditions such as light load, heavy load and power grid imbalance, and has good robustness and engineering applicability. Attached Figure Description

[0032] Figure 1 shows a schematic diagram of the hardware structure application scenario corresponding to the PWM wave optimization method based on single-cycle control of VIENNA rectifier described in the embodiments of this application.

[0033] Figure 2 shows a schematic diagram of the overall process of the PWM wave optimization method based on single-cycle control of VIENNA rectifier described in the embodiments of this application.

[0034] Figure 3 shows a schematic flowchart of the optimization method of the PWM wave optimization method based on single-cycle control of VIENNA rectifier described in the embodiment of this application.

[0035] Figure 4A shows a schematic diagram of the VIENNA main circuit structure of the PWM wave optimization method based on single-cycle control of the VIENNA rectifier described in the embodiment of this application.

[0036] Figure 4B shows a schematic diagram of the first type of PWM wave generation under normal conditions.

[0037] Figure 4C shows a schematic diagram of the voltage vector corresponding to the generation of the first type of PWM wave under normal conditions.

[0038] Figure 4D shows a schematic diagram of the output voltage synthesis vector corresponding to Figure 4C.

[0039] Figure 5A shows a schematic diagram of the output voltage vector generated by the PWM wave in the second case under normal conditions.

[0040] Figure 5B shows a schematic diagram of the output voltage synthesis vector corresponding to Figure 5A.

[0041] Figure 6 shows a schematic diagram of placing the high level of the PWM wave with a current greater than zero at both ends of the triangular carrier in the PWM wave optimization method based on single-cycle control of VIENNA rectifier according to the embodiment of this application.

[0042] Figure 7A shows a schematic diagram of the output PWM switching vector of the PWM wave optimization method based on single-cycle control of VIENNA rectifier described in the embodiments of this application.

[0043] Figure 7B shows a schematic diagram of the modified output voltage synthesis vector corresponding to Figure 7A.

[0044] Figure 8A shows a schematic diagram of the modified output voltage vector of PWM wave generation in the second case of the PWM wave optimization method based on VIENNA rectifier single-cycle control described in the embodiments of this application.

[0045] Figure 8B shows a schematic diagram of the modified output voltage synthesis vector corresponding to Figure 8A.

[0046] Figure 9 shows a schematic diagram of the experimental simulation results of the PWM wave optimization method based on single-cycle control of VIENNA rectifier described in the embodiments of this application.

[0047] Figure 10 shows a schematic diagram of the structural principle of the PWM wave optimization system based on single-cycle control of VIENNA rectifier according to an embodiment of this application.

[0048] Figure 11 shows a schematic diagram of the PWM wave optimization device based on single-cycle control of VIENNA rectifier according to an embodiment of this application.

[0049] Figure 12 shows a schematic diagram of the structure of the electronic terminal described in an embodiment of this application.

[0050] Component designation explanation

[0051] 1. DSP-controlled VIENNA three-phase rectifier 11 Main circuit 12 Sampling circuit 13 Control unit 14 PWM drive unit 15 Load 21 Data acquisition module 22 Position information determination module 23 Duty cycle calculation module 24 Drive signal output module 31 Current sampling circuit 32 Controller 33 Drive circuit 40 Electronic equipment 41 Processor 42 Memory Steps S1~S5 surface Detailed Implementation

[0052] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0053] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0054] This application provides a PWM waveform optimization method and system based on single-cycle control of a VIENNA rectifier, applicable to power electronic conversion hardware scenarios including but not limited to charging devices, industrial frequency converters, uninterruptible power supplies (UPS), photovoltaic grid-connected inverters, and power storage converters (PCS). The method provided in this application dynamically adjusts the PWM waveform output timing by detecting the direction of the three-phase input current, avoiding the use of long-distance zero vectors, thereby significantly reducing current harmonics and improving system efficiency and waveform quality. The following description uses a VIENNA three-phase rectifier controlled by a DSP (such as the TI TMS320F28335) as an example.

[0055] As shown in Figure 1, this embodiment provides a hardware application scenario for a DSP-controlled VIENNA three-phase rectifier. The specific hardware structure of the device mainly includes:

[0056] (1) Main circuit 11: adopts a three-phase VIENNA rectifier topology;

[0057] (2) Sampling circuit 12: used to collect input current and DC bus voltage;

[0058] (3) Control Unit 13: Implements single-cycle control algorithm and PWM optimization logic based on DSP / FPGA;

[0059] (4) PWM drive unit 14: used to generate optimized six drive signals;

[0060] (5) Load 15 and circuit interface.

[0061] Specifically, the main circuit 11 adopts a three-phase three-level VIENNA rectifier structure, including a three-phase input inductor, a rectifier bridge composed of six switching transistors and six diodes, a DC-side support capacitor, and a load. Its function is to convert the three-phase AC input power into a stable DC output under the drive of the control signal, and to reduce switching stress and output voltage harmonics through the three-level mechanism.

[0062] The sampling circuit 12 detects the three-phase input current and DC bus voltage in real time through Hall sensors or sampling resistors, and converts them into signals that can be processed by the control unit. This part provides necessary feedback information for the control system and is a prerequisite for realizing closed-loop control and PWM optimization.

[0063] The control unit 13 uses a DSP (Digital Signal Processor) or an FPGA (Field-Programmable Gate Array) as its core, runs a single-cycle control algorithm, and calculates the duty cycle of each phase in real time. Based on this, it dynamically adjusts the PWM waveform generation strategy according to the polarity of the input current, placing the high-level segment of the phase with positive current at both ends of the carrier cycle, thereby optimizing the voltage vector synthesis path and avoiding the use of zero vectors that are far from the target vector.

[0064] The PWM drive unit 14 can receive the PWM modulation signal output by the control unit, and after level conversion and isolation driving, generate six drive signals that meet the requirements of the power switching transistors. Its core function is to convert the optimized PWM logic into electrical signals that can actually drive the main circuit switching transistors, ensuring accurate and reliable switching action.

[0065] The load interface connects the DC output to the electrical equipment; the grid interface connects to the three-phase AC grid through filtering and protection circuits to ensure that the system meets power quality and safety standards when operating on the grid.

[0066] Specifically, the electrical connections and signal flow between the various hardware modules are as follows: the power grid interface is directly connected to the main circuit; the sampling circuit collects the current and voltage signals in the main circuit and inputs them to the control unit; the control unit generates a PWM signal based on the sampled signal and optimization algorithm and outputs it to the PWM drive module; the PWM drive module converts the control signal into a signal suitable for driving the switching transistor and controls the operation of the main circuit; the main circuit outputs DC power to supply the DC load.

[0067] During system operation, the sampling circuit collects the grid current and DC voltage in real time and sends them to the control unit. The control unit calculates the duty cycle of each phase based on a single-cycle control algorithm and reconstructs and optimizes the PWM waveform based on the current polarity judgment result, ensuring that the synthesized voltage vector consists only of the three closest effective vectors. The optimized PWM signal is amplified by the drive module and then controls the main circuit switching transistors to operate, ultimately achieving high-efficiency, low-harmonic rectification and conversion.

[0068] Therefore, the core of this application lies in adjusting the PWM wave generation method to place the high-level signal of the phase with a current greater than 0 at both ends of the triangular carrier wave, thereby optimizing the synthesis path of the output voltage vector, avoiding the use of a zero vector that is far from the target vector, significantly reducing the harmonic content of the output voltage and current, and improving the overall energy efficiency and power quality of the system. This system can be widely used in power electronic devices with high requirements for input current quality, such as new energy grid-connected devices, electric vehicle charging systems, industrial frequency converters, and data center power supply systems.

[0069] In summary, the core of the hardware application scenario of this application lies in adjusting the PWM wave output mode according to the phase current direction, avoiding the use of zero vectors (such as 111 or 000) that are far from the target voltage vector, and instead using the three voltage vectors closest to the target vector for synthesis, thereby significantly reducing the harmonic content of the output voltage and current, and improving system efficiency and waveform quality.

[0070] The PWM wave optimization method based on single-cycle control of VIENNA rectifier in this application will be described in detail below with reference to the accompanying drawings in the embodiments of this application.

[0071] Please refer to Figures 2 and 3, which respectively show the overall flowchart of the PWM wave optimization method based on single-cycle control of VIENNA rectifier described in the embodiments of this application and the optimization method flowchart of the PWM wave optimization method based on single-cycle control of VIENNA rectifier described in the embodiments of this application.

[0072] The PWM wave optimization method based on single-cycle control of the VIENNA rectifier described in this application can be implemented on a microcontroller with high-speed digital signal processing capabilities, such as a control system built around a DSP. The VIENNA rectifier main circuit topology shown in Figure 1 is the controlled object. An exemplary hardware platform parameter is as follows: three-phase input phase voltage is 220V / 50Hz, DC bus target voltage is 700V, AC side filter inductance is 500μH, and the switching frequency of the power switching transistors is set to 50kHz. The control system samples the three-phase input current (ia, ib, ic) through Hall current sensors and samples the DC bus voltage Vdc through a resistor divider and isolated operational amplifier circuit. The sampled signals are conditioned and then fed into the DSP's ADC module. The enhanced pulse width modulation (ePWM) module integrated within the DSP generates six drive signals, which are amplified by an isolated drive circuit and used to control the on / off states of the six switching transistors in the VIENNA rectifier. The software algorithm is written in the integrated development environment and downloaded to the DSP for execution.

[0073] As shown in Figures 2 and 3, this embodiment provides a PWM waveform optimization method based on single-cycle control of a VIENNA rectifier. The method includes the following steps:

[0074] S1, obtain the three-phase input current.

[0075] In one embodiment, a current sampling circuit (e.g., based on a Hall current sensor or a sampling resistor in conjunction with an isolation operational amplifier) ​​is used to acquire the current signals (i1, i2, i3) of the three-phase input ports (a, b, c phases) of the VIENNA rectifier in real time.

[0076] Meanwhile, the analog current signal is converted into a digital quantity by an ADC (Analog-to-Digital Converter) and input to a digital controller (such as the DSP chip TMS320F28335).

[0077] Specifically, a DSP or FPGA can be used as the core controller. For current sampling, a Hall effect current sensor (such as LEM LAH25-NP) is used to collect the three-phase input currents i1, i2, and i3, which are then sent to the DSP's ADC module after signal conditioning. For voltage sampling, a resistor divider network is used to sample the DC bus voltage and the capacitor midpoint voltage, which are then conditioned by an isolation operational amplifier before being sent to the ADC.

[0078] Therefore, in this application, the instantaneous values ​​of the three-phase input current are acquired in real time through a synchronous sampling circuit. The purpose is not only to provide feedback for the current loop control, but more importantly, to provide a direct basis for subsequent PWM optimization strategies based on current polarity. The sampled current signal is conditioned and then sent to the digital controller. The system dynamically determines the placement of the corresponding PWM wave high-level segment within the carrier cycle (at both ends or in the middle) based on the instantaneous polarity (positive or negative) of each phase current. This optimizes and reassembles the switching sequence, ensuring that the output voltage vector is synthesized from the three closest basic vectors, ultimately achieving the core effect of significantly reducing current harmonics.

[0079] S2, based on the three-phase input current, determine the direction of the three-phase input current.

[0080] In one embodiment, the digital controller compares the instantaneous sampled value of the three-phase input current with zero to determine the current direction.

[0081] Specifically, the preferred logic for determining the current direction is as follows: if the sampled value of a phase current is greater than zero (> 0), then the direction of the input current of that phase is determined to be positive (i.e., flowing from the grid to the rectifier); if it is less than or equal to zero (≤ 0), then the direction of the input current of that phase is determined to be negative (i.e., flowing from the rectifier to the grid or zero).

[0082] This judgment process is executed in each PWM control cycle (or in each ADC sampling interrupt), resulting in three Boolean flag bits.

[0083] Finally, the three-phase current direction identifiers obtained in this step are used as input conditions and passed to the PWM waveform generation module.

[0084] Based on the aforementioned identifier, the preset judgment logic is executed, namely: for the phase determined to have a positive current direction, the high-level segment of the PWM wave of its corresponding bridge arm is configured at both ends of the triangular carrier period (0 to PRD) (i.e., the beginning segment of the rising edge of the carrier and the end segment of the falling edge); for the phase with a negative current direction, the PWM wave is generated in a conventional manner based on the duty cycle and the comparison with the triangular carrier (the high level is usually located in the middle region of the carrier period).

[0085] It should be noted that the configuration operation here is achieved by setting the relevant registers of the PWM module of the digital controller (such as DSP) (such as comparison value, action limit, dead time control, etc.), and finally generating an optimized PWM drive signal sequence that acts on the VIENNA rectifier switching transistors (S1, S2, S3).

[0086] S3, determine the position of the corresponding PWM wave high level within the switching cycle according to the direction of the three-phase input current; including: for each PWM output channel, select to place the high level at the two ends or in the middle of the switching cycle according to the sign of its associated phase current.

[0087] In one embodiment, when the phase current associated with the PWM1 channel is greater than or equal to 0, the high level of the PWM1 waveform is configured at both ends of the switching cycle; when the phase current associated with the PWM1 channel is less than 0, the high level of the PWM1 waveform is configured in the middle of the switching cycle.

[0088] When the phase current associated with the PWM2 channel is greater than or equal to 0, the high level of the PWM2 waveform is configured at both ends of the switching cycle; when the phase current associated with the PWM2 channel is less than 0, the high level of the PWM2 waveform is configured in the middle of the switching cycle.

[0089] When the phase current associated with the PWM3 channel is greater than or equal to 0, the high level of the PWM3 waveform is configured at both ends of the switching cycle; when the phase current associated with the PWM3 channel is less than 0, the high level of the PWM3 waveform is configured in the middle of the switching cycle.

[0090] Furthermore, the switching cycle corresponds to a switching frequency of 50kHz, and a double-sampling double-update control mode is adopted within one PWM cycle.

[0091] Specifically, a mapping relationship between current direction and PWM channel modulation rules can be established. The modulation strategy of each phase arm (corresponding to one PWM output channel) is independently determined by the sign of its associated phase current. The rules are as follows: if the phase current sign is positive, the high-level pulse of this channel in this cycle (i.e., the effective voltage vector action period) is mainly placed at the beginning and / or end of the switching cycle, forming a pulse waveform similar to edge alignment; if the phase current sign is negative, the high-level pulse of this channel is placed in the middle stage of the switching cycle, forming a centrally symmetrical pulse waveform. The theoretical basis of this rule is that when the current direction is coordinated with the voltage change direction caused by the switching action, arranging the switching time at discontinuous positions helps to reduce switching losses.

[0092] Then, after determining the high-level position strategy for each channel, specific PWM duty cycles and timing parameters need to be generated based on the target voltage requirements. The controller calculates the required standard duty cycle D for each phase using algorithms such as vector control. For channels with positive current, the comparison value can be directly calculated based on D, and comparison matching is usually performed during the timer count increment from zero to generate leading or trailing edges. For channels with negative current, to achieve high-level centering, the modulation waveform needs to be considered complementary or offset. The actual value loaded into the PWM comparison register may be (1-D) or subject to corresponding mathematical transformations. At the same time, the PWM timer is configured in center-aligned counting mode to make the generated pulse symmetrical about the period center.

[0093] Next, the PWM module needs to be configured and dynamically controlled at the hardware level. The PWM timer in the microcontroller or FPGA needs to have its switching frequency (period value) pre-set. During operation, the system needs to adjust the output logic of each channel in real time according to the current sign updated in each cycle. This can be achieved by dynamically switching the PWM output polarity; or, while maintaining the center-aligned counting mode, indirectly controlling the pulse position by calculating and loading different sets of comparison values ​​for channels with different signs. Regardless of the method used, it is essential to ensure that a dead time is strictly inserted during the switching process to prevent shoot-through of the upper and lower transistors of the bridge arm.

[0094] Finally, the entire process needs to be encapsulated as a real-time closed-loop task. All the above steps—current sampling, sign determination, rule selection, duty cycle calculation, and PWM parameter updates—must be completed within each PWM switching cycle and take effect before the start of the next cycle. The system needs to efficiently coordinate the pulse position decisions of the three-phase channels to ensure the accuracy and smoothness of the overall output voltage. Simultaneously, the program should have explicit handling logic for boundary conditions such as current zero crossings to ensure a smooth transition during the modulation process.

[0095] S4, calculate the duty cycle based on the position of the PWM wave high level within the switching cycle.

[0096] In one embodiment, an input current signal is acquired; a bus voltage signal is obtained; a voltage closed-loop calculation is performed based on the bus voltage signal to obtain a voltage adjustment command; the voltage closed-loop calculation includes comparing the bus voltage signal with a target voltage and generating the voltage adjustment command through a regulator; the duty cycle is calculated based on the voltage adjustment command, and a PWM control signal is generated. Alternatively, the duty cycle of the three-phase PWM wave can be calculated based on the output value of the voltage loop PI regulator and the current sampling value.

[0097] Specifically, the following formula can be used for calculation:

[0098]

[0099] in, , , Represents the three-phase input current; Rs represents the equivalent resistance of the current sampling; u m This represents the output value of the voltage loop PI regulator; da, db, and dc represent the duty cycle data of the three-way switch PWM waves, respectively.

[0100] S5, based on the position of the PWM wave high level within the switching cycle and the duty cycle, generate a PWM drive signal for controlling the VIENNA rectifier switching transistor.

[0101] In one embodiment, the switching vector sequence corresponding to the PWM drive signal has a seven-segment symmetrical structure within a single switching cycle and is composed of four different basic voltage vectors. The selection of the four basic voltage vectors is such that the output voltage composite vector is synthesized from the vectors of the three nearest vertices in its spatial vector diagram.

[0102] Specifically, logic gating is performed based on the current direction to generate the final safe drive signal. Since the VIENNA rectifier's switching transistors are only allowed to conduct when the current direction meets specific conditions, the raw PWM signal generated in the preceding steps must undergo safety arbitration. The system uses the real-time current direction signal as an enable condition: only when the current direction of a phase matches the preset effective operating direction of that phase's switching transistor is the raw PWM pulse allowed to be output to the drive terminal of that switching transistor through the logic circuit; otherwise, the drive signal will be forcibly locked in the off state. This step is crucial for ensuring the safe operation of the topology and preventing invalid switching actions.

[0103] Next, the drive signal needs to be amplified and isolated, and a necessary dead time needs to be inserted. The drive signal power after logic gating is relatively small and insufficient to directly drive the switching transistors. It needs to be amplified and level-converted by a dedicated gate driver chip. At the same time, although the VIENNA rectifier has no bridge arm shoot-through risk, in order to suppress interference caused by parasitic parameters, it is sometimes necessary to configure an extremely short dead time or minimum pulse width limit in software or hardware to ensure the reliability and determinism of the power transistor operation, and finally generate a strong drive signal that can be sent to the gate of each switching transistor.

[0104] Finally, this process needs to be run in a closed loop at a fixed switching frequency. All the above steps constitute a complete calculation and control loop that must be completed within each PWM cycle. At the beginning of each cycle, the system samples the current and voltage, sequentially performs duty cycle calculation, modulation wave generation, carrier comparison, logic gating, and drive update, and outputs all drive signals before the start of the next cycle. At the same time, the DC side midpoint potential balance control algorithm also needs to be integrated into the modulation wave generation stage, which is achieved by injecting zero-sequence voltage components, thereby ensuring that the system maintains a stable balance of the two DC side capacitor voltages while optimizing switching behavior.

[0105] As mentioned above, this application breaks away from the fixed-mode PWM generation logic in traditional single-cycle control. By judging the polarity of the three-phase input current in real time, it dynamically and specifically adjusts the distribution position of the high level in each phase PWM wave within the switching cycle. Its fundamental purpose is to optimize the voltage vector sequence synthesized within a PWM cycle, so that the effective vector used for synthesis is as close as possible to the desired output voltage vector, thereby reducing the ripple of output voltage and current and significantly reducing harmonic content.

[0106] In general, the method provided in this application mainly includes the following steps:

[0107] (1) Real-time acquisition and determination of the direction (positive or negative) of the three-phase input current;

[0108] (2) Based on the current direction of each phase, determine a corresponding PWM high-level position allocation strategy for each phase PWM channel: whether to place the high level at both ends of the switching cycle (corresponding to the triangular carrier cycle) or in the middle region;

[0109] (3) Based on the single-cycle control principle, the original duty cycle command required for the three-phase bridge arm is calculated;

[0110] (4) Combining the above high-level position strategy and the original duty cycle instruction, calculate and set the key parameters of the PWM generation module (such as the ePWM module of the DSP) to finally generate a PWM waveform with the optimal vector synthesis sequence for driving the switching transistor.

[0111] The above steps mainly involve determining the direction of the three-phase input current, determining and implementing the PWM high-level position allocation strategy, calculating the duty cycle based on single-cycle control, and synthesizing and outputting the PWM drive signal. The details are as follows:

[0112] 1. The direction of the three-phase input current is determined by whether the magnitude of the three-phase input current is zero.

[0113] 2. Determination and implementation of the PWM high-level position allocation strategy: The strategy rule is as follows: For phases with positive current direction, the high-level portion of their PWM output waveform is adjusted to the beginning and end segments (i.e., "both ends") of the triangular carrier cycle; for phases with negative or zero current direction, the traditional PWM generation method is maintained, i.e., the high level is concentrated in the middle of the carrier cycle. This strategy can be implemented through flexible configuration in the ePWM module of the TMS320F28335 DSP. This module typically operates in "increment / decrement counting" mode, where the triangular carrier counter increments from 0 to the cycle value and then decrements back to 0. Assume the PWM output is active high. This includes the following different scenarios:

[0114] (1) For cases where the phase current is greater than zero, the high-level pulses need to be symmetrically distributed at the beginning and end of the PWM cycle. Specifically, the output logic of the ePWM module is configured as follows: when the counter value is in the lower or higher range, a high level is output, while in the middle range, a low level is output. By adjusting a comparison value, the width of these two high-level ranges can be controlled, thereby achieving a symmetrical distribution of the pulse waveform at both ends of the cycle while maintaining the total high-level time equal to the required duty cycle.

[0115] (2) For phases with negative or zero current direction, maintain the conventional center-symmetric PWM configuration. In this configuration, the high-level pulse is concentrated in the middle part of each PWM cycle, thus forming a waveform symmetrical about the center point of the cycle. The main purpose of this arrangement is to distribute the switching action evenly within the cycle, thereby optimizing and balancing the switching losses of the system.

[0116] 3. Calculation of duty cycle based on single-cycle control

[0117] In this section, the outer-loop PI regulator outputs a regulation signal u based on the deviation between the DC bus voltage setpoint and the feedback value. m Based on the three-phase current sampling values, the duty cycle of each phase is calculated according to the basic principle of single-cycle control.

[0118] 4. Synthesis and Output of PWM Drive Signals

[0119] In this step, the controller combines the duty cycle command with preset waveform generation rules in real time to calculate the control parameters required for each phase in the current PWM cycle. When using the "double update" operating mode, these calculated parameter values ​​are updated once at the beginning and once at the midpoint of each PWM cycle to ensure precise waveform symmetry. Finally, the ePWM hardware module automatically generates the required symmetrical PWM waveform based on these real-time updated parameters.

[0120] The following explanation uses the optimization process of traditional single-cycle control PWM generation as an example.

[0121] Please refer to Figures 4A to 4D, 5A to 5B, 6, 7A to 7B, 8A, 8B and 9.

[0122] (a) Conventional technology

[0123] As shown in Figure 4A, under normal circumstances, in the first type of traditional single-cycle control PWM generation, the PWM wave is generated by a triangular carrier wave, as shown in Figure 4B. That is, the triangular carrier wave rises from 0 to the period value PRD, and then falls back to 0, completing one carrier cycle. When the carrier wave value is the same as the triangular wave value, the PWM wave flips, as shown in Figure 4B, thus generating the PWM wave.

[0124] Therefore, it can be seen that the conventional VIENNA output PWM wave is shown in Figure 4C, with an output voltage vector Vg, and the corresponding three-phase output voltages are V1, V2, and V3, respectively. Among them, phase V1 is a positive voltage with an output duty cycle of 10% for S1; V2 is a negative voltage with an output duty cycle of 50% for S2; and V3 is a negative voltage with an output duty cycle of 60% for S3. The output duty cycle is shown in Figure 4C, and the corresponding voltage vector is shown in Figure 4B.

[0125] Furthermore, as shown in Figure 4C, the three-phase voltage transmission can be divided into 7 segments according to the switching change points: 000, 001, 011, 111, 011, 001, and 000. The first three switching vectors are identical to the last three, and they form a left-right symmetrical relationship about the center line. Therefore, these 7 vector segments are actually 4 different voltage component vectors, corresponding to the 4 vectors marked in gray in Figure 4D.

[0126] Therefore, it can be seen that the output voltage synthesis vector Vg in Figure 4D is synthesized from vector voltages 000, 001, 011 and 111; among them, 111 is the zero vector. Because this vector is far away from the desired output voltage vector Vg, it will cause the output voltage to fluctuate more, which will further lead to a larger switching ripple of the output current.

[0127] As can be seen from the above, the optimal synthesis method for Vg is to synthesize the three voltage vectors 011(100), 000, and 001 corresponding to the three vertices of the small triangle where Vg is located. These three voltage vectors are the three voltage vectors closest to the target vector Vg, which will reduce the output voltage harmonics and current harmonics.

[0128] Similarly, in the second case of traditional single-cycle control output, when the output voltage vector Vh is, the corresponding three-phase output voltages are V1, V2 and V3 respectively; where V1 is a positive voltage and S1 output duty cycle is 50%; V2 is a positive voltage and S2 output duty cycle is 60%; V3 is a negative voltage and S3 output duty cycle is 10%; the output duty cycle is shown in Figure 5A, and the output voltage vector Vh is shown in Figure 5B.

[0129] As shown in Figure 5B, the three-phase voltage transmission can be divided into 7 segments according to the switching change points, namely: 000, 010, 110, 111, 110, 010 and 000; the first 3 switching vectors are the same as the last 3 switching vectors, forming a left-right symmetrical relationship about the center line. Thus, the 7 segments of vectors are actually 4 different voltage sub-vectors, corresponding to the 4 vectors marked in gray in Figure 5B.

[0130] Therefore, the output voltage synthesis vector Vh in Figure 5B is synthesized from vector voltages 000, 010, 110 and 111, where 111 is the zero vector. Since this vector is far from the desired output voltage vector Vg, it will cause large output voltage fluctuations and further lead to large switching ripple of the output current.

[0131] (ii) The scheme adopted in this application:

[0132] As can be seen from the above, this application has optimized this situation. The specific details are as follows:

[0133] In this application, the high level of the PWM wave for the phase with a current greater than zero is placed at both ends of the triangular carrier wave. In the VIENNA control flow, when the phase current is greater than zero, i x >0 (x=1, 2, 3), the PWM wave will be generated and output as shown in Figure 6.

[0134] The PWM wave corresponding to the output voltage vector Vg in the conventional technology is modified, as shown in Figure 7A. In Figure 7A, the output PWM switching vectors are: 100, 000, 001, 011, 001, 000, 001. The first three switching vectors are the same as the last three switching vectors, forming a left-right symmetrical relationship about the center line. The seven switching vector segments are composed of four different switching vectors, corresponding to the four vectors marked in gray in Figure 7B.

[0135] For the second case: the PWM wave corresponding to the output voltage vector Vh is modified, as shown in Figure 8A. In Figure 8A, the output PWM switching vectors are 110, 010, 000, 001, 000, 010, and 110. The first three switching vectors are the same as the last three switching vectors, forming a left-right symmetrical relationship about the center line. The seven switching vector segments are composed of four different switching vectors, corresponding to the four vectors marked in gray in Figure 8B.

[0136] In this embodiment, the simulation data used are: input voltage 220V, 50Hz, input current RMS value 10.8A, bus voltage 700V; inductance 500uH; switching frequency 50kHz, and a double sampling and double update method is used within one PWM wave.

[0137] Experimental simulations were conducted based on the technical solution of this application. The experimental results are shown in Figure 9. The blue waveform at the peak and trough is the current waveform corresponding to the traditional PWM waveform of VIENNA single-cycle control, with a current harmonic content of 5.81%. The orange waveform at other locations is the current waveform corresponding to the improved PWM waveform of VIENNA single-cycle control, with a current harmonic content of 2.86%. After adopting the new method, the current harmonic content is reduced by 50.8%.

[0138] In other words, according to the method in this application, the optimal synthesis method for Vh is to synthesize the three voltage vectors 001(110), 000, and 010 corresponding to the three vertices of the small triangle where Vg is located. These three voltage vectors are the three voltage vectors closest to the target vector Vh, which reduces output voltage harmonics and current harmonics. That is, after optimization by the method provided in this application, the PWM switching sequence has been fundamentally changed. Taking the target vector Vg in Figure 4D as an example, the sequence generated by the traditional method contains the relatively distant zero vector 111, while the optimized sequence (Figure 7B) becomes 100, 000, 001, 011, etc. These vectors are precisely the three basic vectors closest to Vg and their complementary vectors, thus achieving optimal synthesis and effectively reducing harmonics.

[0139] Therefore, this experimental result demonstrates that the method provided in this application, while maintaining the single-cycle control duty cycle calculation unchanged, detects and determines the direction of the three-phase input current in real time. Based on the determination result, it reconfigures the high-level segment of the PWM wave corresponding to the bridge arm with the positive current direction, which was previously generated by comparing with the triangular carrier wave, to the two ends of the triangular carrier wave cycle. This current direction-based PWM waveform arrangement rule changes the combination method of the basic voltage vectors in the switching sequence, ensuring that the basic vectors used to synthesize the target output voltage vector in each switching cycle are the three vectors closest to the target vector. This effectively avoids the large ripples introduced by using distant zero vectors in traditional methods, ultimately achieving the technical effect of significantly reducing input current harmonic content and improving power quality.

[0140] In summary, this application fundamentally avoids the problems of output voltage fluctuations and increased harmonics caused by the forced introduction of distant zero vectors in traditional single-cycle control by dynamically identifying the position of the target voltage vector in the spatial vector diagram and selecting only the three closest voltage vectors for synthesis. This method significantly reduces input current harmonic content without adding extra hardware or increasing the switching frequency, effectively improving system power quality, overall energy efficiency, and grid compatibility. Furthermore, by implementing this algorithm in a digital controller, this application features a simple structure, ease of integration, robustness adaptable to various operating conditions including light load, heavy load, and grid imbalance, and possesses significant engineering practical value.

[0141] The scope of protection of the PWM wave optimization method based on single-cycle control of VIENNA rectifier described in this application is not limited to the execution order of the steps listed in this embodiment. Any solution implemented by adding, subtracting, or replacing steps in the prior art based on the principles of this application is included within the scope of protection of this application.

[0142] This application also provides a PWM wave optimization system based on single-cycle control of a VIENNA rectifier. The PWM wave optimization system based on single-cycle control of a VIENNA rectifier can implement the PWM wave optimization method based on single-cycle control of a VIENNA rectifier described in this application. However, the implementation device of the PWM wave optimization method based on single-cycle control of a VIENNA rectifier described in this application includes, but is not limited to, the structure of the PWM wave optimization system based on single-cycle control of a VIENNA rectifier listed in this embodiment. All structural modifications and substitutions of the prior art made according to the principles of this application are included within the protection scope of this application.

[0143] As shown in Figure 10, this embodiment provides a PWM wave optimization system based on single-cycle control of a VIENNA rectifier, including: a data acquisition module 21, a position information determination module 22, a duty cycle calculation module 23, and a drive signal output module 24.

[0144] The data acquisition module 21 is used to acquire the three-phase input current and determine the direction of the three-phase input current based on the three-phase input current.

[0145] In this embodiment, a current sampling circuit (e.g., based on a Hall current sensor or a sampling resistor in conjunction with an isolation operational amplifier) ​​is used to acquire the current signals (i1, i2, i3) at the three-phase input ports (a, b, c phases) of the VIENNA rectifier in real time. Simultaneously, the analog current signals are converted into digital quantities by an ADC and input to the digital controller.

[0146] Furthermore, in the digital controller, the instantaneous sampled values ​​of the acquired three-phase input current are compared with zero values ​​to determine the current direction.

[0147] The position information determination module 22 is used to determine the position of the corresponding PWM wave high level within the switching cycle according to the direction of the three-phase input current; including: for each PWM output channel, selecting to place the high level at the two ends or in the middle of the switching cycle according to the associated phase current sign.

[0148] In this embodiment, when the phase current associated with the PWM1 channel is greater than or equal to 0, the high level of the PWM1 waveform is configured at both ends of the switching cycle; when the phase current associated with the PWM1 channel is less than 0, the high level of the PWM1 waveform is configured in the middle of the switching cycle.

[0149] When the phase current associated with the PWM2 channel is greater than or equal to 0, the high level of the PWM2 waveform is configured at both ends of the switching cycle; when the phase current associated with the PWM2 channel is less than 0, the high level of the PWM2 waveform is configured in the middle of the switching cycle.

[0150] When the phase current associated with the PWM3 channel is greater than or equal to 0, the high level of the PWM3 waveform is configured at both ends of the switching cycle; when the phase current associated with the PWM3 channel is less than 0, the high level of the PWM3 waveform is configured in the middle of the switching cycle.

[0151] Furthermore, the switching cycle corresponds to a switching frequency of 50kHz, and a double-sampling double-update control mode is adopted within one PWM cycle.

[0152] The duty cycle calculation module 23 is used to calculate the duty cycle based on the position of the PWM wave high level within the switching cycle.

[0153] In this embodiment, an input current signal is acquired; a bus voltage signal is obtained; a voltage closed-loop calculation is performed based on the bus voltage signal to obtain a voltage adjustment command; the voltage closed-loop calculation includes comparing the bus voltage signal with a target voltage and generating the voltage adjustment command through a regulator; the duty cycle is calculated based on the voltage adjustment command, and a PWM control signal is generated. Alternatively, the duty cycle of the three-phase PWM wave can be calculated based on the output value of the voltage loop PI regulator and the current sampling value.

[0154] The drive signal output module 24 is used to generate and output a PWM drive signal for controlling the VIENNA rectifier switching transistor based on the position of the PWM wave high level within the switching cycle and the duty cycle.

[0155] In this embodiment, the switching vector sequence corresponding to the PWM drive signal has a seven-segment symmetrical structure within a single switching cycle and is composed of four different basic voltage vectors. The selection of the four basic voltage vectors ensures that the output voltage composite vector is synthesized from the vectors of the three nearest vertices in its spatial vector diagram.

[0156] The structure and principle of the data acquisition module 21, the position information determination module 22, the duty cycle calculation module 23, and the drive signal output module 24 correspond one-to-one with the steps in the PWM wave optimization method based on the single-cycle control of the VIENNA rectifier, so they will not be described again here.

[0157] In summary, the system provided in this application, by implementing the aforementioned optimization algorithm in a digital controller (such as a DSP or FPGA), can achieve optimal vector selection and PWM wave generation in real time and with high accuracy. The system has a simple structure and is easy to integrate into existing control architectures. It is not only suitable for ideal power grid conditions, but its vector nearest neighbor selection principle also enables it to maintain excellent low-harmonic performance under various operating conditions such as light load, heavy load, and power grid imbalance, demonstrating good robustness and engineering applicability.

[0158] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, or methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules / units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or units may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of apparatuses or modules or units may be electrical, mechanical, or other forms.

[0159] The modules / units described as separate components may or may not be physically separate. The components shown as modules / units may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules / units can be selected to achieve the objectives of the embodiments of this application, depending on actual needs. For example, the functional modules / units in the various embodiments of this application may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0160] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0161] This application also provides a PWM wave optimization device based on single-cycle control of a VIENNA rectifier. The PWM wave optimization device based on single-cycle control of a VIENNA rectifier can implement the PWM wave optimization method based on single-cycle control of a VIENNA rectifier of this application. However, the implementation device of the PWM wave optimization method based on single-cycle control of a VIENNA rectifier of this application includes, but is not limited to, the structure of the PWM wave optimization device based on single-cycle control of a VIENNA rectifier listed in this embodiment. All structural modifications and substitutions of the prior art made according to the principles of this application are included within the protection scope of this application.

[0162] As shown in Figure 11, this embodiment provides a PWM wave optimization device based on single-cycle control of a VIENNA rectifier, including: a current sampling circuit 31, a controller 32, and a drive circuit 33.

[0163] The current sampling circuit 31 is used to collect the three-phase input current;

[0164] The controller 32 is configured to: determine the direction of each phase based on the sampled current, determine the high-level position of the PWM, calculate the duty cycle, and generate an optimized PWM waveform;

[0165] The drive circuit 33 is used to amplify the PWM signal generated by the controller to drive the power switching transistor of the VIENNA rectifier.

[0166] Since the specific implementation of this embodiment corresponds to the aforementioned method embodiment, the same details will not be repeated here. Those skilled in the art should also understand that the division of each module in the embodiment of Figure 11 is only a logical functional division. In actual implementation, all or part of them can be integrated into one or more physical entities. These modules can all be implemented in software through processing element calls, or all of them can be implemented in hardware. Alternatively, some modules can be implemented in software through processing element calls, and some modules can be implemented in hardware.

[0167] Please refer to Figure 12, which shows a schematic diagram of the structure of the electronic device described in an embodiment of this application. As shown in Figure 12, this embodiment provides an electronic device 40, which includes a memory 41 and a processor 42.

[0168] The memory 41 is used to store computer programs; preferably, the memory 41 includes various media that can store program code, such as ROM, RAM, magnetic disk, USB flash drive, memory card or optical disk.

[0169] Specifically, memory 41 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) and / or cache memory. Electronic device 40 may further include other removable / non-removable, volatile / non-volatile computer system storage media. Memory 41 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of this application. It is understood that memory 41 may be volatile memory or non-volatile memory, or both. Non-volatile memory may be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of the present invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0170] The processor 42 is connected to the memory 41 and is used to execute the computer program stored in the memory 41 so that the electronic device 40 executes the PWM wave optimization method based on VIENNA rectifier single-cycle control as described in any embodiment of this application.

[0171] Optionally, the processor 42 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0172] This application also provides a computer-readable storage medium. Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing a processor. The program can be stored in a computer-readable storage medium, which is a non-transitory medium, such as random access memory, read-only memory, flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disk, and any combination thereof. The storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DVD)), or a semiconductor medium (e.g., solid-state drive (SSD)).

[0173] This application embodiment may also provide a computer program product comprising one or more computer instructions. When the computer instructions are loaded and executed on a computing device, all or part of the processes or functions described in this application embodiment are generated. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0174] When the computer program product is executed by a computer, the computer performs the method described in the foregoing method embodiments. The computer program product can be a software installation package; when the foregoing method is required, the computer program product can be downloaded and executed on the computer.

[0175] In summary, the PWM waveform optimization method based on single-cycle control of a VIENNA rectifier provided in this application has the following beneficial effects:

[0176] The PWM waveform optimization method and system based on single-cycle control of a VIENNA rectifier provided in this application can dynamically identify the position of the target voltage vector in the spatial vector diagram and synthesize only the three closest voltage vectors. This fundamentally avoids the problems of output voltage fluctuation and increased harmonics caused by the forced introduction of distant zero vectors in traditional single-cycle control. This method can significantly reduce the input current harmonic content (harmonic reduction of up to 50.8% under simulation conditions) without adding extra hardware or increasing the switching frequency, effectively improving system power quality, overall energy efficiency, and grid compatibility. The corresponding optimization system, by implementing the algorithm in a digital controller, has a simple structure, is easy to integrate, and is robust to various operating conditions such as light load, heavy load, and grid imbalance, possessing good engineering practical value. Therefore, this application also has broad applicability.

[0177] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0178] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A PWM waveform optimization method based on single-cycle control of a VIENNA rectifier, characterized in that, The method includes: acquiring three-phase input current; determining the direction of the three-phase input current based on the three-phase input current; determining the position of the corresponding PWM wave high level within the switching cycle according to the direction of the three-phase input current; including: for each PWM output channel, selecting to place the high level at the two ends or in the middle of the switching cycle according to the associated phase current sign; calculating the duty cycle based on the position of the PWM wave high level within the switching cycle; and generating a PWM drive signal for controlling the switching transistors of the VIENNA rectifier based on the position of the PWM wave high level within the switching cycle and the duty cycle.

2. The PWM waveform optimization method based on single-cycle control of a VIENNA rectifier according to claim 1, characterized in that, Determining the position of the corresponding PWM waveform high level within the switching cycle based on the direction of the three-phase input current includes: when the phase current associated with the PWM1 channel is greater than or equal to 0, the high level of the PWM1 waveform is positioned at both ends of the switching cycle; when the phase current associated with the PWM1 channel is less than 0, the high level of the PWM1 waveform is positioned in the middle of the switching cycle; when the phase current associated with the PWM2 channel is greater than or equal to 0, the high level of the PWM2 waveform is positioned at both ends of the switching cycle; when the phase current associated with the PWM2 channel is less than 0, the high level of the PWM2 waveform is positioned in the middle of the switching cycle; when the phase current associated with the PWM3 channel is greater than or equal to 0, the high level of the PWM3 waveform is positioned at both ends of the switching cycle; when the phase current associated with the PWM3 channel is less than 0, the high level of the PWM3 waveform is positioned in the middle of the switching cycle.

3. The PWM waveform optimization method based on single-cycle control of a VIENNA rectifier according to claim 1, characterized in that, Also includes: The duty cycle of the three-phase PWM wave is calculated based on the output value of the voltage loop PI regulator and the current sampling value.

4. The PWM waveform optimization method based on single-cycle control of a VIENNA rectifier according to claim 1, characterized in that, Calculating the duty cycle based on the position of the PWM wave high level within the switching cycle includes: acquiring the input current signal; obtaining the bus voltage signal; performing voltage closed-loop calculation based on the bus voltage signal to obtain a voltage adjustment command; the voltage closed-loop calculation includes comparing the bus voltage signal with the target voltage and generating the voltage adjustment command through the regulator; calculating the duty cycle based on the voltage adjustment command and generating a PWM control signal.

5. The PWM waveform optimization method based on single-cycle control of a VIENNA rectifier according to claim 1, characterized in that, The switching vector sequence corresponding to the PWM drive signal has a seven-segment symmetrical structure within a single switching cycle and is composed of four different basic voltage vectors.

6. The PWM waveform optimization method based on single-cycle control of a VIENNA rectifier according to claim 5, characterized in that, The selection of the four basic voltage vectors ensures that the output voltage composite vector is synthesized from the vectors of the three nearest vertices in the spatial vector diagram in which it resides.

7. The PWM waveform optimization method based on single-cycle control of a VIENNA rectifier according to claim 1, characterized in that, The switching cycle corresponds to a switching frequency of 50kHz, and a double-sampling double-update control mode is used within one PWM cycle.

8. A PWM waveform optimization system based on single-cycle control of a VIENNA rectifier, characterized in that, include: The data acquisition module is used to acquire the three-phase input current and determine the direction of the three-phase input current based on the three-phase input current. The position information determination module is used to determine the position of the corresponding PWM wave high level within the switching cycle based on the direction of the three-phase input current; including: for each PWM output channel, selecting to place the high level at the two ends or in the middle of the switching cycle according to the sign of its associated phase current; The duty cycle calculation module is used to calculate the duty cycle based on the position of the PWM wave high level within the switching cycle; the drive signal output module is used to generate and output a PWM drive signal for controlling the VIENNA rectifier switching transistor based on the position of the PWM wave high level within the switching cycle and the duty cycle.

9. A PWM waveform optimization device based on single-cycle control of a VIENNA rectifier, characterized in that, The device includes: a current sampling circuit, a controller, and a drive circuit; the current sampling circuit is used to collect three-phase input current; the controller is configured to: determine the direction of each phase based on the sampled current, determine the PWM high-level position, calculate the duty cycle, and generate an optimized PWM waveform; the drive circuit is used to amplify the PWM signal generated by the controller to drive the power switching transistors of the VIENNA rectifier.

10. An electronic terminal, characterized in that, include: Processor and memory; The memory is used to store computer programs; the processor is connected to the memory and is used to execute the computer programs stored in the memory, so that the PWM wave optimization device based on VIENNA rectifier single-cycle control performs the PWM wave optimization method based on VIENNA rectifier single-cycle control as described in any one of claims 1 to 7.

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