Storage and calculation integrated peripheral circuit device based on 3D VRRAM and matrix calculation method

Abstract

The invention relates to a storage and calculation integrated peripheral circuit device based on a 3D VRRAM and a matrix calculation method, belongs to the technical field of memories, and solves the problem that the structure of an existing two-dimensional resistive random access memory array is not suitable for a neural network with a high calculation power demand. The device comprises a matrix multiplier for multiplying an input data matrix by a weight matrix; the input ends of the analog-to-digital converters are connected to the output ends of the column control switches so as to convert the analog product result into a digital product result; the plurality of samplers are connected with the output end of the analog-to-digital converter so as to sample the digital product result; the output ends of the plurality of samplers are connected with the input end of the matrix adder through the matrix adder so as to realize digital product result shifting, then shifting data are accumulated, and an accumulation result is stored in a temporary register; and the updating register adds the accumulation result and the data in the updating register to obtain sum data, and updates the data in the updating register by using the sum data. And high-storage and high-computing-power-density operation is realized so as to be suitable for a neural network.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a 3D VRRAM-based in-memory computing peripheral circuit device and matrix calculation method. Background Technology

[0002] Existing two-dimensional resistive switching memory (SSN) arrays with in-memory computing architecture can dynamically adjust weights to simulate the dynamic changes in connection weights in neural networks, and can be used in neuromorphic chips. However, this two-dimensional SSN array structure has a large storage cell area and low storage density, making it unsuitable for neural networks with high computing power requirements.

[0003] Existing three-dimensional resistive random access memory (RRRAM) devices, combined with current-mode sensitive amplifier circuits, sense and amplify the difference between the read current of a selected memory cell and the read current of a reference cell in a three-dimensional RRAM array, thereby enabling the reading of stored information. However, this technology only involves the read circuit and not the write circuit; the read circuit can only read multiple bits and cannot perform specific calculations.

[0004] Existing three-dimensional vertically stacked resistive random access memory (RRAM) has proposed cell structures, array architectures, and operating algorithms that can effectively suppress IR drop voltage drop and read / write interference. However, the read circuit of this technology can only perform multi-bit readings and can only store and read stored contents, but cannot perform actual operations. Summary of the Invention

[0005] Based on the above analysis, the embodiments of the present invention aim to provide a 3D VRRAM-based in-memory computing peripheral circuit and matrix calculation method to solve the problems of existing two-dimensional resistive random access memory arrays having large storage cell area, low storage density, unsuitability for neural networks with high computing power requirements, and existing read circuits only being able to read multiple bits and not perform specific calculations.

[0006] On one hand, embodiments of the present invention provide a 3D VRRAM-based in-memory computing peripheral circuit, comprising: a matrix multiplier including a layer control switch, a three-dimensional storage array, and a column control switch, wherein the layer control switch is used to receive an input data matrix under the control of a control signal, the three-dimensional storage array is used to store a weight matrix and multiply the input data matrix by the stored weight matrix, and the column control switch is used to output an analog product result under the control of the control signal; a plurality of analog-to-digital converters, the input terminals of which are connected to the output terminals of the column control switches to convert the analog product result into a digital product result; a plurality of samplers connected to the output terminals of the analog-to-digital converters to sample the digital product result; a matrix adder, used to connect the output terminals of the plurality of samplers to the input terminals of the matrix adder to realize the digital product result shifting, then accumulating the shifted data and storing the accumulated result in a temporary register; and an update register, used to add the accumulated result to the data in the update register to obtain a sum data, and use the sum data to update the data in the update register.

[0007] The beneficial effects of the above technical solution are as follows: matrix multiplication is implemented on the 3D VRRAM array, the ADC converts the matrix multiplication calculation result of the array into a digital signal, and the addition tree accumulates the digital signal again to realize matrix addition. Combined with the large storage density of 3D VRRAM, high storage density and high computing power density operations can be realized, which can be used to accelerate neural networks containing a large number of matrix multiplication and addition operations.

[0008] Based on further improvements to the above-mentioned device, the layer control switch includes a plurality of first MOS transistors located at the front end of the first column of the three-dimensional memory array, which are respectively used to control the corresponding layer memory cells of the three-dimensional memory array; and the column control switch includes a plurality of second MOS transistors located at the bottom layer of the three-dimensional memory array, which are respectively used to control the output of the corresponding column memory cells of the three-dimensional memory array.

[0009] Based on a further improvement of the above device, each first MOS transistor includes a source, a gate, and a drain, wherein the source of the first MOS transistor serves as the input terminal of the three-dimensional memory array; the gate of the first MOS transistor receives a gate control signal obtained by inverting a control signal provided by the controller twice; and the drain of the first MOS transistor is connected to one end of each memory cell in the corresponding layer memory cell; each second MOS transistor includes a source, a gate, and a drain, wherein the source of the second MOS transistor serves as the output terminal of the three-dimensional memory array; the gate of the second MOS transistor receives the gate control signal; and the drain of the second MOS transistor is connected to the other end of each memory cell in the corresponding column memory cell.

[0010] Based on further improvements to the above-mentioned device, the three-dimensional storage array includes multiple regions with the same storage capacity, each region includes multiple groups with the same storage capacity, and each group includes k layers of storage cells. The capacity of each group of storage cells is k layers × m rows × n columns, where k, m, and n are integers greater than 1. The source terminals of the corresponding first MOS transistors in the layer control switches of adjacent groups are connected, and the source terminals of the corresponding second MOS transistors in the column control switches of adjacent groups are connected.

[0011] Based on a further improvement of the above device, the input terminals of the plurality of analog-to-digital converters receive the analog product result from the output terminal of the three-dimensional storage array. Each analog-to-digital converter is a 4-bit successive approximation analog-to-digital converter, including 15 current comparators and a thermometer code to binary code circuit. The 15 current comparators are used to compare the input current with 15 reference currents respectively, and when the input current is greater than a certain reference current, the current current comparator outputs "1", otherwise the current current comparator outputs "1". The thermometer code to binary code circuit is used to convert the outputs of the 15 current comparators into 4-bit binary data.

[0012] Based on a further improvement of the above device, the matrix adder includes n sets of registers and a temporary register, wherein each set of registers includes 4 bits of binary data, the n sets of registers are used to connect the n sets of registers to the outputs of the plurality of samplers to shift the n sets of registers left by 0 bits to n / 2n bits respectively and accumulate the product results of the n sets of shifted numbers to obtain an accumulation result; and the temporary register is used to store the accumulation result in the temporary register.

[0013] Based on further improvements to the above-mentioned device, the first sampler includes a fourth D flip-flop, a third D flip-flop, a second D flip-flop, and a first D flip-flop; the second sampler includes an eighth D flip-flop, a seventh D flip-flop, a sixth D flip-flop, and a fifth D flip-flop. Connecting the multiple sets of registers to the outputs of the multiple samplers by left-shifting the n sets of registers by 0 bits to n / 2n bits further includes: the four output terminals of the first ADC are respectively connected to the input terminals of the fourth D flip-flop, the third D flip-flop, the second D flip-flop, and the first D flip-flop of the first sampler, wherein the input data of the first sampler is the first four-bit data a3a2a1a0; the four output terminals of the second ADC are respectively connected to the eighth D flip-flop, the seventh D flip-flop, the sixth D flip-flop, and the fifth D flip-flop of the second sampler. The input terminals of the second sampler and the fifth D flip-flop are configured such that the input data of the second sampler is the second four-bit data b3b2b1b0; the outputs of the second D flip-flop and the first D flip-flop are respectively used as c1c0 in the sum data c6c5c4c3c2c1c0; the output terminals of the third D flip-flop and the fifth D flip-flop are respectively connected to the first input terminal and the second input terminal of the first adder; the output terminals of the fourth D flip-flop, the sixth D flip-flop, and the carry terminal of the first adder are respectively connected to the three input terminals of the second adder; the output terminal of the seventh D flip-flop and the carry terminal of the second adder are respectively connected to the two input terminals of the third adder; and the output terminal of the eighth D flip-flop and the carry terminal of the third adder are respectively connected to the two input terminals of the fourth adder.

[0014] Based on a further improvement of the above-described device, the three-dimensional storage array includes: a bottom layer circuit located above a semiconductor substrate; an isolation insulating layer located above the bottom layer circuit, including a plurality of contacts that pass through a portion of the isolation insulating layer and are electrically connected to a metal layer in the bottom layer circuit; a plurality of interleaved layers located above the bottom layer circuit, each interleaved layer including a planar conductive layer and an insulating layer located above the planar conductive layer; a vertical columnar electrode that passes through the plurality of interleaved layers and continues through the remaining isolation insulating layer to be electrically connected to the plurality of contacts; and a resistive switching dielectric layer surrounding the periphery of the vertical columnar electrode, such that the planar conductive layer, the resistive switching dielectric layer, and the vertical columnar electrode constitute a resistive switching memory.

[0015] Based on further improvements to the above device, the insulating layer and the isolation insulating layer in the plurality of interleaved layers are made of SiO2; the planar conductive layer in the plurality of interleaved layers is made of TiN; the resistive switching dielectric layer is made of HfOx / TaOx; and the vertical columnar electrode is made of tungsten.

[0016] On the other hand, embodiments of the present invention provide a matrix calculation method, comprising: receiving an input data matrix through a layer control switch in a matrix multiplier, storing a weight matrix in a three-dimensional storage array, and multiplying the input data matrix with the weight matrix to output an analog product result through a column control switch in the matrix multiplier; converting the analog product result into a digital product result through multiple analog-to-digital converters; sampling the digital product result through multiple samplers; connecting the outputs of the multiple samplers to the inputs of the matrix adder to shift the digital product result, then accumulating the shifted data and storing the accumulated result in a temporary register; and adding the accumulated result to the data in an update register to obtain a sum data, and using the sum data to update the data in the update register.

[0017] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0018] 1. Integrating 3D VRRAM and peripheral circuits onto a single chip allows for simultaneous matrix multiplication and addition on a fully hardware system, facilitating embedded applications.

[0019] 2. Matrix multiplication is implemented on a 3D VRRAM array. The ADC converts the matrix multiplication calculation results of the array into digital signals, and the addition tree accumulates the digital signals again to achieve matrix addition. Combined with the high storage density of 3D VRRAM, high storage density and high computing power density operations can be achieved, which can be used to accelerate neural networks containing a large number of matrix multiplication and addition operations.

[0020] 3. Matrix multiplication is implemented on a 3D VRRAM array. The ADC converts the matrix multiplication calculation results of the array into digital signals, and the addition tree accumulates the digital signals again to realize matrix addition. The storage circuit for matrix multiplication and matrix addition is implemented simultaneously using a 3D VRRAM array.

[0021] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0022] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0023] Figure 1 This is a block diagram of a 3D VRRAM-based in-memory computing peripheral circuit device according to an embodiment of the present invention;

[0024] Figure 2 This is an architecture diagram of the 3D VRRAM according to an embodiment of the present invention;

[0025] Figure 3 This is a cross-sectional view of the 3D VRRAM according to an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram illustrating the working principle of the addition tree in an embodiment of the present invention.

[0027] Figure 5 This is a partition diagram of the 3D VRRAM according to an embodiment of the present invention;

[0028] Figure 6 This is a schematic diagram of matrix addition and multiplication in the storage-based peripheral circuit of this invention.

[0029] Figure 7 This is a flowchart of the matrix calculation method according to an embodiment of the present invention;

[0030] Figure 8 This is a diagram illustrating the specific connection between the matrix adder and the sampler in an embodiment of the present invention. Detailed Implementation

[0031] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0032] refer to Figure 1 A specific embodiment of the present invention discloses a 3D VRRAM-based in-memory computing peripheral circuit device, comprising: a matrix multiplier 101, including a layer control switch, a three-dimensional storage array, and a column control switch, wherein the layer control switch is used to receive an input data matrix under the control of a control signal, the three-dimensional storage array is used to store a weight matrix and multiply the input data matrix by the stored weight matrix, and the column control switch is used to output an analog product result under the control of a control signal; multiple analog-to-digital converters 102, the input terminals of which are connected to the output terminals of the column control switches to convert the analog product result into a digital product result; multiple samplers 103, connected to the output terminals of the analog-to-digital converters to sample the digital product result; a matrix adder 104, used to connect the output terminals of the multiple samplers to the input terminals of the matrix adder to realize the digital product result shifting, then accumulating the shifted data and storing the accumulated result in a temporary register; and an update register 105, used to add the accumulated result to the data in the update register to obtain a sum data, and use the sum data to update the data in the update register.

[0033] Compared with the prior art, the in-memory computing peripheral circuit based on 3D VRRAM provided in this embodiment implements matrix multiplication on the 3D VRRAM array. The ADC converts the matrix multiplication calculation result of the array into a digital signal, and the addition tree accumulates the digital signal again to realize matrix addition. Combined with the high storage density of 3D VRRAM, it can realize high storage density and high computing power density operation, which can be used to accelerate neural networks containing a large number of matrix multiplication and addition operations.

[0034] In the following text, refer to Figure 1 The present invention provides a detailed description of a 3D VRRAM-based in-memory computing peripheral circuit device according to an embodiment of the present invention.

[0035] The matrix multiplier 101 includes a layer control switch, a three-dimensional storage array, and a column control switch. The layer control switch is used to receive the input data matrix, the three-dimensional storage array is used to store the weight matrix, and the column control switch is used to output the product of the input data matrix and the weight matrix.

[0036] The layer control switch includes a plurality of first MOS transistors located at the front end of the first column of the three-dimensional memory array, each used to control a corresponding layer memory cell of the three-dimensional memory array. Each first MOS transistor includes a source, a gate, and a drain, wherein the source of the first MOS transistor serves as the input terminal of the three-dimensional memory array; the gate of the first MOS transistor receives a gate control signal obtained by inverting the control signal provided by the controller twice; and the drain of the first MOS transistor is connected to one end of each memory cell in the corresponding layer memory cell.

[0037] The column control switch includes multiple second MOS transistors located at the bottom layer of the three-dimensional memory array, each used to control the output of a corresponding column memory cell in the three-dimensional memory array. Each second MOS transistor includes a source, a gate, and a drain, wherein the source of the second MOS transistor serves as the output terminal of the three-dimensional memory array; the gate of the second MOS transistor receives a gate control signal; and the drain of the second MOS transistor is connected to the other end of each memory cell in the corresponding column memory cell.

[0038] The three-dimensional storage array includes multiple regions with the same storage capacity. Each region includes multiple groups with the same storage capacity, and each group includes k layers of storage cells. The capacity of each group of storage cells is k layers × m rows × n columns, where k, m, and n are integers greater than 1. The source of the corresponding first MOS transistor in the layer control switch of the adjacent group is connected, and the source of the corresponding second MOS transistor in the column control switch of the adjacent group is connected.

[0039] The three-dimensional memory array includes: a bottom circuitry located above a semiconductor substrate; an isolation insulating layer located above the bottom circuitry, including multiple contacts that pass through a portion of the isolation insulating layer and are electrically connected to a metal layer in the bottom circuitry; multiple interleaved layers located above the bottom circuitry, each interleaved layer including a planar conductive layer and an insulating layer located above the planar conductive layer; vertical columnar electrodes (i.e., bit lines BL) passing through the multiple interleaved layers and continuing through the remaining isolation insulating layer to be electrically connected to the multiple contacts; and a resistive switching dielectric layer surrounding the periphery of the vertical columnar electrodes, such that the planar conductive layer (i.e., word lines WL), the resistive switching dielectric layer, and the vertical columnar electrodes constitute a resistive switching memory.

[0040] Specifically, the insulating layer and the isolating insulating layer in the multiple interlayer stack are made of SiO2; the planar conductive layer in the multiple interlayer stack is made of TiN; the resistive switching dielectric layer is made of HfOx / TaOx; and the vertical columnar electrode is made of tungsten.

[0041] Multiple analog-to-digital converters 102, whose inputs are connected to the outputs of column control switches, convert analog product results into digital product results.

[0042] Specifically, the input terminals of multiple analog-to-digital converters 102 receive analog product results from the output terminals of the three-dimensional storage array. Each analog-to-digital converter is a 4-bit successive approximation analog-to-digital converter, including 15 current comparators and a thermometer code to binary code conversion circuit. The 15 current comparators are used to compare the input current with 15 reference currents respectively, and the current comparator outputs "1" when the input current is greater than a certain reference current, and vice versa. The thermometer code to binary code conversion circuit is used to convert the outputs of the 15 current comparators into 4 bits of binary data.

[0043] Multiple samplers 103 are connected to the output of the analog-to-digital converter (ADC) to sample the digital product result. Each sampler includes an edge-triggered D flip-flop, which is composed of CMOS switches and logic gates. Specifically, when the rising edge of the sampling clock arrives, the D flip-flop samples the ADC output and transmits it to the adder tree.

[0044] The matrix adder 104 is used to connect the outputs of multiple samplers to the inputs of the matrix adder to shift the digital product result, then accumulate the shifted data and store the accumulated result in a temporary register.

[0045] Specifically, connecting multiple sets of registers to the outputs of multiple samplers to left-shift the n sets of registers by 0 bits to n / 2n bits includes: the first sampler includes a fourth D flip-flop, a third D flip-flop, a second D flip-flop, and a first D flip-flop; the second sampler includes an eighth D flip-flop, a seventh D flip-flop, a sixth D flip-flop, and a fifth D flip-flop. Connecting the multiple sets of registers to the outputs of multiple samplers to left-shift the n sets of registers by 0 bits to n / 2n bits further includes: the four outputs of the first ADC are respectively connected to the inputs of the fourth D flip-flop, the third D flip-flop, the second D flip-flop, and the first D flip-flop of the first sampler, wherein the input data of the first sampler is the first four-bit data a3a2a1a0; the four outputs of the second ADC are respectively connected to the eighth D flip-flop of the second sampler. The input terminals of the first, second, sixth, and fifth D flip-flops are configured such that the input data of the second sampler is the second four-bit data b3b2b1b0; the outputs of the second and first D flip-flops are respectively used as c1c0 in the sum data c6c5c4c3c2c1c0; the output terminals of the third and fifth D flip-flops are respectively connected to the first and second input terminals of the first adder; the output terminals of the fourth and sixth D flip-flops and the carry terminal of the first adder are respectively connected to the three input terminals of the second adder; the output terminals of the seventh and second D flip-flops and the carry terminal of the second adder are respectively connected to the two input terminals of the third adder; and the output terminals of the eighth D flip-flop and the carry terminal of the third adder are respectively connected to the two input terminals of the fourth adder.

[0046] For example, accumulating shifted data further includes: connecting the Clk pins of D flip-flops D4 and D3, and connecting the Clk pins of D flip-flops D6 and D5. The outputs of D flip-flops D2 and D1 are used as c1 and c0, respectively; connecting the output pin of D flip-flop D3 to pin A of adder ADD1, and connecting the output pin of D flip-flop D5 to pin B of adder ADD1, so that adder ADD1 adds a2 + b0 to obtain the sum c2 and the first carry; and connecting the first carry to pin C of adder ADD2, connecting the output pin of D flip-flop D4 to pin A of adder ADD2, and connecting the output pin of D flip-flop D6 to pin B of adder ADD2, so that adder ADD1... D2 adds a3 + b1 + the first carry-in to obtain a sum c3 and a second carry-in; the second carry-in is connected to pin B of adder ADD3 and the output pin of D flip-flop D7 is connected to pin A of adder ADD3, so that adder ADD3 adds b2 + the second carry-in to obtain a sum c4 and a third carry-in; the third carry-in is connected to pin B of adder ADD4 and the output pin of D flip-flop D8 is connected to pin A of adder ADD4, so that adder ADD4 adds b3 + the third carry-in to obtain a sum c5 and a fourth carry-in as c6.

[0047] For example, refer to Figure 8 The output of each ADC is acquired through four D flip-flops. When the outputs of the two ADCs are added, the first four bits of data a3a2a1a0 are added to the second four bits of data b3b2b1b0 shifted left by 2 bits to obtain the sum c6c5c4c3c2c1c0, that is:

[0048]

[0049] Figure 8 The calculation process after shifting data b3b2b1b0 by 2 bits is as follows: First, the shift is performed, and then a full adder is used to add the carry from the previous stage to the two bits of the current stage. After shifting b3b2b1b0, the lowest 2 bits are a1 and a0, so c1 and c0 are directly equal to a1 and a0. Adding b0 and a2 gives c2 and the first carry. Adding the first carry to b1 and a3 gives c3 and the second carry. Adding the second carry to b2 gives c4 and the third carry. Adding the third carry to b3 gives c5 and the fourth carry, which is c6. Similarly, shifting n bits and 2n bits is done in a similar way, with corresponding bits added after the shift.

[0050] The matrix adder includes n sets of registers and temporary registers, where each set of registers contains 4 bits of binary data.

[0051] Specifically, the n sets of registers are used to connect the n sets of registers to the outputs of multiple samplers, shifting each of the n sets of registers left by 0 bits to n / 2n bits, and accumulating the product results of the n shifted numbers to obtain the accumulated result. The temporary register is used to store the accumulated result.

[0052] Update register 105 is used to add the accumulated result to the data in the update register to obtain the sum data, and use the sum data to update the data in the update register.

[0053] refer to Figure 7 A specific embodiment of the present invention discloses a matrix calculation method, comprising: in step S701, receiving an input data matrix through a layer control switch in a matrix multiplier, storing a weight matrix in a three-dimensional storage array, and multiplying the input data matrix with the weight matrix to output an analog product result through a column control switch in the matrix multiplier; in step S702, converting the analog product result into a digital product result through multiple analog-to-digital converters; in step S703, sampling the digital product result through multiple samplers; in step S704, connecting the output terminals of the multiple samplers to the input terminals of a matrix adder to achieve a shift of the digital product result, then accumulating the shifted data and storing the accumulated result in a temporary register; and in step S705, adding the accumulated result to the data in the update register to obtain a sum data, and using the sum data to update the data in the update register.

[0054] In the following text, refer to Figures 1 to 6 The present invention will be described in detail with specific examples of a 3D VRRAM-based in-memory computing peripheral circuit device according to embodiments thereof.

[0055] This invention utilizes a 3D VRRAM-based in-memory computing peripheral circuit to perform in-memory computing on a three-dimensional vertical resistive random access memory (VRAM). The circuit employs a 3D VRRAM array to perform matrix multiplication, an ADC to convert the array's computational results into digital signals, and an addition tree to accumulate the digital signals to achieve matrix addition. This circuit can be applied to high-performance neural network computations.

[0056] The 3D VRRAM-based in-memory computing peripheral circuit includes a 3D VRRAM memory array, a word line driver (WLdriver), a bit line driver (BL driver), a source line driver (SL driver), an analog-to-digital converter (ADC), edge-triggered D flip-flops (Sampling DFF), and adder trees. The architecture diagram is shown below. Figure 2 As shown, the structure and function of the submodule are as follows:

[0057] The memory array consists of vertical cylindrical electrodes, planar conductive layers, and insulating layers. A resistive switching dielectric layer surrounds the cylindrical electrodes, and planar conductive and insulating layers are stacked sequentially in the horizontal direction. The vertical cylindrical electrodes, resistive switching dielectric layer, and planar conductive layer constitute a resistive switching memory. A cross-sectional view is shown below. Figure 3 As shown.

[0058] The driving circuit includes word line driving circuits, source line driving circuits, and bit line driving circuits, each containing decoding circuits and switches. Its main function is to perform read and write operations on the RRAM cell at the input address. The decoding circuit decodes the input address, generates control signals, and controls the switches to transmit the operating voltage to the corresponding word line / source line / bit line. The switches include NMOS switches and PMOS switches. PMOS switches are used for operating voltages greater than half the power supply voltage, while NMOS switches are used for operating voltages less than half the power supply voltage, thus achieving complete signal transmission.

[0059] The analog-to-digital converter (ADC) is a 4-bit successive approximation type, consisting of 15 current comparators and a thermometer code to binary conversion circuit. Its main function is to convert the input current signal into a 4-bit binary digital signal. Working principle: The current comparators compare the input current with 15 reference currents. If the input current is greater than a certain reference current, the current comparator outputs 1; otherwise, it outputs 0. The 15 current comparators output a total of 15 bits of thermometer code, which is then converted into 4 bits of binary data by the thermometer code to binary conversion circuit.

[0060] The output of the ADC is sampled using an edge-triggered D flip-flop, which consists of CMOS switches and logic gates. Working principle: When the rising edge of the sampling clock arrives, the D flip-flop samples the ADC output and transmits it to the adder tree.

[0061] An addition tree consists of full adders, half adders, and shift registers, and its working principle is as follows: Figure 4 As shown, four ADCs simultaneously input four 4-bit binary data. Data0 does not need to be shifted, data1 is shifted left by 1 / 2 bit, data2 is shifted left by 2 / 4 bit, and data3 is shifted left by 3 / 6 bit. The shifted data are accumulated to obtain 11 bits of data, which are stored in 18 registers. In the next cycle, the 11 bits of data calculated are added to the data in the registers and then stored in the registers. After four cycles, the 18 bits of data in the registers are output.

[0062] The 8-layer 1Mb 3D storage array is partitioned, grouped, and row-based, divided into 16 blocks. Each block has a storage capacity of 8*32*256. There are 8 layers, with each layer having a capacity of 32 rows and 256 columns. Each block is further divided into 32 groups, each group consisting of 8 banks of storage units, with each column having a storage capacity of 256. The specific partitioning diagram is shown below. Figure 5 The transistor on the left is used to select a specific layer, and the transistors below are used to select a specific group. The control terminals of the transistors below each group are interconnected and controlled by the same signal. The memory cells in each group are identical, and the groups are interconnected. Each operation is performed on a zone-by-zone basis. The two ends of the RRAM of an unselected zone are grounded, so a 4-to-16 decoder generates a control signal to select a zone to operate on based on the input address port.

[0063] Stored computing can perform matrix multiplication. Inputs are programmed as voltages and applied to word lines; inputting "1" is programmed to read the voltage V. read The input "0" is programmed as V1, where V1 is the average voltage value at the ADC input terminal. Weights are programmed in RRAM: weight "1" is programmed as LRS, and weight "0" is programmed as HRS. For an input "0" multiplied by either weight "0" or "1", the output value is "0". In the memory array, one end of the storage cell is V1, and the other end is the ADC input terminal. The voltage difference between them is very small, resulting in negligible current (i.e., the current is so small as to be negligible), corresponding to an output of "0". For an input "1" multiplied by weight "0", the reading voltage V1 is... read The action of HRS also produces I HRS The corresponding output is "0"; for an input of "1", multiplying it by a weight of "1" results in the voltage V. read Acting on LRS, it generates I LRS The corresponding output is "1". Since the RRAM's HRS / LRS > 10, the large current is more than 10 times that of the small current. After the currents in the same column converge, the ADC is used to determine the magnitude of the converged current and convert it into a digital signal, which can then realize matrix multiplication.

[0064] The input vector is 1111_0000, the weight is 0111_0000, the WL input in rows 1-4 is the voltage reading, and the WL input in the last four rows is V1. The weight encoding in the first column from top to bottom is HRS / LRS / LRS / LRS / HRS / HRS / HRS / HRS, so the bit line output current is 3×I. LRS +I HRS , is converted to 0011 by ADC.

[0065] For weights with 4 bits or more of stored data, multiple RRAMs are required to store the information. Taking a 4-bit weight as an example, four consecutive RRAMs in the same row are needed to store the information, such as... Figure 6 As shown. After multiplying the input with these 4 bits of data, four multiplication results are obtained in adjacent 4ADCs. These results need to be shifted by 0 / 1 / 2 / 3 bits respectively before being added together. For example, "1*0011", 0011 is represented by 4 RRAM units. The input "1" is multiplied by "0", "0", "1", and "1" respectively to obtain "0", "0", "1", and "1". Shifting and adding these results in "0011". A set of RRAM units has a size of 8*256, therefore 64 addition tree modules are needed. This can generate a matrix containing 64 elements, or multiple matrices with a total of 64 elements. The dimension of the matrix depends on the input and weights.

[0066] In each cycle, a storage and calculation operation is performed on one group of RRAM cells, and the ADC shift and accumulation result is stored in an 11-bit register. The data in the 11-bit register is added to the data in the 18-bit register, and then stored in the 18-bit register. This process is repeated for multiple cycles to achieve matrix addition. For example, in the first cycle, the first group of RRAM cells is processed, and the result 001_0000_1111 is stored in the 11-bit register. The data in the 18-bit register is 0, and the result after addition is still 001_0000_1111. In the second cycle, the second group of RRAM cells is processed, and the result 000_1000_0001 is stored in the 11-bit register. This result is then added to 001_0000_1111 in the 18-bit register to obtain 001_1001_0000, which is then stored in the 18-bit register.

[0067] The purpose of this invention is to provide a 3D VRRAM-based in-memory computing peripheral circuit that integrates 3D VRRAM and peripheral circuitry onto a single chip. This allows for simultaneous matrix multiplication and matrix addition on a fully hardware-based system, facilitating embedded applications. Matrix multiplication is implemented on a 3D VRRAM array. An ADC converts the matrix multiplication results into digital signals, and an addition tree further accumulates these digital signals to perform matrix addition. Combined with the high storage density of 3D VRRAM, this enables high storage density and high computing power density operations, accelerating neural networks that involve numerous matrix multiplication and addition operations.

[0068] The key technical points of this invention are: 1. It realizes an in-memory computing peripheral circuit based on 3D VRRAM; 2. It implements matrix multiplication on the 3D VRRAM array, the ADC converts the matrix multiplication calculation result of the array into a digital signal, and the addition tree accumulates the digital signal again to realize matrix addition. It utilizes the 3D VRRAM array to realize an in-memory computing circuit that simultaneously implements matrix multiplication and matrix addition.

[0069] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0070] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A 3D VRRAM-based in-memory computing peripheral circuit device, characterized in that, include: A matrix multiplier includes a layer control switch, a three-dimensional storage array, and a column control switch. The layer control switch is used to receive an input data matrix under the control of a control signal. The three-dimensional storage array is used to store a weight matrix and multiply the input data matrix with the stored weight matrix. The column control switch is used to output a simulated product result under the control of the control signal. Multiple analog-to-digital converters, whose inputs are connected to the outputs of the column control switch, are used to convert the analog product result into a digital product result. Multiple samplers are connected to the output of the analog-to-digital converter to sample the digital product result; and A matrix adder is used to connect the outputs of the plurality of samplers to the input of the matrix adder to shift the digital product result, then accumulate the shifted data and store the accumulated result in a temporary register; and An update register is used to add the accumulated result to the data in the update register to obtain a sum, and to update the data in the update register using the sum.

2. The in-memory computing peripheral circuit device based on 3D VRRAM according to claim 1, characterized in that, The layer control switch includes a plurality of first MOS transistors located at the front end of the first column of the three-dimensional memory array, each used to control a corresponding layer memory cell of the three-dimensional memory array; as well as The column control switch includes multiple second MOS transistors located at the bottom layer of the three-dimensional memory array, which are used to control the output of the corresponding column memory cells of the three-dimensional memory array.

3. The in-memory computing peripheral circuit device based on 3D VRRAM according to claim 2, characterized in that, Each first MOS transistor includes a source, a gate, and a drain, wherein the source of the first MOS transistor serves as the input terminal of the three-dimensional memory array; the gate of the first MOS transistor receives a gate control signal obtained by inverting a control signal provided by the controller twice; and the drain of the first MOS transistor is connected to one end of each memory cell in the corresponding layer of memory cells. Each second MOS transistor includes a source, a gate, and a drain, wherein the source of the second MOS transistor serves as the output terminal of the three-dimensional memory array; the gate of the second MOS transistor receives the gate control signal; and the drain of the second MOS transistor is connected to the other end of each memory cell in the corresponding column memory cell.

4. The in-memory computing peripheral circuit device based on 3D VRRAM according to claim 2, characterized in that, The three-dimensional storage array comprises multiple zones with the same storage capacity, each zone comprises multiple groups with the same storage capacity, and each group comprises k layers of storage units. The capacity of each group of storage units is k layers × m rows × n columns, where k, m, and n are integers greater than 1. Among them, the source connection of the corresponding first MOS transistor in the layer control switch of the adjacent group, and the source connection of the corresponding second MOS transistor in the column control switch of the adjacent group.

5. The in-memory computing peripheral circuit device based on 3D VRRAM according to claim 3, characterized in that, The input terminals of the plurality of analog-to-digital converters receive the analog product result from the output terminal of the three-dimensional storage array, wherein each analog-to-digital converter is a 4-bit successive approximation analog-to-digital converter, including 15 current comparators and a thermometer code to binary code conversion circuit. The 15 current comparators are used to compare the input current with 15 reference currents respectively, and the current comparator outputs "1" when the input current is greater than a certain reference current, and vice versa; and The thermometer code to binary code circuit is used to convert the outputs of the 15 current comparators into 4-bit binary data.

6. The in-memory computing peripheral circuit device based on 3D VRRAM according to claim 5, characterized in that, The matrix adder includes n sets of registers and temporary registers, wherein each set of registers includes 4 bits of binary data. The n sets of registers are used to connect the n sets of registers to the outputs of the plurality of samplers, thereby shifting the n sets of registers left by 0 bits to n / 2n bits and accumulating the product results of the shifted n sets of numbers to obtain an accumulated result; and The temporary register is used to store the accumulation result.

7. The in-memory computing peripheral circuit device based on 3D VRRAM according to claim 6, characterized in that, The first sampler includes a fourth D flip-flop, a third D flip-flop, a second D flip-flop, and a first D flip-flop; the second sampler includes an eighth D flip-flop, a seventh D flip-flop, a sixth D flip-flop, and a fifth D flip-flop; wherein connecting the multiple sets of registers to the outputs of the multiple samplers by left-shifting the n sets of registers by 0 bits to n / 2n bits further includes: The four output terminals of the first ADC are respectively connected to the input terminals of the fourth D flip-flop, the third D flip-flop, the second D flip-flop and the first D flip-flop of the first sampler, wherein the input data of the first sampler is the first four-bit data a3a2a1a0; The four output terminals of the second ADC are respectively connected to the input terminals of the eighth D flip-flop, the seventh D flip-flop, the sixth D flip-flop, and the fifth D flip-flop of the second sampler. The input data of the second sampler is the second four-bit data b3b2b1b0. The outputs of the second D flip-flop and the first D flip-flop are respectively used as c1c0 in the sum data c6c5c4c3c2c1c0; Connect the outputs of the third and fifth D flip-flops to the first and second inputs of the first adder, respectively. Connect the output of the fourth D flip-flop, the output of the sixth D flip-flop, and the carry of the first adder to the three inputs of the second adder, respectively. Connect the output of the seventh D flip-flop and the carry-in of the second adder to the two inputs of the third adder, respectively; and Connect the output of the eighth D flip-flop and the carry of the third adder to the two inputs of the fourth adder, respectively.

8. The in-memory computing peripheral circuit device based on 3D VRRAM according to claim 5, characterized in that, The three-dimensional storage array includes: The underlying circuitry is located above the semiconductor substrate; An insulating layer is located above the underlying circuitry and includes a plurality of contacts that pass through a portion of the insulating layer and are electrically connected to a metal layer in the underlying circuitry. Multiple interactive stacks are located above the underlying circuit, each interactive stack including a planar conductive layer and an insulating layer located above the planar conductive layer; A vertical columnar electrode passes through the plurality of alternating layers and continues through the remaining insulating layer to be electrically connected to the plurality of contacts; A resistive switching dielectric layer surrounds the periphery of the vertical columnar electrode, such that the planar conductive layer, the resistive switching dielectric layer, and the vertical columnar electrode constitute a resistive switching memory.

9. The in-memory computing peripheral circuit device based on 3D VRRAM according to claim 8, characterized in that, The insulating layer and the isolation insulating layer in the plurality of interlayer stacks are made of SiO2; The material of the planar conductive layer in the plurality of interactive stacks is TiN; The resistive switching dielectric layer is made of HfOx / TaOx; and The material of the vertical columnar electrode is tungsten.

10. A matrix calculation method, characterized in that, include: The input data matrix is ​​received through the layer control switch in the matrix multiplier, the weight matrix is ​​stored in the three-dimensional storage array, and the input data matrix is ​​multiplied by the weight matrix to output the simulated product result through the column control switch in the matrix multiplier. The analog product result is converted into a digital product result by multiple analog-to-digital converters; The numerical product result is sampled using multiple samplers; The outputs of the multiple samplers are connected to the input of the matrix adder to shift the digital product result. The shifted data is then accumulated and the accumulated result is stored in a temporary register. as well as The accumulated result is added to the data in the update register to obtain the sum data, and the data in the update register is updated using the sum data.

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