Semiconductor wafers and methods for manufacturing semiconductor wafers

Abstract

The purpose of this disclosure is to provide a semiconductor wafer that can suppress the shrinkage of the diameter of the convex shape portion by providing cutouts on the outer peripheral surface and the convex shape portion of the semiconductor wafer, and a method for manufacturing the semiconductor wafer. The semiconductor wafer involved in this disclosure has a first surface and a second surface opposite to the first surface. The first surface has a first main surface and a surrounding surface that surrounds the first main surface via a stepped surface and is recessed from the first main surface towards the second surface. A first cutout is provided in a circumferential portion of the stepped surface connecting the first main surface and the surrounding surface, and a second cutout is provided in a circumferential portion of the outer peripheral surface connecting the second surface and the surrounding surface. The first cutout is in the shape of a positioning edge, and the second cutout is in the shape of a notch.

Description

Technical Field

[0001] This disclosure relates to semiconductor wafers and methods for manufacturing semiconductor wafers. Background Technology

[0002] Patent Document 1 proposes a method for forming a convex shape by trimming the edges of a semiconductor wafer to reduce the occurrence of gaps and cracks at the edges when thinning a device structure formed on the surface of a semiconductor substrate.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2021-52178

[0004] In Patent Document 1, the same positioning edge is provided on the outer peripheral surface of the semiconductor wafer and the convex shape portion. If a positioning edge is formed on the outer peripheral surface of the semiconductor wafer, the diameter of the semiconductor wafer becomes smaller. If a positioning edge is further formed on the convex shape portion inside the wafer, the diameter of the convex shape portion becomes even smaller. Summary of the Invention

[0005] Therefore, the object of this disclosure is to provide a semiconductor wafer and a method for manufacturing the semiconductor wafer that can suppress the shrinkage of the diameter of the convex shape portion by providing cutouts on the outer peripheral surface and the convex shape portion of the semiconductor wafer.

[0006] The semiconductor wafer disclosed herein has a first surface and a second surface opposite to the first surface. The first surface has a first main surface and a surrounding surface that surrounds the first main surface via a stepped surface and is recessed from the first main surface towards the second surface. A first cut is provided in a circumferential portion of the stepped surface that connects the first main surface and the surrounding surface, and a second cut is provided in a circumferential portion of the outer peripheral surface that connects the second surface and the surrounding surface. The first cut is in the shape of a positioning edge, and the second cut is in the shape of a notch.

[0007] The semiconductor wafer manufacturing method disclosed herein includes: a preparation step, preparing a semiconductor wafer having a first surface and a second surface opposite to the first surface, and having a second cut portion with a notch shape in a circumferential portion of an outer peripheral surface connecting the first surface and the second surface; a convex structure forming step, cutting a portion of the first surface corresponding to the surrounding surface in such a way that a first main surface is formed on the first surface of the semiconductor wafer and a surrounding surface that surrounds the first main surface via a stepped surface and is recessed from the first main surface towards the second surface; and a grinding step, performing cutting on a first cut portion having a positioning edge shape in a circumferential portion of the stepped surface connecting the first main surface and the surrounding surface.

[0008] According to the semiconductor wafer and semiconductor wafer manufacturing method disclosed herein, a notch is formed on the outer peripheral surface of the semiconductor wafer. The width of the circumferential notch is smaller than the width of the positioning edge. Therefore, a grinding stone larger than the width of the notch can be used to grind the surrounding surface and the first cut portion from above the notch, thereby reducing the width of the radial surrounding surface and the depth of the first cut portion on the inward diameter side. Therefore, it is possible to suppress the shrinkage of the diameter of the convex shape portion. Attached Figure Description

[0009] Figure 1 This is a top view of the semiconductor wafer involved in Embodiment 1.

[0010] Figure 2 This is a schematic cross-sectional view of the semiconductor wafer involved in Embodiment 1.

[0011] Figure 3 This is a top view of the semiconductor wafer before processing according to Embodiment 1.

[0012] Figure 4 This is a schematic cross-sectional view of the semiconductor wafer before processing according to Embodiment 1.

[0013] Figure 5 This is a schematic cross-sectional view of a semiconductor wafer involved in a variation of Embodiment 1.

[0014] Figure 6 This is a top view of the semiconductor wafer on the first main surface side after being divided, as described in Embodiment 1.

[0015] Figure 7 This is a top view of the semiconductor wafer on the second side after being divided, according to Embodiment 1.

[0016] Figure 8 This is a schematic cross-sectional view of the semiconductor wafer on the first main surface side after being divided, as described in Embodiment 1.

[0017] Figure 9 This is a schematic cross-sectional view of the semiconductor wafer on the second side after being divided, as described in Embodiment 1.

[0018] Figure 10 This is a schematic cross-sectional view of the semiconductor wafer on the first main surface side after being divided, as described in the comparative example of Embodiment 1.

[0019] Figure 11 This is a schematic cross-sectional view of the semiconductor wafer on the second side after being divided, as described in the comparative example of Embodiment 1.

[0020] Figure 12 This is a schematic cross-sectional view of a semiconductor wafer formed by joining two components involved in a variation of Embodiment 1.

[0021] Figure 13 This is a schematic cross-sectional view of a semiconductor wafer formed by joining two components involved in a variation of Embodiment 1.

[0022] Figure 14 This is a schematic cross-sectional view of a semiconductor wafer formed by joining two components involved in a variation of Embodiment 1.

[0023] Figure 15 This is a flowchart of the semiconductor wafer manufacturing method according to Embodiment 1.

[0024] Explanation of reference numerals in the attached figures

[0025] 1...First face; 2...Second face; 3...First main face; 4...Stepped face; 5...Outer peripheral face; 6...Bottom point; 8...Cut face; 9...Rounded corner machining; 10...Component on the first main face side; 11...Component on the second face side; 101...Semiconductor wafer; 108...Enclosing face; 121...Semiconductor element structure; 201...First cut; 202...Second cut; 301...Merging face. Detailed Implementation

[0026] 1. Implementation Method 1

[0027] The semiconductor wafer 101 according to Embodiment 1 will be described with reference to the accompanying drawings. Figure 1 This is a top view showing the semiconductor wafer 101 according to Embodiment 1. Additionally, Figure 2 These are schematic cross-sectional views of the semiconductor wafer 101 according to Embodiment 1. Each cross-sectional view is... Figure 1 A sectional view cut off at position X-X, etc. Furthermore, each schematic sectional view is a diagram used to schematically illustrate the characteristics of the parts, and the dimensions of each top view do not correspond to the dimensions of the parts.

[0028] 1-1. Structure of a semiconductor wafer

[0029] Semiconductor wafer 101 is a semiconductor wafer 101 having a first surface 1 and a second surface 2 opposite to the first surface 1. The first surface 1 has a first main surface 3 and a surrounding surface 108 that surrounds the first main surface 3 via a stepped surface 4 and is recessed towards the second surface 2 than the first main surface 3. A portion of the stepped surface 4 between the first main surface 3 and the surrounding surface 108 has a first cut 201 in the circumferential direction, and a portion of the outer peripheral surface 5 between the second surface 2 and the surrounding surface 108 has a second cut 202 in the circumferential direction. The first cut 201 is in the shape of an orientation flat, and the second cut 202 is in the shape of a notch.

[0030] Semiconductor wafers

[0031] In this embodiment, the semiconductor wafer 101 is described as being made of silicon carbide single crystal, but it can also be formed of other semiconductor materials or ceramic materials. Examples of semiconductor materials include silicon, gallium nitride-based materials, gallium oxide-based materials, or diamond. Examples of ceramic materials include α-Al₂O₃ (sapphire).

[0032] When silicon carbide is used as the material, it can be 15R-SiC (15R silicon carbide) or hexagonal polytype silicon carbide, such as 2H-SiC (2H-type silicon carbide), 4H-SiC (4H-type silicon carbide), or 6H-SiC (6H-type silicon carbide), and can also be polycrystalline or sintered. Dopant atoms may also include, for example, nitrogen (N), phosphorus (P), beryllium (Be), boron (B), aluminum (Al), and gallium (Ga). Furthermore, unwanted impurities such as hydrogen, fluorine, and oxygen may also be included.

[0033] The semiconductor wafer 101 may also have an off-axis angle on the C-plane. The off-axis angle is preferably in the A-axis direction ([11-20] direction) of the silicon carbide single crystal. The off-axis angle may be greater than 0° and less than 10°, and it is more preferably greater than 2° and less than 4.5°.

[0034] The diameter of the semiconductor wafer 101 can correspond to a production standard and can be 2 inches, 3 inches, 4 inches, 5 inches, 6 inches, 7 inches, 8 inches, or 12 inches. The thickness of the semiconductor wafer 101 is 0.1 mm or more and 50 mm or less, typically 20 mm or less. When using wafers for device formation cut from silicon carbide ingots, the thickness is 0.2 mm or more and 15 mm or less, preferably 10 mm or less, and more preferably 1 mm or less.

[0035] An epitaxial film can also be formed on the semiconductor wafer 101, and a semiconductor device structure 121 can be formed on the epitaxial film. The formation of the semiconductor device structure 121 includes ion implantation and the formation of surface electrodes. The semiconductor device structure 121 can be, for example, a power device structure such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a diode, or an IGBT (Insulated Gate Bipolar Transistor). Furthermore, when a gallium nitride wafer is used instead of a silicon carbide wafer, the semiconductor device structure 121 can be, for example, a GaN (gallium nitride) high-frequency device structure, and a gallium nitride high-frequency device structure can also be formed on a silicon carbide wafer.

[0036] <First main face and surrounding face>

[0037] Semiconductor wafer 101 is a semiconductor wafer 101 having a first surface 1 and a second surface 2 opposite to the first surface 1. The first surface 1 has a first main surface 3 and a surrounding surface 108 that surrounds the first main surface 3 via a stepped surface 4 and is recessed toward the second surface 2 from the first main surface 3.

[0038] The feature is that the diameter of the first main surface 3 is smaller than the diameter of the second surface 2, and at a part of the outer periphery, the first main surface 3 side has a first cut-out portion 201, and the second surface 2 side has a second cut-out portion 202.

[0039] By Figure 4 The schematic cross-sectional view shows the outer periphery of the semiconductor wafer 101 before grinding, from the first surface 1 to the middle of the thickness direction towards the second surface 2, and as... Figure 2 As shown in the schematic cross-sectional view, the semiconductor wafer 101 is formed as a convex structure.

[0040] As described above, the semiconductor wafer 101 is convex in shape, having a first main surface 3 and a surrounding surface 108. The first main surface 3 is positioned higher than the surrounding surface 108, and the surrounding surface 108 is configured to surround the first main surface 3. The first surface 1 has the surrounding surface 108 and the first main surface 3, and there exists a thickness between the first main surface 3 and the surrounding surface 108, i.e., the thickness on the side of the first main surface 3, and a thickness between the surrounding surface 108 and the second surface 2, i.e., the thickness of the surrounding surface.

[0041] The thickness between the first surface 1 and the second surface 2 varies depending on the thickness of the surrounding surface side and the thickness of the first main surface 3 side. The thickness of the surrounding surface side is preferably 0.05 mm or more and 50 mm or less, and more preferably 0.15 mm or less. The thickness of the second surface 2 side is preferably 0.05 mm or more and 50 mm or less, and more preferably 0.15 mm or less.

[0042] To suppress notches and cracks at the ends, the surrounding surface side is preferably thicker than the first main surface 3 side, which is preferably 100 to 200 micrometers thick to maintain strength after dicing. For example, when the total thickness of the wafer is 350 micrometers, the surrounding surface side is 200 to 250 micrometers thick and the first main surface 3 side is 100 to 150 micrometers thick; when the total thickness of the wafer is 500 micrometers thick, the surrounding surface side is 300 to 400 micrometers thick and the first main surface 3 side is 100 to 200 micrometers thick.

[0043] The difference between the diameter of the first main surface 3 and the diameter of the second surface 2 is preferably less than 2 mm, and more preferably less than 0.5 mm. By reducing the diameter by less than 0.5 mm, it is not necessary to adjust the diameter of the device when forming the semiconductor element structure 121 by dividing the semiconductor wafer 101 (described later) and reprocessing the side of the semiconductor wafer that has not formed the semiconductor element structure 121.

[0044] <First incision and second incision>

[0045] The semiconductor wafer 101 has a first cutout 201 in a circumferential portion of the stepped surface 4 between the first main surface 3 and the surrounding surface 108, and a second cutout 202 in a circumferential portion of the outer peripheral surface 5 between the second surface 2 and the surrounding surface 108.

[0046] like Figure 1 As shown in the top view, in this embodiment, when viewed vertically from the first main surface 3, the bottom point 6 of the notch-shaped second cut 202 overlaps with the cut surface 8 of the positioning edge-shaped first cut 201. When viewed vertically from the first main surface 3, the portion of the cut surface 8 of the positioning edge-shaped first cut 201 closest to the bottom point 6 of the notch-shaped second cut 202 is the center of the cut surface 8 of the first cut 201. According to this structure, the width of the surrounding surface 108 can be reduced to below the depth of the notch-shaped second cut 202, the depth of the first cut 201 can be reduced to below the depth of the notch-shaped second cut 202, and the diameter of the first main surface 3 can be enlarged. Furthermore, since the width of the circumferential notch is smaller than the width of the positioning edge, a grinding stone larger than the width of the notch can be used to grind the surrounding surface 108 and the first cut portion 201 from above the notch, thereby reducing the width of the radial surrounding surface 108 and the depth of the inner diameter side of the first cut portion 201. Moreover, as in Patent Document 1, when the second cut portion 202 is in the shape of a positioning edge, since the positioning edge is wide, it is impossible to grind the surrounding surface 108 and the first cut portion 201 from above the positioning edge. Therefore, the first cut portion 201 needs to be formed inside the positioning edge, increasing the depth of the first cut portion 201 and decreasing the diameter of the first main surface 3.

[0047] Furthermore, when viewed from the vertical direction of the first main surface 3, the shortest distance between the bottom point 6 of the notch-shaped second cut 202 and the cut surface 8 of the positioning edge-shaped first cut 201 can be less than the depth of the second cut 202. According to this structure, even with a certain degree of distance, the width of the surrounding surface 108 and the depth of the first cut 201 can be reduced, and the diameter of the first main surface 3 can be increased.

[0048] Furthermore, the cut shape may not be formed as one on each of the first main surface 3 and the second main surface 2; multiple cuts may be formed. For example, if another positioning edge is formed at a position 90 degrees different in the circumferential direction from the first cut 201, it is easy to determine the specific crystal orientation and conductivity type (P-type or N-type) of the semiconductor wafer 101. The first cut 201 and the second cut 202 may be formed at the same position or at different positions. However, since the cut shape indicates the crystal orientation, it is preferable that the first cut 201 and the second cut 202 are the same.

[0049] like Figure 5 As shown, the corners of the semiconductor wafer 101 can also be rounded 9. By rounding the corners 9, chipping and cracking caused by stress concentration at the ends can be suppressed, thereby improving the strength of the semiconductor wafer 101. A chamfer radius in the range of 0.5 micrometers to 50 micrometers, or 5 micrometers to 20 micrometers, is preferred. This chamfer can be controlled by adjusting the shape of the grinding stone being processed; sometimes, the shape of the grinding stone changes due to wear rather than being intentionally formed. Alternatively, chamfering can also be performed by etching.

[0050] 1-2. Semiconductor wafer manufacturing methods

[0051] In the comparative example, when... Figure 3 Top view and Figure 4 In the schematic cross-sectional view shown, a typical semiconductor wafer 101 having a semiconductor element structure 121 is divided into a first surface 1 and a second surface 2. In this case, the semiconductor wafer 101 is divided into... Figure 10 The schematic cross-sectional view shows a wafer 101 with semiconductor element structure 121, and Figure 11 The schematic cross-sectional view shows a semiconductor wafer 101 that does not contain semiconductor elements. For example... Figure 10 As shown, in the comparative example of the semiconductor element wafer 101, since no convex structure is formed, the edges are formed to be sharp. Because the edges are formed to be sharp, the possibility of stress concentration at the ends, resulting in edge chipping and cracking, is increased.

[0052] exist Figure 15 The flowchart of the manufacturing method of the semiconductor wafer 101 according to Embodiment 1 is shown.

[0053] <Preparation Process S1>

[0054] like Figure 3 Top view and Figure 4As shown in the schematic cross-sectional view, in the preparation process, a semiconductor wafer 101 is prepared having a first surface 1 and a second surface 2 opposite to the first surface 1, and having a second notch 202 in the circumferential direction of a portion of the outer peripheral surface 5 connecting the first surface 1 and the second surface 2. Figure 3 as well as Figure 4 In this process, a semiconductor wafer 101 with a semiconductor element structure 121 formed on the first surface 1 is prepared. However, the structure of the semiconductor wafer 101 can also be formed after the grinding process S3 or the dicing process S4.

[0055] <Convex Structure Formation Process S2>

[0056] like Figure 2 As shown in the schematic diagram, in the convex structure forming process S2, the portion of the first surface 1 corresponding to the surrounding surface 108 is cut in such a manner that a first main surface 3 is formed on the first surface 1 of the semiconductor wafer 101, and a surrounding surface 108 is formed around the first main surface 3 via a stepped surface 4 and recessed towards the second surface 2 from the first main surface 3. The semiconductor wafer 101, which has a second cut 202 in a portion of the circumferential direction of the outer peripheral surface 5 connecting the first surface 1 and the second surface 2, is ground from the first main surface 3 to the middle of the path towards the second surface 2.

[0057] <Grinding process S3>

[0058] In the grinding process S3, a first cut 201 is cut into a locating edge shape on a portion of the step surface 4 that connects the first main surface 3 and the surrounding surface 108.

[0059] The same cutting device is used for both the convex structure forming process S2 and the grinding process S3. This structure reduces manufacturing costs. For example, in the convex structure forming process S2 and the grinding process S3, a device equipped with a grinding stone is used, for instance, on a rotary edge processing machine. As the grinding stone, a stone adjusted to be able to grind the outer periphery of the first surface 1 from above is used. Using a stone larger than the width of the notch of the second cut portion 202, the surrounding surface 108 and the first cut portion 201 can be ground from above the notch.

[0060] Alternatively, the surrounding surface 108 and the first cut portion 201 can be formed by partially cutting the outer periphery of the first surface 1 using a cutting device. In either method, the grinding stone used to process the first cut portion 201 can be the same grinding stone used to process the surrounding surface 108. By processing in this way, a positioning edge can be formed at a position closer to the inside of the notch end.

[0061] <Segmentation Process S4>

[0062] In the dicing process S4, the semiconductor wafer 101 is cut in the same plane as the surrounding surface 108, thus dividing it into semiconductor wafers 101 on the first main surface 3 sides and semiconductor wafers 101 on the second main surface 2 sides. This separates them into... Figure 6 Top view and Figure 8 The schematic cross-sectional view shows the semiconductor wafer 101 on the first main surface 3 sides, and Figure 7 Top view and Figure 9 The schematic cross-sectional view shows the semiconductor wafer 101 on the second side 2. (See diagram below.) Figure 8 As shown, due to the formation of a convex structure, it is similar to... Figure 10 Unlike the comparative example, this design prevents the edges from becoming sharp and reduces the likelihood of edge chipping and breakage. Furthermore, as described above, the diameter of the semiconductor wafer 101 on the first main surface 3 can be reduced.

[0063] The semiconductor wafers 101 on the first main surface 3 sides can be aligned via positioning edges during processing in a semiconductor manufacturing apparatus. Therefore, it is unnecessary to perform additional processing on the semiconductor wafers 101 on the first main surface 3 sides to form positioning notches. Furthermore, the diameter of the semiconductor wafers 101 on the second surface 2 sides is the same as that of the semiconductor wafers 101 before dicing, so it is unnecessary to adjust the diameter of the apparatus when reprocessing the semiconductor wafers 101 on the second surface 2 sides to form semiconductor devices. Additionally, due to the notch, alignment can be performed via the notch during processing in a semiconductor manufacturing apparatus. Therefore, it is unnecessary to perform additional processing on the semiconductor wafers 101 on the second surface 2 sides to form positioning notches.

[0064] The division of semiconductor wafer 101 from the semiconductor wafer 101 to the semiconductor wafer 101 on the first main surface 3 side and the semiconductor wafer 101 on the second surface 2 side can be either a method that contacts the semiconductor wafer 101, such as a cutting saw, or a non-contact method using optical methods.

[0065] <Variation Example>

[0066] like Figures 12 to 14 As shown in the schematic cross-sectional view, the semiconductor wafer 101 can also be constructed by joining the components on the first side with the components on the second side.

[0067] For example, such as Figure 14 As shown in the schematic cross-sectional view, in the semiconductor wafer 101, the mating surface 301 of the component 10 on the first main surface side and the component 11 on the second surface side can also be provided on the same plane as the surrounding surface 108.

[0068] Or, such as Figure 13As shown in the schematic cross-sectional view, in the semiconductor wafer 101, the mating surface 301 of the component 10 on the first main surface side and the component 11 on the second surface side can also be provided at a position closer to the second surface 2 than the surrounding surface 108.

[0069] Or, such as Figure 12 As shown in the schematic cross-sectional view, in the semiconductor wafer 101, the mating surface 301 of the component 10 on the first main surface side and the component 11 on the second surface side can also be provided at a position closer to the first main surface 3 than the surrounding surface 108.

[0070] For example, a room-temperature bonding technique is used to join the two components. With room-temperature bonding, no metal layer or the like is present in the bonding surface 301, resulting in a clean interface. Furthermore, when using room-temperature bonding, an amorphous layer can be formed on the bonding surface 301. The thickness of the amorphous layer is preferably 5 micrometers or less, and more preferably 0.1 micrometers or less.

[0071] The components on the three sides of the first main surface and the two sides of the second surface are made of single crystal. Alternatively, one component on the three sides of the first main surface and the two sides of the second surface may be single crystal, while the other component may be polycrystalline. By using a polycrystalline substrate and wafers made of different materials, a semiconductor wafer 101 can be formed more cost-effectively than bonding single-crystal wafers together. When both components undergo high-temperature processing and implantation processing, the wafer may warp due to stress, so it is preferable to bond materials with similar physical properties. Physical properties, such as the coefficient of thermal expansion and melting point, are included in the selection factors when choosing component materials.

[0072] After joining the two components together, a convex structure having the same first cut portion 201 and second cut portion 202 as the semiconductor wafer 101 is formed using the manufacturing method described above and a rotary edge processing machine or cutting device. Alternatively, wafers with different diameters and cut shapes can be joined together from the beginning to form the same structure as the semiconductor wafer 101.

[0073] Although the case shown is that two components are joined together to form a semiconductor wafer 101, it is also possible to join three or more components to form a semiconductor wafer 101.

Claims

1. A semiconductor wafer having a first surface and a second surface opposite to the first surface, wherein, The first surface has: a first main surface; And a surrounding surface that surrounds the first main surface via a stepped surface and is recessed towards the second surface than the first main surface. A first cutout is provided in a circumferential portion of the stepped surface that connects the first main surface to the surrounding surface. A second cutout is provided in a circumferential portion of the outer peripheral surface that connects the second surface to the surrounding surface. The first cutout is in the shape of a positioning edge, and the second cutout is in the shape of a notch.

2. The semiconductor wafer according to claim 1, wherein, When viewed from the vertical direction of the first main surface, the shortest distance between the bottom point of the second cut portion of the notch shape and the cut surface of the first cut portion of the positioning edge shape is below the depth of the second cut portion.

3. The semiconductor wafer according to claim 1, wherein, When viewed from the vertical direction of the first main surface, the bottom point of the second cut portion of the notch shape overlaps with the cut surface of the first cut portion of the positioning edge shape.

4. The semiconductor wafer according to claim 1, wherein, When viewed from the vertical direction of the first main surface, the part of the cut surface of the first cut portion of the positioning edge shape that is closest to the bottom point of the second cut portion of the notch shape is the center of the cut surface of the first cut portion.

5. The semiconductor wafer according to any one of claims 1 to 4, wherein, The semiconductor wafer is composed of a single component.

6. The semiconductor wafer according to any one of claims 1 to 4, wherein, The semiconductor wafer is formed by bonding components on the first main surface side to components on the second surface side.

7. The semiconductor wafer according to claim 6, wherein, The mating surfaces of the component on the first main surface side and the component on the second surface side are disposed on the same plane as the surrounding surface.

8. The semiconductor wafer according to claim 6, wherein, The mating surface between the component on the first main surface and the component on the second surface is located closer to the second surface than the surrounding surface.

9. The semiconductor wafer according to claim 6, wherein, The mating surface between the component on the first main surface and the component on the second surface is located closer to the first main surface than the surrounding surface.

10. The semiconductor wafer according to any one of claims 1 to 4, wherein, The components on the first main surface and the components on the second surface are made of single crystal.

11. The semiconductor wafer according to any one of claims 1 to 4, wherein, The component on the first main surface side and the component on the second surface side are configured such that one of the components is monocrystalline and the other component is polycrystalline.

12. The semiconductor wafer according to any one of claims 1 to 4, wherein, The corners of the semiconductor wafer are rounded.

13. A method for manufacturing a semiconductor wafer, wherein, have: The preparation process involves preparing a semiconductor wafer having a first surface and a second surface opposite to the first surface, and having a second cut portion with a notch shape in a circumferential portion of the outer peripheral surface that connects the first surface and the second surface. The convex structure forming process involves cutting a portion of the first surface corresponding to the surrounding surface in a manner that forms a first main surface on the first surface of the semiconductor wafer and a surrounding surface that surrounds the first main surface via a stepped surface and is recessed from the first main surface towards the second surface. as well as The grinding process involves cutting a first cut portion that forms a positioning edge shape on a portion of the circumferential direction of the stepped surface connecting the first main surface and the surrounding surface.

14. The method for manufacturing a semiconductor wafer according to claim 13, wherein, The same cutting device is used for both the convex structure forming process and the grinding process.

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